march 1990 revised november 1998 74actq841 quiet series ? 10-bit transparent latch with 3-state outputs ? 1999 fairchild semiconductor corporation ds010688.prf www.fairchildsemi.com 74actq841 quiet series ? 10-bit transparent latch with 3-state outputs general description the actq841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. the 841 is a 10-bit transparent latch, a 10-bit version of the 373. the actq841 utilizes fairchild quiet series ? technology to guarantee quiet output switch- ing and improved dynamic threshold performance. fact quiet series features gto ? output control and undershoot corrector in addition to a split ground bus for superior per- formance. features n guaranteed simultaneous switching noise level and dynamic threshold performance n guaranteed pin-to-pin skew ac performance n inputs and outputs on opposite sides of package allow easy interface with microprocessors n improved latch-up immunity n outputs source/sink 24 ma n has ttl-compatible inputs ordering code: device also available in tape and reel. specify by appending suffix letter x to the ordering code. logic symbols connection diagram pin assignment for dip and soic pin descriptions fact ? , quiet series ? , fact quiet series ? and gto ? are trademarks of fairchild semiconductor corporation. order number package number package description 74actq841sc m24b 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide body 74actq841spc n24c 24-lead plastic dual-in-line package (pdip), jedec, ms-100, 0.300 wide pin names description d 0 Cd 9 data inputs o 0 Co 9 3-state outputs oe output enable le latch enable
www.fairchildsemi.com 2 74actq841 functional description the actq841 consists of ten d-type latches with 3-state outputs. the flip-flops appear transparent to the data when latch enable (le) is high. this allows asynchronous operation, as the output transition follows the data in transi- tion. on the le high-to-low transition, the data that meets the setup and hold time is latched. data appears on the bus when the output enable (oe ) is low. when oe is high the bus output is in the high impedance state. function table h = high voltage level l = low voltage level x = immaterial z = high impedance nc = no change logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays. inputs internal output function oe le d q o x x x x z high z h h l l z high z h h h h z high z h l x nc z latched l h l l l transparent l h h h h transparent l l x nc nc latched
3 www.fairchildsemi.com 74actq841 absolute maximum ratings (note 1) recommended operating conditions note 1: absolute maximum ratings are those values beyond which damage to the device may occur. the databook specifications should be met, with- out exception, to ensure that the system design is rel iable over its power supply, temperature, and output/input loading variables. fairchild does not recommend operation of fact ? circuits outside databook specifications. dc electrical characteristics note 2: all outputs loaded; thresholds on input associated with output under test. supply voltage (v cc ) - 0.5v to + 7.0v dc input diode current (i ik ) v i = - 0.5v - 20 ma v i = v cc + 0.5v + 20 ma dc input voltage (v i ) - 0.5v to v cc + 0.5v dc output diode current (i ok ) v o = - 0.5v - 20 ma v o = v cc + 0.5v + 20 ma dc output voltage (v o ) - 0.5v to v cc + 0.5v dc output source or sink current (i o ) 50 ma dc v cc or ground current per output pin (i cc or i gnd ) 50 ma storage temperature (t stg ) - 65 c to + 150 c dc latch-up source or sink current 300 ma junction temperature (t j ) pdip 140 c supply voltage (v cc ) 4.5v to 5.5v input voltage (v i )0v to v cc output voltage (v o )0v to v cc operating temperature (t a ) - 40 c to + 85 c minimum input edge rate d v/ d t 125 mv/ns v in from 0.8v to 2.0v v cc @ 4.5v, 5.5v symbol parameter v cc t a = + 25 ct a = - 40 c to + 85 c units conditions (v) typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1v input voltage 5.5 1.5 2.0 2.0 or v cc - 0.1v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1v input voltage 5.5 1.5 0.8 0.8 or v cc - 0.1v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = - 50 m a output voltage 5.5 5.49 5.4 5.4 v in = v il or v ih 4.5 3.86 3.76 v i oh = - 24 ma 5.5 4.86 4.76 i oh = - 24 ma (note 2) v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 m a output voltage 5.5 0.001 0.1 0.1 v in = v il or v ih 4.5 0.36 0.44 v i ol = - 24 ma 5.5 0.36 0.44 i ol = - 24 ma (note 2) i in maximum input 5.5 0.1 1.0 m av i = v cc , gnd leakage current i oz maximum 3-state 5.5 0.5 5.0 m av i = v il , v ih leakage current v o = v cc , gnd i cct maximum i cc /input 5.5 0.6 1.5 ma v i = v cc - 2.1v i old minimum dynamic 5.5 75 ma v old = 1.65v max i ohd output current (note 3) 5.5 - 75 ma v ohd = 3.85v min i cc maximum quiescent 5.5 8.0 80.0 m av in = v cc or gnd supply current v olp quiet output 5.0 1.1 1.5 v figure 1, figure 2 maximum dynamic v ol (note 4)(note 5) v olv quiet output 5.0 - 0.6 - 1.2 v figure 1, figure 2 minimum dynamic v ol (note 4)(note 5) v ihd minimum high level 5.0 1.9 2.2 v (note 4)(note 6) dynamic input voltage v ild maximum low level 5.0 1.2 0.8 v (note 4)(note 6) dynamic input voltage
www.fairchildsemi.com 4 74actq841 dc electrical characteristics (continued) note 3: maximum test duration 2.0 ms, one output loaded at a time. note 4: pdip package. note 5: max number of outputs defined as (n). data inputs are driven 0v to 3v. one output @ gnd. note 6: max number of data inputs (n) switching. (n - 1) inputs switching 0v to 3v (actq). input-under-test switching: 3v to threshold (v ild ), 0v to threshold (v ihd ), f = 1 mhz. ac electrical characteristics note 7: voltage range 5.0 is 5.0v 0.5v. note 8: skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the sam e packaged device. the specification applies to any outputs switching in the same direction, either high to low (t oshl ) or low to high (t oslh ). parameter guaranteed by design. not tested. ac operating requirements note 9: voltage range 5.0 is 5.0v 0.5v. capacitance v cc t a = + 25 ct a = - 40 c to + 85 c symbol parameter (v) c l = 50 pf c l = 50 pf units (note 7) min typ max min max t plh propagation delay 5.0 2.5 7.0 9.5 2.0 10.0 ns t phl d n to o n t plh propagation delay 5.0 2.5 7.0 9.5 2.0 10.0 ns t phl le to o n t pzh output enable time 5.0 2.5 8.5 11.0 2.0 12.0 ns t pzl oe to o n t phz output disable time 5.0 1.0 6.0 9.0 1.0 9.5 ns t plz oe to o n t oslh output to output 5.0 0.5 1.0 1.0 ns t oshl skew d n to o n (note 8) v cc t a = + 25 t a = - 40 c to + 85 c symbol parameter (v) c l = 50 pf cc l = 50 pf units (note 9) typ guaranteed minimum t s setup time, high or low 5.0 3.0 3.0 ns d n to le t h hold time, high or low 5.0 1.5 1.5 ns d n to le t w le pulse width, high 5.0 4.0 4.0 ns symbol parameter typ units conditions c in input capacitance 4.5 pf v cc = open c pd power dissipation capacitance 85.0 pf v cc = 5.0v
5 www.fairchildsemi.com 74actq841 fact noise characteristics the setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. the following is a brief description of the setup used to measure the noise characteristics of fact. equipment: hewlett packard model 8180a word generator pc-163a test fixture tektronics model 7854 oscilloscope procedure: 1. verify test fixture loading: standard load 50 pf, 500 w . 2. deskew the hfs generator so that no two channels have greater than 150 ps skew between them. this requires that the oscilloscope be deskewed first. it is important to deskew the hfs generator channels before testing. this will ensure that the outputs switch simultaneously. 3. terminate all inputs and outputs to ensure proper load- ing of the outputs and that the input levels are at the correct voltage. 4. set the hfs generator to toggle all but one output at a frequency of 1 mhz. greater frequencies will increase dut heating and effect the results of the measure- ment. 5. set the hfs generator input levels at 0v low and 3v high for act devices and 0v low and 5v high for ac devices. verify levels with an oscilloscope. note a: v ohv and v olp are measured with respect to ground reference. note b: input pulses have the following characteristics: f = 1 mhz, t r = 3ns, t f = 3 ns, skew < 150 ps. figure 1. quiet output noise voltage waveforms v olp /v olv and v ohp /v ohv : ? determine the quiet output pin that demonstrates the greatest noise levels. the worst case pin will usually be the furthest from the ground pin. monitor the output volt- ages using a 50 w coaxial cable plugged into a standard smb type connector on the test fixture. do not use an active fet probe. ? measure v olp and v olv on the quiet output during the worst case transition for active and enable. measure v ohp and v ohv on the quiet output during the worst case active and enable transition. ? verify that the gnd reference recorded on the oscillo- scope has not drifted to ensure the accuracy and repeat- ability of the measurements. v ild and v ihd : ? monitor one of the switching outputs using a 50 w coaxial cable plugged into a standard smb type connector on the test fixture. do not use an active fet probe. ? first increase the input low voltage level, v il , until the output begins to oscillate or steps out of a min of 2 ns. oscillation is defined as noise on the output low level that exceeds v il limits, or on output high levels that exceed v ih limits. the input low voltage level at which oscillation occurs is defined as v ild . ? next decrease the input high voltage level, v ih , until the output begins to oscillate or steps out a min of 2 ns. oscillation is defined as noise on the output low level that exceeds v il limits, or on output high levels that exceed v ih limits. the input high voltage level at which oscillation occurs is defined as v ihd . ? verify that the gnd reference recorded on the oscillo- scope has not drifted to ensure the accuracy and repeat- ability of the measurements. figure 2. simultaneous switching test circuit
www.fairchildsemi.com 6 74actq841 physical dimensions inches (millimeters) unless otherwise noted 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide body package number m24b
fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. 74actq841 quiet series ? 10-bit transparent latch with 3-state outputs life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com physical dimensions inches (millimeters) unless otherwise noted (continued) 24-lead plastic dual-in-line package (pdip), jedec ms-100, 0.300 wide package number n24c
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