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tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 1 post office box 655303 ? dallas, texas 75265 programmable settling time to 0.5 lsb 2.5 m s or 12.5 m s typ two 12-bit cmos voltage output dacs in an 8-pin package simultaneous updates for dac a and dac b single supply operation 3-wire serial interface high-impedance reference inputs voltage output range ... 2 times the reference input voltage software powerdown mode internal power-on reset tms320 and spi compatible low power consumption: 3 mw typ in slow mode, 8 mw typ in fast mode input data update rate of 1.21 mhz monotonic over temperature available in q-temp automotive highrel automotive applications configuration control / print support qualification to automotive standards applications battery powered test instruments digital offset and gain adjustment battery operated/remote industrial controls machine and motion control devices cellular telephones description the tlc5618 is a dual 12-bit voltage output digital-to-analog converter (dac) with buffered reference inputs (high impedance). the dacs have an output voltage range that is two times the reference voltage, and the dacs are monotonic. the device is simple to use, running from a single supply of 5 v. a power-on reset function is incorporated in the device to ensure repeatable start-up conditions. digital control of the tlc5618 is over a 3-wire cmos-compatible serial bus. the device re- ceives a 16-bit word for programming and producing the analog output. the digital inputs feature schmitt triggers for high noise immunity. digital communication protocols include the spi ? , qspi ? , and microwire ? standards. two versions of the device are available. the tlc5618 does not have an internal state machine and is dependent on all external timing signals. the tlc5618a has an internal state machine that counts the number of clocks from the falling edge of cs and then updates and disables the device from accepting further data inputs. the tlc5618a is recommended for tms320 and spi processors, and the tlc5618 is recommended only for spi or 3-wire serial port processors. the tlc5618a is backward-compatible and designed to work in tlc5618 designed systems. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation. copyright ? 1999, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 1 2 3 4 8 7 6 5 din sclk cs out a v dd out b refin agnd d, p, or jg package (top view) 19 20 1 32 17 18 16 15 14 13 12 11 9 10 5 4 6 7 8 nc outb nc refin nc nc sclk nc cs nc nc din nc v nc outa nc agnd nc nc fk package (top view) dd on products compliant to mil-prf-38535, all parameters are tested unless otherwise noted. on all other products, production processing does not necessarily include testing of all parameters.
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 2 post office box 655303 ? dallas, texas 75265 description (continued) the 8-terminal small-outline d package allows digital control of analog functions in space-critical applications. the tlc5618c is characterized for operation from 0 c to 70 c. the tlc5618i is characterized for operation from 40 c to 85 c. the tlc5618q is characterized for operation from 40 c to 125 c. the tlc5618m is characterized for operation from 55 c to 125 c. available options package t a small outline 2 (d) plastic dip (p) ceramic dip (jg) 20 pad lcc (fk) 0 c to 70 c tlc5618cd tlc5618acd tlc5618cp tlc5618acp e e e e 40 c to 85 c tlc5618id tlc5618aid tlc5618ip tlc5618aip e e e e 40 c to 125 c tlc5618aqd e e e 55 c to 125 c e e TLC5618AMJG tlc5618amfk 2 the d package is available in tape and reel by adding r to the part number (e.g., tlc5618cdr) device compatibility tlc5618 spi, qspi and microwire tlc5618a tms320cxx, spi, qspi, and microwire
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 3 post office box 655303 ? dallas, texas 75265 functional block diagram _ + dac 12-bit dac register latch a power-up reset control logic 16-bit shift register 4 program bits 12 data bits (lsb) (msb) refin agnd cs sclk din out a (voltage output) _ + rr dac a 2 double buffer latch _ + _ + out b (voltage output) dac b dac r 2 r 12-bit dac register latch b 7 4 6 5 3 2 1 terminal functions terminal i/o description name no. i/o description agnd 5 analog ground cs 3 i chip select, active low din 1 i serial data input out a 4 o dac a analog output out b 7 o dac b analog output refin 6 i reference voltage input sclk 2 i serial clock input v dd 8 positive power supply
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 4 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage (v dd to agnd) 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital input voltage range to agnd 0.3 v to v dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference input voltage range to agnd 0.3 v to v dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage at out from external source v dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current at any terminal 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a : tlc5618c, tlc5618ac 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . tlc5618i, tlc5618ai 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . tlc5618aq 40 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tlc5618am 55 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. dissipation rating table package t a 25 c derating factor t a = 70 c t a = 85 c t a = 125 c package a power rating above t a = 25 c 3 a power rating a power rating a power rating d 635 mw 5.08 mw/ c 407 mw 330 mw e fk 1375 mw 11.00 mw/ c 880 mw 715 mw 275 mw jg 1050 mw 8.40 mw/ c 672 mw 546 mw 210 mw p 1202 mw 9.61 mw/ c 769 mw 625 mw e 3 this is the inverse of the traditional junction-to-ambient thermal resistance (r q ja ). thermal resistances are not production tested and are for informational purposes only. recommended operating conditions min nom max unit supply voltage, v dd 4.5 5 5.5 v high-level digital input voltage, v ih v dd = 5 v 0.7 v dd v low-level digital input voltage, v il v dd = 5 v 0.3 v dd v reference voltage, v ref to refin terminal 2 2.048 v dd 1.1 v load resistance, r l 2 k w tlc5618c, tlc5618ac 0 70 o p erating free air tem p erature t a tlc5618i, tlc5618ai 40 85 c operating free - air temperat u re , t a tlc5618aq 40 125 c tlc5618am 55 125
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 5 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range, v dd = 5 v 5%, v ref(refin) = 2.048 v (unless otherwise noted) static dac specifications parameter test conditions min typ max unit resolution 12 bits integral nonlinearity (inl), end point adjusted v ref(refin) = 2.048 v, see note 1 4 lsb differential nonlinearity (dnl) v ref(refin) = 2.048 v, see note 2 0.5 1 lsb e zs zero-scale error (offset error at zero scale) v ref(refin) = 2.048 v, see note 3 12 mv zero-scale-error temperature coefficient v ref(refin) = 2.048 v, see note 4 3 ppm/ c e g gain error v ref(refin) = 2.048 v, see note 5 0.29 % of fs voltage gain error temperature coefficient v ref(refin) = 2.048 v, see note 6 1 ppm/ c zero scale slow 65 psrr power-su pp ly rejection ratio gain see notes 7 and 8 slo w 65 db psrr power - su ly rejection ratio zero scale see notes 7 and 8 fast 65 db gain fast 65 notes: 1. the relative accuracy or integral nonlinearity (inl) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. 2. the differential nonlinearity (dnl) sometimes referred to as differential error, is the difference between the measured and i deal 1 lsb amplitude change of any two adjacent codes. monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 3. zero-scale error is the deviation from zero voltage output when the digital input code is zero. 4. zero-scale-error temperature coefficient is given by: e zs tc = [e zs (t max ) e zs (t min )]/v ref 10 6 /(t max t min ). 5. gain error is the deviation from the ideal output (v ref 1 lsb) with an output load of 10 k w excluding the effects of the zero-error. 6. gain temperature coefficient is given by: e g tc = [e g (t max ) e g (t min )]/v ref 10 6 /(t max t min ). 7. zero-scale-error rejection ratio (ezs-rr) is measured by varying the v dd from 4.5 v to 5.5 v dc and measuring the proportion of this signal imposed on the zero-code output voltage. 8. gain-error rejection ratio (eg-rr) is measured by varying the v dd from 4.5 v to 5.5 v dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero scale change. out a and out b output specifications parameter test conditions min typ max unit v o voltage output range r l = 10 k w 0 v dd 0.4 v output load regulation accuracy v o(out) = 4.096 v, r l = 2 k w 0.29 % of fs voltage i osc(sink) out p ut short circuit sink current v o(a out) = v dd , v o(b out) =v dd fast 38 ma i osc( s i n k) out ut short circuit sink current v o(b out) = v dd , input code zero slow 23 ma i osc(source) out p ut short circuit source current v o(a out) = 0 v, v o(b out) =0v fast 54 ma i osc( source ) out ut short circuit source current v o(b out) = 0 v , full-scale code slow 29 ma i o(sink) output sink current v o(out) = 0.25 v 5 ma i o(source) output source current v o(out) = 4.2 v 5 ma
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 6 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range, v dd = 5 v 5%, v ref(refin) = 2.048 v (unless otherwise noted) (continued) reference input (refin) parameter test conditions min typ max unit v i input voltage range 0 v dd 2 v r i input resistance 10 m w c i input capacitance 5 pf reference feedthrough refin = 1 v pp at 1 khz + 1.024 v dc (see note 9) 60 db reference in p ut bandwidth (f 3 db) refin = 0 2 v + 1 024 v dc slow 0.5 mhz reference inp u t band w idth (f 3 db) refin = 0 . 2 v pp + 1 . 024 v dc fast 1 mh z note 9: reference feedthrough is measured at the dac output with an input code = 000 hex and a v ref(refin) input = 1.024 v dc + 1 v pp at 1 khz. digital inputs (din, sclk, cs ) parameter test conditions min typ max unit i ih high-level digital input current v i = v dd 1 m a i il low-level digital input current v i = 0 v 1 m a c i input capacitance 8 pf power supply parameter test conditions min typ max unit i dd power su pp ly current v dd = 5.5 v, no load slow 0.6 1 ma i dd po w er s u ppl y c u rrent no load , all inputs = 0 v or v dd fast 1.6 2.5 ma power down supply current d13 = 0 (see table 2) 1 m a operating characteristics over recommended operating free-air temperature range, v dd = 5 v 5%, v ref(refin) = 2.048 v (unless otherwise noted) analog output dynamic performance parameter test conditions min typ max unit sr+ out p ut slew rate p ositive c l = 100 pf, r l 10 k w v ref(refin) = 2.048 v, t a =25 c slow 0.3 0.5 v/ m s sr + o u tp u t sle w rate , positi v e r l = 10 k w , code 32 to code 4096, t a = 25 c , v o from 10% to 90% fast 2.4 3 v/ m s sr out p ut slew rate negative c l = 100 pf, r l 10 k w v ref(refin) = 2.048 v, t a =25 c slow 0.15 0.25 v/ m s sr o u tp u t sle w rate , negati v e r l = 10 k w , code 4096 to code 32, t a = 25 c , v o from 10% to 90% fast 1.2 1.5 v/ m s t out p ut settling time to 0.5 lsb, c l = 100 pf, slow 12.5 m s t s o u tp u t settling time , r l = 10 k w , see note 10 fast 2.5 m s t () output settling time, to 0.5 lsb, c l = 100 pf, slow 2 m s t s(c) g, code-to-code , r l = 10 k w , see note 11 fast 2 m s glitch energy din = all 0s to all 1s, f (sclk) = 100 khz cs = v dd , 5 nvs s/(n+d) signal to noise + distortion v ref(refin) = 1 v pp at 1 khz and 10 khz + 1.024 v dc, input code = 10 0000 0000 78 db notes: 10. settling time is the time for the output signal to remain within 0.5 lsb of the final measured value for a digital input code change of 020 hex to 3ff hex or 3ff hex to 020 hex. 11. settling time is the time for the output signal to remain within 0.5 lsb of the final measured value for a digital input code change of one count.
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 7 post office box 655303 ? dallas, texas 75265 operating characteristics over recommended operating free-air temperature range, v dd = 5 v 5%, v ref(refin) = 2.048 v (unless otherwise noted) (continued) digital input timing requirements min nom max unit t su(ds) setup time, din before sclk low 5 ns t h(dh) hold time, din valid after sclk low 5 ns t su(css) setup time, cs low to sclk low 5 ns t su(cs1) setup time, sclk to cs , external end-of-write 10 ns t su(cs2) setup time, sclk to cs , start of next write cycle 5 ns t w(cl) pulse duration, sclk low 25 ns t w(ch) pulse duration, sclk high 25 ns t d(cs1) delay time, clk to data disable (tlc5618a only) 5 20 ns note a: the input clock, applied at the sclk terminal, should be inhibited high when cs is high to minimize clock feedthrough. ??? ??? ??? ??????? ??????? ??????? t su(css) t w(cl) t w(ch) cs sclk din t su(ds) t h(dh) d15 d14 d13 d12 d11 d0 ??? t s dac a/b out final value 0.5 lsb (see note a) ?????? program bits (4) ????? ????? ????? dac data bits (12) t su(cs1) t su(cs2) figure 1. timing diagram for the tlc5618
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 8 post office box 655303 ? dallas, texas 75265 note a: the input clock, applied at the sclk terminal, should be inhibited high when cs is high to minimize clock feedthrough. ??? ??? ??? ??????? ??????? ??????? t su(css) t w(cl) t w(ch) cs sclk din t su(ds) t h(dh) d15 d14 d13 d12 d11 d0 t s dac a/b out final value 0.5 lsb (see note a) program bits (4) dac data bits (12) t su(cs1) t su(cs2) 16th falling edge t d(cs1) internally generated disable at this time internal latch control (see note a) figure 2. timing diagram for tlc5618a only
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 9 post office box 655303 ? dallas, texas 75265 typical characteristics figure 3 15 10 0 5 012 output sink current ma 20 25 output load voltage v output sink current (fast mode) vs output load voltage 30 3.5 5 35 40 1.5 0.5 2.5 3 4 4.5 v dd = 5 v, input code = 0 figure 4 30 20 10 0 output source current ma 40 50 output load voltage v output source current (fast mode) vs output load voltage 60 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 v dd = 5 v, input code = 4095 figure 5 10 5 0 0 output sink current ma 15 20 output load voltage v output sink current (slow mode) vs output load voltage 25 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 v dd = 5 v, input code = 0 figure 6 15 10 5 0 output source current ma 20 25 output load voltage v output source current (slow mode) vs output load voltage 30 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 v dd = 5 v, input code = 4095
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 10 post office box 655303 ? dallas, texas 75265 typical characteristics figure 7 0.4 supply current ma 1 1.4 supply current vs temperature 1.2 0.8 0.6 0.2 0 60 40 20 0 20 40 60 80 100 120 140 temperature c v dd = 5 v, v refin = 2.048 v, t a = 25 c fast mode slow mode 1.6 figure 8 10 15 20 30 100 1000 relative gain db 5 0 f frequency khz relative gain (fast mode) vs frequency 5 10 k 25 v cc = 5 v, v refin = 0.2 v pp + 2.048 vdc, t a = 25 c figure 9 10 15 20 30 100 1000 relative gain db 5 0 f frequency khz relative gain (slow mode) vs frequency 5 10 k 25 v cc = 5 v, v refin = 0.2 v pp +2.048 vdc, t a = 25 c 35 40 figure 10 80 75 70 65 110 thd total harmonic distortion db 85 90 f frequency khz total harmonic distortion (slow mode) vs frequency 95 100
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 11 post office box 655303 ? dallas, texas 75265 typical characteristics figure 11 70 65 60 110 thd+n total harmonic distortion + noise db 75 80 f frequency khz total harmonic distortion + noise (slow mode) vs frequency 85 100 figure 12 75 70 65 110 snr signal-to-noise ratio db 80 f frequency khz signal-to-noise ratio (slow mode) vs frequency 85 100 figure 13 85 80 75 110 thd total harmonic distortion db 90 f frequency khz total harmonic distortion (fast mode) vs frequency 95 100 figure 14 75 70 65 110 thd+n total harmonic distortion + noise db 80 f frequency khz total harmonic distortion + noise (fast mode) vs frequency 85 100
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 12 post office box 655303 ? dallas, texas 75265 typical characteristics 75 70 65 110 snr signal-to-noise ratio db 80 f frequency khz signal-to-noise ratio (fast mode) vs frequency 85 100 figure 15
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 13 post office box 655303 ? dallas, texas 75265 typical characteristics 0.6 1 0 0.2 0.8 0.6 0.4 0.2 0.4 0.8 1 samples 500 2000 3000 4095 0 1000 1500 2500 3500 dnl differential nonlinearity lsb figure 16. differential nonlinearity with input code 2 1 1.5 1 0.5 0 0.5 2.5 3.0 samples 500 2000 3000 4095 0 1000 1500 2500 3500 inl integral nonlinearity lsb figure 17. integral nonlinearity with input code
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 14 post office box 655303 ? dallas, texas 75265 application information general function the tlc5618 uses a resistor string network buffered with an op amp to convert 12-bit digital data to analog voltage levels (see functional block diagram and figure 18). the output is the same polarity as the reference input (see table 1). the output code is given by: 2 v refin code 4096 an internal circuit resets the dac register to all 0s on power up. _ + resistor string dac 5 v 0.1 m f agnd v dd out refin r r _ + 2 din cs sclk figure 18. tlc5618 typical circuit table 1. binary code table (0 v to 2 v refin output) , gain = 2 input output 1111 1111 1111 2 v refin 4095 4096 : : 1000 0000 0001 2 v refin 2049 4096 1000 0000 0000 2 v refin 2048 4096 v refin 0111 1111 1111 2 v refin 2047 4096 : : 0000 0000 0001 2 v refin 1 4096 0000 0000 0000 0 v
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 15 post office box 655303 ? dallas, texas 75265 application information buffer amplifier the output buffer has a rail-to-rail output with short circuit protection and can drive a 2-k w load with a 100-pf load capacitance. settling time is a software selectable 12.5 m s or 2.5 m s, typical to within 0.5 lsb of final value. external reference the reference voltage input is buffered, which makes the dac input resistance not code dependent. therefore, the refin input resistance is 10 m w and the refin input capacitance is typically 5 pf, independent of input code. the reference voltage determines the dac full-scale output. logic interface the logic inputs function with cmos logic levels. most of the standard high-speed cmos logic families may be used. serial clock and update rate figure 1 shows the tlc5618 timing. the maximum serial clock rate is: f (sclk)max 1 t w ch min t w cl min 20 mhz the digital update rate is limited by the chip-select period, which is: t p(cs) 16 t w ch t w cl t su cs1 this equals an 810-ns or 1.23-mhz update rate. however, the dac settling time to 12 bits limits the update rate for full-scale input step transitions. serial interface when chip select (cs ) is low, the input data is read into a 16-bit shift register with the input data clocked in, most significant bit first. the falling edge of the sclk input shifts the data into the input register. the rising edge of cs then transfers the data to the dac register. when cs is high, input data cannot be clocked into the input register. the 16 bits of data can be transferred with the sequence shown in figure 19. d15 d14 d13 d12 d11 12 data bits d0 program bits data bits 16 bits msb (input word) msb (data) lsb (data, input word) figure 19. input data word format
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 16 post office box 655303 ? dallas, texas 75265 application information table 2 shows the function of program bits d15 d12. table 2. program bits d15 d12 function program bits device function d15 d14 d13 d12 device function 1 x x x write to latch a with serial interface register data and latch b updated with buffer latch data 0 x x 0 write to latch b and double buffer latch 0 x x 1 write to double buffer latch only x 0 x x 12.5 m s settling time x 1 x x 2.5 m s settling time x x 0 x powered-up operation x x 1 x power down mode function of the latch control bits (d15 and d12) three data transfers are possible. all transfers occur immediately after cs goes high and are described in the following sections. latch a write, latch b update (d15 = high, d12 = x) the serial interface register (sir) data are written to latch a and the double buffer latch contents are written to latch b. the double buffer contents are unaffected. this program bit condition allows simultaneous output updates of both dacs. serial interface register d12 = x d15 = high latch a latch b double buffer latch to dac a to dac b figure 20. latch a write, latch b update latch b and double-buffer 1 write (d15 = low, d12 = low) the sir data are written to both latch b and the double buffer. latch a is unaffected. serial interface register d12 = low d15 = low latch a latch b double buffer latch to dac a to dac b figure 21. latch b and double-buffer write
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 17 post office box 655303 ? dallas, texas 75265 application information double-buffer-only write (d15 = low, d12 = high) the sir data are written to the double buffer only. latch a and b contents are unaffected. serial interface register d12 = high d15 = low latch a latch b double buffer to dac a to dac b figure 22. double-buffer-only write purpose and use of the double buffer normally only one dac output can change after a write. the double buffer allows both dac outputs to change after a single write. this is achieved by the two following steps. 1. a double-buffer-only write is executed to store the new dac b data without changing the dac a and b outputs. 2. following the previous step, a write to latch a is executed. this writes the sir data to latch a and also writes the double-buffer contents to latch b. thus both dacs receive their new data at the same time, and so both dac outputs begin to change at the same time. unless a double-buffer-only write is issued, the latch b and double-buffer contents are identical. thus, following a write to latch a or b with another write to latch a does not change the latch b contents. operational examples changing the latch a data from zero to full code assuming that latch a starts at zero code (e.g., after power-up), the latch can be filled with 1s by writing (bit d15 on the left, d0 on the right) 1x0x 1111 1111 1111 to the serial interface. bit d14 can be zero to select slow mode or one to select fast mode. the other x can be zero or one (don't care). the latch b contents and the dac b output are not changed by this write unless the double-buffer contents are different from the latch b contents. this can only be true if the last write was a double-buffer-only write. changing the latch b data from zero to full code assuming that latch b starts at zero code (e.g., after power-up), the latch can be filled with 1s by writing (bit d15 on the left, d0 on the right). 0x00 1111 1111 1111 to the serial interface. bit d14 can be zero to select slow mode or one to select fast mode. the data (bits d0 to d11) are written to both the double buffer and latch b. the latch a contents and the dac a output are not changed by this write.
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 18 post office box 655303 ? dallas, texas 75265 application information double-buffered change of both dac outputs assuming that dacs a and b start at zero code (e.g., after power-up), if dac a is to be driven to mid-scale and dac b to full-scale, and if the outputs are to begin rising at the same time, this can be achieved as follows: first, 0d01 1111 1111 1111 is written (bit d15 on the left, d0 on the right) to the serial interface. this loads the full-scale code into the double buffer but does not change the latch b contents and the dac b output voltage. the latch a contents and the dac a output are also unaffected by this write operation. changing from fast to slow or slow to fast mode changes the supply current which can glitch the outputs, and so d14 (designated by d in the above data word) should be set to maintain the speed mode set by the previous write. next, 1x0x 1000 0000 0000 is written (bit d15 on the left, d0 on the right) to the serial interface. bit d14 can be zero to select slow mode or one to select fast mode. the other x can be zero or one (don't care). this writes the mid-scale code (100000000000) to latch a and also copies the full-scale code from the double buffer to latch b. both dac outputs thus begin to rise after the second write. dsp serial interface utilizing a simple 3-wire serial interface shown in figure 23, the tlc5618a can be interfaced to tms320 compatible serial ports. the 5618a has an internal state machine that will count 16 clocks after receiving a falling edge of cs and then disable further clocking in of data until the next falling edge is received on cs . therefore cs can be connected directly to the fs pins of the serial port and only the leading falling edge of the dsp will be used to start the write process. the tlc5618a is designed to be used with the tms320cxx dsp in burst mode serial port transmit operation.
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 19 post office box 655303 ? dallas, texas 75265 application information sclk din cs tlc5618a clkx dx fsx tms320c203 dsp v cc out a out b gnd refin 2.5 v dc fsr to source ground analog output analog output clkr figure 23. interfacing the tlc5618a to the tms320c203 dsp general serial interface both the tlc5618 and tlc5618a are compatible with spi, qspi, or microwire serial standards. the hardware connections are shown in figures 24 and 25. the tlc5618a has an internal state machine that will count 16 clocks after the falling edge of cs and then internally disable the device. the internal edge is ored together with cs so that the rising edge can be provided to cs prior to the occurrence of the internal edge to also disable the device. the spi and microwire interfaces transfer data in 8-bit bytes, therefore, two write cycles are required to input data to the dac. the qspi interface, which has a variable input data length from 8 to 16 bits, can load the dac input register in one write cycle. sclk din cs tlc5618, tlc5618a sk so i/o microwire port figure 24. microwire connection
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 20 post office box 655303 ? dallas, texas 75265 application information sclk din cs tlc5618, tlc5618a sck mosi i/o spi/qspi port cpol = 1, cpha = 0 figure 25. spi/qspi connection linearity, offset, and gain error using single end supplies when an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. with a positive offset, the output voltage changes on the first code change. with a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. the output amplifier attempts to drive the output to a negative voltage. however, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 v. the output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in figure 26. dac code output voltage 0 v negative offset figure 26. effect of negative offset (single supply) this offset error, not the linearity error, produces this breakpoint. the transfer function would have followed the dotted line if the output buffer could drive below the ground rail. for a dac, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. however, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. so the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. the code is calculated from the maximum specification for the negative offset.
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 21 post office box 655303 ? dallas, texas 75265 application information power-supply bypassing and ground management printed-circuit boards that use separate analog and digital ground planes offer the best system performance. wire-wrap boards do not perform well and should not be used. the two ground planes should be connected together at the low-impedance power-supply source. the best ground connection may be achieved by connecting the dac agnd terminal to the system analog ground plane making sure that analog ground currents are well-managed. a 0.1- m f ceramic bypass capacitor should be connected between v dd and agnd and mounted with short leads as close as possible to the device. use of ferrite beads may further isolate the system analog and digital power supplies. figure 27 shows the ground plane layout and bypassing technique. 0.1 m f analog ground plane 1 2 3 4 8 7 6 5 figure 27. power-supply bypassing saving power setting the dac register to all 0s minimizes power consumption by the reference resistor array and the output load when the system is not using the dac. ac considerations/analog feedthrough higher frequency analog input signals may couple to the output through internal stray capacitance. analog feedthrough is tested by holding cs high, setting the dac code to all 0s, sweeping the frequency applied to refin, and monitoring the dac output.
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 22 post office box 655303 ? dallas, texas 75265 mechanical data d (r-pdso-g**) plastic small-outline package 14 pin shown 4040047 / d 10/96 0.228 (5,80) 0.244 (6,20) 0.069 (1,75) max 0.010 (0,25) 0.004 (0,10) 1 14 0.014 (0,35) 0.020 (0,51) a 0.157 (4,00) 0.150 (3,81) 7 8 0.044 (1,12) 0.016 (0,40) seating plane 0.010 (0,25) pins ** 0.008 (0,20) nom a min a max dim gage plane 0.189 (4,80) (5,00) 0.197 8 (8,55) (8,75) 0.337 14 0.344 (9,80) 16 0.394 (10,00) 0.386 0.004 (0,10) m 0.010 (0,25) 0.050 (1,27) 0 8 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. falls within jedec ms-012
tlc5618, tlc5618a programmable dual 12-bit digital-to-analog converters slas156e july 1997 revised september 1999 23 post office box 655303 ? dallas, texas 75265 mechanical data fk (s-cqcc-n**) leadless ceramic chip carrier 4040140 / c 11/95 28 terminals shown b 0.358 (9,09) max (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) a no. of min max 0.358 0.660 0.761 0.458 0.342 (8,69) min (11,23) (16,26) 0.640 0.740 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32) (18,78) ** 20 28 52 44 68 84 0.020 (0,51) terminals 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 12 13 14 15 16 18 17 11 10 8 9 7 5 4 3 2 0.020 (0,51) 0.010 (0,25) 6 1 28 26 27 19 21 b sq a sq 22 23 24 25 20 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a metal lid. d. the terminals are gold-plated. e. falls within jedec ms-004
mechanical data mcer001a january 1995 revised january 1997 24 post office box 655303 ? dallas, texas 75265 mechanical data jg (r-gdip-t8) ceramic dual-in-line 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) seating plane 4040107/c 08/96 5 4 0.065 (1,65) 0.045 (1,14) 8 1 0.020 (0,51) min 0.400 (10,16) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) max 0.130 (3,30) min 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0 15 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a ceramic lid using glass frit. d. index point is provided on cap for terminal identification. e. falls within mil std 1835 gdip1-t8
mechanical data mcer001a january 1995 revised january 1997 25 post office box 655303 ? dallas, texas 75265 mechanical data p (r-pdip-t8) plastic dual-in-line package 4040082 / b 03/95 0.310 (7,87) 0.290 (7,37) 0.010 (0,25) nom 0.400 (10,60) 0.355 (9,02) 5 8 4 1 0.020 (0,51) min 0.070 (1,78) max 0.240 (6,10) 0.260 (6,60) 0.200 (5,08) max 0.125 (3,18) min 0.015 (0,38) 0.021 (0,53) seating plane m 0.010 (0,25) 0.100 (2,54) 0 15 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-001
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated

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