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32-bit risc microcontroller tx03 series TMPM376FDDFG / tmpm376fdfg semiconduct or & storage products company
revision history date rev description 2011/12/28 1.0 first release 2013/4/12 2.0 contents revised TMPM376FDDFG/fdfg *************************************************************************************************************** arm, arm powered, amba, adk, arm9tdmi, tdmi, primecell, realview, thumb, cortex, coresight, arm9, arm926ej-s, embedded trace macrocell, etm, ahb, apb, and keil are registered trademarks or trademarks of arm limited in the eu and other countries. **************************************************************************************************************** ? y TMPM376FDDFG/fdfg page 1-1 TMPM376FDDFG/fdfg 2013/4/12 TMPM376FDDFG/fdfg TMPM376FDDFG/fdfg is a 32-bit risc micr oprocessor series with an arm cortex ? -m3 microprocessor core. features of the TMPM376FDDFG/fdfg are as follows: 1.1 features 1. arm cortex-m3 microprocessor core a. improved code efficiency has been realized through the use of thumb ? -2 instruction. ? new 16-bit thumb instructions for improved program flow ? new 32-bit thumb instructions for improved performance ? new thumb mixed 16-/32-bit instruction set can produce faster, more efficient code. b. both high performance and low power consumption have been achieved. [high performance] ? 32-bit multiplication (32 32 = 32bit) can be executed with one clock. ? division takes between 2 and 12 cycles depending on dividend and devisor [low power consumption] ? optimized design using a low power consumption library ? standby function that stops the operation of the micro controller core c. high-speed interrupt response suitable for real-time control ? an interruptible long instruction. ? stack push automatically handled by hardware. 2. on chip program memory and data memory ? on-chip ram : 32kbyte ? on-chip flashrom : 512kbyte 3. 16-bit timer (tmrb) : 8 channels ? 16-bit interval timer mode ? 16-bit event counter mode ? input capture function ? external trigger ppg output 4. watchdog timer (wdt) : 1 channel product name rom (flash) ram package TMPM376FDDFG 512 kbyte 32 kbyte p-qfp100-1420-0.65q tmpm376fdfg 512 kbyte 32 kbyte p-lqfp100-1414-0.50h page 1-2 1.1 features TMPM376FDDFG/fdfg 2013/4/12 watchdog timer (wdt) generates a reset or a non-maskable interrupt (nmi). 5. power_on reset function (por) 6. voltage detect function (vltd) 7. oscillation frequency detect function (ofd) 8. vector engine (ve) : 1unit ? calculation circuit for motor control ? corresponding to 2 motors 9. programmable motor driver (pmd) : 2channels ? 3phase complementary pwm generator ? synchronous ad convert start trigger generator ? emergency protective function (emg ) 10. encoder input circuit (enc) : 2channels ? correspond to incremental encoder (ab / abz) ? rotation direction detection ? counter for absolute position detection ? comparator for position detection ? noise filter ? 3 phase sensor input 11. general-purpose serial interface(sio/uart) : 4channels either uart mode or synchronous mode can be selected (4byte fifo equipped) 12. serial bus interface (i2c/sio) : 1 channel either i2c bus mode or synchronous mode can be selected. 13. 12 bit ad converter (adc) : 2units ( analog input : 22channel ) ? start by the internal trigger : tmrb interrupt / pmd trigger ? constant conversion mode ? ad monitoring 2ch ? conversion speed 2 sec (@adc conversion clock = 40 mhz) 14. input/ output ports (port) : 82 pins i/o pin : 80 pins input pin : 2 pins 15. interrupt source ? internal 63 factors : the order of precedence can be set over 7 levels . (except the watc hdog timer inter- rupt) ? external 16 factors : the order of precedence can be set over 7 levels. page 1-3 TMPM376FDDFG/fdfg 2013/4/12 16. standby mode standby modes : idle, stop 17. clock generator (cg) ? on-chip pll (8 times) ? clock gear function : the high-speed clock can be divided into 1/1, 1/2, 1/4, 1/8 or 1/16. 18. endian little endian 19. internal high-speed oscillation circuit 20. maximum operating frequency : 80 mhz 21. operating voltage range 4.5 v to 5.5 v ( with on-chip regulator ) 22. temperature range ? ?40 c to 85 c (except during flash writing/ erasing) ?0 c to 70 c (during flash writing/ erasing) 23. package ? p-qfp100-1420-0.65q (14 mm 20 mm, 0.65 mm pitch) ? p-lqfp100-1414-0.50h (14 mm 14 mm, 0.5 mm pitch) page 1-4 1.2 block diagram TMPM376FDDFG/fdfg 2013/4/12 1.2 block diagram figure 1-1 TMPM376FDDFG/fdfg block diagram cortex-m3 cpu nvic debug ahb-bus-matrix (80mhz) i-code d-code system i/f nano flash i/f ram i/f boot rom regulator bus?bridge 3.3v 1.5v 5v io-bus (80mhz) ofd on_chip oscillator cg pll wdt tmrb port oscillator internal high-speed oscillator ve!arom ve enc adc pmd por / vltd sio / uart i2c / sio page 1-5 TMPM376FDDFG/fdfg 2013/4/12 1.3 pin layout (top view) the pin layout of TMPM376FDDFG/fdfg is a figure below. figure 1-2 pin layout (qfp100) 1 5 10 15 20 25 30 85 90 95 100 50 45 40 35 80 75 70 65 60 55 top view pn1/si/scl pn1/si/scl pn0/so/sda pn0/so/sda dvss pa0/tb0in/int3 pa1/tb0out pa2/tb1in/int4 pa3/tb1out pa4/sclk1/cts1 pa5/txd1/tb6out pa6/rxd1/tb6in pa7/tb4in/int8 pe0/txd0 pe1/rxd0 pe2/sclk0/cts0 pe3/tb4out dvdd5 pe4/tb2in/int5 pe5/tb2out pe6/tb3in/int6 pe7/tb3out/int7 dvss pl0/intb pl1/inta pc0/uo0 pc1/xo0 pc2/vo0 pc3/yo0 pc4/wo0 pc5/zo0 pc6/emg0 dvss pm0/x1 pm0/x1 pg7/ovv1 pg6/emg1 pg5/zo1 pg4/wo1 pg3/yo1 dvss dvdd5 pg2/vo1 pg1/xo1 pg0/uo1 pd6/rxd2 pd5/txd2 pd4/sclk2/cts2 pd3/int9 pd2/encz0 pd1/encb0/tb5out pd0/enca0/tb5in pc7/ovv0 pj2/ainb5 pj3/ainb6 pj4/ainb7 pj5/ainb8 pj6/intc/ainb9 pj7/intd/ainb10 pk0/inte/ainb11 pk1/intf/ainb12 pb7/trst pb6/tdi pb5/tdo/swv pb4/tck/swclk pb3/tms/swdio pb2/tracedata1 pb1/tracedata0 pb0/traceclk dvss dvdd5 vout3 reset rvdd5 mode dvss vout15 pf4/encz1/rxd3 pf3/encb1/txd3 pf2/enca1/sclk3 /cts3 pf1/tb7out pf0/tb7in/boot pm1/x2 pm1/x2 pj1/ainb4 pj0/ainb3 avssb/vreflb avdd5b/vrefhb pi3/aina11/ainb2 pi2/aina10/ainb1 pi1/aina9/ainb0 avssa/vrefla avdd5a/vrefha pi0/aina8 ph7/aina7 ph6/aina6 ph5/aina5 ph4/aina4 ph3/aina3 ph2/int2/aina2 ph1/int1/aina1 ph0/int0/aina0 pn3/tb7in pn3/tb7in pn2/sck pn2/sck TMPM376FDDFG pn2/sck pn3/tb7in pn1/si/scl pn0/so/sda pm0/x1 pm1/x2 page 1-6 1.3 pin layout (top view) TMPM376FDDFG/fdfg 2013/4/12 figure 1-3 pin layout (lqfp100) 1 5 10 15 20 25 80 85 90 95 100 50 45 40 35 30 75 70 65 60 55 top view dvss pa0/tb0in/int3 pa1/tb0out pa2/tb1in/int4 pa3/tb1out pa4/sclk1/cts1 pa5/txd1/tb6out pa6/rxd1/tb6in pa7/tb4in/int8 pe0/txd0 pe1/rxd0 pe2/sclk0/cts0 pe3/tb4out dvdd5 pe4/tb2in/int5 pe5/tb2out pe6/tb3in/int6 pe7/tb3out/int7 dvss pl0/intb pl1/inta pc0/uo0 pc1/xo0 pc2/vo0 pc3/yo0 pf0/tb7in/boot pm1/x2 pm1/x2 dvss pm0/x1 pm0/x1 pg7/ovv1 pg6/emg1 pg5/zo1 pg4/wo1 pg3/yo1 dvss dvdd5 pg2/vo1 pg1/xo1 pg0/uo1 pd6/rxd2 pd5/txd2 pd4/sclk2/cts2 pd3/int9 pd2/encz0 pd1/encb0/tb5out pd0/enca0/tb5in pc7/ovv0 pc6/emg0 pc5/zo0 pc4/wo0 pj5/ainb8 pj6/intc/ainb9 pj7/intd/ainb10 pk0/inte/ainb11 pk1/intf/ainb12 pb7/trst pb6/tdi pb5/tdo/swv pb4/tck/swclk pb3/tms/swdio pb2/tracedata1 pb1/tracedata0 pb0/traceclk dvss dvdd5 vout3 reset rvdd5 mode dvss vout15 pf4/encz1/rxd3 pf3/encb1/txd3 pf2/enca1/sclk3 /cts3 pf1/tb7out pj4/ainb7 pj3/ainb6 pj2/ainb5 pj1/ainb4 pj0/ainb3 avssb/vreflb avdd5b/vrefhb pi3/aina11/ainb2 pi2/aina10/ainb1 pi1/aina9/ainb0 avssa/vrefla avdd5a/vrefha pi0/aina8 ph7/aina7 ph6/aina6 ph5/aina5 ph4/aina4 ph3/aina3 ph2/int2/aina2 ph1/int1/aina1 ph0/int0/aina0 pn3/tb7in pn3/tb7in pn2/sck pn2/sck pn1/si/scl pn1/si/scl pn0/so/sda pn0/so/sda tmpm376fdfg pm1/x2 pn1/si/scl pn0/so/sda pn2/sck pn3/tb7in pm0/x1 page 1-7 TMPM376FDDFG/fdfg 2013/4/12 1.4 pin names and functions table 1-1 sorts the input and output pins of the tmpm3 76fddfg/fdfg by pin or port. each table includes alter- nate pin names and functions for multi-function pins. 1.4.1 sorted by port table 1-1 pin names and functions sorted by port (1/5) port type pin no. (dfg/ fg) pin name input / output function port a function 4 / 2 pa0 tb0in int3 i/o i i i/o port inputting the timer b capture trigger external interrupt pin port a function 5 / 3 pa1 tb0out i/o o i/o port timer b output port a function 6 / 4 pa2 tb1in int4 i/o i i i/o port inputting the timer b capture trigger external interrupt pin port a function 7 / 5 pa3 tb1out i/o o i/o port timer b output port a function 8 / 6 pa4 sclk1 cts1 i/o i/o i i/o port serial clock input/ output handshake input pin port a function 9 / 7 pa5 txd1 tb6out i/o o o i/o port sending serial data timer b output port a function 10 / 8 pa6 rxd1 tb6in i/o i i i/o port receiving serial data inputting the timer b capture trigger port a function 11 / 9 pa7 tb4in int8 i/o i i i/o port inputting the timer b capture trigger external interrupt pin port b function/ debug 65 / 63 pb0 traceclk i/o o i/o port debug pin port b function/ debug 66 / 64 pb1 tracedata0 i/o o i/o port debug pin port b function/ debug 67 / 65 pb2 tracedata1 i/o o i/o port debug pin port b function/ debug 68 / 66 pb3 tms/swdio i/o i/o i/o port debug pin port b function/ debug 69 / 67 pb4 tck/swclk i/o i i/o port debug pin port b function/ debug 70 / 68 pb5 tdo/swv i/o o i/o port debug pin port b function/ debug 71 / 69 pb6 tdi i/o i i/o port debug pin port b function/ debug 72 / 70 pb7 trst i/o i i/o port debug pin port c function 24 / 22 pc0 uo0 i/o o i/o port u-phase output pin page 1-8 1.4 pin names and functions TMPM376FDDFG/fdfg 2013/4/12 port c function 25 / 23 pc1 xo0 i/o o i/o port x-phase output pin port c function 26 / 24 pc2 vo0 i/o o i/o port v-phase output pin port c function 27 / 25 pc3 yo0 i/o o i/o port y -phase output pin port c function 28 / 26 pc4 wo0 i/o o i/o port w-phase output pin port c function 29 / 27 pc5 zo0 i/o o i/o port z-phase output pin port c function 30 / 28 pc6 emg0 i/o i i/o port emergency status detection input port c function 31 / 29 pc7 ovv0 i/o i i/o port overvoltage detection input port d function 32 / 30 pd0 enca0 tb5in i/o i i i/o port a-phase input pin inputting the timer b capture trigger port d function 33 / 31 pd1 encb0 tb5out i/o i o i/o port b-phase input pin timer b output port d function 34 / 32 pd2 encz0 i/o i i/o port z-phase input pin port d function 35 / 33 pd3 int9 i/o i i/o port external interrupt pin port d function 36 / 34 pd4 sclk2 cts2 i/o i/o i i/o port serial clock input/ output handshake input pin port d function 37 / 35 pd5 txd2 i/o o i/o port sending serial data port d function 38 / 36 pd6 rxd2 i/o i i/o port receiving serial data port e function 12 / 10 pe0 txd0 i/o o i/o port sending serial data port e function 13 / 11 pe1 rxd0 i/o i i/o port receiving serial data port e function 14 / 12 pe2 sclk0 cts0 i/o i/o i i/o port serial clock input/ output handshake input pin port e function 15 / 13 pe3 tb4out i/o o i/o port timer b output port e function 17 / 15 pe4 tb2in int5 i/o i i i/o port inputting the timer b capture trigger external interrupt pin port e function 18 / 16 pe5 tb2out i/o o i/o port timer b output port e function 19 / 17 pe6 tb3in int6 i/o i i i/o port inputting the timer b capture trigger external interrupt pin table 1-1 pin names and functions sorted by port (2/5) port type pin no. (dfg/ fg) pin name input / output function page 1-9 TMPM376FDDFG/fdfg 2013/4/12 porte function 20 / 18 pe7 tb3out int7 i/o o i i/o port timer b output external interrupt pin port f function/ control 52 / 50 pf0 tb7in boot i/o i i i/o port inputting the timer b capture trigger (note 3) boot mode pin. (note) this pin goes into single boot mode by sampling "low" at the rise of a reset signal. port f function 53 / 51 pf1 tb7out i/o o i/o port timer b output port f function 54 / 52 pf2 enca1 sclk3 cts3 i/o i i/o i i/o port encoder input serial clock input/ output handshake input pin port f function 55 / 53 pf3 encb1 txd3 i/o i o i/o port encoder input sending serial data port f function 56 / 54 pf4 encz1 rxd3 i/o i i i/o port encoder input receiving serial data port g function 39 / 37 pg0 uo1 i/o o i/o port u-phase output pin port g function 40 / 38 pg1 xo1 i/o o i/o port x-phase output pin port g function 41 / 39 pg2 vo1 i/o o i/o port v-phase output pin port g function 44 / 42 pg3 yo1 i/o o i/o port y-phase output pin port g function 45 / 43 pg4 wo1 i/o o i/o port w-phase output pin port g function 46 / 44 pg5 zo1 i/o o i/o port z-phase output pin port g function 47 / 45 pg6 emg1 i/o i i/o port emergency status detection input port g function 48 / 46 pg7 ovv1 i/o i i/o port overvoltage detection input port h function 98 / 96 ph0 int0 aina0 i/o i i i/o port external interrupt pin analog input port h function 97 / 95 ph1 int1 aina1 i/o i i i/o port external interrupt pin analog input port h function 96 / 94 ph2 int2 aina2 i/o i i i/o port external interrupt pin analog input port h function 95 / 93 ph3 aina3 i/o i i/o port analog input port h function 94 / 92 ph4 aina4 i/o i i/o port analog input table 1-1 pin names and functions sorted by port (3/5) port type pin no. (dfg/ fg) pin name input / output function page 1-10 1.4 pin names and functions TMPM376FDDFG/fdfg 2013/4/12 port h function 93 / 91 ph5 aina5 i/o i i/o port analog input port h function 92 / 90 ph6 aina6 i/o i i/o port analog input port h function 91 / 89 ph7 aina7 i/o i i/o port analog input port i function 90 / 88 pi0 aina8 i/o i i/o port analog input port i function 87 / 85 pi1 aina9/ainb0 i/o i i/o port analog input port i function 86 / 84 pi2 aina10/ainb1 i/o i i/o port analog input port i function 85 / 83 pi3 aina11/ainb2 i/o i i/o port analog input port j function 82 / 80 pj0 ainb3 i/o i i/o port analog input port j function 81 / 79 pj1 ainb4 i/o i i/o port analog input port j function 80 / 78 pj2 ainb5 i/o i i/o port analog input port j function 79 / 77 pj3 ainb6 i/o i i/o port analog input port j function 78 / 76 pj4 ainb7 i/o i i/o port analog input port j function 77 / 75 pj5 ainb8 i/o i i/o port analog input port j function 76 / 74 pj6 intc ainb9 i/o i i i/o port external interrupt pin analog input port j function 75 / 73 pj7 intd ainb10 i/o i i i/o port ex ternal interrupt pin analog input port k function 74 / 72 pk0 inte ainb11 i/o i i i/o port external interrupt pin analog input port k function 73 / 71 pk1 intf ainb12 i/o i i i/o port external interrupt pin analog input port l function 22 / 20 pl0 intb i i input port external interrupt pin port l function 23 / 21 pl1 inta i i input port external interrupt pin port m function / clock 49 / 47 pm0 x1 i/o i i/o port connected to a high-speed oscillator port m function / clock 51 / 49 pm1 x2 i/o o i/o port connected to a high-speed oscillator table 1-1 pin names and functions sorted by port (4/5) port type pin no. (dfg/ fg) pin name input / output function page 1-11 TMPM376FDDFG/fdfg 2013/4/12 note 1: avss must be connected to gnd even if the ad converter is not used. note 2: must be connected to power suppl y even if ad converter is not used. note 3: tb7in cannot be used simultaneously. port n function 2 / 100 pn0 so / sda i/o i/o i/o port if the serial bus interface operates -in the sio mode: data pin / -in the i2c mode: data pin port n function 1 / 99 pn1 si / scl i/o i/o i/o port if the serial bus interface operates -in the sio mode: data pin / -in the i2c mode: clock pin port n function 100 / 98 pn2 sck i/o i/o i/o port inputting and outputting a clock if the serial bus interface operates in the sio mode. port n function 99 / 97 pn3 tb7in i/o i i/o port inputting the timer b capture trigger (note3) - control 59 / 57 mode i mode pin (note) mode pin must be connected to gnd. - function 61 / 59 reset i reset input pin (note) with a pull-up and a noise filter (about 30ns (typical value)) -p s3 / 1d v s s ? gnd pin - ps 21 / 19 dvss ? gnd pin - ps 43 / 41 dvss ? gnd pin - ps 50 / 48 dvss ? gnd pin - ps 58 / 56 dvss ? gnd pin - ps 64 / 62 dvss ? gnd pin - ps 16 / 14 dvdd5 ? power supply pin - ps 42 / 40 dvdd5 ? power supply pin - ps 63 / 61 dvdd5 ? power supply pin - ps 60 / 58 rvdd5 ? power supply pin - ps 57 / 55 vout15 ? power supply pin - ps 62 / 60 vout3 ? power supply pin - ps 83 / 81 avssb vreflb ? ad converter: gnd pin (note 1) supplying the ad converter with a reference power supply. - ps 84 / 82 avdd5b vrefhb ? supplying the ad converter with a power supply. (note2) supplying the ad converter with a reference power supply. - ps 88 / 86 avssa vrefla ? ad converter: gnd pin (note 1) supplying the ad converter with a reference power supply. - ps 89 / 87 avdd5a vrefha ? supplying the ad converter with a power supply. (note2) supplying the ad converter with a reference power supply. table 1-1 pin names and functions sorted by port (5/5) port type pin no. (dfg/ fg) pin name input / output function page 1-12 1.5 pin numbers and power supply pins TMPM376FDDFG/fdfg 2013/4/12 1.5 pin numbers and power supply pins note: vout15 and vout3 must be connected with the same value of capacitors. table 1-2 pin numbers and power supplies power supply voltage range pin no. (dfg / fg) pin name dvdd5 4.5 to 5.5v 16 / 14 , 42 / 40 , 63 / 61 pa,pb,pc,pd,pe,pf,pg,pl,pm pn, reset ,mode avdd5a 89 / 87 ph, pi avdd5b 84 / 82 pj, pk rvdd5 60 / 58 ? vout15 1.35 to 1.65v 57 / 55 vout15 must be connected to dvss through 3.3 to 4.7 f capacitor for supply power to internal circuit. vout3 2.7 to 3.6v 62 / 60 vout3 must be connected to dvss through 3.3 to 4.7 f capacitor for supply power to internal circuit. page 2-1 TMPM376FDDFG/fdfg 2013/4/12 2. processor core the tx03 series has a high-performance 32-bit processor core (the arm cortex-m3 processor core). for infor- mation on the operations of this processor core, please re fer to the "cortex-m3 technical reference manual" issued by arm limited.this chapter describes the functions unique to the tx03 series that are not explained in that docu- ment. 2.1 information on the processor core the following table shows the revision of th e processor core in the TMPM376FDDFG/fdfg. refer to the detailed information about the cpu core an d architecture, refer to the arm manual "cortex-m series processors" in th e following url: http://infocenter.arm.com/help/index.jsp 2.2 configurable options the cortex-m3 core has optional blocks. the optional blocks of the revision r2p0 are etm ? and mpu. the fol- lowing tables shows the configurable options in the TMPM376FDDFG/fdfg. product name core revision TMPM376FDDFG/ fdfg r2p0 configurable options implementation fpb two literal comparators six instruction comparators dwt four comparators itm implementable mpu not implementable etm implementable ahb-ap implementable ahb trace macrocell interface implementable tpiu implementable wic not implementable page 2-2 2. processor core 2.3 exceptions/ interruptions TMPM376FDDFG/fdfg 2013/4/12 2.3 exceptions/ interruptions exceptions and interruptions are described in the following section. 2.3.1 number of interrupt inputs the number of interrupt inputs can optionally be defined from 1 to 240 in the cortex-m3 core. TMPM376FDDFG/fdfg has 79 interrupt inputs. the number of interrupt inputs is reflected in page 2-3 TMPM376FDDFG/fdfg 2013/4/12 2.4 events the cortex-m3 core has event output signals and event input signals. an event output signal is output by sev instruction execution. if an event is input, the core returns from low-power consumption mode caused by wfe instruction. TMPM376FDDFG/fdfg does not use event output signals and event input signals. please do not use sev instruction and wfe instruction. 2.5 power management the cortex-m3 core provides power management syst em which uses sleeping signal and sleepdeep signal. sleepdeep signals are output when page 2-4 2. processor core 2.6 exclusive access TMPM376FDDFG/fdfg 2013/4/12 page 3-1 mpm376fddfg/fdfg 2013/4/12 3. memory map 3.1 memory map the memory maps for mpm376fddfg/ fdfg are based on the arm cortex -m3 processor core memory map. the internal rom, internal ram and special function registers (sfr) of mpm376fddfg/fdfg are mapped to the code, sram and peripheral regions of the cortex-m3 resp ectively. the special functi on register (sfr) means the control registers of all input/output ports and peripheral functions. the sram and sfr areas are all included in the bit-band region. the cpu register area is the processo r core?s internal register region. for more information on each region, see th e "cortex-m3 technical reference manual". note that access to regions indicated as "fault" causes a memory fault if memo ry faults are enabled, or causes a hard fault if memory faults are disabled. also, do not access the ve ndor-specific region. 3.1.1 mpm376fddfg/fdfg memory map figure 3-1 shows the memory map of the mpm376fddfg/fdfg. figure 3-1 memory map sfr , q w h u q d o ram (32k) internal rom (512k) [ b [ ) ) b ) ) ) ) [ b ) ) ) [ b [ b ) ) ) ) [ b vendor-specific cpu register region fault fault fault [ ( b [ ( ) b ) ) ) ) [ ( b [ ) ) ) ) b ) ) ) ) page 3-2 3. memory map 3.2 details of sfr area mpm376fddfg/fdfg 2013/4/12 3.2 details of sfr area table 3-1 shows the de tails of the sfr area. do not access a reserved area in table 3-1. see the chaper of each peripheral function for datails. table 3-1 details of sfr start address end address peripheral 0x4000_0000 0x4000_037f port 0x4000_0380 0x4000_ffff reserved 0x4001_0000 0x4001_01ff tmrb 0x4001_0200 0x4001_03ff reserved 0x4001_0400 0x4001_053f enc 0x4001_0540 0x4001_ffff reserved 0x4002_0000 0x4002_007f i2c/sio 0x4002_0080 0x4002_017f sio/uart 0x4002_0180 0x4002_ffff reserved 0x4003_0000 0x4003_02ff adc 0x4003_0300 0x4003_ffff reserved 0x4004_0000 0x4004_003f wdt 0x4004_0040 0x4004_01ff reserved 0x4004_0200 0x4004_023f cg 0x4004_0240 0x4004_07ff reserved 0x4004_0800 0x4004_083f ofd 0x4004_0840 0x4004_08ff reserved 0x4004_0900 0x4004_093f vltd 0x4004_0940 0x4004_ffff reserved 0x4005_0000 0x4005_023f ve 0x4005_0240 0x4005_03ff reserved 0x4005_0400 0x4005_04ff pmd 0x4005_0500 0x4007_ffff reserved 0x4008_0000 0x41ff_efff hard fault 0x41ff_f000 0x41ff_f03f flash 0x41ff_f040 0x41ff_ffff reserved page 4-1 TMPM376FDDFG/fdfg 2013/4/12 4. reset operation 4.1 initial state the internal circuits, register settings and pin status are undefined right after the power-on. the state continues until the reset pin receives "low" level signal after all the power supply voltage is applied. 4.2 reset operation TMPM376FDDFG/fdfg has power-on reset circuit, power- on reset signal is generated when power supply is turned on. when reset from external reset pin, input reset signal to reset pin at "low" level for minimum dura- tion of 1.2 sec while power supply voltage is in the operating range. 4.3 after reset when the reset is released, the system control register and the internal i/o register of the cortex-m3 processor core are initialized. note that the pll multiplication circ uit stops after releasing the reset. therefore, set cgosccr register and cgpllsel register to use pll multiplication circuit. after the reset exception handling is executed, the progra m branches off to the interrupt service routine. the address with which the interrupt service routine starts is stored in 0x0000_0004. note 1: it is possible to turn power on after reset pin is set to "low". note 2: the reset operation may alter the internal ram state. page 4-2 4. reset operation 4.3 after reset TMPM376FDDFG/fdfg 2013/4/12 page 5-1 TMPM376FDDFG/fdfg 2013/4/12 5. clock / mode control 5.1 features the clock/mode control block enables to select clock gear, prescaler clock and warm-up of the pll clock multipli- cation circuit and oscillator. there is also the low power consumption mode which can reduce power consumption by mode transitions. this chapter describes how to control clock operating modes and mode transitions. the clock/mode control block has the following functions: ? controls the system clock ? controls the prescaler clock ? controls the pll multiplication circuit ? controls the warm-up timer in addition to normal mode, the TMPM376FDDFG/fdfg can operate in six types of low power mode to reduce power consumption accord ing to its usage conditions. page 5-2 5. clock / mode control 5.2 registers TMPM376FDDFG/fdfg 2013/4/12 5.2 registers 5.2.1 register list the following table shows the cg-r elated register s and addresses. base address = 0x4004_0200 register name address (base+) system control register cgsyscr 0x0000 oscillation control register cgosccr 0x0004 standby control register cgstbycr 0x0008 pll selection register cgpllsel 0x000c page 5-3 TMPM376FDDFG/fdfg 2013/4/12 5.2.2 cgsyscr (system control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000001 15 14 13 12 11 10 9 8 bit symbol - - - fpsel - prck after reset00000000 7 6 5 4 3 2 1 0 bit symbol----- gear after reset00000000 bit bit symbol type function 31-18 ? r read as "0". 17-16 ? r/w write as "01". 15-13 ? r read as "0". 12 fpsel r/w selects fperiph source clock 0: fgear 1: fc 11 ? r read as "0". 10- 8 prck[2:0] r/w prescaler clock 000: fperiph 001: fperiph/2 010: fperiph/4 011: fperiph/8 100: fperiph/16 101: fperiph/32 110: reserved 111: reserved specifies the prescaler clock to peripheral i/o. 7-3 ? r read as "0". 2-0 gear[2:0] r/w high-speed clock (fc) gear 000: fc 001: reserved 010: reserved 011: reserved 100: fc/2 101: fc/4 110: fc/8 111: fc/16 page 5-4 5. clock / mode control 5.2 registers TMPM376FDDFG/fdfg 2013/4/12 5.2.3 cgosccr (oscilla tion control register) 31 30 29 28 27 26 25 24 bit symbol wuodr after reset10000000 23 22 21 20 19 18 17 16 bit symbol wuodr wupsel2 hoscon oscsel xen2 after reset00000001 15 14 13 12 11 10 9 8 bit symbol-------xen1 after reset00000000 7 6 5 4 3 2 1 0 bit symbol----wupsel1pllonwuefwueon after reset00000000 page 5-5 TMPM376FDDFG/fdfg 2013/4/12 note 1: when the page 5-6 5. clock / mode control 5.2 registers TMPM376FDDFG/fdfg 2013/4/12 5.2.4 cgstbycr (standby control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------drve after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------rxen after reset00000001 7 6 5 4 3 2 1 0 bit symbol----- stby after reset00000011 bit bit symbol type function 31-18 ? r read as "0". 17 ? r/w write as "0". 16 drve r/w pin status in stop mode 0: inactive 1: active 15-10 ? r read as "0". 9 ? r/w write as "0". 8 rxen r/w high-speed oscillator operation after releasing the stop mode. write as "1". 7-3 ? r read as "0". 2-0 stby[2:0] r/w low power consumption mode 000: reserved 001: stop 010: reserved 011: idle 100: reserved 101: reserved 110: reserved 111: reserved to enter the stop mode, disable the oscillation (osc1 or osc2) which is unused as system clock. page 5-7 TMPM376FDDFG/fdfg 2013/4/12 5.2.5 cgpllsel (pll selection register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset10100001 7 6 5 4 3 2 1 0 bit symbol-------pllsel after reset00111110 bit bit symbol type function 31-16 ? r read as "0". 15-12 ? r/w write as "1010". 11 ? r read as "0". 10-1 ? r/w write as "00_1001_1111". 0 pllsel r/w use of pll 0: fosc use 1: pll use specifies use or disuse of the clock multiplied by the pll. "fosc" is automatically set after reset. resetting is required when using the pll. page 5-8 5. clock / mode control 5.3 clock control TMPM376FDDFG/fdfg 2013/4/12 5.3 clock control 5.3.1 clock type each clock is defined as follows : the high-speed clock fc and the prescaler clock t0 are dividable as follows. 5.3.2 initial values after reset reset operation initializes the clock configuration as follows. reset operation causes all the clock co nfigurations to be the same as f osc2 . fosc1 : clock input from external high-speed oscillator (x1 and x2) fosc2 : clock input from internal high-speed oscillator fosc : high-speed clock specified by cgosccr page 5-9 TMPM376FDDFG/fdfg 2013/4/12 5.3.3 clock system diagram figure 5-1 shows the clock system diagram. figure 5-1 clock block diagram the input clocks selector shown with an arrow are set as default after reset. warm-up timer cgosccr page 5-10 5. clock / mode control 5.3 clock control TMPM376FDDFG/fdfg 2013/4/12 5.3.4 clock multiplication circuit (pll) this circuit outputs the f pll clock that is octuple of the high-speed oscillator output clock (fosc.) as a result, the input frequency to oscillator can be low, and the internal clock be made high-speed. the pll is disabled after reset. to enable the pll, set "1" to the cgosccr page 5-11 TMPM376FDDFG/fdfg 2013/4/12 5.3.5 warm-up function the warm-up function secures the stability time for the oscillator and the pll with the warm-up timer. the warm-up function is used when returning from stop mo de. for detail function, describes in "5.6.6 warm-up". note:do not shift to stop mode, during operating warm-up timer. in this case, an interrupt for returning from the lo w power consumption mode triggers the automatic timer count. after the specified time is reached, the syst em clock is output and the cpu starts operation. in stop modes, the pll is disabled. when returning from these modes, configur e the warm-up time in con- sideration of the stability time of the pll and the internal oscillator. how to configure the warm-up function. 1. specify the count up clock specify the count up clock for the warm -up counter in the cgosccr page 5-12 5. clock / mode control 5.3 clock control TMPM376FDDFG/fdfg 2013/4/12 the following shows the warm-up setting. page 5-13 TMPM376FDDFG/fdfg 2013/4/12 5.3.6 system clock the TMPM376FDDFG/fdfg offers high-speed clock as sy stem clock. system clock is selectable from internal oscillator or external oscillator. after reset, inte rnal oscillator is enabled and external oscillator is dis- abled. the high-speed clock is dividable. ? input frequency from x1 and x2 : 8 mhz to 10mhz ? internal oscillator frequency : 10mhz ? clock gear : 1/1, 1/2, 1/4, 1/8, 1/16 (after reset : 1/1) note 1: pll=on/off setting: available in cgosccr page 5-14 5. clock / mode control 5.3 clock control TMPM376FDDFG/fdfg 2013/4/12 5.3.7 prescaler clock control each peripheral function has a prescaler for dividing a clock. as the clock t0 to be input to each prescaler, the "fperiph" clock specified in the cgsyscr page 5-15 TMPM376FDDFG/fdfg 2013/4/12 5.4 modes and mode transitions 5.4.1 mode transitions the normal mode use the high-speed clock for the system clock . the idle and stop modes can be used as the low power consumption mode that enables to reduce power consumption by halting processor core operation. figure 5-3 shows mode transition diagram. for a detail of sleep-on-exit, refer to "cortex-m3 technical reference manual". figure 5-3 mode transition diagram note:the warm-up is needed. the warm-up time must be set in normal mode before changing to stop mode. regarding warm-up time, refer to "5.6.6 warm-up". reset has been performed. interrupt (note) normal mode reset idle mode (stops cpu) (selectable io operation) stop mode (halts all circuit) instruction/ sleep on exit instruction/ sleep on exit interrupt (note) page 5-16 5. clock / mode control 5.5 operation mode TMPM376FDDFG/fdfg 2013/4/12 5.5 operation mode as an operation mode, normal is av ailable. the features of normal mode are described in the following sec- tion. 5.5.1 normal mode this mode is to operate the cpu core and the pe ripheral hardware by using the high-speed clock. it is shifted to the normal mode after reset. page 5-17 TMPM376FDDFG/fdfg 2013/4/12 5.6 low power consumption modes the TMPM376FDDFG/fdfg has two low power consumption modes: idle and stop. to shift to the low power consumption mode, specify the mode in the system control register cgstbycr page 5-18 5. clock / mode control 5.6 low power consumption modes TMPM376FDDFG/fdfg 2013/4/12 5.6.2 stop mode all the internal circuits including the internal os cillator are brought to a stop in the stop mode. by releasing the stop mode, the de vice returns to the preceding mode of the stop mode and starts opera- tion. the stop mode enables to select the pin status by setting the cgstbycr page 5-19 TMPM376FDDFG/fdfg 2013/4/12 5.6.3 low power cons umption mode setting the low power consumption mode is specified by the setting of the standby control register cgst- bycr page 5-20 5. clock / mode control 5.6 low power consumption modes TMPM376FDDFG/fdfg 2013/4/12 5.6.4 operational status in each mode table 5-4 shows the operational status in each mode. for i/o port, " " and " " indicate that input/output is enabled and disabled respectively. for other functions, " " and " " indicate that clock is supplied and is not supplied respectively. note 1: it depends on cgstbycr page 5-21 TMPM376FDDFG/fdfg 2013/4/12 note 1: to release the low power consumption mode by usi ng the level mode interrupt, keep the level until the inter- rupt handling is started. changing the level before then will prevent the interrupt handling from starting properly. note 2: for shifting to the low power consumption mode, set the cpu to prohibit all the interrupts other than the release source. if not, releasing may be executed by an unspecified for wake up. note 3: refer to "5.6.6 warm-up" about warm-up time. ? release by interrupt request to release the low power consumption mode by an interrupt, the cpu must be set in advance to detect the interrupt. in addition to the setting in the cpu, the clock generator must be set to detect the interrupt to be used to release the stop modes. ? release by non-maskab le interrupt (nmi) there is a watchdog timer interr upt (intwdt) as a non-maskabl e interrupt source. intwdt can only be used in the idle mode. ? release by reset any low power consumption mode can be released by reset from the reset pin. after that, the mode switches to the normal mode and all the regi sters are initialized as is the case with normal reset. table 5-5 release source in each mode low power consumption mode idle (programable) stop int0 to f (note1) ? intrx0 to 3, inttx0 to 3 ? intvcna, intvcnb ? intemg0 to 1 ? intovv0 to 1 ? intadapda, intadbpda, intadapdb, intadbpdb ? release source interrupt inttb00, 10, 20, 30, 40, 50, 60, 70 inttb01, 11, 21, 31, 41, 51, 61, 71 ? intpmd0, 1 ? intcap00, 10, 20, 30, 40, 50, 60, 70 intcap01, 11, 21, 31, 41, 51, 61, 71 ? intadacpa, intadbcpa, intadacpb, intadbcpb ? intadasft, intadbsft ? intadatmr, intadbtmr ? intenc0, intenc1 ? intsbi ? systick ? nmi (intwdt) ? reset ( reset pin) ? : : starts the interrupt handling after the mode is released. (the reset initializes the lsi) unavailable page 5-22 5. clock / mode control 5.6 low power consumption modes TMPM376FDDFG/fdfg 2013/4/12 ? release by systick interrupt systick interrupt can only be used in idle mode. refer to "interrupts" for detail. page 5-23 TMPM376FDDFG/fdfg 2013/4/12 5.6.6 warm-up mode transition may require the warm-up so that the internal oscillator prov ides stable oscillation. in the mode transition from stop to the normal, the warm-up counter is activated automatically. and then the system clock output is starte d after the elapse of configured warm -up time. it is necessary to set a oscillator to be used for warm-up in the cgos ccr page 5-24 5. clock / mode control 5.6 low power consumption modes TMPM376FDDFG/fdfg 2013/4/12 5.6.7 clock operation in mode transition the clock operation in mode transition are described chapter 5.6.7.1 . 5.6.7.1 transition of operation modes : normal stop normal when returning to the normal mode from the stop mode, the warm-up is activated automatically. it is necessary to set the warm-up time before entering the stop mode. returning to the normal mode by reset does not induce the automatic warm-up. keep the reset sig- nal asserted until the oscillat or operation becomes stable. fsys (system clock) stop fosc normal normal mode warm-up system clock stops high-speed clock starts oscillating warm-up starts wfi execute/ sleep on exit release event occurs warm-up completes. system clock starts. page 6-1 TMPM376FDDFG/fdfg 2013/4/12 6. exceptions this chapter describes features, types and handling of exceptions. exceptions have close relation to the cpu core. refer to "cortex-m3 tec hnical reference manual" if needed. 6.1 overview exceptions have close relation to the cpu core. refer to "cortex-m3 tec hnical reference manual" if needed. there are two types of exceptions: those that are generate d when some error condition occurs or when an instruc- tion to generate an exception is executed; and those that ar e generated by hardware, such as an interrupt request sig- nal from an external pin or peripheral function. all exceptions are handled by the nested vectored inte rrupt controller (nvic) in the cpu according to the respective priority levels. when an excep tion occurs, the cpu stores the current state to the stack and branches to the corresponding interrupt service routine (isr). upon completi on of the isr, the information stored to the stack is automatically restored. 6.1.1 exception types the following types of exceptions exist in the cortex-m3. for detailed descriptions on each exception, refer to "cortex- m3 technical reference manual". ? reset ? non-maskable interrupt (nmi) ? hard fault ? memory management ? bus fault ? usage fault ? svcall (supervisor call) ? debug monitor ? pendsv ?systick ? external interrupt page 6-2 6. exceptions 6.1 overview TMPM376FDDFG/fdfg 2013/4/12 6.1.2 handling flowchart each step is described later in this chapter. the following shows how an exception/interrupt is handled. in the following descriptions, indicates hardware handling. indicates software handling. processing description see detection by cg/cpu the cg/cpu detects the exception request. section 6.1.2.1 handling by cpu the cpu handles the exception request. section 6.1.2.2 branch to isr the cpu branches to the corresponding interrupt service routine (isr). execution of isr necessary proce ssing is executed. section 6.1.2.4 return from exception the cpu branches to another isr or returns to the previous program. section 6.1.2.4 page 6-3 TMPM376FDDFG/fdfg 2013/4/12 6.1.2.1 exception request and detection (1) exception occurrence exception sources include instruction execution by the cpu, memory accesses, and interrupt requests from external interrupt pins or peripheral functions. an exception occurs when the cpu executes an in struction that causes an exception or when an error condition occurs dur ing instruction execution. an exception also occurs by an in struction fetch from the execute never (xn) region or an access violation to the fault region. an interrupt request is generated from an extern al interrupt pin or peripheral function.for inter- rupts that are used for releasing a standby mode, rele vant settings must be made in the clock genera- tor. for details, refer to "6.5 interrupts". (2) exception detection if multiple exceptions occur simultaneously, the cpu takes the exception with the highest priority. table 6-1 shows the priority of exceptions. "conf igurable" means that you can assign a priority level to that exception. memory management, bus fault and usage fault exceptions can be enabled or disabled. if a disabled exception occurs, it is handled as hard fault. note 1: this product does not contain the mpu. note 2: external interrupts have different sources and numbers in each product. for details, see"6.5.1.5 list of interrupt sources". table 6-1 exception types and priority no. exception type priority description 1 reset ? 3 (highest) reset pin, wdt, por, vltd, ofd or sysretreq 2 non-maskable interrupt ? 2 w d t 3 hard fault ? 1 fault that cannot activate because a higher-priority fault is being han- dled or it is disabled 4 memory management configurable exception from the memory pr otection unit (mpu) (note 1) instruction fetch from the execute never (xn) region 5 bus fault configurable access violation to the hard fault region of the memory map 6 usage fault configurable undefined instruction execution or other faults related to instruction execution 7~10 reserved ? 11 svcall configurable system service call with svc instruction 12 debug monitor configurable debug monitor when the cpu is not faulting 13 reserved ? 14 pendsv configurable pendable system service request 15 systick configurable notification from system timer 16~ external interrupt configurable external in terrupt pin or peripheral function (note2) page 6-4 6. exceptions 6.1 overview TMPM376FDDFG/fdfg 2013/4/12 (3) priority setting ? priority level the external interrupt priority is set to the interrupt priority register and other exceptions are set to page 6-5 TMPM376FDDFG/fdfg 2013/4/12 6.1.2.2 exception handling and branch to the interrupt service routine (pre-emption) when an exception occurs, the cpu suspends the currently executing pr ocess and branches to the inter- rupt service routine. this is called "pre-emption". (1) stacking when the cpu detects an exception, it pushes the contents of the followin g eight registers to the stack in the following order : ? program counter (pc) ? program status register (xpsr) ?r0 to r3 ?r12 ? link register (lr) the sp is decremented by eight words by the completion of the stack push.the following shows the state of the stack after the regi ster contents have been pushed. (2) fetching an isr the cpu enables instruction to fetch the interrupt processing with data store to the register. prepare a vector table containing the top addresses of isrs for each exception.after reset, the vec- tor table is located at address 0x0000_0000 in the code area.by setting the vector table offset reg- ister, you can place the vector table at any address in the code or sram space. the vector table should also contain the initial value of the main stack. (3) late-arriving if the cpu detects a higher pr iority exception before executing the isr for a previous exception, the cpu handles the higher pr iority exception first. this is called "late-arriving". a late-arriving exception causes the cpu to fetch a new vector address for branching to the corre- sponding isr, but the cpu does not newly push the register contents to the stack. old sp page 6-6 6. exceptions 6.1 overview TMPM376FDDFG/fdfg 2013/4/12 (4) vector table the vector table is configured as shown below. you must always set the first four words (stack top address, reset isr a ddress, nmi isr address, and hard fault isr address). set isr addr esses for other exceptions if necessary. 6.1.2.3 executing an isr an isr performs necessary processing for the corresponding exception. isrs must be prepared by the user. an isr may need to include code fo r clearing the interrupt request so that the same interrupt will not occur again upon return to normal program execution. for details about interrupt handling, see "6.5 interrupts". if a higher priority exception o ccurs during isr executio n for the current excep tion, the cpu abandons the currently executing isr and serv ices the newly detected exception. offset exception contents setting 0x00 reset initial value of the main stack required 0x04 reset isr address required 0x08 non-maskable interrupt isr address required 0x0c hard fault isr address required 0x10 memory management isr address optional 0x14 bus fault isr address optional 0x18 usage fault isr address optional 0x1c to 0x28 reserved 0x2c svcall isr address optional 0x30 debug monitor isr address optional 0x34 reserved 0x38 pendsv isr address optional 0x3c systick isr address optional 0x40 external interrupt isr address optional page 6-7 TMPM376FDDFG/fdfg 2013/4/12 6.1.2.4 exception exit (1) execution after re turning from an isr when returning from an isr, the cpu takes one of the following actions : ? tail-chaining if a pending exception exists an d there are no stacked excepti ons or the pending exception has higher priority than all stacked exceptions, the cpu returns to the isr of the pending exception. in this case, the cpu skips the pop of eight re gisters and push of ei ght registers when exit- ing one isr and entering another. this is called "tail-chaining". ? returning to the last stacked isr if there are no pending excepti ons or if the highest priority stacked exception is of higher priority than the highest priority pending excep tion, the cpu returns to the last stacked isr. ? returning to the previous program if there are no pending or st acked exceptions, the cpu retu rns to the previous program. (2) exception exit sequence when returning from an isr, the cpu performs the following operations : ? pop eight registers pops the eight registers (pc, xpsr, r0 to r3, r12 and lr) from the stack and adjust the sp. ? load current active interrupt number loads the current active interrupt number fr om the stacked xpsr. the cpu uses this to track which interrupt to return to. ? select sp if returning to an exception (handler mode), sp is sp_main. if returning to thread mode, sp can be sp_main or sp_process. page 6-8 6. exceptions 6.2 reset exceptions TMPM376FDDFG/fdfg 2013/4/12 6.2 reset exceptions reset exceptions are generated from the following six sources. use the reset flag (cgrstflg) register of the clock generator to identify the source of a reset. ? external reset pin a reset exception occurs when an external reset pin changes from "low" to "high". ? reset exception by por please refer the chapter "por power on reset circuit" for detail. ? reset exception by vltd please refer the chapter "vltd voltage detection circuit" for detail. ? reset exception by ofd please refer the chapter "ofd oscilla tion frequency detector" for detail. ? reset exception by wdt the watchdog timer (wdt) has a reset generating feature. for details, see the chapter on the wdt. ? reset exception by sysresetreq a reset can be generated by setting the sysresetreq bit in the nvic's application interrupt and reset control register. 6.3 non-maskable interrupts (nmi) the watchdog timer (wdt) has a non-maskable interrupt ge nerating feature. for details, see the chapter on the wdt. use the nmi flag (cgnmiflg) register of the clock generator to identify the source of a non-maskable inter- rupt. 6.4 systick systick provides interrupt features using the cpu's system timer. when you set a value in the systick reload value register and enable the systick features in the systick control and status register, the counter loads with the value set in the reload value register and begins counting down.when the counter reaches "0", a systick exception occurs.you may be pending exceptions and use a flag to know when the timer reaches "0". the systick calibration value register holds a reload value for counting 10 ms with the system timer. the count clock frequency varies with each product, and so the value set in the sy stick calibration value register also varies with each product. note: in this product, fosc which is selected by cgosccr page 6-9 TMPM376FDDFG/fdfg 2013/4/12 6.5 interrupts this chapter describes routes, sources and required settings of interrupts. the cpu is notified of interrupt requests by th e interrupt signal from each interrupt source. it sets priority on interrupts and handles an interrupt request with the highest priority. interrupt requests for clearing a standby mode are notified to the cpu via the clock generator. therefore, appropri- ate settings must be made in the clock generator. 6.5.1 interrupt sources 6.5.1.1 interrupt route figure 6-1 shows an interrupt request route. the interrupts issued by the peripheral function that is not used to release standby are directly input to the cpu (route1). the peripheral function interrupts used to release standby (route 2) and interrupts from the external interrupt pin (route 3) are input to the clock generator and are input to the cpu through the logic for releasing standby (route 4 and 5). if interrupts from the external interrupt pins are not us ed to release standby, they are directly input to the cpu, not through the logic for standby release (route 6). figure 6-1 interrupt route 6.5.1.2 generation an interrupt request is generated from an external pin or peripheral function assigned as an interrupt source or by setting the nvic's interrupt set-pending register. peripheral function cpu exiting standby mode clock generator peripheral function interrupt request q external interrupt pin page 6-10 6. exceptions 6.5 interrupts TMPM376FDDFG/fdfg 2013/4/12 ? from external pin set the port control register so that the external pin can perform as an interrupt function pin. ? from peripheral function set the peripheral function to make it possible to output interrupt requests. see the chapter of each peri pheral function for details. ? by setting interrupt set-pending register (forced pending) an interrupt request can be generated by setting the relevant bit of the interrupt set-pending register. 6.5.1.3 transmission an interrupt signal from an external pin or peripheral function is directly sent to the cpu unless it is used to exit a standby mode. interrupt requests from interrupt sources that can be used for clearing a standb y mode are transmitted to the cpu via the clock generator. for these interrupt sources, appropriate settings must be made in the clock generator in advance. external interrupt sources not used for exiting a standby mode can be used without setting the clock generator. 6.5.1.4 precautions when using external interrupt pins if you use external interrupts, be aware the followings not to generate unexpected interrupts. if input disabled (pxie page 6-11 TMPM376FDDFG/fdfg 2013/4/12 6.5.1.5 list of interrupt sources table 6-3 shows the list of interrupt sources. table 6-3 list of interrupt sources no. interrupt source active level (clearing standby) cg interrupt mode control register 0 int0 interrupt pin high/low edge/level selectable cgimcga 1 int1 interrupt pin 2 int2 interrupt pin 3 int3 interrupt pin 4 int4 interrupt pin high/low edge/level selectable cgimcgb 5 int5 interrupt pin 6 intrx0 serial reception (channel0) 7 inttx0 serial transmit (channel0) 8 intrx1 serial reception (channel1) 9 inttx1 serial transmit (channel1) 10 intvcna vector engine interrupt a 11 intvcnb vector engine interrupt b 12 intemg0 pmd0 emg interrupt 13 intemg1 pmd1 emg interrupt 14 intovv0 pmd0 ovv interrupt 15 intovv1 pmd1 ovv interrupt 16 intadapda adca conversion tr iggered by pmd0 is finished 17 intadbpda adcb conversion tr iggered by pmd0 is finished 18 intadapdb adca conversion tr iggered by pmd1 is finished 19 intadbpdb adcb conversion tr iggered by pmd1 is finished 20 inttb00 16bit tmrb0 compare match detection 0/ over flow 21 inttb01 16bit tmrb0 compare match detection 1 22 inttb10 16bit tmrb1 compare match detection 0/ over flow 23 inttb11 16bit tmrb1 compare match detection 1 24 inttb40 16bit tmrb4 compare match detection 0/ over flow 25 inttb41 16bit tmrb4 compare match detection 1 26 inttb50 16bit tmrb5 compare match detection 0/ over flow 27 inttb51 16bit tmrb5 compare match detection 1 28 intpmd0 pmd0 pwm interrupt 29 intpmd1 pmd1 pwm interrupt 30 intcap00 16bit tmrb0 input capture 0 31 intcap01 16bit tmrb0 input capture 1 32 intcap10 16bit tmrb1 input capture 0 33 intcap11 16bit tmrb1 input capture 1 34 intcap40 16bit tmrb4 input capture 0 35 intcap41 16bit tmrb4 input capture 1 36 intcap50 16bit tmrb5 input capture 0 page 6-12 6. exceptions 6.5 interrupts TMPM376FDDFG/fdfg 2013/4/12 37 intcap51 16bit tmrb5 input capture 1 38 int6 interrupt pin high/low edge/level selectable cgimcgb 39 int7 interrupt pin 40 intrx2 serial reception (channel2) 41 inttx2 serial transmit (channel2) 42 intadacpa adca conversion monitoring function interrupt a 43 intadbcpa adcb conversion monitoring function interrupt a 44 intadacpb adca conversion monitoring function interrupt b 45 intadbcpb adcb conversion monitoring function interrupt b 46 inttb20 16bit tmrb2 compare match detection 0/ over flow 47 inttb21 16bit tmrb2 compare match detection 1 48 inttb30 16bit tmrb3 compare match detection 0/ over flow 49 inttb31 16bit tmrb3 compare match detection 1 50 intcap20 16bit tmrb2 input capture 0 51 intcap21 16bit tmrb2 input capture 1 52 intcap30 16bit tmrb3 input capture 0 53 intcap31 16bit tmrb3 input capture 1 54 intadasft adc unit a conversion started by software is fin- ished 55 intadbsft adc unit b conversion started by software is fin- ished 56 intadatmr adc unit a conversion triggered by timer is finished 57 intadbtmr adc unit b conversion triggered by timer is finished table 6-3 list of interrupt sources no. interrupt source active level (clearing standby) cg interrupt mode control register page 6-13 TMPM376FDDFG/fdfg 2013/4/12 6.5.1.6 active level the active level indicates which change in signal of an interrupt source trigge rs an interrupt. the cpu recognizes interrupt signals in "high" level as inte rrupt. interrupt signals directly sent from peripheral functions to the cpu are configured to output "high" to indicate an interrupt request. active level is set to the clock generator for interr upts which can be a trigger to release standby. inter- rupt requests from peripheral functio ns are set as rising-edge or fallin g-edge triggered. interrupt requests from interrupt pins can be set as level-sensitive ("hi gh" or "low") or edge-triggered (rising or falling). if an interrupt source is used for clearing a standby mode, setting the relevant clock generator register is also required. enable the cg imcgx page 6-14 6. exceptions 6.5 interrupts TMPM376FDDFG/fdfg 2013/4/12 6.5.2 interrupt handling 6.5.2.1 flowchart the following shows how an interrupt is handled. the following shows how an exception/interrupt is handled. in the following descriptions, indicates hardware handling. indicates software handling. page 6-15 TMPM376FDDFG/fdfg 2013/4/12 processing details see setting for detection set the relevant nvic registers for detecting interrupts. set the clock generator as well if each interrupt source is used to clear a standby mode. common setting nvic registers setting to clear standby mode clock generator "6.5.2.2 preparation" setting for sending interrupt signal execute an appropriate setting to send the interrupt signal depending on the interrupt type. setting for interrupt from external pin port setting for interrupt from peripheral function peripheral function (see the chapter of each peripheral function for details.) interrupt generation an interrupt request is generated. interrupt lines used for clearing a stand by mode are connected to the cpu via the clock generator. "6.5.2.3 detection by clock generator" cpu detects interrupt. the cpu detects the interrupt. "6.5.2.4 detection by cpu" if multiple interrupt requests occur simultaneously, the interrupt request with the highest priority is detected according to the priority order. cpu handles interrupt. the cpu handles the interrupt. "6.5.2.5 cpu process- ing" the cpu pushes register contents to the stack before entering the isr. isr execution program for the isr. clear the interrupt source if needed. "6.5.2.6 interrupt service routine (isr)" return to preceding program configure to return to the preceding program of the isr. cg detects interrupt (clearing standby mode) clearing standby mode not clearing standby mode page 6-16 6. exceptions 6.5 interrupts TMPM376FDDFG/fdfg 2013/4/12 6.5.2.2 preparation when preparing for an interrupt, you need to pay a ttention to the order of configuration to avoid any unexpected interrupt on the way. initiating an interrupt or changing its configuration must be implemented in the following order basi- cally. disable the interrupt by the cp u. configure from the farthest rout e from the cpu. then enable the interrupt by the cpu. to configure the clock generator, you must follow the order indicated here not to cause any unexpected interrupt. first, configure the precondition. secondly, clear the data related to the interrupt in the clock generator and then enable the interrupt. the following sections are listed in the order of in terrupt handling and describe how to configure them. 1. disabling interrupt by cpu 2. cpu registers setting 3. preconfiguration (1) (inter rupt from external pin) 4. preconfiguration (2) (interrupt from peripheral function) 5. preconfiguration (3) (inter rupt set-pending register) 6. configuring the clock generator 7. enabling interrupt by cpu (1) disabling interrupt by cpu to make the cpu for not accepting any interrupt, write "1" to the corresponding bit of the pri- mask register. all interrupts and exceptions other than non-maskable interrupts and hard faults can be masked. use "msr" instruction to set this register. note 1: primask register cannot be modified by the user access level. note 2: if a fault causes when "1" is set to the primask register, it is treated as a hard fault. (2) cpu registers setting you can assign a priority level by writing to page 6-17 TMPM376FDDFG/fdfg 2013/4/12 note: "n" indicates the corresponding exceptions/interrupts. this product uses three bits fo r assigning a priority level. (3) preconfiguration (1) (interrupt from external pin) set "1" to the port function register of the corr esponding pin. setting pxfrn[m] allows the pin to be used as the function pin. setting pxie[m] allows the pin to be used as the input port. note: x: port number / m: corresponding bit / n: function register number in modes other than stop mode, setting pxie to enable input enables the co rresponding interrupt input regardless of the pxfr setting. be careful not to enable interrupts that are not used. also, be aware of the descrip- tion of "6.5.1.4 precautions when using external interrupt pins". (4) preconfiguration (2) (interrupt from peripheral function) the setting varies depending on the peripheral function to be used. see the chapter of each periph- eral function for details. (5) preconfiguration (3) (interrupt set-pending register) to generate an interrupt by using the interrupt set-pending register, set "1" to the corresponding bit of this register. note: m: corresponding bit (6) configuring the clock generator for an interrupt source to be used for exiting a standby mode, you need to set the active level and enable interrupts in the cgimcg register of the cl ock generator. the cgimcg register is capable of configuring each source. before enabling an interr upt, clear the corresponding interrupt request already held. this can avoid unexpected interrupt.to clear co rresponding interrupt request, write a value corresponding to the interrupt to be used to the cg icrcg register.see "6.6.3.5 cgi crcg (cg interrupt request clear register)" for each value. nvic register page 6-18 6. exceptions 6.5 interrupts TMPM376FDDFG/fdfg 2013/4/12 interrupt requests from external pins can be used without setting the clock generator if they are not used for exiting a standby mode. however, an "high" pulse or "high"-level signal must be input so that the cpu can detect it as an interrupt request. also, be aware of the description of "6.5.1.4 pre- cautions when using external interrupt pins". note: n: register number / m: number assigned to interrupt source (7) enabling interrupt by cpu enable the interrupt by the cpu as shown below. clear the suspended interrupt in the interrupt clear -pending register. enable the intended interrupt with the interrupt set-enable register. each bit of the register is assigned to a single interrupt source. writing "1" to the corresponding bit of the inte rrupt clear-pending register clears the suspended interrupt. writing "1" to the corresponding bit of the interrupt set-enable register enables the intended interrupt. to generate interrupts in the interrupt set-pending register setting, factors to trigger interrupts are lost if pending interrupts are cleared. thus, this operation is not necessary. at the end, primask re gister is zero cleared. note 1: m : corresponding bit note 2: primask register cannot be modified by the user access level. 6.5.2.3 detection by clock generator if an interrupt source is used for exiting a standby mode, an interrupt request is de tected according to the active level specified in the clock ge nerator, and is notified to the cpu. an edge-triggered interrup t request, once detected, is held in the clock generator. a level-sensitive interrupt request must be held at the active level un til it is detected, otherwise the interrupt request will cease to exist when the signal leve l changes from active to inactive. when the clock generator detects an interrupt request, it keeps sending the interrupt signal in "high" level to the cpu until the interrupt request is cleared in the cg interrupt request clear (cgicrcg) reg- ister. if a standby mode is exited without clearing the interrupt request, the same interrupt will be detected again when normal operation is resumed. be sure to clear each interr upt request in the isr. 6.5.2.4 detection by cpu the cpu detects an interrupt requ est with the highest priority. clock generator register cgimcgn page 6-19 TMPM376FDDFG/fdfg 2013/4/12 6.5.2.5 cpu processing on detecting an interrupt, the cpu pushes the contents of pc, psr, r0-r3, r12 and lr to the stack then enter the isr. 6.5.2.6 interrupt service routine (isr) an isr requires specific programmi ng according to the application to be used. this section describes what is recommended at the service routin e programming and how the source is cleared. (1) pushing during isr an isr normally pushes register contents to th e stack and handles an in terrupt as required. the cortex-m3 core automatically push es the contents of pc, psr, r0 -r3, r12 and lr to the stack. no extra programming is required for them. push the contents of ot her registers if needed. interrupt requests wi th higher priority and exceptions such as nmi are accepted even when an isr is being executed. we recommend y ou to push the contents of general-purpose registers that might be rewritten. (2) clearing an interrupt source if an interrupt s ource is used for clearing a standby mode, each interrupt request must be cleared with the cg interrupt request clear (cgicrcg) register. if an interrupt source is set as level-sensitive, an interrupt request continues to exist until it is cleared at its source. therefore, the interrupt source must be cl eared. clearing the interrupt source automatically clears the interrupt reque st signal from the clock generator. if an interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding value in the cgicrcg register. when an active edge occurs again, a new interrupt request will be detected. page 6-20 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 6.6 exception / interrupt-related registers the cpu's nvic registers and clock generator registers described in this chapter are shown below with their respective addresses. 6.6.1 register list nvic registers base address = 0xe000_e000 register name address systick control and status register 0x0010 systick reload value register 0x0014 systick current value register 0x0018 systick calibration value register 0x001c interrupt set-enable register 1 0x0100 interrupt set-enable register 2 0x0104 interrupt set-enable register 3 0x0108 interrupt clear-enable register 1 0x0180 interrupt clear-enable register 2 0x0184 interrupt clear-enable register 3 0x0188 interrupt set-pending register 1 0x0200 interrupt set-pending register 2 0x0204 interrupt set-pending register 3 0x0208 interrupt clear-pending register 1 0x0280 interrupt clear-pending register 2 0x0284 interrupt clear-pending register 3 0x0288 interrupt priority register 0x0400 ~ 0x0460 vector table offset register 0x0d08 application interrupt and reset control register 0x0d0c system handler priority r egister 0x0d18, 0x0d1c, 0x0d20 system handler control and state register 0x0d24 page 6-21 TMPM376FDDFG/fdfg 2013/4/12 note:access to the "reserved" areas is prohibited. clock generator register base address = 0x4004_0200 register name address cg interrupt request clear register cgicrcg 0x0014 nmi flag register cgnmiflg 0x0018 reset flag register cgrstflg 0x001c cg interrupt mode control register a cgimcga 0x0020 cg interrupt mode control register b cgimcgb 0x0024 cg interrupt mode control register c cgimcgc 0x0028 cg interrupt mode control register d cgimcgd 0x002c reserved - 0x0030 reserved - 0x0034 reserved - 0x0038 reserved - 0x003c page 6-22 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 6.6.2 nvic registers 6.6.2.1 systick control and status register note: in this product, fosc which is selected by cgoscc r page 6-23 TMPM376FDDFG/fdfg 2013/4/12 6.6.2.2 systick reload value register 6.6.2.3 systick correct value register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol reload after reset undefined 15 14 13 12 11 10 9 8 bit symbol reload after reset undefined 7 6 5 4 3 2 1 0 bit symbol reload after reset undefined bit bit symbol type function 31-24 ? r read as 0, 23-0 reload r/w reload value set the value to load into the systick current value register when the timer reaches "0". 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol current after reset undefined 15 14 13 12 11 10 9 8 bit symbol current after reset undefined 7 6 5 4 3 2 1 0 bit symbol current after reset undefined bit bit symbol type function 31-24 ? r read as 0. 23-0 current r/w [read] current systick timer value [write] clear writing to this register with any value clears it to 0. clearing this register also clears the page 6-24 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 6.6.2.4 systick calibration value register note: in the case of a multishot, please use page 6-25 TMPM376FDDFG/fdfg 2013/4/12 6.6.2.5 interrupt set-enable register 1 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 31 30 29 28 27 26 25 24 bit symbol setena (interrupt 31) setena (interrupt 30) setena (interrupt 29) setena (interrupt 28) setena (interrupt 27) setena (interrupt 26) setena (interrupt 25) setena (interrupt 24) a f t e r r e s e t00000000 23 22 21 20 19 18 17 16 bit symbol setena (interrupt 23) setena (interrupt 22) setena (interrupt 21) setena (interrupt 20) setena (interrupt 19) setena (interrupt 18) setena (interrupt 17) setena (interrupt 16) a f t e r r e s e t00000000 15 14 13 12 11 10 9 8 bit symbol setena (interrupt 15) setena (interrupt 14) setena (interrupt 13) setena (interrupt 12) setena (interrupt 11) setena (interrupt 10) setena (interrupt 9) setena (interrupt 8) a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol setena (interrupt 7) setena (interrupt 6) setena (interrupt 5) setena (interrupt 4) setena (interrupt 3) setena (interrupt 2) setena (interrupt 1) setena (interrupt 0) a f t e r r e s e t00000000 bit bit symbol type function 31-0 setena r/w interrupt number [31:0] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. page 6-26 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 6.6.2.6 interrupt set-enable register 2 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 31 30 29 28 27 26 25 24 bit symbol setena (interrupt 63) setena (interrupt 62) setena (interrupt 61) setena (interrupt 60) setena (interrupt 59) setena (interrupt 58) setena (interrupt 57) setena (interrupt 56) a f t e r r e s e t00000000 23 22 21 20 19 18 17 16 bit symbol setena (interrupt 55) setena (interrupt 54) setena (interrupt 53) setena (interrupt 52) setena (interrupt 51) setena (interrupt 50) setena (interrupt 49) setena (interrupt 48) a f t e r r e s e t00000000 15 14 13 12 11 10 9 8 bit symbol setena (interrupt 47) setena (interrupt 46) setena (interrupt 45) setena (interrupt 44) setena (interrupt 43) setena (interrupt 42) setena (interrupt 41) setena (interrupt 40) a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol setena (interrupt 39) setena (interrupt 38) setena (interrupt 37) setena (interrupt 36) setena (interrupt 35) setena (interrupt 34) setena (interrupt 33) setena (interrupt 32) a f t e r r e s e t00000000 bit bit symbol type function 31-0 setena r/w interrupt number [63:32] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. page 6-27 TMPM376FDDFG/fdfg 2013/4/12 6.6.2.7 interrupt set-enable register 3 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol - setena (interrupt 78) setena (interrupt 77) setena (interrupt 76) setena (interrupt 75) setena (interrupt 74) setena (interrupt 73) setena (interrupt 72) a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol setena (interrupt 71) setena (interrupt 70) setena (interrupt 69) setena (interrupt 68) setena (interrupt 67) setena (interrupt 66) setena (interrupt 65) setena (interrupt 64) a f t e r r e s e t00000000 bit bit symbol type function 31-15 ? r/w read as 0. 14-0 setena r/w interrupt number [78:64] [write] 1: enable [read] 0: disabled 1: enabled each bit corresponds to the specified number of interrupts. writing "1" to a bit in this register enables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. page 6-28 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 6.6.2.8 interrupt clear-enable register 1 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 31 30 29 28 27 26 25 24 bit symbol clrena (interrupt 31) clrena (interrupt 30) clrena (interrupt 29) clrena (interrupt 28) clrena (interrupt 27) clrena (interrupt 26) clrena (interrupt 25) clrena (interrupt 24) a f t e r r e s e t00000000 23 22 21 20 19 18 17 16 bit symbol clrena (interrupt 23) clrena (interrupt 22) clrena (interrupt 21) clrena (interrupt 20) clrena (interrupt 19) clrena (interrupt 18) clrena (interrupt 17) clrena (interrupt 16) a f t e r r e s e t00000000 15 14 13 12 11 10 9 8 bit symbol clrena (interrupt 15) clrena (interrupt 14) clrena (interrupt 13) clrena (interrupt 12) clrena (interrupt 11) clrena (interrupt 10 clrena (interrupt 9) clrena (interrupt 8) a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol clrena (interrupt 7) clrena (interrupt 6) clrena (interrupt 5) clrena (interrupt 4) clrena (interrupt 3) clrena (interrupt 2 clrena (interrupt 1) clrena (interrupt 0) a f t e r r e s e t00000000 bit bit symbol type function 31-0 clrena r/w interrupt number [31:0] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. page 6-29 TMPM376FDDFG/fdfg 2013/4/12 6.6.2.9 interrupt clear-enable register 2 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 31 30 29 28 27 26 25 24 bit symbol clrena (interrupt 63) clrena (interrupt 62) clrena (interrupt 61) clrena (interrupt 60) clrena (interrupt 59) clrena (interrupt 58) clrena (interrupt 57) clrena (interrupt 56) a f t e r r e s e t00000000 23 22 21 20 19 18 17 16 bit symbol clrena (interrupt 55) clrena (interrupt 54) clrena (interrupt 53) clrena (interrupt 52) clrena (interrupt 51) clrena (interrupt 50) clrena (interrupt 49) clrena (interrupt 48) a f t e r r e s e t00000000 15 14 13 12 11 10 9 8 bit symbol clrena (interrupt 47) clrena (interrupt 46) clrena (interrupt 45) clrena (interrupt 44) clrena (interrupt 43) clrena (interrupt 42) clrena (interrupt 41) clrena (interrupt 40) a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol clrena (interrupt 39) clrena (interrupt 38) clrena (interrupt 37) clrena (interrupt 36) clrena (interrupt 35) clrena (interrupt 34) clrena (interrupt 33) clrena (interrupt 32) a f t e r r e s e t00000000 bit bit symbol type function 31-0 clrena r/w interrupt number [63:32] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. page 6-30 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 6.6.2.10 interrupt clear-enable register 3 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 6.6.2.11 interrupt set-pending register 1 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol - clrena (interrupt 78) clrena (interrupt 77) clrena (interrupt 76) clrena (interrupt 75) clrena (interrupt 74) clrena (interrupt 73) clrena (interrupt 72) a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol clrena (interrupt 71) clrena (interrupt 70) clrena (interrupt 69) clrena (interrupt 68) clrena (interrupt 67) clrena (interrupt 66) clrena (interrupt 65) clrena (interrupt 64) a f t e r r e s e t00000000 bit bit symbol type function 31-15 ? r/w read as 0. 14-0 clrena r/w interrupt number [78:64] [write] 1: disabled [read] 0: disabled 1: enable each bit corresponds to the specified number of interrupts. it can be performed to enable interrupts and to check if interrupts are disabled. writing "1" to a bit in this register disables the corresponding interrupt. writing "0" has no effect. reading the bits can see the enable/disable condition of the corresponding interrupts. 31 30 29 28 27 26 25 24 bit symbol setpend (interrupt 31) setpend (interrupt 30) setpend (interrupt 29) setpend (interrupt 28) setpend (interrupt 27) setpend (interrupt 26) setpend (interrupt 25) setpend (interrupt 24) after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol setpend (interrupt 23) setpend (interrupt 22) setpend (interrupt 21) setpend (interrupt 20) setpend (interrupt 19) setpend (interrupt 18) setpend (interrupt 17) setpend (interrupt 16) after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol setpend (interrupt 15) setpend (interrupt 14) setpend (interrupt 13) setpend (interrupt 12) setpend (interrupt 11) setpend (interrupt 10 setpend (interrupt 9) setpend (interrupt 8) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol setpend (interrupt 7) setpend (interrupt 6) setpend (interrupt 5) setpend (interrupt 4) setpend (interrupt 3) setpend (interrupt 2 setpend (interrupt 1) setpend (interrupt 0) after reset undefined undefined undefined undefined undefined undefined undefined undefined page 6-31 TMPM376FDDFG/fdfg 2013/4/12 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". bit bit symbol type function 31-0 setpend r/w interrupt number [31:0] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. page 6-32 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 6.6.2.12 interrupt set-pending register 2 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 31 30 29 28 27 26 25 24 bit symbol setpend (interrupt 63) setpend (interrupt 62) setpend (interrupt 61) setpend (interrupt 60) setpend (interrupt 59) setpend (interrupt 58) setpend (interrupt 57) setpend (interrupt 56) after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol setpend (interrupt 55) setpend (interrupt 54) setpend (interrupt 53) setpend (interrupt 52) setpend (interrupt 51) setpend (interrupt 50) setpend (interrupt 49) setpend (interrupt 48) after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol setpend (interrupt 47) setpend (interrupt 46) setpend (interrupt 45) setpend (interrupt 44) setpend (interrupt 43) setpend (interrupt 42) setpend (interrupt 41) setpend (interrupt 40) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol setpend (interrupt 39) setpend (interrupt 38) setpend (interrupt 37) setpend (interrupt 36) setpend (interrupt 35) setpend (interrupt 34) setpend (interrupt 33) setpend (interrupt 32) after reset undefined undefined undefined undefined undefined undefined undefined undefined bit bit symbol type function 31-0 setpend r/w interrupt number [63:32] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. page 6-33 TMPM376FDDFG/fdfg 2013/4/12 6.6.2.13 interrupt set-pending register 3 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 31 30 29 28 27 26 25 24 bit symbol-------- after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol-------- after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol - setpend (interrupt 78) setpend (interrupt 77) setpend (interrupt 76) setpend (interrupt 75) setpend (interrupt 74) setpend (interrupt 73) setpend (interrupt 72) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol setpend (interrupt 71) setpend (interrupt 70) setpend (interrupt 69) setpend (interrupt 68) setpend (interrupt 67) setpend (interrupt 66) setpend (interrupt 65) setpend (interrupt 64) after reset undefined undefined undefined undefined undefined undefined undefined undefined bit bit symbol type function 31-15 ? r/w read as 0. 14-0 setpend r/w interrupt number [78:64] [write] 1: pend [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register pends the corresponding interrupt. however, writing "1" has no effect on an interrupt that is already pending or is disabled. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. writing "1" to a corresponding bit in the interrupt cle ar-pending register clears the bit in this register. page 6-34 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 6.6.2.14 interrupt clear-pending register 1 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 31 30 29 28 27 26 25 24 bit symbol clrpend (interrupt 31) clrpend (interrupt 30) clrpend (interrupt 29) clrpend (interrupt 28) clrpend (interrupt 27) clrpend (interrupt 26) clrpend (interrupt 25) clrpend (interrupt 24) after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol clrpend (interrupt 23) clrpend (interrupt 22) clrpend (interrupt 21) clrpend (interrupt 20) clrpend (interrupt 19) clrpend (interrupt 18) clrpend (interrupt 17) clrpend (interrupt 16) after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol clrpend (interrupt 15) clrpend (interrupt 14) clrpend (interrupt 13) clrpend (interrupt 12) clrpend (interrupt 11) clrpend (interrupt 10) clrpend (interrupt 9) clrpend (interrupt 8) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol clrpend (interrupt 7) clrpend (interrupt 6) clrpend (interrupt 5) clrpend (interrupt 4) clrpend (interrupt 3) clrpend (interrupt 2) clrpend (interrupt 1) clrpend (interrupt 0) after reset undefined undefined undefined undefined undefined undefined undefined undefined bit bit symbol type function 31-0 clrpend r/w interrupt number [31:0] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. page 6-35 TMPM376FDDFG/fdfg 2013/4/12 6.6.2.15 interrupt clear-pending register 2 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". 6.6.2.16 interrupt clear-pending register 3 31 30 29 28 27 26 25 24 bit symbol clrpend (interrupt 63) clrpend (interrupt 62) clrpend (interrupt 61) clrpend (interrupt 60) clrpend (interrupt 59) clrpend (interrupt 58) clrpend (interrupt 57) clrpend (interrupt 56) after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol clrpend (interrupt 55) clrpend (interrupt 54) clrpend (interrupt 53) clrpend (interrupt 52) clrpend (interrupt 51) clrpend (interrupt 50) clrpend (interrupt 49) clrpend (interrupt 48) after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol clrpend (interrupt 47) clrpend (interrupt 46) clrpend (interrupt 45) clrpend (interrupt 44) clrpend (interrupt 43) clrpend (interrupt 42) clrpend (interrupt 41) clrpend (interrupt 40) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol clrpend (interrupt 39) clrpend (interrupt 38) clrpend (interrupt 37) clrpend (interrupt 36) clrpend (interrupt 35) clrpend (interrupt 34) clrpend (interrupt 33) clrpend (interrupt 32) after reset undefined undefined undefined undefined undefined undefined undefined undefined bit bit symbol type function 31-0 clrpend r/w interrupt number [63:32] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. 31 30 29 28 27 26 25 24 bit symbol-------- after reset undefined undefined undefined undefined undefined undefined undefined undefined 23 22 21 20 19 18 17 16 bit symbol-------- after reset undefined undefined undefined undefined undefined undefined undefined undefined 15 14 13 12 11 10 9 8 bit symbol - clrpend (interrupt 78) clrpend (interrupt 77) clrpend (interrupt 76) clrpend (interrupt 75) clrpend (interrupt 74) clrpend (interrupt 73) clrpend (interrupt 72) after reset undefined undefined undefined undefined undefined undefined undefined undefined 7 6 5 4 3 2 1 0 bit symbol clrpend (interrupt 71) clrpend (interrupt 70) clrpend (interrupt 69) clrpend (interrupt 68) clrpend (interrupt 67) clrpend (interrupt 66) clrpend (interrupt 65) clrpend (interrupt 64) after reset undefined undefined undefined undefined undefined undefined undefined undefined page 6-36 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 note: for descriptions of interrupts and interrupt numbers, see section "6.5.1.5 list of interrupt sources". bit bit symbol type function 31-15 ? r/w read as 0. 14-0 clrpend r/w interrupt number [78:64] [write] 1: clear pending interrupt [read] 0: not pending 1: pending each bit corresponds to the specified number can forc e interrupts into the pending state and determines which interrupts are currently pending. writing "1" to a bit in this register clears the correspo nding pending interrupt. however, writing "1" has no effect on an interrupt that is already being serviced. writing "0" has no effect. reading the bit returns the current state of the corresponding interrupts. page 6-37 TMPM376FDDFG/fdfg 2013/4/12 6.6.2.17 interrupt priority register each interrupt is provided with eight b its of an interrupt priority register. the following shows the addresses of the interrupt priority registers corresponding to interrupt num- bers. the number of bits to be used for assigning a priori ty varies with each product. this product uses three bits for assigning a priority. the following shows the fields of the interrupt prior ity registers for interrupt numbers 0 to 3. the inter- rupt priority registers for all other interrupt numbers have the identical fields . unused bits return "0" when read, and writing to unused bits has no effect. 31 24 23 16 15 8 7 0 0xe000_e400 pri_3 pri_2 pri_1 pri_0 0xe000_e404 pri_7 pri_6 pri_5 pri_4 0xe000_e408 pri_11 pri_10 pri_9 pri_8 0xe000_e40c pri_15 pri_14 pri_13 pri_12 0xe000_e410 pri_19 pri_18 pri_17 pri_16 0xe000_e414 pri_23 pri_22 pri_21 pri_20 0xe000_e418 pri_27 pri_26 pri_25 pri_24 0xe000_e41c pri_31 pri_30 pri_29 pri_28 0xe000_e420 pri_35 pri_34 pri_33 pri_32 0xe000_e424 pri_39 pri_38 pri_37 pri_36 0xe000_e428 pri_43 pri_42 pri_41 pri_40 0xe000_e42c pri_47 pri_46 pri_45 pri_44 0xe000_e430 pri_51 pri_50 pri_49 pri_48 0xe000_e434 pri_55 pri_54 pri_53 pri_52 0xe000_e438 pri_59 pri_58 pri_57 pri_56 0xe000_e43c pri_63 pri_62 pri_61 pri_60 0xe000_e440 pri_67 pri_66 pri_65 pri_64 0xe000_e444 pri_71 pri_70 pri_69 pri_68 0xe000_e448 pri_75 pri_74 pri_73 pri_72 0xe000_e44c ? pri_78 pri_77 pri_76 31 30 29 28 27 26 25 24 bit symbol pri_3 ????? a f t e r r e s e t00000000 23 22 21 20 19 18 17 16 bit symbol pri_2 ????? a f t e r r e s e t00000000 15 14 13 12 11 10 9 8 bit symbol pri_1 ????? a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol pri_0 ????? a f t e r r e s e t00000000 page 6-38 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 bit bit symbol type function 31-29 pri_3 r/w priority of interrupt number 3 28-24 ? r read as 0, 23-21 pri_2 r/w priority of interrupt number 2 20-16 ? r read as 0, 15-13 pri_1 r/w priority of interrupt number 1 12-8 ? r read as 0, 7-5 pri_0 r/w priority of interrupt number 0 4-0 ? r read as 0, page 6-39 TMPM376FDDFG/fdfg 2013/4/12 6.6.2.18 vector table offset register 31 30 29 28 27 26 25 24 bit symbol - - tblbase tbloff after reset00000000 23 22 21 20 19 18 17 16 bit symbol tbloff after reset00000000 15 14 13 12 11 10 9 8 bit symbol tbloff after reset00000000 7 6 5 4 3 2 1 0 bit symboltbloff------- after reset00000000 bit bit symbol type function 31-30 ? r read as 0, 29 tblbase r/w table base the vector table is in: 0 : code space 1: sram space 28-7 tbloff r/w offset value set the offset value from the top of the space specified in tblbase. the offset must be aligned based on the number of exce ptions in the table.this means that the minimum align- ment is 32 words that you can use for up to 16 interrupt s.for more interrupts, you must adjust the alignment by rounding up to the next power of two. 6-0 ? r read as 0, page 6-40 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 6.6.2.19 application interrupt and reset control register note 1: little-endian is the default memory format for this product. note 2: when sysresetreq is output, warm reset is pe rformed on this product. page 6-41 TMPM376FDDFG/fdfg 2013/4/12 6.6.2.20 system handler priority register each exception is provided with eight bits of a system handler priority register. the following shows the addresses of the system handler priority registers corresponding to each exception. the number of bits to be used for assigning a priori ty varies with each product. this product uses three bits for assigning a priority. the following shows the fields of the system handler priority regi sters for memory management, bus fault and usage fault. unused bits return "0" when read, and writing to unused bits has no effect. 31 24 23 16 15 8 7 0 0xe000_ed18 pri_7 pri_6 (usage fault) pri_5 (bus fault) pri_4 (memory management) 0xe000_ed1c pri_11 (svcall) pri_10 pri_9 pri_8 0xe000_ed20 pri_15 (systick) pri_14 (pendsv) pri_13 pri_12 (debug monitor) 31 30 29 28 27 26 25 24 bit symbol pri_7 ----- after reset00000000 23 22 21 20 19 18 17 16 bit symbol pri_6 ----- after reset00000000 15 14 13 12 11 10 9 8 bit symbol pri_5 ----- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pri_4 ----- after reset00000000 bit bit symbol type function 31-29 pri_7 r/w reserved 28-24 ? r read as 0, 23-21 pri_6 r/w priority of usage fault 20-16 ? r read as 0, 15-13 pri_5 r/w priority of bus fault 12-8 ? r read as 0, 7-5 pri_4 r/w priority of memory management 4-0 ? r read as 0, page 6-42 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 6.6.2.21 system handler control and state register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 b i t s y m b o l----- usgfault ena busfault ena memfault ena a f t e r r e s e t00000000 15 14 13 12 11 10 9 8 bit symbol svcall pended busfault pended memfault pended usgfault pended systickact pendsvact - monitor act a f t e r r e s e t00000000 7 6 5 4 3 2 1 0 bit symbol svcallact - - - usgfault act - busfault act memfault act a f t e r r e s e t00000000 page 6-43 TMPM376FDDFG/fdfg 2013/4/12 note: you must clear or set the active bits with extreme caut ion because clearing and setting thes e bits does not repair stack c on- tents. bit bit symbol type function 31-19 ? r read as 0, 18 usgfault ena r/w usage fault 0: disabled 1: enabled 17 busfaul tena r/w bus fault 0: disable 1: enable 16 memfault ena r/w memory management 0: disable 1: enable 15 svcall pended r/w svcall 0: not pended 1: pended 14 busfault pended r/w bus fault 0: not pended 1: pended 13 memfault pended r/w memory management 0: not pended 1: pended 12 usgfault pended r/w usage fault 0: not pended 1: pended 11 systickact r/w systick 0: inactive 1: active 10 pendsvact r/w pendsv 0: inactive 1: active 9 ? r read as 0, 8 monitoract r/w debug monitor 0: inactive 1: active 7 svcallact r/w svcall 0: inactive 1: active 6-4 ? r read as 0, 3usgfault act r/w usage fault 0: inactive 1: active 2 ? r read as 0, 1 busfault act r/w bus fault 0: inactive 1: active 0memfault act r/w memory management 0: inactive 1: active page 6-44 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 6.6.3 clock generator registers 6.6.3.1 cgimcga (cg interrupt mode control register a) 31 30 29 28 27 26 25 24 bit symbol - emcg3 emst3 - int3en after reset001000undefined0 23 22 21 20 19 18 17 16 bit symbol - emcg2 emst2 - int2en after reset001000undefined0 15 14 13 12 11 10 9 8 bit symbol - emcg1 emst1 - int1en after reset001000undefined0 7 6 5 4 3 2 1 0 bit symbol - emcg0 emst0 - int0en after reset001000undefined0 page 6-45 TMPM376FDDFG/fdfg 2013/4/12 bit bit symbol type function 31 ? r read as 0. 30-28 emcg3[2:0] r/w active level setting of int3 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 27-26 emst3[1:0] r active level of int3 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 25 ? r reads as undefined. 24 int3en r/w int3 clear input 0: disable 1: enable 23 ? r read as 0. 22-20 emcg2[2:0] r/w active level setting of int2 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 19-18 emst2[1:0] r active level of int2 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 17 ? r reads as undefined. 16 int2en r/w int2 clear input 0:disable 1: enable 15 ? r read as 0. 14-12 emcg1[2:0] r/w active level setting of int1 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 11-10 emst1[1:0] r active level of int1 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 9 ? r reads as undefined. 8 int1en r/w int1 clear input 0: disable 1: enable 7 ? r read as 0, 6-4 emcg0[2:0] r/w active level setting of int0 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 3-2 emst0[1:0] r active level of int0 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 1 ? r reads as undefined. page 6-46 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 note 1: page 6-47 TMPM376FDDFG/fdfg 2013/4/12 6.6.3.2 cgimcgb (cg interrupt mode control register b) 31 30 29 28 27 26 25 24 bit symbol - emcg7 emst7 - int7en after reset001000undefined0 23 22 21 20 19 18 17 16 bit symbol - emcg6 emst6 - int6en after reset001000undefined0 15 14 13 12 11 10 9 8 bit symbol - emcg5 emst5 - int5en after reset001000undefined0 7 6 5 4 3 2 1 0 bit symbol - emcg4 emst4 - int4en after reset001000undefined0 page 6-48 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 page 6-49 TMPM376FDDFG/fdfg 2013/4/12 bit bit symbol type function 31 ? r read as 0. 30-28 emcg7[2:0] r/w active level setting of int7 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 27-26 emst7[1:0] r active level of int7 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 25 ? r reads as undefined. 24 int7en r/w int7 clear input 0: disable 1: enable 23 ? r read as 0. 22-20 emcg6[2:0] r/w active level setting of int6 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 19-18 emst6[1:0] r active level of int6 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 17 ? r reads as undefined. 16 int6en r/w int6 clear input 0:disable 1: enable 15 ? r read as 0. 14-12 emcg5[2:0] r/w active level setting of int5 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 11-10 emst5[1:0] r active level of int5 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 9 ? r reads as undefined. 8 int5en r/w int5 clear input 0: disable 1: enable 7 ? r read as 0. 6-4 emcg4[2:0] r/w active level setting of int4 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 3-2 emst4[1:0] r active level of int4 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 1 ? r reads as undefined. page 6-50 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 note 1: page 6-51 TMPM376FDDFG/fdfg 2013/4/12 6.6.3.3 cgimcgc (cg interrupt mode control register c) 31 30 29 28 27 26 25 24 bit symbol - emcgb emstb - intben after reset001000undefined0 23 22 21 20 19 18 17 16 bit symbol - emcga emsta - intaen after reset001000undefined0 15 14 13 12 11 10 9 8 bit symbol - emcg9 emst9 - int9en after reset001000undefined0 7 6 5 4 3 2 1 0 bit symbol - emcg8 emst8 - int8en after reset001000undefined0 page 6-52 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 page 6-53 TMPM376FDDFG/fdfg 2013/4/12 bit bit symbol type function 31 ? r read as 0. 30-28 emcgb[2:0] r/w active level setting of intb standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 27-26 emstb[1:0] r active level of intb standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 25 ? r reads as undefined. 24 intben r/w intb clear input 0: disable 1: enable 23 ? r read as 0. 22-20 emcga[2:0] r/w active level setting of inta standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 19-18 emsta[1:0] r active level of inta standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 17 ? r reads as undefined. 16 intaen r/w inta clear input 0:disable 1: enable 15 ? r read as 0. 14-12 emcg9[2:0] r/w active level setting of int9 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 11-10 emst9[1:0] r active level of int9 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 9 ? r reads as undefined. 8 int9en r/w int9 clear input 0: disable 1: enable 7 ? r read as 0. 6-4 emcg8[2:0] r/w active level setting of int8 standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 3-2 emst8[1:0] r active level of int8 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 1 ? r reads as undefined. page 6-54 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 note 1: page 6-55 TMPM376FDDFG/fdfg 2013/4/12 6.6.3.4 cgimcgd (cg interrupt mode control register d) 31 30 29 28 27 26 25 24 bit symbol - emcgf emstf - intfen after reset001000undefined0 23 22 21 20 19 18 17 16 bit symbol - emcge emste - inteen after reset001000undefined0 15 14 13 12 11 10 9 8 bit symbol - emcgd emstd - intden after reset001000undefined0 7 6 5 4 3 2 1 0 bit symbol - emcgc emstc - intcen after reset001000undefined0 page 6-56 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 bit bit symbol type function 31 ? r read as 0. 30-28 emcgf[2:0] r/w active level setting of intf standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 27-26 emstf[1:0] r active level of intf standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 25 ? r reads as undefined. 24 intfen r/w intf clear input 0: disable 1: enable 23 ? r read as 0. 22-20 emcge[2:0] r/w active level setting of inte standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 19-18 emste[1:0] r active level of inte standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 17 ? r reads as undefined. 16 inteen r/w inte clear input 0: disable 1: enable 15 ? r read as 0. 14-12 emcgd[2:0] r/w active level setting of intd standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 11-10 emstd[1:0] r active level of intd standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 9 ? r reads as undefined. 8 intden r/w intd clear input 0: disable 1: enable 7 ? r read as 0. 6-4 emcgc[2:0] r/w active level setting of intc standby clear request. (101 to 111: setting prohibited) 000: "low" level 001: "high" level 010: falling edge 011: rising edge 100: both edge 3-2 emstc[1:0] r active level of intc standby clear request 00: ? 01: rising edge 10: falling edge 11: both edge 1 ? r reads as undefined. page 6-57 TMPM376FDDFG/fdfg 2013/4/12 note 1: page 6-58 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 6.6.3.5 cgicrcg (cg interrupt request clear register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - icrcg after reset00000000 bit bit symbol type function 31-5 ? r read as 0, 4-0 icrcg[4:0] w clear interrupt requests. 0_0000:int0 0_1000: int8 0_0001: int1 0_1001: int9 0_0010: int2 0_1010: inta 0_0011: int3 0_1011: intb 0_0100: int4 0_1100: intc 0_0101: int5 0_1101: intd 0_0110: int6 0_1110: inte 0_ 0111: int7 0_1111: intf 1_0000 to 1_ 1111: reserved read as 0. page 6-59 TMPM376FDDFG/fdfg 2013/4/12 6.6.3.6 cgnmiflg (nmi flag register) note: page 6-60 6. exceptions 6.6 exception / interrupt-related registers TMPM376FDDFG/fdfg 2013/4/12 6.6.3.7 cgrstflg (reset flag register) note 1: this flag indicates a reset generated by the sysresetreq bit of the application interrupt and reset control register of the cpu's nvic. note 2: this product has power-on reset circui t and this register is initialized only by power-on reset. therefore, "1" is set t o the page 7-1 TMPM376FDDFG/fdfg 2013/4/12 7. input / output ports 7.1 port functions 7.1.1 function list TMPM376FDDFG/fdfg has 82 ports.besides the ports func tion, these ports can be used as i/o pins for peripheral functions. table 7-1 shows the port function table. table 7-1 port function list port pin input /out- put pull-up pull-down schmitt input noise fil- ter program- mable open- drain function pin porta pa0 i/o pull-up / pull-down ?? tb0in , int3 pa1 i/o pull-up / pull-down - tb0out pa2 i/o pull-up / pull-down ?? tb1in , int4 pa3 i/o pull-up / pull-down - tb1out pa4 i/o pull-up / pull-down - sclk1 , cts1 pa5 i/o pull-up / pull-down - txd1 , tb6out pa6 i/o pull-up / pull-down - rxd1 , tb6in pa7 i/o pull-up / pull-down ?? tb4in , int8 portb pb0 i/o pull-up / pull-down - traceclk pb1 i/o pull-up / pull-down - tracedata0 pb2 i/o pull-up / pull-down - tracedata1 pb3 i/o pull-up / pull-down - tms / swdio pb4 i/o pull-up / pull-down - tck / swclk pb5 i/o pull-up / pull-down - tdo / swv pb6 i/o pull-up / pull-down - tdi pb7 i/o pull-up / pull-down ?? trst portc pc0 i/o pull-up / pull-down - uo0 pc1 i/o pull-up / pull-down - xo0 pc2 i/o pull-up / pull-down - vo0 pc3 i/o pull-up / pull-down - yo0 pc4 i/o pull-up / pull-down - wo0 pc5 i/o pull-up / pull-down - zo0 pc6 i/o pull-up / pull-down - emg0 pc7 i/o pull-up / pull-down - ovv0 portd pd0 i/o pull-up / pull-down - enca0 , tb5in : exist - : not exist page 7-2 7. input / output ports 7.1 port functions TMPM376FDDFG/fdfg 2013/4/12 pd1 i/o pull-up / pull-down - encb0 , tb5out pd2 i/o pull-up / pull-down - encz0 pd3 i/o pull-up / pull-down ?? int9 pd4 i/o pull-up / pull-down - sclk2 , cts2 pd5 i/o pull-up / pull-down - txd2 pd6 i/o pull-up / pull-down - rxd2 porte pe0 i/o pull-up / pull-down - txd0 pe1 i/o pull-up / pull-down - rxd0 pe2 i/o pull-up / pull-down - sclk0 , cts0 pe3 i/o pull-up / pull-down - tb4out pe4 i/o pull-up / pull-down ?? tb2in , int5 pe5 i/o pull-up / pull-down - tb2out pe6 i/o pull-up / pull-down ?? tb3in , int6 pe7 i/o pull-up / pull-down ?? tb3out , int7 portf pf0 i/o pull-up / pull-down - tb7in , boot pf1 i/o pull-up / pull-down - tb7out pf2 i/o pull-up / pull-down - enca1 , sclk3 , cts3 pf3 i/o pull-up / pull-down - encb1 , txd3 pf4 i/o pull-up / pull-down - encz1 , rxd3 portg pg0 i/o pull-up / pull-down - uo1 pg1 i/o pull-up / pull-down - xo1 pg2 i/o pull-up / pull-down - vo1 pg3 i/o pull-up / pull-down - yo1 pg4 i/o pull-up / pull-down - wo1 pg5 i/o pull-up / pull-down - zo1 pg6 i/o pull-up / pull-down - emg1 pg7 i/o pull-up / pull-down - ovv1 porth ph0 i/o pull-up / pull-down ?? int0 , aina0 ph1 i/o pull-up / pull-down ?? int1 , aina1 ph2 i/o pull-up / pull-down ?? int2 , aina2 ph3 i/o pull-up / pull-down - aina3 ph4 i/o pull-up / pull-down - aina4 ph5 i/o pull-up / pull-down - aina5 ph6 i/o pull-up / pull-down - aina6 ph7 i/o pull-up / pull-down - aina7 porti table 7-1 port function list port pin input /out- put pull-up pull-down schmitt input noise fil- ter program- mable open- drain function pin : exist - : not exist page 7-3 TMPM376FDDFG/fdfg 2013/4/12 note:the noise elimination width of the noise fi lter is approximately 30 ns under typical conditions. pi0 i/o pull-up / pull-down - aina8 pi1 i/o pull-up / pull-down - aina9 / ainb0 pi2 i/o pull-up / pull-down - aina10 / ainb1 pi3 i/o pull-up / pull-down - aina11 / ainb2 portj pj0 i/o pull-up / pull-down - ainb3 pj1 i/o pull-up / pull-down - ainb4 pj2 i/o pull-up / pull-down - ainb5 pj3 i/o pull-up / pull-down - ainb6 pj4 i/o pull-up / pull-down - ainb7 pj5 i/o pull-up / pull-down - ainb8 pj6 i/o pull-up / pull-down ?? intc , ainb9 pj7 i/o pull-up / pull-down ?? intd , ainb10 portk pk0 i/o pull-up / pull-down ?? inte , ainb11 pk1 i/o pull-up / pull-down ?? intf , ainb12 portl pl0 input - ? -intb pl1 input - ? -inta portm pm0 i/o pull-up / pull-down - x1 pm1 i/o pull-up / pull-down - x2 portn pn0 i/o pull-up / pull-down - so / sda pn1 i/o pull-up / pull-down - si / scl pn2 i/o pull-up / pull-down - sck pn3 i/o pull-up / pull-down - tb7in table 7-1 port function list port pin input /out- put pull-up pull-down schmitt input noise fil- ter program- mable open- drain function pin : exist - : not exist page 7-4 7. input / output ports 7.1 port functions TMPM376FDDFG/fdfg 2013/4/12 7.1.2 port registers outline the following registers need to be configured to use ports. ? pxdata: port x data register to read / write port data. ? pxcr: port x output control register to control output. pxie needs to be configured to control input. ? pxfrn: port x function register n to set function. an assigned function can be activated by setting "1". ? pxod: port x open drain control register to control the programmable open drain. programmable open drain is function to be mate rialized pseudo-open-drain by setting the pxod. when pxod is set "1",output buffer is disabled and pseudo-open-drain is materialized. ? pxpup: port x pull-up control register to control programmable pull ups. ? pxpdn: port x pull-down control register to control programmable pull downs. ? pxie:port x input control register to control inputs. for avoided through current, default setting prohibits inputs. page 7-5 TMPM376FDDFG/fdfg 2013/4/12 7.1.3 port states in stop mode input and output in stop mode are enable d / disabled by the cgstbycr page 7-6 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2 port functions this chapter describes the port registers detail. this chapter describes only "circuit type" reading circuit configuration. for detailed circuit diagram, refer to"7.3 block diagrams of ports". 7.2.1 port a (pa0 to pa7) the port a is a general-purpose, 8-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purp ose input / output functi on, the port a performs the serial interface func- tion (sio / uart), the external signal interrup t input, the 16-bit timer input/output function. reset initializes all bits of the port a as general- purpose ports with input, output, pull-up and pull-down dis- abled. the port a has two types of function register. if you us e the port a as a general-purpose port, set "0" to the corresponding bit of the two registers.if you use the port a as other than a general-purpose port, set "1" to the corresponding bit of the function register.do not set "1 " to the some function registers at the same time. to use the external interrupt input for releasing stop mode, select this function in the pafr and enable input in the paie register. these settings enable the interrupt input even if the cgstbycr page 7-7 TMPM376FDDFG/fdfg 2013/4/12 7.2.1.3 padata (port a data register) 7.2.1.4 pacr (port a output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7 to pa0 r/w port a data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7c pa6c pa5c pa4c pa3c pa2c pa1c pa0c after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7c to pa0c r/w output 0: disable 1: enable page 7-8 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.1.5 pafr1 (port a function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7f1 pa6f1 pa5f1 pa4f1 pa3f1 pa2f1 pa1f1 pa0f1 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 pa7f1 r/w 0 : port 1 : tb4in 6 pa6f1 r/w 0: port 1: rxd1 5 pa5f1 r/w 0: port 1: txd1 4 pa4f1 r/w 0: port 1: sclk1 3 pa3f1 r/w 0: port 1: tb1out 2 pa2f1 r/w 0: port 1: tb1in 1 pa1f1 r/w 0: port 1: tb0out 0 pa0f1 r/w 0: port 1: tb0in page 7-9 TMPM376FDDFG/fdfg 2013/4/12 7.2.1.6 pafr2 (port a function register 2) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7f2 pa6f2 pa5f2 pa4f2 - pa2f2 - pa0f2 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 pa7f2 r/w 0 : port 1 : int8 6 pa6f2 r/w 0: port 1: tb6in 5 pa5f2 r/w 0: port 1: tb6out 4 pa4f2 r/w 0: port 1: cts1 3 ? r read as 0. 2 pa2f2 r/w 0: port 1: int4 1 ? r read as 0. 0 pa0f2 r/w 0: port 1: int3 page 7-10 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.1.7 paod (port a open drain control register) 7.2.1.8 papup (port a pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7od pa6od pa5od pa4od pa3od pa2od pa1od pa0od after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7od to pa0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7up pa6up pa5up pa4up pa3up pa2up pa1up pa0up after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7up to pa0up r/w pull-up 0: disable 1: enable page 7-11 TMPM376FDDFG/fdfg 2013/4/12 7.2.1.9 papdn (port a pull-down control register) 7.2.1.10 paie (port a input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7dn pa6dn pa5dn pa4dn pa3dn pa2dn pa1dn pa0dn after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7dn to pa0dn r/w pull-down 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pa7ie pa6ie pa5ie pa4ie pa3ie pa2ie pa1ie pa0ie after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pa7ie to pa0ie r/w input 0: disable 1: enable page 7-12 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.2 port b (pb0 to pb7) the port b is a general-purpose, 8-bit input / output port.for this port, inputs and outputs can be specified in units of bits. besides the general-pu rpose input / output function, the port b performs the debug interface func- tion and the debug tr ace output function. reset initializes pb3, pb4, pb5, pb6 an d pb7 to perform debug interface function. when pb3 functions as the tms or swdio, input, ou tput and pull-up are enable d. when pb4 functions as the tck or swclk, input, pull-down are enabled. when pb5 functions as the tdo or swv, output is enabled. when pb6 functions tdi, input, pull-up are enabled. when pb7 functions as trst input, pull-up is enabled. pb0, pb1, pb2 perform as the general-purpose port s with input, output, pull-up, pull-down disabled. note:if pb3 is configured as the tms/swdio pin, output is enabled even in stop mode regardless of the cgst- bycr page 7-13 TMPM376FDDFG/fdfg 2013/4/12 7.2.2.3 pbdata (port b data register) 7.2.2.4 pbcr (port b output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7 to pb0 r/w port b data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7c pb6c pb5c pb4c pb3c pb2c pb1c pb0c after reset00101000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7c to pb0c r/w output 0: disable 1: enable page 7-14 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.2.5 pbfr1 (port b function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7f1 pb6f1 pb5f1 pb4f1 pb3f1 pb2f1 pb1f1 pb0f1 after reset11111000 bit bit symbol type function 31-8 ? r read as 0. 7pb7f1 r/w0 : port 1 : trst 6pb6f1 r/w0: port 1: tdi 5pb5f1 r/w0: port 1: tdo / swv 4pb4f1 r/w0: port 1: tck / swclk 3pb3f1 r/w0: port 1: tms / swdio 2pb2f1 r/w0: port 1: tracedata1 1pb1f1 r/w0: port 1: tracedata0 0pb0f1 r/w0: port 1: traceclk page 7-15 TMPM376FDDFG/fdfg 2013/4/12 7.2.2.6 pbod (port b open drain control register) 7.2.2.7 pbpup (port b pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7od pb6od pb5od pb4od pb3od pb2od pb1od pb0od after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7od to pb0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7up pb6up pb5up pb4up pb3up pb2up pb1up pb0up after reset11001000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7up to pb0up r/w pull-up 0: disable 1: enable page 7-16 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.2.8 pbpdn (port b pull-down control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7dn pb6dn pb5dn pb4dn pb3dn pb2dn pb1dn pb0dn after reset00010000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7dn to pbdn r/w pull-down 0: disable 1: enable page 7-17 TMPM376FDDFG/fdfg 2013/4/12 7.2.2.9 pbie (port b input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pb7ie pb6ie pb5ie pb4ie pb3ie pb2ie pb1ie pb0ie after reset11011000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pb7ie to pb0ie r/w input 0: disable 1: enable page 7-18 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.3 port c (pc0 to pc7) the port c is a general-purpose, 8-bit input / output po rt. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input / output function, the port c performs the input/output port for three-phase motor control (pmd). reset initializes all bits of the port c as general- purpose ports with input, output, pull-up and pull-down dis- abled. 7.2.3.1 port c circuit type 7.2.3.2 port c register 76543210 type t3 t3 t1 t1 t1 t1 t1 t1 base address = 0x4000_0080 register name address(base+) port c data register pcdata 0x0000 port c output control register pccr 0x0004 port c function register 1 pcfr1 0x0008 port c open drain control register pcod 0x0028 port c pull-up control register pcpup 0x002c port c pull-down control register pcpdn 0x0030 port c input control register pcie 0x0038 page 7-19 TMPM376FDDFG/fdfg 2013/4/12 7.2.3.3 pcdata (port c data register) 7.2.3.4 pccr (port c output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pc7 to pc0 r/w port c data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pc7c pc6c pc5c pc4c pc3c pc2c pc1c pc0c after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pc7c to pc0c r/w output 0: disable 1: enable page 7-20 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.3.5 pcfr1 (port c function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pc7f1 pc6f1 pc5f1 pc4f1 pc3f1 pc2f1 pc1f1 pc0f1 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 pc7f1 r/w 0 : port 1 : ovv0 6 pc6f1 r/w 0: port 1: emg0 5 pc5f1 r/w 0: port 1: zo0 4 pc4f1 r/w 0: port 1: wo0 3 pc3f1 r/w 0: port 1: yo0 2 pc2f1 r/w 0: port 1: vo0 1 pc1f1 r/w 0: port 1: xo0 0 pc0f1 r/w 0: port 1: uo0 page 7-21 TMPM376FDDFG/fdfg 2013/4/12 7.2.3.6 pcod (port c open drain control register) 7.2.3.7 pcpup (port c pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbolpc7odpc6odpc5odpc4odpc3odpc2odpc1odpc0od after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pc7od to pc0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pc7up pc6up pc5up pc4up pc3up pc2up pc1up pc0up after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pc7up to pc0up r/w pull-up 0: disable 1: enable page 7-22 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.3.8 pcpdn (port c pull-down control register) 7.2.3.9 pcie (port c input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pc7dn pc6dn pc5dn pc4dn pc3dn pc2dn pc1dn pc0dn after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pc7dn to pc0dn r/w pull-down 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pc7ie pc6ie pc5ie pc4ie pc3ie pc2ie pc1ie pc0ie after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pc7ie to pc0ie r/w input 0: disable 1: enable page 7-23 TMPM376FDDFG/fdfg 2013/4/12 7.2.4 port d (pd0 to pd6) the port d is a general-purpose, 7-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purp ose input / output functi on, the port d performs the serial interface func- tion (sio / uart), the external signal interrupt input, the 16-bit timer input/output function and the encoder input function. reset initializes all bits of the port d as general- purpose ports with input, output, pull-up and pull-down dis- abled. the port d has two types of function register. if you us e the port d as a general-purpose port, set "0" to the corresponding bit of the two registers.if you use the port d as other than a general-purpose port, set "1" to the corresponding bit of the function register.do not set "1 " to the some function registers at the same time. to use the external interrupt input for releasing stop mode, select this function in the pdfr1 and enable input in the pdie register. these settings enable the interrupt input even if the cgstbycr page 7-24 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.4.3 pddata (port d data register) 7.2.4.4 pdcr (port d output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - pd6 pd5 pd4 pd3 pd2 pd1 pd0 after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6-0 pd6 to pd0 r/w port d data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - pd6c pd5c pd4c pd3c pd2c pd1c pd0c after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6-0 pd6c to pd0c r/w output 0: disable 1: enable page 7-25 TMPM376FDDFG/fdfg 2013/4/12 7.2.4.5 pdfr1 (port d function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - pd6f1 pd5f1 pd4f1 pd3f1 pd2f1 pd1f1 pd0f1 after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6 pd6f1 r/w 0: port 1:rxd2 5 pd5f1 r/w 0: port 1: txd2 4 pd4f1 r/w 0: port 1: sclk2 3 pd3f1 r/w 0: port 1: int9 2 pd2f1 r/w 0: port 1: encz0 1 pd1f1 r/w 0: port 1: encb0 0 pd0f1 r/w 0: port 1: enca0 page 7-26 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.4.6 pdfr2 (port d function register 2) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pd4f2 - - pd1f2 pd0f2 after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4 pd4f2 r/w 0: port 1: cts2 3-2 ? r read as 0. 1 pd1f2 r/w 0: port 1: tb5out 0 pd0f2 r/w 0: port 1: tb5in page 7-27 TMPM376FDDFG/fdfg 2013/4/12 7.2.4.7 pdod (port d open drain control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - pd6od pd5od pd4od pd3od pd2od pd1od pd0od after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6-0 pd6od to pd0od r/w 0 : cmos 1 : open-drain page 7-28 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.4.8 pdpup (port d pull-up control register) 7.2.4.9 pdpdn (port d pull-down control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - pd6up pd5up pd4up pd3up pd2up pd1up pd0up after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6-0 pd6up to pd0up r/w pull-up 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - pd6dn pd5dn pd4dn pd3dn pd2dn pd1dn pd0dn after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6-0 pd6dn to pd0dn r/w pull-down 0: disable 1: enable page 7-29 TMPM376FDDFG/fdfg 2013/4/12 7.2.4.10 pdie (port d input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - pd6ie pd5ie pd4ie pd3ie pd2ie pd1ie pd0ie after reset00000000 bit bit symbol type function 31-7 ? r read as 0. 6-0 pd6ie to pd0ie r/w input 0: disable 1: enable page 7-30 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.5 port e (pe0 to pe7) the port e is a general-purpose, 8-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input / output function, the port e performs the serial interface func- tion (sio / uart), the external signal interrupt input and the 16-bit timer input/output function. reset initializes all bits of the port e as general-purpose ports with input, output, pull-up and pull-down dis- abled. the port e has two types of function register. if you use the port e as a general-purpose port, set "0" to the corresponding bit of the two registers.if you use the port e as other than a general-purpose port, set "1" to the corresponding bit of the function register.do not set "1 " to the some function registers at the same time. to use the external interrupt input for releasing stop mode, select th is function in the pefr2 and enable input in the peie register. these settings enable the interrupt input even if the cgstbycr page 7-31 TMPM376FDDFG/fdfg 2013/4/12 7.2.5.3 pedata (port e data register) 7.2.5.4 pecr (port e output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pe7 to pe0 r/w port e data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7c pe6c pe5c pe4c pe3c pe2c pe1c pe0c after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pe7c to pe0c r/w output 0: disable 1: enable page 7-32 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.5.5 pefr1 (port e function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7f1 pe6f1 pe5f1 pe4f1 pe3f1 pe2f1 pe1f1 pe0f1 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7pe7f1 r/w0: port 1:tb3out 6pe6f1 r/w0: port 1:tb3in 5pe5f1 r/w0: port 1: tb2out 4pe4f1 r/w0: port 1: tb2in 3pe3f1 r/w0: port 1: tb4out 2pe2f1 r/w0: port 1: sclk0 1pe1f1 r/w0: port 1: rxd0 0pe0f1 r/w0: port 1: txd0 page 7-33 TMPM376FDDFG/fdfg 2013/4/12 7.2.5.6 pefr2 (port e function register 2) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7f2 pe6f2 - pe4f2 - pe2f2 - - after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7pe7f2 r/w0 : port 1 : int7 6pe6f2 r/w0: port 1: int6 5 ? r read as 0. 4pe4f2 r/w0: port 1: int5 3 ? r read as 0. 2pe2f2 r/w0: port 1: cts0 1-0 ? r read as 0. page 7-34 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.5.7 peod (port e open drain control register) 7.2.5.8 pepup (port e pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7od pe6od pe5od pe4od pe3od pe2od pe1od pe0od after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pe7od to pe0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7up pe6up pe5up pe4up pe3up pe2up pe1up pe0up after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pe7up to pe0up r/w pull-up 0: disable 1: enable page 7-35 TMPM376FDDFG/fdfg 2013/4/12 7.2.5.9 pepdn (port e pull-down control register) 7.2.5.10 peie (port e input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7dn pe6dn pe5dn pe4dn pe3dn pe2dn pe1dn pe0dn after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pe7dn to pe0dn r/w pull-down 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pe7ie pe6ie pe5ie pe4ie pe3ie pe2ie pe1ie pe0ie after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pe7ie to pe0ie r/w input 0: disable 1: enable page 7-36 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.6 port f (pf0 to pf4) the port f is a general-purpose, 5-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purp ose input / output function, the port f performs the serial interface func- tion (sio / uart), the 16-bit timer input/output function, the encoder input function and the operation mode setting. while a reset signal is in "0"state, the pf0 input and pull-up are enabled. at the rising edge of the reset sig- nal, if pf0 is "1", the device enters single mode and boots from the on-chip flash memory. if pf0 is "0", the device enters single boot mode and boots from the internal boot program. for details of single boot mode, refer to chapter "flash memory operation". reset initializes all bits of the port f as general-pur pose ports with input, output, pull-up and pull-down dis- abled. 7.2.6.1 port f circuit type 7.2.6.2 port f register 76543210 type ??? t11 t10 t15 t2 t20 base address = 0x4000_0140 register name address(base+) port f data register pfdata 0x0000 port f output control register pfcr 0x0004 port f function register 1 pffr1 0x0008 port f function register 2 pffr2 0x000c port f function register 3 pffr3 0x0010 port f open drain control register pfod 0x0028 port f pull-up control register pfpup 0x002c port f pull-down control register pfpdn 0x0030 port f input control register pfie 0x0038 page 7-37 TMPM376FDDFG/fdfg 2013/4/12 7.2.6.3 pfdata (port f data register) 7.2.6.4 pfcr (port f output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4 pf3 pf2 pf1 pf0 after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4-0 pf4 to pf0 r/w port f data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4c pf3c pf2c pf1c pf0c after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4-0 pf4c to pf0c r/w output 0: disable 1: enable page 7-38 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.6.5 pffr1 (port f function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4f1 pf3f1 pf2f1 pf1f1 pf0f1 after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4 pf4f1 r/w 0: port 1: encz1 3 pf3f1 r/w 0: port 1: encb1 2 pf2f1 r/w 0: port 1: enca1 1 pf1f1 r/w 0: port 1: tb7out 0 pf0f1 r/w 0: port 1: tb7in page 7-39 TMPM376FDDFG/fdfg 2013/4/12 7.2.6.6 pffr2 (port f function register 2) 7.2.6.7 pffr3 (port f function register 3) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4f2 pf3f2 pf2f2 - - after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4 pf4f2 r/w 0: port 1: rxd3 3 pf3f2 r/w 0: port 1: txd3 2 pf2f2 r/w 0: port 1: sclk3 1-0 ? r read as 0. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-----pf2f3-- after reset00000000 bit bit symbol type function 31-3 ? r read as 0. 2 pf2f3 r/w 0: port 1: cts3 1-0 ? r read as 0. page 7-40 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.6.8 pfod (port f open drain control register) 7.2.6.9 pfpup (port f pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4od pf3od pf2od pf1od pf0od after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4-0 pf4od to pf0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4up pf3up pf2up pf1up pf0up after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4-0 pf4up to pf0up r/w pull-up 0: disable 1: enable page 7-41 TMPM376FDDFG/fdfg 2013/4/12 7.2.6.10 pfpdn (port f pull-down control register) 7.2.6.11 pfie (port f input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4dn pf3dn pf2dn pf1dn pf0dn after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4-0 pf4dn to pf0dn r/w pull-down 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pf4ie pf3ie pf2ie pf1ie pf0ie after reset00000000 bit bit symbol type function 31-5 ? r read as 0. 4-0 pf4ie to pf0ie r/w input 0: disable 1: enable page 7-42 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.7 port g (pg0 to pg7) the port g is a general-purpose, 8-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input / output function, the port g performs the input/output port for three-phase motor control (pmd) function. reset initializes all bits of the port g as general- purpose ports with input, output, pull-up and pull-down dis- abled. 7.2.7.1 port g circuit type 7.2.7.2 port g register 76543210 type t3 t3 t1 t1 t1 t1 t1 t1 base address = 0x4000_0180 register name address(base+) port g data register pgdata 0x0000 port g output control register pgcr 0x0004 port g function register 1 pgfr1 0x0008 port g open drain control register pgod 0x0028 port g pull-up control register pgpup 0x002c port g pull-down control register pgpdn 0x0030 port g input control register pgie 0x0038 page 7-43 TMPM376FDDFG/fdfg 2013/4/12 7.2.7.3 pgdata (port g data register) 7.2.7.4 pgcr (port g output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbolpg7pg6pg5pg4pg3pg2pg1pg0 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7 to pg0 r/w port g data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pg7c pg6c pg5c pg4c pg3c pg2c pg1c pg0c after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7c to pg0c r/w output 0: disable 1: enable page 7-44 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.7.5 pgfr1 (port g function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pg7f1 pg6f1 pg5f1 pg4f1 pg3f1 pg2f1 pg1f1 pg0f1 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7 pg7f1 r/w 0: port 1: ovv1 6 pg6f1 r/w 0: port 1: emg1 5 pg5f1 r/w 0: port 1: zo1 4 pg4f1 r/w 0: port 1: wo1 3 pg3f1 r/w 0: port 1: yo1 2 pg2f1 r/w 0: port 1: vo1 1 pg1f1 r/w 0: port 1: xo1 0 pg0f1 r/w 0: port 1: uo1 page 7-45 TMPM376FDDFG/fdfg 2013/4/12 7.2.7.6 pgod (port g open drain control register) 7.2.7.7 pgpup (port g pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pg7od pg6od pg5od pg4od pg3od pg2od pg1od pg0od after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7od to pg0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pg7up pg6up pg5up pg4up pg3up pg2up pg1up pg0up after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7up to pg0up r/w pull-up 0: disable 1: enable page 7-46 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.7.8 pgpdn (port g pull-down control register) 7.2.7.9 pgie (port g input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pg7dn pg6dn pg5dn pg4dn pg3dn pg2dn pg1dn pg0dn after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7dn to pg0dn r/w pull-down 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pg7ie pg6ie pg5ie pg4ie pg3ie pg2ie pg1ie pg0ie after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pg7ie to pg0ie r/w input 0: disable 1: enable page 7-47 TMPM376FDDFG/fdfg 2013/4/12 7.2.8 port h (ph0 to ph7) the port h is a general-purpose, 8-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input / output function, the port h performs the analog input of the ad converter and the external signal interrupt input. reset initializes all bits of the port h as general- purpose ports with input, output, pull-up and pull-down dis- abled. to use the external interrupt input for releasing stop mode, select this function in the phfr1 and enable input in the phie register. these settings enable the interrupt input even if the cgstbycr page 7-48 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.8.3 phdata (port h data register) 7.2.8.4 phcr (port h output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 ph7 to ph0 r/w port h data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol ph7c ph6c ph5c ph4c ph3c ph2c ph1c ph0c after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 ph7c to ph0c r/w output 0: disable 1: enable page 7-49 TMPM376FDDFG/fdfg 2013/4/12 7.2.8.5 phfr1 (port h function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-----ph2f1ph1f1ph0f1 after reset00000000 bit bit symbol type function 31-3 ? r read as 0. 2 ph2f1 r/w 0: port 1: int2 1 ph1f1 r/w 0: port 1: int1 0 ph0f1 r/w 0: port 1: int0 page 7-50 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.8.6 phod (port h open drain control register) 7.2.8.7 phpup (port h pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbolph7odph6odph5odph4odph3odph2odph1odph0od after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 ph7od to ph0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol ph7up ph6up ph5up ph4up ph3up ph2up ph1up ph0up after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 ph7up to ph0up r/w pull-up 0: disable 1: enable page 7-51 TMPM376FDDFG/fdfg 2013/4/12 7.2.8.8 phpdn (port h pull-down control register) 7.2.8.9 phie (port h input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol ph7dn ph6dn ph5dn ph4dn ph3dn ph2dn ph1dn ph0dn after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 ph7dn to ph0dn r/w pull-down 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol ph7ie ph6ie ph5ie ph4ie ph3ie ph2ie ph1ie ph0ie after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 ph7ie to ph0ie r/w input 0: disable 1: enable page 7-52 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.9 port i (pi0 to pi3) the port i is a general-purpose, 4-bit input / output port. for this port, in puts and outputs can be specified in units of bits. besides the general-purpose input / output function, the port i performs the analog input of the ad converter. reset initializes all bits of the port i as general- purpose ports with input, output, pull-up and pull-down dis- abled. note:unless you use all the bits of port i as analog input pins, conversion accuracy may be reduced.be sure to ver- ify that this causes no problem on your system. 7.2.9.1 port i circuit type 7.2.9.2 port i register 76543210 type ???? t16 t16- t16 t16 base address = 0x4000_0200 register name address(base+) port i data register pidata 0x0000 port i output control register picr 0x0004 port i open drain control register piod 0x0028 port i pull-up control register pipup 0x002c port i pull-down control register pipdn 0x0030 port i input control register piie 0x0038 page 7-53 TMPM376FDDFG/fdfg 2013/4/12 7.2.9.3 pidata (port i data register) 7.2.9.4 picr (port i output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pi3pi2pi1pi0 after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3-0 pi3 to pi0 r/w port i data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pi3cpi2c-pi1c-pi0c- after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3-0 pi3c to pi0c r/w output 0: disable 1: enable page 7-54 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.9.5 piod (port i open drain control register) 7.2.9.6 pipup (port i pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pi3odpi2odpi1odpi0od after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3-0 pi3od-pi0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pi3uppi2uppi1uppi0up after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3-0 pi3up to pi0up r/w pull-up 0: disable 1: enable page 7-55 TMPM376FDDFG/fdfg 2013/4/12 7.2.9.7 pipdn (port i pull-down control register) 7.2.9.8 piie (port i input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pi3dnpi2dnpi1dnpi0dn after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3-0 pi3dn to pi0dn r/w pull-down 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pi3iepi2iepi1iepi0ie after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3-0 pi3ie to pi0ie r/w input 0: disable 1: enable page 7-56 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.10 port j (pj0 to pj7) the port j is a general-purpose, 8-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input / output function, the port j perfor ms the analog input of the ad converter and the external signal interrupt input. reset initializes all bits of the port j as general- purpose ports with input, output, pull-up and pull-down dis- abled. to use the external interrupt input for releasing stop mode, select this function in the pjfr1 and enable input in the pjie register. these settings enable the interrupt input even if the cgstbycr page 7-57 TMPM376FDDFG/fdfg 2013/4/12 7.2.10.3 pjdata (port j data register) 7.2.10.4 pjcr (port j output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7 to pj0 r/w port j data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pj7c pj6c pj5c pj4c pj3c pj2c pj1c pj0c a f t e r r e s e t00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7c to pj0c r/w output 0: disable 1: enable page 7-58 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.10.5 pjfr1 (port j function register 1) 7.2.10.6 pjod (port j open drain control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbolpj7f1pj6f1------ after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7pj7f1 r/w0: port 1: intd 6pj6f1 r/w0: port 1: intc 5-0 ? r read as 0. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pj7od pj6od pj5od pj4od pj3od pj2od pj1od pj0od after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7od to pj0od r/w 0 : cmos 1 : open-drain page 7-59 TMPM376FDDFG/fdfg 2013/4/12 7.2.10.7 pjpup (port j pull-up control register) 7.2.10.8 pjpdn (port j pull-down control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pj7up pj6up pj5up pj4up pj3up pj2up pj1up pj0up after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7up to pj0up r/w pull-up 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pj7dn pj6dn pj5dn pj4dn pj3dn pj2dn pj1dn pj0dn after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7dn-pj0dn r/w pull-down 0: disable 1: enable page 7-60 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.10.9 pjie (port j input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol pj7ie pj6ie pj5ie pj4ie pj3ie pj2ie pj1ie pj0ie after reset00000000 bit bit symbol type function 31-8 ? r read as 0. 7-0 pj7ie to pj0ie r/w input 0: disable 1: enable page 7-61 TMPM376FDDFG/fdfg 2013/4/12 7.2.11 port k (pk0 to pk1) the port k is a general-purpose, 2-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input / output function, the port k performs the analog input of the ad converter and the external signal interrupt input. reset initializes all bits of the port k as general- purpose ports with input, output, pull-up and pull-down dis- abled. to use the external interrupt input for releasing stop mode, select this function in the pkfr1 and enable input in the pkie register. these settings enable the interrupt input even if the cgstbycr page 7-62 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.11.3 pkdata (port k data register) 7.2.11.4 pkcr (port k output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pk1pk0 after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pk1 to pk0 r/w port k data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - - pk1c pk0c after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pk1c to pk0c r/w output 0: disable 1: enable page 7-63 TMPM376FDDFG/fdfg 2013/4/12 7.2.11.5 pkfr1 (port k function register 1) 7.2.11.6 pkod (port k open drain control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pk1f1pk0f1 after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1pk1f1 r/w0: port 1: intf 0pk0f1 r/w0: port 1: inte 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pk1odpk0od after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pk1od to pk0od r/w 0 : cmos 1 : open-drain page 7-64 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.11.7 pkpup (port k pull-up control register) 7.2.11.8 pkpdn (port k pull-down control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pk1uppk0up after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pk1up to pk0up r/w pull-up 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pk1dnpk0dn after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pk1dn- pk0dn r/w pull-down 0: disable 1: enable page 7-65 TMPM376FDDFG/fdfg 2013/4/12 7.2.11.9 pkie (port k input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pk1iepk0ie after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pk1ie-pk0ie r/w input 0: disable 1: enable page 7-66 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.12 port l (pl0 to pl1) the port l is a general-purpose, 2-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input / output function, the port l performs the external signal inter- rupt input. reset initializes all bits of the port l as general-purpose ports with input disabled. to use the external interrupt input for releasing stop mode, select th is function in the plfr1 and enable input in the plie register. these settings enable the interrupt input even if the cgstbycr page 7-67 TMPM376FDDFG/fdfg 2013/4/12 7.2.12.3 pldata (port l data register) 7.2.12.4 plfr1 (port l function register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pl1pl0 after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pl1 to pl0 r/w port l data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pl1f1pl0f1 after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1pl1f1 r/w0: port 1: inta 0pl0f1 r/w0: port 1: intb page 7-68 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.12.5 plie (port l input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pl1iepl0ie after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pl1ie to pl0ie r/w input 0: disable 1: enable page 7-69 TMPM376FDDFG/fdfg 2013/4/12 7.2.13 port m (pm0 to pm1) the port m is a general-purpose, 2-bit input/output port . for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input/o utput function, the port m performs the high-speed oscillator1(x1 and x2) by cgosccr page 7-70 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.13.3 pmdata (port m data register) 7.2.13.4 pmcr (port m output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pm1pm0 after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pm1 to pm0 r/w port m data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pm1cpm0c after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pm1c to pm0c r/w output 0: disable 1: enable page 7-71 TMPM376FDDFG/fdfg 2013/4/12 7.2.13.5 pmod (port m open drain control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pm1odpm0od after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pm1od to pm0od r/w 0 : cmos 1 : open-drain page 7-72 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.13.6 pmpup (port m pull-up control register) 7.2.13.7 pmpdn (port m pull-down control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pm1uppm0up after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pm1up to pm0up r/w pull-up 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pm1dnpm0dn after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pm1dn to pm0dn r/w pull-down 0: disable 1: enable page 7-73 TMPM376FDDFG/fdfg 2013/4/12 7.2.13.8 pmie (port m input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol------pm1iepm0ie after reset00000000 bit bit symbol type function 31-2 ? r read as 0. 1-0 pm1ie to pm0ie r/w input 0: disable 1: enable page 7-74 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.14 port n (pn0 to pn3) the port n is a general-purpose, 4-bit input / output port. for this port, inputs and outputs can be specified in units of bits. besides the general-purpose input / output function, the port n performs the serial bus interface function (i2c / sio) and the 16-bit timer input function. reset initializes all bits of the port n as general- purpose ports with input, output, pull-up and pull-down dis- abled. 7.2.14.1 port n circuit type 7.2.14.2 port n register 76543210 type - - - - t3 t22 t22 t22 base address = 0x4000_0340 register name address(base+) port n data register pndata 0x0000 port n output control register pncr 0x0004 port n function register 1 pnfr1 0x0008 port n open drain control register pnod 0x0028 port n pull-up control register pnpup 0x002c port n pull-down control register pnpdn 0x0030 port n input control register pnie 0x0038 page 7-75 TMPM376FDDFG/fdfg 2013/4/12 7.2.14.3 pndata (port n data register) 7.2.14.4 pncr (port n output control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pn3pn2pn1pn0 after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3-0 pn3 to pn0 r/w port n data register 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pn3cpn2cpn1cpn0c after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3-0 pn3c to pn0c r/w output 0: disable 1: enable page 7-76 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.14.5 pnfr1 (port n function register 1) note: when you set 1 to page 7-77 TMPM376FDDFG/fdfg 2013/4/12 7.2.14.6 pnod (port n open drain control register) 7.2.14.7 pnpup (port n pull-up control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pn3odpn2odpn1odpn0od after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3-0 pn3od to pn0od r/w 0 : cmos 1 : open-drain 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pn3uppn2uppn1uppn0up after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3-0 pn3up to pn0up r/w pull-up 0: disable 1: enable page 7-78 7. input / output ports 7.2 port functions TMPM376FDDFG/fdfg 2013/4/12 7.2.14.8 pnpdn (port n pull-down control register) 7.2.14.9 pnie (port n input control register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pn3dnpn2dnpn1dnpn0dn after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3-0 pn3dn to pn0dn r/w pull-down 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol----pn3iepn2iepn1iepn0ie after reset00000000 bit bit symbol type function 31-4 ? r read as 0. 3-0 pn3ie to pn0ie r/w input 0: disable 1: enable page 7-79 TMPM376FDDFG/fdfg 2013/4/12 7.3 block diagra ms of ports 7.3.1 port types the ports are classified as shown below. please refer to the following pages for the block diagrams of each port type. dot lines in the figure indicate the part of the equivale nt circuit described in the "block diagrams of ports". table 7-3 function lists type gp port function1 function2 function3 analog pull-up pull-dn program- mable open-drain note t1 i / o output ??? rr function output triggered by enable signal t2 i / o output ??? rr t3 i / o input ??? rr t4 i / o input (int) ??? rr t5 input input (int) ?????? t6 i / o i / o ??? nor ?? function output triggered by enable signal t7 i / o input ??? nor ?? t8 i / o input ???? nor ? t9 i / o i / o input ?? rr t10 i / o input output ?? rr t11 i / o input input ?? rr t12 i / o input input(int) ?? rr t13 i / o output output ?? rr t14 i / o output i / o ?? rr t15 i / o input i / o input ? rr t16 i / o ??? rr t17 i / o input(int) ?? rr t18 i / o output ??? r ?? t19 i / o output ??? nor ?? function output triggered by enable signal t20 i / o input ??? nor nor boot input enabled during reset t21 i / o - (osc1) ??? rr high-speed osscillator (external) t22 i / o i / o ??? r int : interrupt input - : not exist o : exist r: forced disable during reset nor: unaffected by reset page 7-80 7. input / output ports 7.3 block diagrams of ports TMPM376FDDFG/fdfg 2013/4/12 7.3.2 type t1 figure 7-1 port type t1 pxpup (pull-up control) i /o port port read 0 1 1 0 reset drive disable in stop mode (set by page 7-81 TMPM376FDDFG/fdfg 2013/4/12 7.3.3 type t2 figure 7-2 port type t2 pxpup (pull-up control) port read 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output controll) pxpdn (pull-down control) function output 0 1 internal data bus i /o port programable pull-up and pull-down drive disable in stop mode (set by page 7-82 7. input / output ports 7.3 block diagrams of ports TMPM376FDDFG/fdfg 2013/4/12 7.3.4 type t3 figure 7-3 port type t3 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output controll) pxpdn (pull-down control) port read i /o port programable pull-up and pull-down drive disable in stop mode (set by page 7-83 TMPM376FDDFG/fdfg 2013/4/12 7.3.5 type t4 figure 7-4 port type t4 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output controll) pxpdn (pull-down control) + p v g t t w r v + p r w v internal data bus port read i /o port drive disable in stop mode (set by page 7-84 7. input / output ports 7.3 block diagrams of ports TMPM376FDDFG/fdfg 2013/4/12 7.3.6 type t5 figure 7-5 port type t5 0 1 pxie (input control) pxfr1 (function control) , q w h u u x s w , q s x w i /o port drive disable in stop mode (set by page 7-85 TMPM376FDDFG/fdfg 2013/4/12 7.3.7 type t6 figure 7-6 port type t6 pxpup (pull-up control) 0 1 1 0 pxie (input control) pxdata (output latch) pxfr1 (function control) pxcr (output controll) 0 1 1 0 ( w p e v k q p + p r w v port read function output function output enable i /o port drive disable in stop mode (set by page 7-86 7. input / output ports 7.3 block diagrams of ports TMPM376FDDFG/fdfg 2013/4/12 7.3.8 type t7 figure 7-7 port type t7 pxpup (pull-up control) 0 1 pxie (input control) pxdata (output latch) pxfr1 (?(??) pxcr (output control) 1 0 reset ( w p e v k q p + p r w v port read i /o port drive disable in stop mode (set by page 7-87 TMPM376FDDFG/fdfg 2013/4/12 7.3.9 type t8 figure 7-8 port type t8 0 1 pxie (input control) pxdata (output latch) pxfr1 (?(??) pxcr (output control) 1 0 ( w p e v k q p + p r w v reset pxpdn (pull-down control) internal data bus port read i /o port drive disable in stop mode (set by page 7-88 7. input / output ports 7.3 block diagrams of ports TMPM376FDDFG/fdfg 2013/4/12 7.3.10 type t9 figure 7-9 port type t9 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) 0 1 ( w p e v k q p + p r w v pxfr2 (function control ( w p e v k q p input2 i /o port drive disable in stop mode (set by page 7-89 TMPM376FDDFG/fdfg 2013/4/12 7.3.11 type t10 figure 7-10 port type t10 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) 0 1 ( w p e v k q p + p r w v1 pxfr2 (function control) i /o port drive disable in stop mode (set by page 7-90 7. input / output ports 7.3 block diagrams of ports TMPM376FDDFG/fdfg 2013/4/12 7.3.12 type t11 figure 7-11 port type t11 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) ( w p e v k q p + p r w v1 pxfr2 (function control) ( w p e v k q p input2 internal data bus port read i /o port drive disable in stop mode (set by page 7-91 TMPM376FDDFG/fdfg 2013/4/12 7.3.13 type t12 figure 7-12 port type t12 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) ( w p e v k q p input1 pxfr2 (function control) + p v g t t w r v + p r w v i /o port drive disable in stop mode (set by page 7-92 7. input / output ports 7.3 block diagrams of ports TMPM376FDDFG/fdfg 2013/4/12 7.3.14 type t13 figure 7-13 port type t13 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) 0 1 pxfr2 (function control) 0 1 internal data bus function output1 function output2 port read i /o port drive disable in stop mode (set by page 7-93 TMPM376FDDFG/fdfg 2013/4/12 7.3.15 type t14 figure 7-14 port type t14 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) pxfr2 (function control) + p v g t t w r v + p r w v 0 1 internal data bus function output port read i /o port drive disable in stop mode (set by page 7-94 7. input / output ports 7.3 block diagrams of ports TMPM376FDDFG/fdfg 2013/4/12 7.3.16 type t15 figure 7-15 port type t15 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain contro) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) 0 1 ( w p e v k q p + p r w v1 pxfr2 (function control) pxfr3 (function control) ( w p e v k q p + p r w v2 ( w p e v k q p + p r w v3 i /o port drive disable in stop mode (set by page 7-95 TMPM376FDDFG/fdfg 2013/4/12 7.3.17 type t16 figure 7-16 port type t16 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxcr (output control) pxpdn (pull-down control) analog input internal data bus port read i /o port drive disable in stop mode (set by page 7-96 7. input / output ports 7.3 block diagrams of ports TMPM376FDDFG/fdfg 2013/4/12 7.3.18 type t17 figure 7-17 port type t17 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) interrupt input analog input i /o port drive disable in stop mode (set by page 7-97 TMPM376FDDFG/fdfg 2013/4/12 7.3.19 type t18 figure 7-18 port type t18 pxpup (pull-up control) 0 1 1 0 pxie (input control) pxdata (output latch) pxfr1 (function control) pxcr (output control) 0 1 reset port read internal data bus function output1 i /o port drive disable in stop mode (set by page 7-98 7. input / output ports 7.3 block diagrams of ports TMPM376FDDFG/fdfg 2013/4/12 7.3.20 type t19 figure 7-19 port type t19 pxpup (pull-up control) 1 0 pxie (input control) pxdata (output latch) pxfr1 (function control) pxcr (output control) 0 1 0 1 i /o port drive disable in stop mode (set by page 7-99 TMPM376FDDFG/fdfg 2013/4/12 7.3.21 type t20 pxpup (pull-up control) 0 1 reset pxie (input control)) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) ( w p e v k q p + p r w v1 boot port read internal data bus i /o port drive disable in stop mode (set by page 7-100 7. input / output ports 7.3 block diagrams of ports TMPM376FDDFG/fdfg 2013/4/12 7.3.22 type t21 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxcr (output control) pxpdn (pull-down control) external high-speed oscillator port read internal data bus i /o port drive disable in stop mode (set by page 7-101 TMPM376FDDFG/fdfg 2013/4/12 7.3.23 type t22 pxpup (pull-up control) 0 1 reset pxie (input control) pxod (open drain control) pxdata (output latch) pxfr1 (function control) pxcr (output control) pxpdn (pull-down control) 0 1 function input1 port read internal data bus function output1 i /o port drive disable in stop mode (set by page 7-102 7. input / output ports 7.4 appendix port setting list TMPM376FDDFG/fdfg 2013/4/12 7.4 appendix port setting list the following table shows the re gister setting for each function. initialization of the ports where the [ ? ]does not exist in the "after reset" field is set to "0" for all register settings. setting for the bit "x" can be arbitrarily-specified. 7.4.1 port a setting table 7-4 port setting list(port a) pin port type function after reset pacr pafr1 pafr2 paod papup papdn paie pa0 t12 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 tb0in (input) 0 1 0 x x x 1 int7 (input) 0 0 1 x x x 1 pa1 t2 input port 0 0 - x x x 1 output port 1 0 - x x x 0 tb0out(output) 1 1 - x x x 0 pa2 t12 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 tb1in (input) 0 1 0 x x x 1 int4 (input) 0 0 1 x x x 1 pa3 t2 input port 0 0 - x x x 1 output port 1 0 - x x x 0 tb1out(output) 1 1 - x x x 0 pa4 t9 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 sclk1 (i / o) 110xxx1 cts1 (input) 0 0 1 x x x 1 pa5 t13 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 txd1 (output) 1 1 0 x x x 0 tb6out(output) 1 0 1 x x x 0 pa6 t11 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 rxd1 (input) 0 1 0 x x x 1 tb6in (input) 0 0 1 x x x 1 pa7 t12 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 tb4in (input) 0 1 0 x x x 1 int8 (input) 0 0 1 x x x 1 page 7-103 TMPM376FDDFG/fdfg 2013/4/12 7.4.2 port b setting table 7-5 port setting list(port b) pin port type function after reset pbcr pbfr1 pbod pbpup pbpdn pbie pb0 t18 input port 0 0 x x x 1 output port 10xxx0 traceclk (output) 110000 pb1 t18 input port 0 0 x x x 1 output port 10xxx0 tracedata0 (output) 110000 pb2 t18 input port 0 0 x x x 1 output port 10xxx0 tracedata1 (output) 110000 pb3 t6 input port 0 0 x x x 1 output port 10xxx0 tms / swdio (i / o) 110101 pb4 t8 input port 0 0 x x x 1 output port 10xxx0 tck / swclk (input) 010011 pb5 t19 input port 0 0 x x x 1 output port 10xxx0 tdo / swv (output) 110000 pb6 t7 input port 0 0 x x x 1 output port 10xxx0 tdi (input) 010101 pb7 t7 input port 0 0 x x x 1 output port 10xxx0 trst (input) 0 1 0111 page 7-104 7. input / output ports 7.4 appendix port setting list TMPM376FDDFG/fdfg 2013/4/12 7.4.3 port c setting table 7-6 port setting list(port c) pin port type function after reset pccr pcfr1 pcod pcpup pcpdn pcie pc0 t1 input port 0 0 x x x 1 output port 10xxx0 uo0 (output) 1 1 x x x 0 pc1 t1 input port 0 0 x x x 1 output port 10xxx0 xo0 (output) 1 1 x x x 0 pc2 t1 input port 0 0 x x x 1 output port 10xxx0 vo0 (output) 1 1 x x x 0 pc3 t1 input port 0 0 x x x 1 output port 10xxx0 yo0 (output) 1 1 x x x 0 pc4 t1 input port 0 0 x x x 1 output port 10xxx0 wo0 (output) 1 1 x x x 0 pc5 t1 input port 0 0 x x x 1 output port 10xxx0 zo0 (output) 1 1 x x x 0 pc6 t3 input port 0 0 x x x 1 output port 10xxx0 emg0 (input) 0 1 x x x 1 pc7 t3 input port 0 0 x x x 1 output port 10xxx0 ovv0 (input) 0 1 x x x 1 page 7-105 TMPM376FDDFG/fdfg 2013/4/12 7.4.4 port d setting table 7-7 port setting list(port d) pin port type function after reset pdcr pdfr1 pdfr2 pdod pdpup pdpdn pdie pd0 t11 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 enca0 (input) 0 1 0 x x x 1 tb5in (input) 0 0 1 x x x 1 pd1 t10 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 encb0 (input) 0 1 0 x x x 1 tb5out (output) 1 0 1 x x x 0 pd2 t3 input port 0 0 - x x x 1 output port 1 0 - x x x 0 encz0(input) 0 1 - x x x 1 pd3 t4 input port 0 0 - x x x 1 output port 1 0 - x x x 0 int9 (input) 0 1 - x x x 1 pd4 t9 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 sclk2 (i / o) 110xxx1 cts2 (input) 0 0 1 x x x 1 pd5 t2 input port 0 0 - x x x 1 output port 1 0 - x x x 0 txd2 (output) 1 1 - x x x 0 pd6 t3 input port 0 0 - x x x 1 output port 1 0 - x x x 0 rxd2 (input) 0 1 - x x x 1 page 7-106 7. input / output ports 7.4 appendix port setting list TMPM376FDDFG/fdfg 2013/4/12 7.4.5 port e setting table 7-8 port setting list(port e) pin port type function after reset pecr pefr1 pefr2 peod pepup pepdn peie pe0 t2 input port 0 0 - x x x 1 output port 1 0 - x x x 0 txd0 (output) 1 1 - x x x 0 pe1 t3 input port 0 0 - x x x 1 output port 1 0 - x x x 0 rxd0 (input) 0 1 - x x x 1 pe2 t9 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 sclk0 (i / o) 110xxx1 cts0 (input) 0 0 1 x x x 1 pe3 t2 input port 0 0 - x x x 1 output port 1 0 - x x x 0 tb4out (output) 1 1 - x x x 0 pe4 t12 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 tb2in (input) 0 1 0 x x x 1 int5 (input) 0 0 1 x x x 1 pe5 t2 input port 0 0 - x x x 1 output port 1 0 - x x x 0 tb2out (output) 1 1 - x x x 0 pe6 t12 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 tb3in (input) 0 1 0 x x x 1 int6 (input) 0 0 1 x x x 1 pe7 t14 input port 0 0 0 x x x 1 output port 1 0 0 x x x 0 tb3out (output) 1 1 0 x x x 0 int7 (input) 0 0 1 x x x 1 page 7-107 TMPM376FDDFG/fdfg 2013/4/12 7.4.6 port f setting note:the pf0 input and pull-up are enabled and act as boot input pin while a reset is in "low" state table 7-9 port setting list(port f) pin port type function after reset pfcr pffr1 pffr2 pffr3 pfod pfpup pfpdn pfie pf0 t20 input port 0 0 - - x x x 1 output port 1 0 - - x x x 0 tb7in (input) 0 1 - - x x x 1 pf1 t2 input port 0 0 - - x x x 1 output port 1 0 - - x x x 0 tb7out (output) 1 1 - - x x x 0 pf2 t15 input port 0 0 0 0 x x x 1 output port 1 0 0 0 x x x 0 enca1 (input) 0 1 0 0 x x x 1 sclk3 (i / o) 1 0 1 0 x x x 1 cts3 (input) 0 0 0 1 x x x 1 pf3 t10 input port 0 0 0 - x x x 1 output port 1 0 0 - x x x 0 encb1 (input) 0 1 0 - x x x 1 txd3 (output) 1 0 1 - x x x 0 pf4 t11 input port 0 0 0 - x x x 1 output port 1 0 0 - x x x 0 encz1 (input) 0 1 0 - x x x 1 rxd3 (input) 0 0 1 - x x x 1 page 7-108 7. input / output ports 7.4 appendix port setting list TMPM376FDDFG/fdfg 2013/4/12 7.4.7 port g setting table 7-10 port setting list(port g) pin port type function after reset pgcr pgfr1 pgod pgpup pgpdn pgie pg0 t1 input port 0 0 x x x 1 output port 10xxx0 uo1 (output) 1 1 x x x 0 pg1 t1 input port 0 0 x x x 1 output port 10xxx0 xo1 (output) 1 1 x x x 0 pg2 t1 input port 0 0 x x x 1 output port 10xxx0 vo1 (output) 1 1 x x x 0 pg3 t1 input port 0 0 x x x 1 output port 10xxx0 yo1 (output) 1 1 x x x 0 pg4 t1 input port 0 0 x x x 1 output port 10xxx0 wo1 (output) 1 1 x x x 0 pg5 t1 input port 0 0 x x x 1 output port 10xxx0 zo1 (output) 1 1 x x x 0 pg6 t3 input port 0 0 x x x 1 output port 10xxx0 emg1 (input) 0 1 x x x 1 pg7 t3 input port 0 0 x x x 1 output port 10xxx0 ovv1 (input) 0 1 x x x 1 page 7-109 TMPM376FDDFG/fdfg 2013/4/12 7.4.8 port h setting table 7-11 port setting list(port h) pin port type function after reset phcr phfr1 phod phpup phpdn phie ph0 t17 input port 0 0 x x x 1 output port 10xxx0 analog input 0 0 0000 int0 (input) 0 1 x x x 1 ph1 t17 input port 0 0 x x x 1 output port 10xxx0 analog input 0 0 0000 int1 (input) 0 1 x x x 1 ph2 t17 input port 0 0 x x x 1 output port 10xxx0 analog input 0 0 0000 int2 (input) 0 1 x x x 1 ph3 t16 input port 0 - x x x 1 output port 1-xxx0 analog input 0 - 0000 ph4 t16 input port 0 - x x x 1 output port 1-xxx0 analog input 0 - 0000 ph5 t16 input port 0 - x x x 1 output port 1-xxx0 analog input 0 - 0000 ph6 t16 input port 0 - x x x 1 output port 1-xxx0 analog input 0 - 0000 ph7 t16 input port 0 - x x x 1 output port 1-xxx0 analog input 0 - 0000 page 7-110 7. input / output ports 7.4 appendix port setting list TMPM376FDDFG/fdfg 2013/4/12 7.4.9 port i setting table 7-12 port setting list(port i) pin port type function after reset picr piod pipup pipdn piie pi0 t16 input port 0xxx1 output port 1 x x x 0 analog input 00000 pi1 t16 input port 0xxx1 output port 1 x x x 0 analog input 00000 pi2 t16 input port 0xxx1 output port 1 x x x 0 analog input 00000 pi3 t16 input port 0xxx1 output port 1 x x x 0 analog input 00000 page 7-111 TMPM376FDDFG/fdfg 2013/4/12 7.4.10 port j setting table 7-13 port setting list(port j) pin port type function after reset pjcr pjfr1 pjod pjpup pjpdn pjie pj0 t16 input port 0 - x x x 1 output port 1 - x x x 0 analog input 0 - 0000 pj1 t16 input port 0 - x x x 1 output port 1 - x x x 0 analog input 0 - 0000 pj2 t16 input port 0 - x x x 1 output port 1 - x x x 0 analog input 0 - 0000 pj3 t16 input port 0 - x x x 1 output port 1 - x x x 0 analog input 0 - 0000 pj4 t16 input port 0 - x x x 1 output port 1 - x x x 0 analog input 0 - 0000 pj5 t16 input port 0 - x x x 1 output port 1 - x x x 0 analog input 0 - 0000 pj6 t17 input port 0 0 x x x 1 output port 1 0 x x x 0 analog input 000000 intc (input) 0 1 x x x 1 pj7 t17 input port 0 0 x x x 1 output port 1 0 x x x 0 analog input 000000 intd (input) 0 1 x x x 1 page 7-112 7. input / output ports 7.4 appendix port setting list TMPM376FDDFG/fdfg 2013/4/12 7.4.11 port k setting 7.4.12 port l setting 7.4.13 port m setting note:x1,x2 exist table 7-14 port setting list(port k) pin port type function after reset pkcr pkfr1 pkod pkpup pkpdn pkie pk0 t17 input port 0 0 x x x 1 output port 10xxx0 analog input 0 0 0000 inte (input) 0 1 x x x 1 pk1 t17 input port 0 0 x x x 1 output port 10xxx0 analog input 0 0 0000 intf (input) 0 1 x x x 1 table 7-15 port setting list(port l) pin port type function after reset plfr1 plie pl0 t5 input port 0 1 output port 0 0 intb (input) 1 1 pl1 t5 input port 0 1 output port 0 0 inta (input) 1 1 table 7-16 port setting list(port m) pin port type function after reset pmcr pmod pmpup pmpdn pmie pm0 t21 input port 0xxx1 output port 1 x x x 0 pm1 t21 input port 0xxx1 output port 1 x x x 0 page 7-113 TMPM376FDDFG/fdfg 2013/4/12 7.4.14 port n setting note:when you set 1 to page 7-114 7. input / output ports 7.4 appendix port setting list TMPM376FDDFG/fdfg 2013/4/12 page 8-1 TMPM376FDDFG/fdfg 2013/4/12 8. 16-bit timer / event counters (tmrb) 8.1 outline tmrb operate in the following four operation modes: ? 16-bit interval timer mode ? 16-bit event counter mode ? 16-bit programmable pulse generation mode (ppg) ? external trigger programmable pulse generation mode (ppg) the use of the capture function allows tmrb to perform the following two measurements. ? one shot pulse output by an external trigger ? pulse width measurement in the following explanation of this s ection, "x" indicates a channel number. page 8-2 8. 16-bit timer / event counters (tmrb) 8.2 differences in the specifications TMPM376FDDFG/fdfg 2013/4/12 8.2 differences in the specifications TMPM376FDDFG/fdfg contains 8-channel of tmrb. each channel functions independently and the channels oper ate in the same way except for the differences in their specification as shown in table 8-1. table 8-1 differences in the specifications of tmrb modules specification external pins interrupt internal connection channel external clock / capture trigger input pins timer flip-flop output pin capture interrupt tmrb interrupt adc conversion start timer flip-flop output tbxout from sio/uart (txtrg: transfer clock) signal name signal name tmrb0 tb0in tb0out intcap00 intcap01 inttb00 inttb01 tmrb1 tb1in tb1out intcap10 intcap11 inttb10 inttb11 tmrb2 tb2in tb2out intcap20 intcap21 inttb20 inttb21 tmrb3 tb3in tb3out intcap30 intcap31 inttb30 inttb31 tmrb4 tb4in tb4out intcap40 intcap41 inttb40 inttb41 sio0,sio1 tmrb5 tb5in tb5out intcap50 intcap51 inttb50 inttb51 inttb51 tmrb6 tb6in tb6out intcap60 intcap61 inttb60 inttb61 tmrb7 tb7in tb7out intcap70 intcap71 inttb70 inttb71 sio2,sio3 page 8-3 TMPM376FDDFG/fdfg 2013/4/12 8.3 configuration each channel consists of a 16-bit up-counter, two 16-bit timer registers (double-buffe red), two 16-bit capture reg- isters, two comparators, a capt ure input control, a timer flip-flop and its associated control circuit. timer operation modes and the timer flip-flop ar e controlled by a register. figure 8-1 tmrbx blo ck diagram (x= 0 to 7) 2 4 8 16 32 t1 t4 t16 t1 t4 t16 tmrbx interrupt inttbx1 inttbx0 tbxin internal data bus run/ clear tbxmod page 8-4 8. 16-bit timer / event counters (tmrb) 8.4 registers TMPM376FDDFG/fdfg 2013/4/12 8.4 registers 8.4.1 register list according to channel the following table shows the register names and addresses of each channel. channel x base address channel0 0x4001_0000 channel1 0x4001_0040 channel2 0x4001_0080 channel3 0x4001_00c0 channel4 0x4001_0100 channel5 0x4001_0140 channel6 0x4001_0180 channel7 0x4001_01c0 register name (x=0 to 7) address (base+) enable register tbxen 0x0000 run register tbxrun 0x0004 control register tbxcr 0x0008 mode register tbxmod 0x000c flip-flop control register tbxffcr 0x0010 status register tbxst 0x0014 interrupt mask register tbxim 0x0018 up counter capture register tbxuc 0x001c timer register 0 tbxrg0 0x0020 timer register 1 tbxrg1 0x0024 capture register 0 tbxcp0 0x0028 capture register 1 tbxcp1 0x002c page 8-5 TMPM376FDDFG/fdfg 2013/4/12 8.4.2 tbxen(enable register) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symboltben------- after reset00000000 bit bit symbol type function 31-8 ? r read as "0". 7 tben r/w tmrbx operation 0: disable 1: enable specifies the tmrb operation. when the operation is disabled, no clock is supplied to the other registers in the tmrb module. this can reduce power c onsumption. (this disables reading from and writing to the other reg- isters except tbxen register.) to use the tmrb, enable the tmrb operation (set to "1") before programming each register in the tmrb mod- ule. if the tmrb operation is executed and then disabled, the settings will be maintained in each register. 6-0 ? r read as "0". page 8-6 8. 16-bit timer / event counters (tmrb) 8.4 registers TMPM376FDDFG/fdfg 2013/4/12 8.4.3 tbxrun(run register) note 1: when the external trigger start is used ( page 8-7 TMPM376FDDFG/fdfg 2013/4/12 8.4.4 tbxcr(control register) note 1: do not modify tbxcr during operating tmrb. note 2: when the external trigger start is used (< cssel>=1), select page 8-8 8. 16-bit timer / event counters (tmrb) 8.4 registers TMPM376FDDFG/fdfg 2013/4/12 8.4.5 tbxmod(mode register) note:do not change tbxmod register while the timer is operating. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - tbrswr tbcp tbcpm tbcle tbclk after reset00100000 bit bit symbol type function 31-7 ? r read as "0". 6 tbrswr r/w writes to timer registers 0 and 1 (when double buffering is enabled) 0: the data transfer to the timer register 0 and 1 is done by corresponding to the up-counter (uc) regardless of the rewriting of the buffer register 0 and 1. 1: to transfer the buffer registers data to the timer registers, the writing of the timer register 0 and 1 together are needed. 5tbcp w capture control by software 0: capture by software 1: don?t care when "0" is written, the capture register 0 (tbxcp0) takes count value. read as "1". 4-3 tbcpm[1:0] r/w capture timing 00: disable capture timing 01: tbxin takes count values into capture register 0 (tbxcp0) upon rising of tbxin pin input. 10: tbxin tbxin takes count values into capture register 0 (tbxcp0) upon rising of tbxin pin input. takes count values into capture register 1 (tbxcp1) upon falling of tbxin pin input. 11: disable capture timing 2 tbcle r/w up-counter control 0: disables clearing of the up-counter 1: enables clearing of the up-counter. clears and controls the up-counter. when "0" is written, it disables clearing of the up-counter. when "1" is written, it clears up counter when there is a match with timer regsiter1 (tbxrg1). 1-0 tbclk[1:0] r/w selects the tmrbx source clock. 00: tbxin pin input 01: t1 10: t4 11: t16 page 8-9 TMPM376FDDFG/fdfg 2013/4/12 8.4.6 tbxffcr(flip-fl op control register) note:do not change tbxffcr register while the timer is operating. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol - - tbc1t1 tbc0t1 tbe1t1 tbe0t1 tbff0c after reset11000011 bit bit symbol type function 31-8 ? r read as "0". 7-6 ? r read as "1". 5 tbc1t1 r/w tbxff0 reverse trigger when the up-counter value is taken into the tbxcp1. 0: disable trigger 1: enable trigger by setting "1", the timer-flip-flop reverses when the up-counter value is taken into the capture register 1 (tbxcp1). 4 tbc0t1 r/w tbxff0 reverse trigger when the up-counter value is taken into the tbxcp0. 0: disable trigger 1: enable trigger by setting "1", the timer-flip-flop reverses when the up-counter value is taken into the capture register 0 (tbxcp0). 3 tbe1t1 r/w tbxff0 reverse trigger when the up-counter value is matched with tbxrg1. 0: disable trigger 1: enable trigger by setting "1", the timer-flip-flop reverses when the up-counter value is matched with the timer register 1 (tbxrg1). 2 tbe0t1 r/w tbxff0 reverse trigger when t he up-counter value is matched with tbxrg0. 0: disable trigger 1: enable trigger by setting "1", the timer-flip-flop reverses when an up-counter value is matched with the timer register 0 (tbxrg0). 1-0 tbff0c[1:0] r/w tbxff0 control 00: invert reverses the value of tbxff0 (reverse by using software). 01: set sets tbxff0 to "1". 10: clear clears tbxff0 to "0". 11: don't care * this is always read as "11". page 8-10 8. 16-bit timer / event counters (tmrb) 8.4 registers TMPM376FDDFG/fdfg 2013/4/12 8.4.7 tbxst(status register) note 1: the factors only which is not masked by tbxim out put interrupt request to the cpu.even if the mask setting is done, the flag is set. note 2: the flag is cleared by reading the tbxst register.to clear the flag, tbxst register should be read. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-----inttbofinttb1inttb0 after reset00000000 bit bit symbol type function 31-3 ? r read as "0". 2 inttbof r overflow flag 0: no overflow occurs 1: overflow occurs when an up-counter is overflow, "1" is set. 1 inttb1 r match flag (tbxrg1) 0: no match is detected 1: detects a match with tbxrg1 when a match with the timer register 1 (tbxrg1) is detected,"1" is set. 0 inttb0 r match flag (tbxrg0) 0: no match is detected 1: detects a match with tbxrg0 when a match with the timer register 0 (tbxrg0) is detected, "1" is set. page 8-11 TMPM376FDDFG/fdfg 2013/4/12 8.4.8 tbxim(interr upt mask register) note:even if mask configuration by tbxim register is valid, the status is set to tbxst register. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol-------- after reset00000000 7 6 5 4 3 2 1 0 bit symbol-----tbimoftbim1tbim0 after reset00000000 bit bit symbol type function 31-3 ? r read as "0". 2 tbimof r/w overflow interrupt mask 0: disable 1: enable sets the up-counter overflow interrupt to disable or enable. 1 tbim1 r/w match interrupt mask (tbxrg1) 0: disable 1: enable sets the match interrupt mask with the timer register 1 (tbxrg1) to enable or disable. 0 tbim0 r/w match interrupt mask (tbxrg0) 0: disable 1: enable sets the match interrupt mask with the timer register 0 (tbxrg0) to enable or disable. page 8-12 8. 16-bit timer / event counters (tmrb) 8.4 registers TMPM376FDDFG/fdfg 2013/4/12 8.4.9 tbxuc(up counter capture register) note:when the counter is operated and tbxuc is read, the value of the up counter is captured and read. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol tbuc after reset00000000 7 6 5 4 3 2 1 0 bit symbol tbuc after reset00000000 bit bit symbol type function 31-16 ? r read as "0". 15-0 tbuc[15:0] r captures a value by reading up-counter out. if tbxuc is read, current up-counter value can be captured. page 8-13 TMPM376FDDFG/fdfg 2013/4/12 8.4.10 tbxrg0(timer register 0) 8.4.11 tbxrg1(timer register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol tbrg0 after reset00000000 7 6 5 4 3 2 1 0 bit symbol tbrg0 after reset00000000 bit bit symbol type function 31-16 ? r read as "0". 15-0 tbrg0[15:0] r/w sets a value comparing to the up-counter. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol tbrg1 after reset00000000 7 6 5 4 3 2 1 0 bit symbol tbrg1 after reset00000000 bit bit symbol type function 31-16 ? r read as "0". 15-0 tbrg1[15:0] r/w sets a value comparing to the up-counter. page 8-14 8. 16-bit timer / event counters (tmrb) 8.4 registers TMPM376FDDFG/fdfg 2013/4/12 8.4.12 tbxcp0(capture register 0) 8.4.13 tbxcp1(capture register 1) 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol tbcp0 after reset00000000 7 6 5 4 3 2 1 0 bit symbol tbcp0 after reset00000000 bit bit symbol type function 31-16 ? r read as "0". 15-0 tbcp0[15:0] r a value captured from the up-counter is read. 31 30 29 28 27 26 25 24 bit symbol-------- after reset00000000 23 22 21 20 19 18 17 16 bit symbol-------- after reset00000000 15 14 13 12 11 10 9 8 bit symbol tbcp1 after reset00000000 7 6 5 4 3 2 1 0 bit symbol tbcp1 after reset00000000 bit bit symbol type function 31-16 ? r read as "0". 15-0 tbcp1[15:0] r a value captured from the up-counter is read. page 8-15 TMPM376FDDFG/fdfg 2013/4/12 8.5 description of operations for each circuit the channels operate in the same way, except for the di fferences in their specificati ons as shown in table 8-1. 8.5.1 prescaler there is a 4-bit prescaler to generate the source clock for up-counter uc. the prescaler input clock t0 is fperiph/1, fperiph/2, fperiph/4, fp eriph/8, fperiph/16 or fperiph/32 selected by cgsyscr page 8-16 8. 16-bit timer / event counters (tmrb) 8.5 description of operations for each circuit TMPM376FDDFG/fdfg 2013/4/12 table 8-2 prescaler output clock resolutions (fc = 80mhz) select peripheral clock cgsyscr page 8-17 TMPM376FDDFG/fdfg 2013/4/12 note 1: the prescaler output clock tn must be selected so that tn < fsys is satisfied (so that tn is slower than fsys). note 2: do not change the clock gear while the timer is operating. note 3: " ? " denotes a setting prohibited. 1 (fc) 000 (fc) 000 (fperiph/1) fc/2 1 (0.025 s) fc/2 3 (0.1 s) fc/2 5 (0.4 s) 001 (fperiph/2) fc/2 2 (0.05 s) fc/2 4 (0.2 s) fc/2 6 (0.8 s) 010 (fperiph/4) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 100 (fc/2) 000 (fperiph/1) ? fc/2 3 (0.1 s) fc/2 5 (0.4 s) 001 (fperiph/2) fc/2 2 (0.05 s) fc/2 4 (0.2 s) fc/2 6 (0.8 s) 010 (fperiph/4) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 101 (fc/4) 000 (fperiph/1) ? fc/2 3 (0.1 s) fc/2 5 (0.4 s) 001 (fperiph/2) ? fc/2 4 (0.2 s) fc/2 6 (0.8 s) 010 (fperiph/4) fc/2 3 (0.1 s) fc/2 5 (0.4 s) fc/2 7 (1.6 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 110 (fc/8) 000 (fperiph/1) ? ? fc/2 5 (0.4 s) 001 (fperiph/2) ? fc/2 4 (0.2 s) fc/2 6 (0.8 s) 010 (fperiph/4) ? fc/2 5 (0.4 s) fc/2 7 (1.6 s) 011 (fperiph/8) fc/2 4 (0.2 s) fc/2 6 (0.8 s) fc/2 8 (3.2 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) 111 (fc/16) 000 (fperiph/1) ? ? fc/2 5 (0.4 s) 001 (fperiph/2) ? ? fc/2 6 (0.8 s) 010 (fperiph/4) ? fc/2 5 (0.4 s) fc/2 7 (1.6 s) 011 (fperiph/8) ? fc/2 6 (0.8 s) fc/2 8 (3.2 s) 100 (fperiph/16) fc/2 5 (0.4 s) fc/2 7 (1.6 s) fc/2 9 (6.4 s) 101 (fperiph/32) fc/2 6 (0.8 s) fc/2 8 (3.2 s) fc/2 10 (12.8 s) table 8-2 prescaler output clock resolutions (fc = 80mhz) select peripheral clock cgsyscr page 8-18 8. 16-bit timer / event counters (tmrb) 8.5 description of operations for each circuit TMPM376FDDFG/fdfg 2013/4/12 8.5.2 up-counter (uc) uc is a 16-bit binary counter. ? source clock uc source clock, specified by tbxmod page 8-19 TMPM376FDDFG/fdfg 2013/4/12 8.5.5 capture register (tbxcp0, tbxcp1) this register captures an up-counter (uc) value. 8.5.6 up counter capture register (tbxuc) other than the capturing functions shown above, the current count value of the uc can be captured by read- ing the tbxuc registers. 8.5.7 comparators (cp0, cp1) this register compares with the up-counter (uc) and the value setting of the timer register (tbxrg0 and tbxrg1) to detect whether there is a match or not. if a match is detected, inttbx0 and inttbx1 are gener- ated. 8.5.8 timer flip-flop (tbxff0) the timer flip-flop (tbxff0) is reversed by a match sign al from the comparator and a latch signal to the cap- ture registers. it can be enabled or disabled to reverse by setting the tbxffcr page 8-20 8. 16-bit timer / event counters (tmrb) 8.6 description of operations for each mode TMPM376FDDFG/fdfg 2013/4/12 8.6 description of operations for each mode 8.6.1 16-bit interval timer mode in the case of generating constant period interrupt, se t the interval time to the timer register (tbxrg0) to generate the inttbx0 interrupt. same as tbxrg0, inttbx 1 interrupt is generated by setting different inter- val time value to tbxrg1 timer resister. note:x; don?t care ? ; no change 8.6.2 16-bit ev ent counter mode it is possible to make it the event counter by using an input clock as an extern al clock (tbxin pin input). the up-counter counts up on the rising edge of tbxin pin input. it is possible to read the count value by cap- turing value using software and reading the captured value. note:x; don?t care ? ; no change 76543210 tbxen 1 x x x x x x x enables tmrbx operation. tbxrun x x x x x 0 x 0 stops count operation. interrupt set-enable register * * * * * * * * permits inttbx1 interrupt by setting corresponding bit to "1". tbxffcr xx000011 disable to tbxff0 reverse trigger. tbxmod x 0 1 0 0 1 * * changes to prescaler output clock as input clock. specifies capture function to disable. (** = 01, 10, 11) tbxrg1 * * * * * * * * specifies a time interval. (16 bits) ******** tbxrun *****1x1 starts tmrbx. 76543210 tbxen 1 x x x x x x x enables tmrbx operation. tbxrun x x x x x 0 x 0 stops count operation. set port registers. allocates corresponding port to tbxin. tbxffcr xx000011 disable to tbxff0 reverse trigger. tbxmod x 0 1 0 0 0 0 0 changes to tbxin as an input clock. tbxrun *****1x1 starts tmrbx. tbxmod x 0 0 0 0 0 0 0 software capture is done. page 8-21 TMPM376FDDFG/fdfg 2013/4/12 8.6.3 16-bit ppg (programmable pulse generation) output mode square waves with any frequency and any duty (pro grammable square waves) can be output. the output pulse can be either lo w-active or high-active. programmable square waves can be output from the tbxout pin by triggering the timer flip-flop (tbxff) to reverse when the set value of the up-counter (uc) matches the set values of the timer registers (tbxrg0 and tbxrg1). note that the set values of tbxrg0 and tbxrg1 must satisfy the following requirement: set value of tbxrg0 < set value of tbxrg1 figure 8-2 example of output of programmable pulse generation (ppg) in this mode, by enabling the double buffering of tbxrg0, the value of register buffer 0 is shifted into tbxrg0 when the set value of the up-counter matches the set value of tbxrg1. this facilitates handling of small duties. figure 8-3 register buffer operation tbxout pin match with tbxrg0 (inttbx0 interrupt) match with tbxrg1 (inttbx1 interrupt) q 2 q 1 match with tbxrg1 tbxrg0 (compare value) q 3 q 2 register buffer trigger to shift to tbxrg1 write tbxrg0 up-counter= q1 up-counter= q2 match with tbxrg0 q 5 q 4 tbxrg1 (compare value) q 6 q 5 register buffer write tbxrg1 page 8-22 8. 16-bit timer / event counters (tmrb) 8.6 description of operations for each mode TMPM376FDDFG/fdfg 2013/4/12 the block diagram of this mode is shown below. figure 8-4 block diagram of 16-bit ppg mode each register in the 16-bit ppg output mo de must be programmed as listed below. note:x; don?t care ? ; no change 76543210 tbxen 1 x x x x x x x enables tmrbx operation. tbxrun x x x x x 0 x 0 stops count operation. tbxcr 00 ? x ? x 0 0 disables double buffering. tbxrg0 ******** specifies a duty. (16 bits) ******** tbxrg1 ******** specifies a cycle. (16 bits) ******** tbxcr 100x ? x 0 0 enables the tbxrg0 double buffering. (changes the duty/cycle when the inttbx0 interrupt is gener- ated) tbxffcr x x 0 0 1 1 1 0 specifies to trigger tbxff0 to reverse when a match with tbxrg0 or tbxrg1 is detected, and sets the initial value of tbxff0 to "0". tbxmod x 0 1 0 0 1 * * designates the prescaler output clock as the input clock, and disables the capture function. uc is cleared to match tbxrg1. (** = 01, 10, 11) set port registers. allocates co rresponding port to tbxout. tbxrun *****1x1 starts tmrbx. selector selector internal data bus tbxcr page 8-23 TMPM376FDDFG/fdfg 2013/4/12 8.6.4 external trigger programmable pulse genera tion output mode (ppg) using an external count start trigger enables one-shot pulse generation with a short delay. the 16-bit up-counter (uc) is programmed to count up on the rising edge of the tbxin pin (tbxcr[1:0] = "01"). the tbxrg0 is loaded with the pulse delay (d), and the tbxrg1 is loaded with the sum of the tbxrg0 value (d) and the pulse width (p). the above settings must be done while the 16-bit up-counter is stopped (tbxrun page 8-24 8. 16-bit timer / event counters (tmrb) 8.7 applications using the capture function TMPM376FDDFG/fdfg 2013/4/12 8.7 applications usin g the capture function the capture function can be used to develop many applications, including those described below: 1. one-shot pulse output triggered by an external pulse 2. pulse width measurement 8.7.1 one-shot pulse output triggered by an external pulse one-shot pulse output triggered by an external pulse is carried out as follows: the 16-bit up-counter is made to count up by putting it in a free-running state using the prescaler output clock. an external pulse is input through the tbxin pi n. a trigger is generated at the rising of the external pulse by using the capture function and the value of the up-counter is taken into the capture registers (tbxcp0). the cpu must be programmed so that an interrupt intcap x0 is generated at the risi ng of an external trigger pulse. this interrupt is used to set the timer register s (tbxrg0) to the sum of the tbxcp0 value (c) and the delay time (d), (c + d), and set the timer registers (tbxrg1) to the sum of the tbxrg0 values and the pulse width (p) of one-shot pulse, (c + d + p).[tbxrg1 change must be completed before the next match.] in addition, the timer flip-flop control registers(tbxffcr page 8-25 TMPM376FDDFG/fdfg 2013/4/12 the followings show the settings in the case that 2 ms width one-shot pulse is output after 3ms by triggering tbxin input at the rising edge. ( t1 is selected for counting.) note:x; don?t care ? ; no change if a delay is not required, tbxff0 is reversed when data is taken into tbxcp0, and tbxrg1 is set to the sum of the tbxcp0 value (c) and the one-shot pulse width (p), (c + p), by generating the intcapx0 interrupt. tbxrg1 change must be completed before the next match. tbxff0 is enabled to reverse when uc matches with tbxrg1, and is disabled by generating the inttbx1 interrupt. figure 8-7 one-shot pulse output triggered by an external pulse (without delay) 76543210 [[main processing] capture setting by tbxin set port registers. allocates corresponding port to tbxin. tbxen 1 x x x x x x x enables tmrbx operation. tbxrun x x x x x 0 x 0 stops count operation. tbxmod x0101001 changes source clock to t1. fetches a count value into the tbxcp0 at the rising edge of tbxin. tbxffcr x x 0 0 0 0 1 0 clears tbxff0 reverse trigger and disables. set port registers. allocates corresponding port to tbxout. interrupt set-enable register ******** permits to generate interrupts specified by intcapx0 inter- rupt corresponding bit by setting to "1". tbxrun *****1x1 starts the tmrbx module. [processing of intcapx0 interrupt service routine] pulse output setting tbxrg0 ******** sets count value.(tbxcap0 + 3ms/ t1) ******** tbxrg1 ******** sets count value.(tbxcap0 + (3+2)ms/ t1) ******** tbxffcr xx ?? 11 ?? reverses tbxff0 if uc consistent with tbxrg0 and tbxrg1. tbxim xxxxx1 01 masks except tbxrg1 correspondence interrupt. interrupt set-enable register ******** permits to generate interrupt specified by inttbx interrupt corresponding bit setting to "1". [processing of inttbx interrupt service routine] output disable tbxffcr xx ?? 00 ?? clears tbxff0 reverse trigger setting. ******** prohibits interrupts specified by inttbx interrupt correspond- ing bit by setting to "1". count clock (prescaler output clock) timer output tbxout pin tbxin input (external trigger pulse) match with tbxrg1 c (p) c + p enable reverse inttbx1 generation enable reverse when data is taken into tbxcp0. taking data into the capture register tbxcp0. taking data into the capture register tbxcp1. disable reverse when data is taken into tbxcp1. pulse width intcapx0 generation page 8-26 8. 16-bit timer / event counters (tmrb) 8.7 applications using the capture function TMPM376FDDFG/fdfg 2013/4/12 8.7.2 pulse width measurement by using the capture function, the "high" level width of an external pulse can be measured. specifically, by putting it in a free-running state using the prescaler outp ut clock, an external pulse is input through the tbxin pin and the up-counter (uc) is made to count up. a trigger is generated at each rising and falling edge of the external pulse by using the capture function and the valu e of the up-counter is taken into the capture registers (tbxcp0, tbxcp1). the cpu must be programmed so that intcapx1 is generated at the falling edge of an external pulse input through the tbxin pin. the "high" level pulse width can be calculated by multiplying the difference between tbxcp0 and tbxcp1 by the clock cycle of an internal clock. for example, if the difference betw een tbxcp0 and tbxcp1 is 100 and the cycle of the prescaler output clock is 0.5 s, the pulse width is 100 0.5 s = 50 s. caution must be exercised when measuring pulse wi dths exceeding the uc maximum count time which is dependant upon the source clock used. the measurement of such pulse widths must be made using software. the "low" level width of an external pulse can also be measured. in such cases, the difference between c2 generated the first time and c1 generated the second ti me is initially obtained by performing the second stage of intcapx0 interrupt processing as shown in figure 8-8 and this difference is multiplied by the cycle of the prescaler output clock to obtain the "low" level width. figure 8-8 pulse width measurement prescaler output clock taking data into tbxcp1 tbxin pin input (external pulse) taking data into tbxcp0 c1 c1 c1 c2 c2 c2 intcapx1 intcapx0 page 9-1 TMPM376FDDFG/fdfg 2013/4/12 9. serial channel (sio/uart) 9.1 overview this device has two mode for the serial channel, one is the synchronous communication mode (i/o interface mode), and the other is the asynchron ous communication mode (uart mode). their features are given in the following. ? transfer clock - dividing by the prescaler, from the peripheral clock ( t0) frequency into 1/2, 1/8, 1/32, 1/128. - make it possible to divide from the prescaler output clock frequency into 1-16. - make it possible to divide from the prescaler out put clock frequency into 1, n+m/16 (n=2-15, m=1- 15). (only uart mode) - the usable system clock (only uart mode). ? double buffer /fifo the usable double buffer function, and the usable fifo buffers of transmit and receive in all for maxi- mum 4-byte. ? i/o interface mode - transfer mode: the half duplex (transmit/receive), the full duplex - clock: output (fixed rising edge) /i nput (selectable rising/falling edge) - make it possible to specify the interval time of continuous transmission. ? uart mode - data length: 7 bits, 8bits, 9bits - add parity bit (to be against 9bits data length) - serial links to use wake-up function - handshaking function with cts pin in the following explanation, "x" represents channel number. 9.2 difference in the spec ifications of sio modules TMPM376FDDFG/fdfg has four sio channels. each channel functions independently. the used pins , interrupt, dma request and uart source clock in each channel are collected in the following. table 9-1 difference in the specifications of sio modules pin name interrupt uart source clock txd rxd ctsx / sclkx receive interrupt transmit interrupt channel 0 pe0 pe1 pe2 intrx0 inttx0 tb4out channel 1 pa5 pa6 pa4 intrx1 inttx1 tb4out channel 2 pd5 pd6 pd4 intrx2 inttx2 tb7out channel 3 pf3 pf4 pf2 intrx3 inttx3 tb7out page 9-2 9. serial channel (sio/uart) 9.3 configuration TMPM376FDDFG/fdfg 2013/4/12 9.3 configuration figure 9-1 shows sio block diagram. figure 9-1 sio block diagram t0 f sys - t1 - t4 - t16 - t64 - t1 scxbrcr |