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2.0a low output voltage ultra ldo regulator TJ2132 a ug . 2014 C rev.1. 1. 3 1 htc features ? works with 1.1 v ~ 5.5v v in ? ultra low dropout voltage ? low quiescent current ? excellent line and load regulation ? guaranteed output current of 2 .0 a ? adjustable output voltage down to 0. 6 v ? v out power ok signal ? programmabl e soft - start ? logic controlled shutdown option ? over - temperature/over - current protection ? - 40 to 125 junction temperature range application ? motherboards and graphic cards ? microprocessor and chipset power supplies ? peripheral cards ? low voltage digital ics ? high efficiency linear regulators ? smps post regulators descripsion the TJ2132 is a 2 .0 a high performance ult ra low - dropout linear regulator ideal for powering core voltages of low - power microprocessors. the TJ2132 implements a dual supply configuration allowing for very low output impedance. the TJ2132 requires a bias input supply and a main input supply, allowing for ultra - low input voltages on the main supply rail. the input supply operates from 1. 1 v to 5.5v and the bias supply requires between 2.7 v and 5.5v for proper operation . the soft - start reduces inrush current of the load capacitors and minimizes stress on the input power source during start - up. the TJ2132 delivers high current and ultra - low - dropout ou tput voltage as low as 0. 6 v for applications where v out is very close to v in . the tj 2132 is developed on a cmos technology which allows low quiescent current opera tion independent of output current. this technology also allows the TJ2132 to operate under extremely low dropout conditions. sop 8 - pp dfn 3 x 3 - 8l ordering information device package TJ2132 g dp sop8 - pp TJ2132gq dfn 3 x3 - 8l operating ratings characteristic symbol min. max. unit recommend operating input voltage v in 1.1 5.5 v recommend operating bias v oltage v bias v out +2.1 5.5 v enable input voltage v en 0 5.5 v operating junction temperature range t jopr - 40 125 package thermal resistance * ? ja - sop8 - pp 68 /w * calculated from package in sill air, mounted to 2.6mm x 3.5mm(minimum foot print) 2 layer pcb without thermal vias per jesd51 standards.
2.0a low output voltage ultra ldo regulator TJ2132 a ug . 2014 C rev.1. 1. 3 2 htc maximum ratings characteristic symbol min. max. unit lead temperature (soldering, 5 sec) t sol 260 storage temperature range t stg - 65 150 o rdering information package order no. description package marking compliance supplied as sop8 - pp TJ2132 gdp 2 .0a, enable, adjustable , power ok , soft start TJ2132 g rohs, halogen free reel dfn 3 x3 - 8l TJ2132g q 2 .0a, enable, adjustable , power ok, soft start 2132 rohs, halogen free reel o rdering information (continued)
2.0a low output voltage ultra ldo regulator TJ2132 a ug . 2014 C rev.1. 1. 3 3 htc pin configuration sop8 - pp dfn 3 x3 - 8l pin description pin no. pin name pin function 1 pok power ok indication. this pin is an open - drain output and is set high impedance once v out reaches 92% of its rating voltage. 2 en enable input. pulling this pin below 0.4 v turns the regulator off. do not float . 3 in power input. this pin is the drain input to the power device that supply current to output pin. 4 bias supply input for internal circuit. input bias voltage for powering all circuitry on the regulator except the output power tr. 5 ss soft - start pin. connect a capacitor between this pin and the groun d to de termine the soft - start time. if soft - start is not needed, the ss pin can be left floating. (do not connect to ground directly .) 6 out power output. this pin is power output of the device. 7 fb feedback voltage. a resistor divider from the output to gnd is used to set the regulation voltage as v out = 0 .6 v x (1+r2/r1) 8 gnd ground - thermal exposed pad connect to ground. 1 2 3 4 8 7 6 5 p o k 1 2 3 8 7 6 e n i n g n d f b o u t 4 5 b i a s s s t o p v i e w
2.0a low output voltage ultra ldo regulator TJ2132 a ug . 2014 C rev.1. 1. 3 4 htc block diagram typical application
2.0a low output voltage ultra ldo regulator TJ2132 a ug . 2014 C rev.1. 1. 3 5 htc electrical characteristics unless otherwise specified: v bias = 5 v, v in = v o(nom) + 0.5 v, v en =v bias , i l = 1 0 ma , t j =25 . parameter symbol test condition min. typ. max. unit power input voltage v in v out =v ref 1. 1 - 5.5 v bias input voltage v bias v out =v ref 2.7 - 5.5 v v out >v ref v out +2.1 5.5 v reference voltage v ref v bias =v in =v en =5.0v, i out =10ma, v out =v ref 0. 5 8 8 0. 6 0. 612 v v in line regulation (note 1) v line ( in ) v out + 0.5 v 2.0a low output voltage ultra ldo regulator TJ2132 a ug . 2014 C rev.1. 1. 3 6 htc typical operating characteristics - test circuit circuit #01 circuit #02 circuit #03 circuit #04 circuit #05
2.0a low output voltage ultra ldo regulator TJ2132 a ug . 2014 C rev.1. 1. 3 7 htc - v in : 1v/div, v out : 1v/div, pok: 5v/div , 500us/div - v in : 1v/div, v out : 1v/div, pok: 5v/div , 500us/div start up @ i out =10ma , circuit #1 start up @ i out =2a , circuit #1 (c ff =10nf, c ss =470pf, r1=r2=10k , v en =v bias =5.0v) (c ff =10nf, c ss =470pf, r1=r2=10k , v en =v bias =5.0v) - v in : 2v/div, v bias : 5v/div, v out : 500mv/div , 500us/div - v in : 2v/div, v bias : 5v/div, v out : 500mv/div , 500us/div start up @ i out =10ma, circuit #2 start up @ i out =2a, circuit #2 (c ff =10nf, c ss =470pf, r1=r2=10k , v in =1.7v, v en =5.0v) (c ff =10nf, c ss =470pf, r1=r2=10k , v in =1.7v, v en =5.0v) - v en : 2 v/div, v out : 500m v/div, pok: 2 v/div , 500us/div - v en : 2 v/div, v out : 500 m v/div, pok: 2 v/div , 500us/div start up @ i out =10ma, circuit #1 start up @ i out =2a, circuit #1 (c ff =10nf, c ss =470pf, r1=r2=10k , v in =1.7v, v bias =5.0v) (c ff =10nf, c ss =470pf, r1=r2=10k , v in =1.7v, v bias =5.0v) v i n v out pok v i n v out pok v i n v bias v out v i n v bias v out v e n v out pok v e n v out pok
2.0a low output voltage ultra ldo regulator TJ2132 a ug . 2014 C rev.1. 1. 3 8 htc - v bias : 3 v/div, v en : 2 v/div, v out : 5 00m v/div, 2m s/div - v bias : 3 v/div, v en : 2 v/div, v out : 5 00m v/div, 2m s/div start up @ i out =10ma, circuit #1 start up @ i out =2a, circuit #1 ( c ss is varied, c ff =10nf, r1=r2=10k , v in =1.7v, v en =v bias =5.0v) ( css is varied, c ff =10nf, r1=r2=10k , v in =1.7v, v en =v bias =5.0v) - v en : 2 v/div, v out : 500m v/div , 1m s/div - v en : 2 v/div, v out : 500 v/div , 2m s/div start up @ i out =10ma, circuit #1 start up @ i out =10ma, circuit #5 (c ff is varied, c ss =open, r1=r2=10k , v in =1.7v, v bias =5.0v) (c delay is varied , c ss =open, r1=r2=10k , v in =1.7v, v bias =5.0v) - v out : 100m v/div, i out : 1a /div , 2 00us/div - v out : 100m v/div, i out : 1a /div , 2 00us/div load transient response load transient response (c ff =10nf, c ss =470pf, r1=r2=10k , v in =1.7v, v en =v bias =5.0v) (c ff =10nf, c ss =470pf, r1=r2=10k , v in =1.7v, v en =v bias =5.0v) v out i out v out i out v e n v out 10nf 10 0 nf 330 nf v e n v out 10nf 10 0 nf v bias v en v out 470pf 1nf v bias v en v out 2.7 nf 5.6 nf 10 nf 470pf 1nf 2.7 nf 5.6 nf 10 nf
2.0a low output voltage ultra ldo regulator TJ2132 a ug . 2014 C rev.1. 1. 3 9 htc - x - axis: v out [v], y - axis: v in [v] - x - axis: v out [v], y - axis: v bias [v] v out vs. v in @ v bias =5.5v v out vs. v bias @ v in =5.5v dropout voltage v drop vs. v bias @ v out =1.2v v drop vs. v bias @ v out =1.8v v drop vs. v bias @ v out =2.5 v 0 50 100 150 200 250 300 350 0 0.5 1 1.5 2 vdrop [mv] iout [a] 0 50 100 150 200 250 300 350 0 0.5 1 1.5 2 vdrop [mv] iout [a] vbias=5v vbias=3.3v 0 50 100 150 200 250 300 350 0 0.5 1 1.5 2 vdrop [mv] iout [a] vbias=5v vbias=3.9v 0 50 100 150 200 250 300 350 0 0.5 1 1.5 2 vdrop [mv] iout [a] vbias=5v vbias=4.6v v out =2.5v v out =1.8 v v out =1.2 v
2.0a low output voltage ultra ldo regulator TJ2132 a ug . 2014 C rev.1. 1. 3 10 htc application information the TJ2132 is a high performance, low dropout linear regulator, designed for high current application that requires fast transient response. the TJ2132 operates from two input supply voltages, significantly reducing dropout voltage. the TJ2132 is designed so that a minimum of external component are necessary. bias supply voltage the TJ2132 control circuitry is supplied by the bias pin which requires a very low bias current even at the maximum output current level. a bypass capacitor on the bias pin is recommended to improve the performance of the TJ2132 during line and load transient. a s mall ceramic capacitor from bias pin to ground reduces high frequency noise that could be injected into the control circuitry from the bias rail. in practical applications, a 1uf capacitor and smaller valued capacitors such as 0.01uf or 0.001uf in paralle l with that larger capacitor may be used to decouple the bias supply. the bias input voltage must be 2.1v above the output voltage, with a minimum bias input voltage of 2.7 v. adjustable regulator design an adjustable output device has output voltage rang e of 0.6v to v bias - 2.1v. to obtain a desired output voltage, the following equation can be used two external resistors as presented in the typical application circuit. the resistor values are given by; ? 2 = ? 1 ( ? ??? 0 . 6 ? 1 ) (1) it is suggested to use r1 values lower than 10k? to obtain better load transient performances. even, higher values up to 100 k? are suitable . enable the TJ2132 feature an active high enable input (en) that allows on/off control of the regulator. the enable function of TJ2132 has hysteresis characteristics. pulling v en lower than 0.4v disables the chip. pulling v en higher than 1.5v enables the output voltage. s upply power sequencing in common applications where the power on transient of v in and v bias voltages are not particularly fast (tr > 100us), no power sequencing is required. where voltage transient input is very fast(tr<100us), it is recommended to have the v in voltage present before or, at least, at the same time as the v bias voltage in order to avoid over voltage spikes during the power on transient. output capacitors the TJ2132 requires an of output capacitance to maintain stability. the output capacitor must meet both requirements for minimum amount of capacitance and esr in all ldos application. the TJ2132 is designed specifically to work with low esr ceramic output capacitor in space - saving and performance consideration. using a ceramic capacitor which value is at least 10 u f on the TJ2132 output ensures stability. output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and psrr. a minimum ceramic capacitor over than 10uf should be very closely placed to the output voltage pin of the TJ2132. input capacitor a large bulk capacitance over than 10uf should be closely placed to the input supply pin of the TJ2132 to ensure that the input supply voltage does not sag. also a minimum of 10uf ceramic capacitor is recommended to be placed directly next to the in p in. it allows for the device being some distance from
2.0a low output voltage ultra ldo regulator TJ2132 a ug . 2014 C rev.1. 1. 3 11 htc any bulk capacitor on the rail. additionally, input d roop due to load transients is reduced, improving load transient response. additional capacitance may be added if required by the application. soft start time the TJ2132 has an internal current source that charges an external slow start capacitor to implement a slow start time. equation 2 and table 1 shows how to select a slow start capacitor based on an expected slow start time. t he r is 302k , v o is 0.6v and i (t) is 40na. ( ) = ? ( ) ? ? (2) table 1. capacitor values for the soft - start time c ss calculated soft - start time measured soft - start time 470pf 0.56ms 0.64ms 1nf 1.18ms 1.23ms 2.7nf 3.18ms 3.44ms 5.6nf 6.6ms 7.1ms 10nf 11.8ms 12.0ms decoupling (bypass) capacitor in very electrically noisy environments, it is recommended that additional ceramic capacitors be placed from vin to gnd. the use of multiple lower value ceramic capacitors in parallel with output capacitor also allows to achieve better transient performance and stability if required by the application. (see fig.1) feed - forward capacitor to get the higher psrr th an the inherent performance of TJ2132 , it is recommended that additional ceramic feed - forward capacitor be placed from out pin to fb pin. the capacitance of feed - forward capacitor with range of 10pf to 1uf allows to achieve better psrr performance when req uired by the application. (see fig.1) fig.1 application with decoupling & feed - forward capacitor maximum output current capability the tj 2132 can deliver a continuous current of 2a over the full operating junction temperature range. however, the output current is limited by the restriction of power dissipation which differs from packages. a heat sink may be required depending on the maximum power dissipation and maximum ambient
2.0a low output voltage ultra ldo regulator TJ2132 a ug . 2014 C rev.1. 1. 3 12 htc temperature of application. with respect to the applied package, t he maximum output current of 2a may be still undeliverable due to the restriction of the power dissipation of tj 2132 . under all possible conditions, the junction temperature must be within the range specified under operating conditions. the temperatures ov er the device are given by: t c = t a + p d x ca t j = t c + p d x jc t j = t a + p d x ja where t j is the junction temperature, t c is the case temperature, t a is the ambient temperature, p d is the total power dissipation of the device, ca is the thermal resi stance of case - to - ambient, jc is the thermal resistance of junction - to - case, and ja is the thermal resistance of junction to ambient. the total power dissipation of the device is given by: p d = p in C p out = { (v in x i in ) + (v bias x i bias )} C (v out x i out ) where i gnd is the operating ground current of the device which is specified at the electrical characteristics. the maximum allowable temperature rise (t rmax ) depends on the maximum ambient temperature (t amax ) of the application, and the maximum allowable junction temperature (t jmax ): t rmax = t jmax C t amax the maximum allowable value for junction - to - ambient thermal resistance, ja , can be calculated using the formula: ja = t rmax / p d tj 2132 is available in sop8 - pp packages. the thermal resistance depends on amount of copper area or heat sink, and on air flow. if proper cooling solution such as heat sink, copper plane area, or air flow is applied, the maximum allowable power dissipation could be increased. however, if the ambient temperature is inc reased, the allowable power dissipation would be decreased.
2.0a low output voltage ultra ldo regulator TJ2132 a ug . 2014 C rev.1. 1. 3 13 htc the graph above is valid for the thermal impedance specified in the absolute maximum ratings section on page 1. the ja could be decreased with respect to the copper plane area. so, the speci fication of maximum power dissipation for an application is fixed, the proper plane area could be estimated by following graphs. wider copper plane area leads lower ja . the maximum allowable power dissipation is also influenced by the ambient temperature. with the ja - copper plane area relationship, the maximum allowable power dissipation could be evaluated with respect to the ambient temperature. as shown in graph, the h igher copper plane area leads ja . and the higher ambient temperature leads lower maximum allowable power dissipation.

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