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| fn7696 rev 6.00 page 1 of 13 november 6, 2014 fn7696 rev 6.00 november 6, 2014 ISL78302 dual ldo with low noise, high performance and low iq datasheet ISL78302 is a high performance dual ldo capable of sourcing 300ma current from each output . it has a low standby current and is stable with an output capacitance of 1f to 10f and an esr of up to 200m . the device integrates an individual power-on-reset (por) function for each output. the por delay for vo2 can be externally programmed by connecting a timing capacitor to the cpor pin. the por delay for vo1 is internally fixed at approximately 2ms. a reference bypass pin is also provided for connecting a noise filtering capacitor for low noise and high- psrr applications. the quiescent current is typically only 47a with both ldos enabled and active. separate enable pins control each individual ldo output. when both enable pins are low, the device is in shutdown, typically drawing less than 0.5a. the part operates down to 2.3v and up to 6.5v input. the typical output voltage can be as low as 1.2v and as high as 3.3v for each regulator. please refer to the ?ordering information? on page 3 for standard options. the ISL78302 is aec-q100 qualified at the automotive temperature range of -40c to +105c. features ? integrates two 300ma high performance ldos ? excellent transient respon se to large current steps ? 1.8% accuracy over all operating conditions ? excellent load regulation: <0.1% voltage change across full range of load current ? extremely low quiescent current: 47a (both ldos active) ? wide input voltage capability: 2.3v to 6.5v ? low dropout voltage: typically 300mv at 300ma ? low output noise: typically 37v rms at 100a (1.5v) ? stable with 1f to 10f ceramic capacitors ? separate enable and por pins for each ldo ? soft-start and staged turn-on to limit input current surge during enable ? current limit and over-temperature protection ? tiny 10 lead 3mm x 3mm dfn package ? aec-q100 qualified ? pb-free (rohs compliant) applications ? radio receivers ? camera modules ?gps/navigation ? infotainment systems c1, c4, c5: 1f x5r ceramic capacitor c2: 0.01f x7r ceramic capacitor ISL78302 vin en1 en2 cbyp cpor vo1 vo2 por2 por1 gnd 10 9 8 7 6 1 2 3 4 5 vin (2.3 to 6.5v) enable1 enable2 v out1 v out2 reset1 reset2 c1 c2 c3 c4 c5 c3: 0.01f x7r ceramic capacitor off on off on (200ms delay, c3 = 0.01f) (2ms delay) v out2 too low v out2 ok v out1 too low v out1 ok figure 1. typical application
ISL78302 fn7696 rev 6.00 page 2 of 13 november 6, 2014 block diagram vo2 ldo error amplifier is1 1v qen1 ldo-1 ldo-2 por comparator vok1 por1 vref trim vin vo1 vo2 por2 por1 gnd en2 en1 control logic por2 delay por1 delay voltage reference generator bandgap and temperature sensor uvlo vok2 vok1 1.00v 0.94v 0.90v is1 is2 qen1 qen2 vo2 vo1 100k 100k cpor cbyp vo1 ~1.0v vok2 por2 ISL78302 fn7696 rev 6.00 page 3 of 13 november 6, 2014 pin configuration ISL78302 (10 ld 3x3 dfn) top view vin en1 en2 cbyp cpor vo1 vo2 por2 por1 gnd 2 3 4 1 5 9 8 7 10 6 pin descriptions pin number pin name type description 1 vin analog i/o supply voltage/ldo input. connect a 1f capacitor to gnd. 2 en1 low voltage compatible cmos input ldo-1 enable. enable = high 3 en2 low voltage compatible cmos input ldo-2 enable. enable = high 4 cbyp analog i/o reference bypass capacitor pin. re commended to connect capacitor of value 0.01f between this pin and gnd for optimum noise and psrr performance. 5 cpor analog i/o por2 delay setting capacitor pin. connect a capacitor between this pin and gnd to delay the por2 output release after ldo-2 output reac hes 94% of its specified voltage level. (200ms delay per 0.01f). 6 gnd ground gnd is the connection to syst em ground. connect to pcb ground plane. 7por1 open-drain output (1ma) open-drain por output for ldo-1 (active-low). internally connected to vo1 through 100k resistor. 8por2 open-drain output (1ma) open-drain por output for ldo-2 (active-low). internally connected to vo2 through 100k resistor. 9vo2 analog i/o ldo-2 output. connect capacitor of value 1f to 10f to gnd (1f recommended). 10 vo1 analog i/o ldo-1 output. connect capacitor of value 1f to 10f to gnd (1f recommended). ordering information part number ( notes 1 , 2 , 3 ) part marking vo1 voltage (v) vo2 voltage (v) temp range (c) package (pb-free) pkg dwg. # ISL78302arfbz dnab 2.5 1.5 -40 to +105 10 ld 3x3 dfn l10.3x3c ISL78302arbfz dnac 1.5 2.5 -40 to +105 10 ld 3x3 dfn l10.3x3c ISL78302arnbz dnad 3.3 1.5 -40 to +105 10 ld 3x3 dfn l10.3x3c ISL78302arbnz dnae 1.5 3.3 -40 to +105 10 ld 3x3 dfn l10.3x3c ISL78302arnwz dnaf 3.3 1.2 -40 to +105 10 ld 3x3 dfn l10.3x3c ISL78302arwcz dnag 1.2 1.8 -40 to +105 10 ld 3x3 dfn l10.3x3c ISL78302arfwz dnah 2.5 1.2 -40 to +105 10 ld 3x3 dfn l10.3x3c ISL78302arcwz dnaj 1.8 1.2 -40 to +105 10 ld 3x3 dfn l10.3x3c ISL78302ar1az dnav 1.25 3.3 -40 to +105 10 ld 3x3 dfn l10.3x3c notes: 1. add ?-t*?suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL78302 . for more information on msl please see techbrief tb363 . ISL78302 fn7696 rev 6.00 page 4 of 13 november 6, 2014 absolute maximum rating s thermal information supply voltage (v in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.1v v o 1, v o 2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (v in + 0.3)v esd ratings human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 3kv machine model (tested per jesd-a115-a) . . . . . . . . . . . . . . . . . . . 200v charge device model (tested per aec-q100-011). . . . . . . . . . . . . . . 2kv thermal resistance ( notes 4 , 5 ) ? ja (c/w) ? jc (c/w) 10 ld 3x3 dfn package . . . . . . . . . . . . . . . 59 18.5 junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c operating temperature range . . . . . . . . . . . . . . . . . . . . . .-40c to +105c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions ambient temperature range (t a ) . . . . . . . . . . . . . . . . . . .-40c to +105c supply voltage (v in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3v to 6.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: t a = -40c to +105c; v in = (v o + 0.5v) to 6.5v with a minimum v in of 2.3v; c in = 1f; c o = 1f; c byp = 0.01f; c por = 0.01f. boldface limits apply across the operatin g temperature range, -40c to +105c. parameter symbol test conditions min ( note 7 )typ max ( note 7 )units dc characteristics supply voltage v in 2.3 6.5 v ground current quiescent condition: i o1 = 0a; i o2 = 0a i dd1 one ldo active 30 36 a i dd2 both ldo active 47 55 a shutdown current i dds 0.3 2.1 a uvlo threshold v uv+ 1.9 2.1 2.3 v v uv- 1.6 1.8 2.0 v regulation voltage accuracy v in = v o + 0.5v to 5.5v, i o = 10a to 300ma, t j = +25c -0.8 +0.8 % v in = v o + 0.5v to 5.5v, i o = 10a to 300ma, t j = -40c to +105c -1.8 +1.8 % maximum output current i max continuous 300 ma internal current limit i lim 320 475 650 ma dropout voltage ( note 6 )v do i o = 300ma 300 mv i o = 150ma 150 250 mv thermal shutdown temperature t sd+ 145 c t sd- 110 c ac characteristics ripple rejection i o = 10ma, v in = 2.8v(min), v o = 1.5v, c byp = 0.01f at 1khz 64 db at 10khz 51 db at 100khz 38 db ISL78302 fn7696 rev 6.00 page 5 of 13 november 6, 2014 output noise voltage i o = 100a, v o = 1.5v, t a = +25c, c byp = 0.01f bw = 10hz to 100khz 37 v rms device start-up characteristics device enable time t en time from assertion of the enx pin to when the output voltage reaches 95% of the vo(nom) 250 500 s ldo soft-start ramp rate t ssr slope of linear portion of ldo output voltage ramp during start-up, v out > 1.25v 30 60 s/v slope of linear portion of ldo output voltage ramp during start-up, v out 1.25v 40 80 s/v en1, en2 pin characteristics input low voltage v il -0.3 0.5 v input high voltage v ih 1.35 v in + 0.3 v input leakage current i il , i ih 0.1 a pin capacitance c pin informative 5 pf por1 , por2 pin characteristics por1 , por2 thresholds v por+ as a percentage of nominal output voltage 91 94 97 % v por- 87 90 93 % por1 delay t p1lh 0.5 2.0 3.2 ms t p1hl 25 s por2 delay t p2lh c por = 0.01f 100 200 300 ms t p2hl 25 s por1 , por2 pin output low voltage v ol at i ol = 1.0ma 0.2 v por1 , por2 pin internal pull-up resistance r por 78 100 180 k notes: 6. vox = 0.98*vox(nom); valid for vox greater than 1.85v. 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: t a = -40c to +105c; v in = (v o + 0.5v) to 6.5v with a minimum v in of 2.3v; c in = 1f; c o = 1f; c byp = 0.01f; c por = 0.01f. boldface limits apply across the operatin g temperature range, -40c to +105c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )units ISL78302 fn7696 rev 6.00 page 6 of 13 november 6, 2014 v por+ v por+ v por- ISL78302 fn7696 rev 6.00 page 8 of 13 november 6, 2014 figure 9. ground current vs load figure 10. ground current vs temperature figure 11. power-up/power-down figure 12. power-up/power-down with por signals figure 13. turn-on/turn-off response figure 14. load transient response typical performance curves (continued) 40 60 80 100 120 140 160 180 200 0 50 100 150 200 250 300 350 400 load current (ma) +105c -40c +25c ground current (a) v in = 3.5v v o 1 = 2.5v v o 2 = 1.5v 40 45 50 55 60 -40 -25 -10 5 20 35 50 65 80 95 110 temperature (c) ground current (a) v in = 3.6v v o 1 = 2.5v i load = 0a both outputs on v o 2 = 1.5v v o 1 = 2.5v v o 2 = 1.5v i l 1 = 300ma i l 2 = 300ma vin v o 1 v 0 2 v o 1 = 2.5v v o 2 = 1.5v i l 1 = 300ma i l 2 = 300ma cpor = 0.01f v o 1 por1 v o 2 por2 v o 1 = 2.5v v o 2 = 1.5v i l 1, i l 2 = 300ma c byp = 0.01f c l 1, c l 2 = 1f v o 2 (10mv/div) i load v in = 3.5v v o = 1.5v v o (50mv/div) ISL78302 fn7696 rev 6.00 page 9 of 13 november 6, 2014 figure 15. psrr vs frequency figure 16. spectral noise density vs frequency (2.5v output, 10ma load) figure 17. spectral noise density vs frequency (2.5v output, 300ma load) figure 18. spectral noise density vs frequency (1.5v output, 10ma load) figure 19. spectral noise density vs frequency (1.5v output, 300ma load) typical performance curves (continued) 0 10 20 30 40 50 60 70 80 90 100 10 100 1k 10k 100k 1m v in = 3.3v v out = 1.5v i o = 10ma c load = 1f c byp = 0.01f frequency (hz) psrr (db) 0.01 0.1 1 10 10 100 1k 10k 100k 1m frequency (hz) spectral noise density (mv/hz) v in = 3.6v v out = 2.5v i load = 10ma c in = 1f c load = 1f c byp = 0.01f 0.01 0.1 1 10 10 100 1k 10k 100k 1m frequency (hz) v in = 3.6v v out = 2.5v i load = 300ma c in = 1f c load = 1f c byp = 0.01f spectral noise density (mv/hz) 0.01 0.1 1 10 10 100 1k 10k 100k 1m v in = 3.6v v out = 1.5v i load = 10ma c in = 1f c load = 1f c byp = 0.01f frequency (hz) spectral noise density (mv/hz) 0.01 0.1 1 10 10 100 1k 10k 100k 1m frequency (hz) v in = 3.6v v out = 1.5v i load = 300ma c in = 1f c out = 1f c byp = 0.01f spectral noise density (mv/hz) ISL78302 fn7696 rev 6.00 page 10 of 13 november 6, 2014 functional description the ISL78302 contains two hi gh performance ldos. high performance is achieved through a circuit that delivers fast transient response to varying load conditions. in a quiescent condition, the ISL78302 adjusts its biasing to achieve the lowest standby current consumption. the device also integrates current limit protection, smart thermal shutdown protection, staged turn-on and soft-start. smart thermal shutdown protects the device against overheating. staged turn-on and soft-start minimize start-up input current surges without causing excessive device turn-on time. power control the ISL78302 has two separate enable pins (en1 and en2) to individually control power to each of the ldo outputs. when both en1 and en2 are low, the device is in shutdown mode. during this condition, all on-chip circui ts are off, and the device draws minimum current, typically less than 0.5a. when one or both of the enable pins is asserted, the device first polls the output of the uvlo detector to ensure that vin voltage is at least about 2.1v. once verified , the device initiates a start-up sequence. during the start-up se quence, trim settings are first read and latched. then, sequentially, the bandgap, reference voltage and current generation circuitry power-up. once the references are stable, a fast-sta rt circuit quickly charges the external reference bypass capacitor (connected to the cbyp pin) to the proper operating voltage. after the bypass capacitor has been charged, the ldos power-up in their specified sequence. soft-start circuitry integrated into each ldo limits the initial ramp-up rate to about 30s/v to minimize cu rrent surge. if en1 is brought high and en2 goes high before the vo1 output stabilizes, the ISL78302 delays the vo2 turn-on until the vo1 output reaches its target level. if en2 is brought high and en1 goes high before vo2 starts its output ramp, then vo1 turns on first and, the ISL78302 delays the vo2 turn-on until the vo1 output reaches its target level. if en2 is brought high and en1 goes high after vo2 starts its output ramp, then the ISL78302 im mediately starts to ramp up the vo1 output. if both en1 and en2 are brought high at the same time, the vo1 output has priority and is always powered up first. during operation, whenever the vin voltage drops below 1.8v, the ISL78302 immediately disables both ldo outputs. when vin rises back above 2.1v, the device reinitiates its start-up sequence, and ldo operation will resume automatically. reference generation the reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an rc noise filter. the filter includes the external capacitor connected to the cbyp pin. a 0.01f (capacitor connected cbyp) implements a 100hz lowpass filter and is recommended for most high-p erformance applications. capacitor values above 0.01f are not recommended for the cbyp pin. the bandgap generates a zero temperature coefficient (tc) voltage for the reference divider. the reference divider provides the regulation reference, por detection thresholds, and other voltage references required for current generation and over-temperature detection. the current generator provides the references required for adaptive biasing as well as refe rences for ldo output current limit and thermal shutdown determination. ldo regulation and programmable output divider the ldo regulator is implemente d with a high-gain operational amplifier driving a pmos pass tr ansistor. the design of the ISL78302 provides a regulator that has low quiescent current, fast transient response, and overall st ability across all operating and load current conditions. ldo stability is guaranteed for a 1f to 10f output capacitor that has a tolerance better than 20% and an esr less than 200m . the design is performance-optimized for a 1f capacitor. unless limited by th e application, use of an output capacitor value above 4.7f is not normally needed, as ldo performance improvement is minimal. each ldo uses an independently trimmed 1v reference. an internal resistor divider drops the ldo output voltage down to 1v. this is compared to the 1v reference for regulation. the resistor division ratio is programmed in the factory to the output voltages of 1.2v, 1.5v, 1.8v, 2.5v and 3.3v. power-on reset generation each ldo has a separate power-on reset signal generation circuit, which outputs to the respective por pins. the por signal is generated as follows. a por comparator continuously monitors the output of each ldo. the ldo enters a power-good state when the output voltage is above 94% of the expected output voltage for a period exceeding the ldo pgood entry delay time. in the power-good state, the open-drain porx output is in a high-impedance state. an internal 100k pull-up resistor pulls the pin up to the respective ldo output voltage. an external resistor can be added between the porx output and the ldo output for a faster rise time; however, the porx output should not connect through an external resistor to a supply greater than the associated ldo voltage. the ISL78302 offers 1.2v and 1.5v regulated outputs in several options. on these low output voltage versions, it has been found that the internal pull-ups on por outputs do not always function correctly above v in = 3.9v. for this reason, it is recommended to use an external 100k pull-up resistor for either por pin if its associated output is either 1.2v or 1.5v. for outputs higher than 1.5v, no external resistor is required over the full input range from 2.3v to 6.5v. the power-good state is exited when the ldo output falls below 90% of the expected output voltage for a period longer than the pgood exit delay time . while power-good is false, the ISL78302 pulls the respective por pin low. for ldo-1, the pgood entry delay time is fixed at about 2ms, while the pgood exit delay is about 25s. for ldo-2, the pgood entry and exit delays are determined by the value of the external fn7696 rev 6.00 page 11 of 13 november 6, 2014 ISL78302 intersil automotive qualified products are manufactured, asse mbled and tested utilizing ts16949 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2011-2014. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. capacitor connected to the cpor pin. for a 0.01f capacitor, the entry and exit delays are 200ms and 25s, respectively. larger or smaller capacitor values will yield proportionately longer or shorter delay times. the por exit delay should never be allowed to be less than 10s to ensure sufficient immunity against transient induced false por triggering. over-temperature detection the bandgap provides a proportion al-to-temperature current that indicates the temperature of the silicon. this current is compared with references to determine whether the device is in danger of damage from overheating. when the die temperature reaches about +145c, one or both of the ldos momentarily shuts down until the die cools sufficiently. in the overheat condition, only the ldo sourcing more than 50ma is shut off. this shutoff does not affect the operation of the other ldo. if both ldos source more than 50ma and an overheat condition occurs, both ldo outputs are disabled. once the die temperature falls back below about +110c and disabled ldos are re-enabled, the soft-start automatically takes place. the ISL78302 provides short-circui t protection by limiting the output current to about 475ma. if short circuited, an output current of 475ma causes die heating. if the short circuit lasts long enough, the overheat detection circuit turns off the output. ISL78302 fn7696 rev 6.00 page 12 of 13 november 6, 2014 about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change november 6, 2014 fn7696.6 changed testing information for charged device model from: charged device model(tested per jesd22-c101c)...2kv to: with charged device model(tested per aec-q100-011)..2kv december 4, 2013 fn7696.5 page 1: changed last paragraph in description from: "the ISL78302 is rated for the automotive temperature range (-40c to +105c)." to: "the ISL78302 is aec-q100 rated. the ISL78302 is rated for the automotive temperature range (-40c to +105c)." features bullet changed from: "qualified for automotive applications" to: "aec-q100 tested" november 5, 2013 fn7696.4 page 1 - added the words "qualified for automotive applications" under the features section page 13 - updated l10.3x3c pod from rev 2 to rev 3. changes from rev 2: removed package outline and included center to ce nter distance between lands on recommended land pattern. removed note 4 "dimension b applies to the metall ized terminal and is measured between 0.18mm and 0.30mm from the terminal tip." july 31, 2013 fn7696.3 added part number ISL78302ar1az to ?ordering information? on page 3 electrical spec table changed ldo soft-start ramp rate test conditions under device start-up characteristics on page 5 from: v out > 1.2v to v out > 1.25v from: v out = 1.2v to v out <= 1.25v march 15, 2012 fn7696.2 removed "other voltage selections are available upon request." from page 1. corrected "vo2" to "vo1" (tied to por1#) in ?block diagram? on page 2. corrected "vo4" to vo2" (tied to por2#) in ?block diagram? on page 2. removed note 2 "for other output voltages, contact intersil." from ?ordering information? on page 3. corrected part marking for ISL78302arcwz from danj to dnaj. added ?v out > 1.2v? to conditions of ?ldo soft-start ra mp rate? on page 5 where typ/max are 30/60s/v. added line for v out = 1.2v with typ/max specs of 40/80s/v. added paragraph to ?power-on reset generation? on pa ge 10 ("the ISL78302 offers ... is required over the full input range from 2.3v to 6.5v."). december 5, 2011 fn7696.1 removed ?coming soon? from parts in ?ordering information? on page 3. january 28, 2011 fn7696.0 initial release. ISL78302 fn7696 rev 6.00 page 13 of 13 november 6, 2014 package outline drawing l10.3x3c 10 lead dual flat package (dfn) rev 3, 10/11 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 5. either a mold or mark feature. 3. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.10 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail "x" c c 4 5 5 a b 0.10 c 2 6 10 1 0.90 0.20 0.50 2.38 3.00 (10x 0.25) (8x 0.50) 2.38 1.64 (10 x 0.60) 3.00 0.05 0.20 ref 10 x 0.25 10x 0.40 1.64 cb max (4x) 0.10 cb m 6. compliant to jedec mo-229-weed-3 except for e-pad dimensions. 2.80 typ |
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