p p j s68 34 march 6,2015 - rev.00 page 1 2 0 v n - c hannel enhancement mode mosfet voltage 2 0 v current 750m a sot - 23 6l unit: inch(mm) f eatures ? low voltage d rive (1.2v) . ? advanced trench process technology ? specially designed for switch load, pwm application , etc. ? esd protected ? lead free in compliance wit h eu rohs 2011/65/eu directive. ? green molding compound as per iec61249 std. (halogen free) mechanical data ? case: sot - 2 3 6l package ? terminals: solderable per mil - std - 750, method 2026 ? approx. weight: 0.00 0 5 ounces, 0.0 141 grams ? marking: s g 4 parameter symbol limit units drain - source voltage v ds 20 v gate - source voltage v gs + 10 v continuous drain current i d 750 ma pulsed drain current (note 4 ) i dm 1500 ma power dissipation t a =25 o c p d 500 m w derate above 25 o c 4 m w/ o c operatin g junction an d storage temperature range t j ,t stg - 55~150 o c typical thermal resistance - j unction to ambient (note 3 ) r ja 10 0 o c /w maximum ratings and thermal characteristics (t a =25 o c unless otherwise noted)
p p j s68 34 march 6,2015 - rev.00 page 2 e lectrical c haracteristics (t a =25 o c unless otherwise noted) parameter symbol test condition min. typ. max. units static drain - source breakdown vo ltage bv dss v gs = 0 v, i d = 25 0ua 2 0 - - v gate threshold voltage v gs(th) v ds =v gs , i d = 250 ua 0.3 0.65 0.9 v drain - source on - state resistance r ds(on) v gs = 4.5 v, i d = 600m a - 2 80 400 m gs = 2.5 v, i d = 200m a - 3 50 650 v gs = 1.8 v, i d = 100m a - 400 800 v gs = 1.5 v, i d = 50m a - 500 1200 v gs = 1.2 v, i d = 20m a - 1000 3000 zero gate voltage drain current i dss v ds = 16 v, v gs =0v - - 1 u a gate - source leakage current i gss v gs = + 8 v, v ds =0v - + 0.5 + 10 u a dynamic (note 5 ) total gate charge q g v ds = 10 v, i d = 600m a, v gs = 4.5v (note 1 , 2 ) - 1.4 - nc gate - source charge q gs - 0.22 - gate - drain charge q gd - 0.21 - input capacitance ciss v ds = 10 v, v gs = 0 v, f=1.0mhz - 67 - pf output capacitance coss - 19 - reverse transfer capacitance crss - 6 - turn - on delay time t d (on) v dd = 10 v, i d =150m a, v g s = 4.0v, r g = 10 (note 1 , 2 ) - 2.8 - ns turn - on rise time tr - 20 - turn - o ff delay time t d (off) - 23 - turn - o ff fall time tf - 23 - drain - source diode maximum continuous drain - source diode forward current i s --- - - 500 m a diode forwar d voltage v sd i s = 500m a, v gs = 0 v - 0.87 1.3 v notes : 1. pulse width < 300us, duty cycle < 2% 2. essentially independent of operating temperature typical characteristics . 3. r ? ja is the sum of the junction - to - case and case - to - ambient thermal resistance where the case th ermal reference is defined as the solder mounting surface of the drain pins m ounted on a 1 inch fr - 4 with 2oz . square pad of copper . 4. the maximum current rating is package limited. 5. guaranteed by design, not subject to product ion testing.
p p j s68 34 march 6,2015 - rev.00 page 3 t ypical charac teristic curves fig.1 on - region characteristics fig. 2 transfer characteristics fig. 3 on - resistance vs. drain current fig. 4 on - resistance vs. junction temperature fig. 5 on - resistance variation with vgs. fig. 6 body d i ode cha racteristics
p p j s68 34 march 6,2015 - rev.00 page 4 t ypical characteristic curves fig. 7 gate - charge characteristics fig. 8 threshold voltage variation with temperature . fig. 9 capacitance vs. drain - source voltage.
p p j s68 34 march 6,2015 - rev.00 page 5 part no packing code version mounting pad layout p art n o packing c ode package type packing type marking ver sion PJS6834 _s1_00001 sot - 23 6l 3k pcs / 7 0.024 (0.60) 0 . 0 2 6 ( 0 . 6 7 ) 0 . 0 9 6 ( 2 . 4 3 ) 0.037 (0.95) 0.037 (0.95)
p p j s68 34 march 6,2015 - rev.00 page 6 disclaimer
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