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nuvoton 8 - bit 8051 - based microcontroller N78E366A data sheet
n78e366 a data sheet publication release date: march 11, 2011 - 2 - revision : v2.0 contents 1. description ................................ ................................ ................................ ................................ .................. 4 2. features ................................ ................................ ................................ ................................ ....................... 5 3. block diagram ................................ ................................ ................................ ................................ ............ 7 4. pin configuration s ................................ ................................ ................................ ................................ ... 8 5. memory organizati on ................................ ................................ ................................ ............................ 14 5.1 internal program memory ................................ ................................ ................................ ................. 14 5.2 external program memory ................................ ................................ ................................ ................ 16 5.3 in ternal data memory ................................ ................................ ................................ ....................... 17 5.4 on - chip xram ................................ ................................ ................................ ................................ .. 19 5.5 external data memory ................................ ................................ ................................ ...................... 19 6. special function register (sfr) ................................ ................................ ................................ ....... 21 7. general 80c51 sys tme control ................................ ................................ ................................ ......... 24 8. auxiliary ram (xr am) ................................ ................................ ................................ ............................... 28 9. i/o port structur e and operation ................................ ................................ ................................ .. 30 10. timers/counters ................................ ................................ ................................ ................................ .... 34 10.1 timer/counters 0 an d 1 ................................ ................................ ................................ .................. 34 10.1.1 mode 0 (13 - bit timer) ................................ ................................ ................................ ...... 36 10.1.2 mode 1 (16 - bit timer) ................................ ................................ ................................ ...... 37 10.1.3 mode 2 (8 - bit auto - reload timer) ................................ ................................ .................... 37 10.1.4 mode 3 (two separate 8 - bit timers) ................................ ................................ ............... 38 10.2 timer/counter 2 ................................ ................................ ................................ .............................. 39 10.2.1 capture mode ................................ ................................ ................................ .................. 42 10.2.2 auto - reload mode ................................ ................................ ................................ ............ 42 10.2.3 baud rate genera tor mode ................................ ................................ ............................ 43 10.2.4 clock - out mode ................................ ................................ ................................ ................ 44 11. watchdog timer ................................ ................................ ................................ ................................ ..... 45 11.1 function description of watchdog timer ................................ ................................ ........................ 45 11.2 applications of watchdog timer ................................ ................................ ................................ ..... 47 12. power down wakin g - up timer ................................ ................................ ................................ .......... 48 12.1 function description of power down waking - up timer ................................ ................................ . 48 12.2 applications of power down waking - up timer ................................ ................................ ............... 49 13. serial port ................................ ................................ ................................ ................................ ............... 51 13.1 mode 0 ................................ ................................ ................................ ................................ ............ 53 13.2 mode 1 ................................ ................................ ................................ ................................ ............ 55 13.3 mode 2 ................................ ................................ ................................ ................................ ............ 57 13.4 mode 3 ................................ ................................ ................................ ................................ ............ 59 13.5 baud rate ................................ ................................ ................................ ................................ ....... 61 13.6 multiprocessor communication ................................ ................................ ................................ ....... 62 14. serial periphera l interface (spi) ................................ ................................ ................................ ... 64 14.1 features ................................ ................................ ................................ ................................ .......... 64 14.2 function description ................................ ................................ ................................ ....................... 64 14.3 control registers of spi ................................ ................................ ................................ ................. 67 14.4 operating modes ................................ ................................ ................................ ............................ 69 14.4.1 master mode ................................ ................................ ................................ .................... 69 14.4.2 slave mode ................................ ................................ ................................ ...................... 69 14.5 clock formats and data tr ansfer ................................ ................................ ................................ ... 70 14.6 slave select pin configuration ................................ ................................ ................................ ....... 72
publication release date: march 11, 2011 - 3 - revision : v 2.0 14.7 mode fault detection ................................ ................................ ................................ ...................... 73 14.8 write collision error ................................ ................................ ................................ ........................ 73 14.9 overrun error ................................ ................................ ................................ ................................ .. 73 14.10 spi interrupts ................................ ................................ ................................ ................................ 74 15. pulse width modu lator (pwm) ................................ ................................ ................................ ......... 75 16. timed access pro tection (ta) ................................ ................................ ................................ ........... 79 17. interrupt system ................................ ................................ ................................ ................................ .. 81 17.1 priority level structure ................................ ................................ ................................ .................... 87 17.2 interrupt latency ................................ ................................ ................................ ............................. 89 18. in syste m programming (isp) ................................ ................................ ................................ ............. 90 18.1 isp procedure ................................ ................................ ................................ ................................ . 90 18.2 isp commands ................................ ................................ ................................ ............................... 93 18.3 user guide of isp ................................ ................................ ................................ ........................... 93 18.4 isp demo codes ................................ ................................ ................................ ............................ 94 19. power saving mod es ................................ ................................ ................................ ............................ 98 19.1 idle mode ................................ ................................ ................................ ................................ ........ 98 19.2 power down mode ................................ ................................ ................................ .......................... 99 20. clock system ................................ ................................ ................................ ................................ ........ 100 20.1 12t/6t mode ................................ ................................ ................................ ................................ . 100 20.2 external clock source ................................ ................................ ................................ .................. 102 20.3 on - chip rc oscillator ................................ ................................ ................................ ................... 102 21. power monitoring ................................ ................................ ................................ .............................. 103 21.1 power - on detection ................................ ................................ ................................ ...................... 103 21.2 brown - out detection ................................ ................................ ................................ ..................... 103 22. reset conditions ................................ ................................ ................................ ................................ . 107 22.1 power - on reset ................................ ................................ ................................ ............................ 108 22.2 brown - out reset ................................ ................................ ................................ ........................... 108 22.3 rst pin reset ................................ ................................ ................................ .............................. 108 22.4 watchdog timer reset ................................ ................................ ................................ ................. 109 22.5 software re set ................................ ................................ ................................ .............................. 109 22.6 boot select ................................ ................................ ................................ ................................ .... 110 22.7 reset state ................................ ................................ ................................ ................................ ... 111 23. auxiliary features ................................ ................................ ................................ ............................. 113 24. config bytes ................................ ................................ ................................ ................................ .......... 114 25. instruction set ................................ ................................ ................................ ................................ .... 117 26. el ectrical characteris tics ................................ ................................ ................................ ........... 121 26.1 absolute maximum ratings ................................ ................................ ................................ .......... 121 26.2 dc electrical characteristics ................................ ................................ ................................ ........ 121 26.3 ac electrical characteristics ................................ ................................ ................................ ......... 127 27. packages ................................ ................................ ................................ ................................ ................. 131 28. document revisio n history ................................ ................................ ................................ ............ 135
n78e366 a data sheet publication release date: march 11, 2011 - 4 - revision : v2.0 1. description N78E366A is an 8 - bit microcontroller, which has an in - system programmable flash supported . the instru c tion set of N78E366A is fully compatible with the standard 8051 . N78E366A c o n tains a 64 k byte s of main flash a prom, in which the contents of the main program code can be u p dated by parallel programmer/writer or in system programming ( isp ) method which enables on - chip firmware updating . there is a n a d ditional 2 .5 k byte s called ldrom for isp function . N78E366A provi des 256 byte s of sram , 1 k byte s of auxi l iary ram (xram) , four 8 - bit bi - directional and bit - addressable i/o ports , an additional 8 - bit bi - directional and bit - addressable port p4 for lqpf - 48 pac k age ( plcc - 44 and pqfp - 44 just have low nibble 4 bits of p4 and dip - 40 does not have this additional p4 ) , three 16 - bit t imer s / c ounters , one uart , five pwm output channels , and one spi. these peripherals equip with 11 - source with 4 - level priority interrupt s capability. to facilitate programming and verif i- cation, the fla sh inside the N78E366A allows the program memory to be programmed and read e lectronically. once the code confirm s , the user can lock the code for security. N78E366A is built in a precise on - chip rc oscillator of 22 . 1184mhz/11.0592mhz selected by config set ting, factory trimmed t o 1% at room temperature . N78E366A provides add i tional power monitoring detection such as power - on and brown - out detection. it stabilize s the power - on / off sequence for a high reliability system d e- sign. N78E366A microcontroller opera tion consumes a very low power. t wo economic power modes to reduce po w- er consumption , idle mode and p ower d own mode . b oth of them are software selec t able. the idle mode turns off the cpu clock but allows continu ing peripheral operation. the p ower d own mode stops the whole system clock for minimum power co n sumption .
publication release date: march 11, 2011 - 5 - revision : v 2.0 2. features ? fully static design 8 - bit cmos microcontroller . ? wide supply voltage of 2.4 v to 5.5v and wide frequency from 4mhz to 40 mhz. ? 12t mode compatible with the tra dition 8051 timing. ? 6t mode su pported for double performance. ? on - chip rc oscillator of 22.1184mhz/11.0592mhz , trimmed to 1% at room temperature for the precise sy s tem clock. ? 64 k bytes flash aprom for the a p plication p rogram. ? 2.5 k bytes flash ldrom for isp code . ? in - system - programmable (isp) built in . isp erasing or programming supports wide operating voltage 3.0 v~5.5v. ? flash 10,000 writing cycle endurance . greater than 10 years data retention unde r 85 . ? 256 bytes of on - chip ram . ? 1k bytes of on - chip auxiliary ram (xram) . ? 64 k bytes program memory address space and 64 k bytes data memory address space. ? maximum five 8 - bit general purpose i/o ports pin - to - pin compat i ble with standard 8051 , additional and on packages e x cept dip - 40. ? three 16 - bit t imer s / c ounters . ? one dedicate timer for power down mode waking - up. ? one full - duplex uart port . ? f ive pulse width modulated (pwm) output channels . ? one spi communication p ort. ? 11 - source , 4 - priority - level interrupt s capability . ? programmable watchdog timer. ? power - on reset. ? brown - out d etect ion interrupt and reset , 4 - level selected . ? supports s oftware r eset function. ? built - in power management with i dle mode and p ower d own mode . ? code lock for data security. 2 int 3 int
n78e366 a data sheet publication release date: march 11, 2011 - 6 - revision : v2.0 ? much lower power consumption than other standard 8051 pr o ductions. ? industrial temperature grade, - 40 ~85 . ? strong esd, ef t immunity. ? development tool : C parallel programmer / writer . C nuvoton 8 - bit micro controller isp writer. ? p ackag e : p art number aprom p ackage N78E366Ad g 64k bytes 40 - pin dip N78E366A pg 44 - pin plcc N78E366A fg 44 - pin pqfp N78E366Al g 48 - pin lqfp
publication release date: march 11, 2011 - 7 - revision : v 2.0 3. block diagram figure 3 C 1 shows the functional block diagram of N78E366A . it gives the outline of the device. the user can find all the device ? s p e rip heral functions in the diagram. figure 3 C 1 . N78E366A function block diagram 1 2 t 8 0 c 5 1 c p u 6 4 k b y t e s a p r o m f l a s h 2 5 6 b y t e s i n t e r n a l r a m 1 0 2 4 b y t e s x r a m ( a u x i l i a r y r a m ) p w m w a t c h d o g t i m e r 1 2 t / 6 t d i v i d e r o s c i l l a t i n g c i r c u i t s e r i a l p o r t ( u a r t ) t i m e r 0 t i m e r 1 t i m e r 2 b r o w n o u t a n d l o w v o l t a g e d e t e c t i o n s p i x t a l 1 x t a l 2 p 0 [ 7 : 0 ] p 4 [ 7 : 0 ] p 1 [ 7 : 0 ] p 2 [ 7 : 0 ] p 3 [ 7 : 0 ] i n t 1 ( p 3 . 3 ) i n t 0 ( p 3 . 2 ) i n t 3 ( p 4 . 2 ) i n t 2 ( p 4 . 3 ) r x d ( p 3 . 0 ) t x d ( p 3 . 1 ) m o s i ( p 1 . 5 ) m i s o ( p 1 . 6 ) s s ( p 1 . 4 ) s p c l k ( p 1 . 7 ) p w m 0 ~ p w m 4 ( p 1 . 3 ~ p 1 . 7 ) 8 - b i t i n t e r n a l b u s e x t e r n a l i n t e r r u p t t 1 ( p 3 . 5 ) t 0 ( p 3 . 4 ) t 2 e x ( p 1 . 1 ) t 2 ( p 1 . 0 ) v d d v s s o n - c h i p r c o s c i l l a t o r r s t e x t e r n a l m e m o r y b u s i n t e r f a c e r d ( p 3 . 7 ) a l e w r ( p 3 . 6 ) a d [ 7 : 0 ] ( p 0 [ 7 : 0 ] ) a [ 1 5 : 8 ] ( p 2 [ 7 : 0 ] ) i / o p o r t , p 0 i / o p o r t , p 1 i / o p o r t , p 2 i / o p o r t , p 3 i / o p o r t , p 4 2 . 5 k b y t e s l d r o m f l a s h 8 8 8 8 8 8 8 p s e n s y s t e m c l o c k p o w e r m a n a g e m e n t 5 p o w e r d o w n w a k i n g - u p t i m e r
n78e366 a data sheet publication release date: march 11, 2011 - 8 - revision : v2.0 4. pin configuration s figure 4 C 1 . pin assignment of dip 40 - pin figure 4 C 2 . pin assignment of plcc 44 - pin 1 0 9 1 2 1 1 1 4 1 3 1 6 1 5 1 7 m i s o , p w m 3 , p 1 . 6 m o s i , p w m 2 , p 1 . 5 r s t s p c l k , p w m 4 , p 1 . 7 r x d , p 3 . 0 t x d , p 3 . 1 t 0 , p 3 . 4 t 1 , p 3 . 5 2 1 4 3 6 5 8 7 p w m 0 , p 1 . 3 p 1 . 2 s s , p w m 1 , p 1 . 4 t 2 e x , p 1 . 1 t 2 , p 1 . 0 1 9 1 8 2 0 x t a l 2 x t a l 1 3 8 3 9 3 6 3 7 3 4 3 5 3 2 3 3 3 0 3 1 2 9 2 8 4 0 2 6 2 7 2 4 2 5 2 2 2 3 2 1 p 2 . 1 , a 9 p 2 . 2 , a 1 0 p 2 . 3 , a 1 1 p 2 . 4 , a 1 2 p 2 . 0 , a 8 p 2 . 5 , a 1 3 p 2 . 6 , a 1 4 p 2 . 7 , a 1 5 a l e p 0 . 7 , a d 7 p 0 . 6 , a d 6 p 0 . 5 , a d 5 p 0 . 4 , a d 4 p 0 . 0 , a d 0 p 0 . 1 , a d 1 p 0 . 2 , a d 2 p 0 . 3 , a d 3 v d d d i p 4 0 - p i n v s s i n t 0 , p 3 . 2 i n t 1 , p 3 . 3 w r , p 3 . 6 e a p s e n r d , p 3 . 7 8 1 8 6 7 1 0 9 1 2 1 1 1 4 1 3 1 6 1 5 1 7 5 4 3 2 1 4 4 4 3 4 2 4 1 4 0 3 8 3 9 3 6 3 7 3 4 3 5 3 2 3 3 3 0 3 1 2 9 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 m i s o , p w m 3 , p 1 . 6 m o s i , p w m 2 , p 1 . 5 r s t s p c l k , p w m 4 , p 1 . 7 i n t 2 , p 4 . 3 r x d , p 3 . 0 t x d , p 3 . 1 t 0 , p 3 . 4 t 1 , p 3 . 5 p w m 0 , p 1 . 3 p 1 . 2 s s , p w m 1 , p 1 . 4 t 2 e x , p 1 . 1 t 2 , p 1 . 0 a d 0 , p 0 . 0 i n t 3 , p 4 . 2 a d 1 , p 0 . 1 a d 2 , p 0 . 2 a d 3 , p 0 . 3 v d d a l e p 0 . 7 , a d 7 p 4 . 1 p 0 . 6 , a d 6 p 0 . 5 , a d 5 p 0 . 4 , a d 4 p 2 . 5 , a 1 3 p 2 . 6 , a 1 4 p 2 . 7 , a 1 5 x t a l 2 x t a l 1 v s s p 2 . 1 , a 9 p 4 . 0 p 2 . 2 , a 1 0 p 2 . 3 , a 1 1 p 2 . 4 , a 1 2 p 2 . 0 , a 8 p l c c 4 4 - p i n i n t 0 , p 3 . 2 p 3 . 7 , r d i n t 1 , p 3 . 3 p s e n e a p 3 . 6 , w r
publication release date: march 11, 2011 - 9 - revision : v 2.0 figure 4 C 3 . pin assignment of pqfp 44 - pin figure 4 C 4 . pin assignment of lqfp 48 - pin 2 1 2 4 4 1 4 3 6 5 8 7 1 0 9 1 1 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 2 3 3 3 0 3 1 2 8 2 9 2 6 2 7 2 4 2 5 2 3 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 m i s o , p w m 3 , p 1 . 6 m o s i , p w m 2 , p 1 . 5 r s t s p c l k , p w m 4 , p 1 . 7 i n t 2 , p 4 . 3 r x d , p 3 . 0 t x d , p 3 . 1 t 0 , p 3 . 4 t 1 , p 3 . 5 p w m 0 , p 1 . 3 p 1 . 2 s s , p w m 1 , p 1 . 4 t 2 e x , p 1 . 1 t 2 , p 1 . 0 a d 0 , p 0 . 0 i n t 3 , p 4 . 2 a d 1 , p 0 . 1 a d 2 , p 0 . 2 a d 3 , p 0 . 3 v d d a l e p 0 . 7 , a d 7 p 4 . 1 p 0 . 6 , a d 6 p 0 . 5 , a d 5 p 0 . 4 , a d 4 p 2 . 5 , a 1 3 p 2 . 6 , a 1 4 p 2 . 7 , a 1 5 x t a l 2 x t a l 1 v s s p 2 . 1 , a 9 p 4 . 0 p 2 . 2 , a 1 0 p 2 . 3 , a 1 1 p 2 . 4 , a 1 2 p 2 . 0 , a 8 p q f p 4 4 - p i n i n t 0 , p 3 . 2 p 3 . 7 , r d i n t 1 , p 3 . 3 p s e n e a p 3 . 6 , w r 2 4 4 1 4 3 6 5 8 7 1 0 9 1 1 4 8 4 2 4 1 4 0 3 9 3 8 3 7 3 2 3 3 3 0 3 1 2 8 2 9 2 6 2 7 2 5 1 3 1 4 1 5 1 6 1 8 1 9 2 0 2 1 2 2 1 2 1 7 2 3 2 4 3 4 3 5 3 6 4 6 4 7 4 3 4 5 p 4 . 5 p 4 . 6 l q f p 4 8 - p i n p 4 . 4 m i s o , p w m 3 , p 1 . 6 m o s i , p w m 2 , p 1 . 5 r s t s p c l k , p w m 4 , p 1 . 7 i n t 2 , p 4 . 3 r x d , p 3 . 0 t x d , p 3 . 1 t 0 , p 3 . 4 t 1 , p 3 . 5 i n t 0 , p 3 . 2 i n t 1 , p 3 . 3 x t a l 2 x t a l 1 v s s p 2 . 1 , a 9 p 4 . 0 p 2 . 2 , a 1 0 p 2 . 3 , a 1 1 p 2 . 4 , a 1 2 p 2 . 0 , a 8 p 3 . 7 , r d p 3 . 6 , w r a l e p 0 . 7 , a d 7 p 4 . 1 p 0 . 6 , a d 6 p 0 . 5 , a d 5 p 0 . 4 , a d 4 p 2 . 5 , a 1 3 p 2 . 6 , a 1 4 p 2 . 7 , a 1 5 p s e n e a p 4 . 7 p w m 0 , p 1 . 3 p 1 . 2 s s , p w m 1 , p 1 . 4 t 2 e x , p 1 . 1 t 2 , p 1 . 0 a d 0 , p 0 . 0 i n t 3 , p 4 . 2 a d 1 , p 0 . 1 a d 2 , p 0 . 2 a d 3 , p 0 . 3 v d d
n78e366 a data sheet publication release date: march 11, 2011 - 10 - revision : v2.0 table 4 C 1 . pin description pin number s y m bol alternate fun c tion type [1] d escription dip plcc pqfp lqfp 1 2 19 21 15 16 xtal1 i (st) crystal1: this is the i nput pin to the internal i n- verting amplifier . the system clock is from e xternal cry s tal or resonator when fosc ( config3 .1 ) is logic 1 by default . a 0.1 f capac itor is recommended to be add ed on xtal1 pin to gain the more precise freque n cy of the internal rc oscillator frequency if it is s e- lected as the system clock source. 18 20 14 15 xtal2 o crystal2: this is the o utput pin from the internal invertin g amplifier. it emits the inverted signal of xtal1. while on - chip rc oscillator is used, float xtal2 pin always. 40 44 38 41 vdd p power supply: supply voltage v dd for oper a tion. 20 22 16 17 vss p ground: ground potential. 31 35 29 31 i external access enable: to force low will make the cpu execute the external program memory . the address and data will be pr e sented on the bus p0 and p2. if the pin is high, cpu will fetch intern al code unless the p rogram c ounter a d- dresses the area out of the internal program memory . this will make cpu run external program mem o ry con tinuously. possesses reset lock. after all reset , the state will be latched and any state change of this pin after reset will not switch between internal and e x- ternal program memory execution . the user should take care of this pin from floa t- ing but connect ing to v dd directly if internal pr o- gram memory is used. 30 33 27 29 ale o address latch enable: ale is used to en a- ble the address latch that separates the address from the data on port 0. ale runs at 1/6 of the fosc [2] . an ale pulse is omitted always. the u ser can turn ale off by setting a le off (auxr.0) to reduce emi. s etting aleoff will just make ale activating only during external memory access through a movc or movx instruction . ale will stay high in other cond i tions. 29 32 26 28 o program store enable: strobes the ex ternal program memory . when internal pr o gram memory access is performed, there will be no strobe si g nal output from this pin. 9 10 4 4 rst i (st) reset: rst pin is a schmitt trigger input pin for hardware device reset. a high on this pin for two m a chine - cycle s while the system clock is running will reset the device. r s t pin has an internal pull - down resistor allowing power - on reset by simply ea ea ea ea ea psen psen psen
publication release date: march 11, 2011 - 11 - revision : v 2.0 table 4 C 1 . pin description pin number s y m bol alternate fun c tion type [1] d escription dip plcc pqfp lqfp 1 2 connecting an external capac i tor to v dd . 39 43 37 40 p0.0 ad0 d, i/o port0: p ort 0 is an 8 - bit open - drain port by d e fault. via setting p0up ( p0or.0 ) , p0 will switch as weakly pulled up internally . p0 has an alternative function as ad[7:0] while e x- ternal memory accessing. during the external memory access, p 0 will output high will be internal strong pull ed - up rather than weak pull - up in order to drive out high byte address for exte r nal devices. 38 42 36 39 p0.1 ad1 d, i/o 37 41 35 38 p0.2 ad2 d, i/o 36 40 34 37 p0.3 ad3 d, i/o 35 39 33 35 p0.4 ad4 d, i/o 34 38 32 34 p0.5 ad5 d, i/ o 33 37 31 33 p0.6 ad6 d, i/o 32 36 30 32 p0.7 ad7 d, i/o 1 2 40 43 p1.0 t2 i/o port1: p ort 1 is an 8 - bit quasi bi - directional i/o port. its multifunction pins are for t2, t2ex, pwm0 ~ pwm4, , mosi , miso, and spclk . 2 3 41 44 p1.1 t2ex i/o 3 4 42 45 p1.2 i/o 4 5 43 46 p1.3 pwm0 i/o 5 6 44 47 p1.4 pwm1 i/o 6 7 1 1 p1.5 pwm2 mosi i/o 7 8 2 2 p1.6 pwm3 miso i/o 8 9 3 3 p1.7 pwm4 spclk i/o 21 24 18 19 p2.0 a8 i/o port2: p ort 2 is an 8 - bit quasi bi - directional i/o port. it has an alte r native function as a[15:8] while external memory accessing. during the external memory access, p2 will output high will be internal strong pull ed - up rather than weak pull - up in order to drive out high byte add ress for external devices. 22 25 19 20 p2.1 a9 i/o 23 26 20 21 p2.2 a10 i/o 24 27 21 22 p2.3 a11 i/o 25 28 22 23 p2.4 a12 i/o 26 29 23 25 p2.5 a13 i/o 27 30 24 26 p2.6 a14 i/o 28 31 25 27 p2.7 a15 i/o ss ss
n78e366 a data sheet publication release date: march 11, 2011 - 12 - revision : v2.0 table 4 C 1 . pin description pin number s y m bol alternate fun c tion type [1] d escription dip plcc pqfp lqfp 1 2 10 11 5 5 p3.0 rxd i/o port3: p o rt 3 is an 8 - bit quasi bi - directional i/o port. its multifunction pins are for rxd, txd , , , t0, t1, , and . 11 13 7 7 p3.1 txd i/o 12 14 8 8 p3.2 i/o 13 15 9 9 p3.3 i/o 14 16 10 10 p3.4 t0 i/o 15 17 11 11 p3.5 t1 i/o 16 18 12 13 p3.6 i/o 17 19 13 14 p3.7 i/o - 23 17 18 p4.0 i/o port4 [3] : p ort 4 is an 8 - bit quasi bi - directional i/o port. it also possesses bit - addressable feature as p0~p3. p4.2 and p4.3 are alternative fun c tion pins of and . - 34 28 30 p4.1 i/o - 1 39 42 p4.2 i/o - 12 6 6 p4.3 i/o - - - 48 p4.4 i/o - - - 12 p4.5 i/o - - - 24 p4.6 i/o - - - 36 p4.7 i/o [1] i/o type description. i: input, o: output, i/o: quasi bi - direction , d: open - drain, p: power pins, st: schmitt tr igger. [2] while switching to 6t mode, ale will run at 1/ 3 of fosc. [3] a full 8 - bit p4 is just on lqpf - 48 package . plcc - 44 and pqfp - 44 just have low nibble 4 bits of p4. dip - 40 does not have this additional p4 . 0 int 1 int wr rd 0 int 1 int wr rd 3 int 2 int 3 int 2 int
publication release date: march 11, 2011 - 13 - revision : v 2.0 the application circuit is shown below . the user is recommended follow the circuit enclosed by gray blocks to achieve the most stable and reliable operation of mcu especially in a noisy power environment for a healthy em s immunity . if internal rc oscillator is used as the sy s tem clock, a 0. 1 f capacitor should be added to gain a precise rc frequency. figure 4 C 5 . application circuit for execution of internal pr o gram code with external crystal crystal frequency r c1 c 2 4mhz~33mhz without d epend on crystal spec i fications 33mhz~40mhz 5k~10k figure 4 C 6 . application circuit for execution of internal pr o gram code with internal rc oscillator x t a l 2 x t a l 1 n 7 8 e 3 6 6 a r s t v d d e a 1 0 f 1 0 k g n d v d d 0 . 1 f 0 . 1 f 1 0 f a s c l o s e t o t h e p o w e r s o u r c e a s p o s s i b l e a s c l o s e t o m c u a s p o s s i b l e 0 . 1 f a s c l o s e t o m c u a s p o s s i b l e v s s x t a l 2 x t a l 1 n 7 8 e 3 6 6 a c 1 c 2 r v s s r s t v d d e a 1 0 f 1 0 k g n d v d d 0 . 1 f 0 . 1 f 1 0 f a s c l o s e t o t h e p o w e r s o u r c e a s p o s s i b l e a s c l o s e t o m c u a s p o s s i b l e
n78e366 a data sheet publication release date: march 11, 2011 - 14 - revision : v2.0 5. memory organization a standard 8051 base d mcu divides the memory into two different sections, the p rogram m emory and the d a- ta memory . the program memory is used to store the instru c tion codes, whereas the data memory is used to store data o r variations du ring the pr o gram execution . data memory occupies a separate address space from program memory . in N78E366A , the re are 256 byte s of internal scratch - pad ram and up to 64 k byte s of memory space for external data memory . the mcu gene r- ates the 16 - bit or 8 - bit addresses , read and write strobe signals ( and , respectively) during external data memory access. for many applications which need more internal ram, N78E366A possesses on - chip 1 k byte s of ram (called xram ) ac cessed by movx instruction. t he whole embedded flash is divided in to 3 b anks , ap rom for storage of user ? s program code , ld rom for isp pr o gram and config bytes . e a ch b ank is accumulated page by page and the page size is 256 byte s. the flash control unit sup ports page erase, byte program , and byte read modes. the external writer tools though specific i/o pins and the internal isp (in s ys tem p rogram ming ) function both can pe r form these modes. 5.1 internal program m emory program memory is the one, which stores the program codes to execute, a s shown in figure 5 C 1 . while pin is pulled high and a fter any reset, the cpu begins execution from location 0000h where should be the starting point of the user ? s application code. to service the interrupts, the interrupt service locations (called i n- terrupt vectors) should be located in the program memory . e ach interrupt is assigned with a fixed location in the program memory . the interrupt causes the cpu to jump to that location with where it commences exec u- tion of the interrupt service routine ( isr ) . external interrupt 0, for example, is assigned to location 0003h. if external interrupt 0 is going to be used, its service routine must begin at location 0003h. if the interrupt is not going to be used, its service loc a tion is available as general purpose program memory . the interrupt service locations are spaced at an inte r val of 8 byte s : 0003h for external interrupt 0, 000bh for timer 0, 0013h for e x ternal interrupt 1 , 001bh for timer 1, etc. if an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8 - byte interval. however l onger service routines should use a jmp instruction to skip over subseque nt interrupt locations if other inte r rupts are in use . N78E366A provides two internal program memory bank aprom and ldrom. although they both behave the same as the standard 8051 program memory , they play different rules according to their rom size. the rd wr ea
publication release date: march 11, 2011 - 15 - revision : v 2.0 ap rom on N78E366A is 64 k - byte size . the user ? s main program code is normally put inside. all instructions are fetched for exec u tion from this area. the movc instruction can also read this flash memory region. N78E366A supports the other individual program m emory bank called ldrom besides aprom. the main fun c tion of ldrom is to store the isp application program. u ser may develop the isp in ldrom for updating aprom content. the program in aprom can also re - program ldrom. for isp detail s and configuration bit s e t ting related with aprom and ldrom , see section 18. i n system programming ( isp ) on page 90 . note that because aprom and ldrom are hardwa re individual blocks, consequently if cpu reboots from ldrom, cpu will automatically re - vectors program c ounter 0000h to the ldrom start a d dress. therefore, cpu accounts the ldrom as an independent program memory and all interrupt vectors are i n dependent f rom aprom. figure 5 C 1 . N78E366A program memory structure l d r o m 0 0 0 0 h 0 0 0 0 h 0 9 f f h f f f f h 0 0 0 0 h e x t e r n a l p r o g r a m m e m o r y e a = 1 , b s = 0 [ 1 ] e a = 1 , b s = 1 e a = 0 f f f f h [ 1 ] e a i s t h e s t a t e o f e a p i n a f t e r p o w e r - o n r e s e t . b s i s b i t 1 o f c h p c o n . [ 2 ] w h i l e e x e c u t i o n b e y o n d t h e t o p b o u n d a r y o f i n t e r n a l p r o g r a m m e m o r y , c p u w i l l s w i t c h t o e x t e r n a l p r o g r a m m e m o r y t o c o n t i n u e . a p r o m f f f f h i n t e r n a l p r o g r a m m e m o r y [ 2 ] f f f f h
n78e366 a data sheet publication release date: march 11, 2011 - 16 - revision : v2.0 5.2 external program m emory N78E366A is a 16 - bit address - width cpu. it can address 64k - byte program code. besides the interna l pr o- gram memory , the external additional program memory is also can be used. the exte rnal program addressing will be ex e cuted under cases below, 1. the pc (program c ounter) value is beyond the boundary size address of aprom or ldrom while pin is pulled high during power on. the cpu will continue to fetch the external p rogram memory . 2. while pin is pulled low during power on p erio d, the cpu will run totally 64k - byte code externally. while the external mode is running, the p0 and p2 will produce a d dress and data signals to fetching external p rogram memory . in this case, p0 and p2 cannot be general pu r pose i/o any mor e. will also toggle out to strobe the e x ternal program memory . for the ha rdware circuit for external program execution, see figure 5 C 2 . program memory interface . for security pin state will be locked after power on. the user cannot switch the program running inte rnally or externally by after power on. the other design for data security is movc lock enable (movcl, config0.2). while this bit is set 0, the external program memory code is inhibited to read internal aprom or ldrom contents throu gh movc instruction. figure 5 C 2 . program memory interface ea ea psen n 7 8 e 3 6 6 a l a t c h e x t e r n a l p r o g r a m m e m o r y 8 8 8 p 0 p 2 a l e p s e n e a o e d a t a [ 7 : 0 ] a d d r e s s [ 7 : 0 ] a d d r e s s [ 1 5 : 8 ] p 0 p 0
publication release date: march 11, 2011 - 17 - revision : v 2.0 5.3 internal data memory figure 5 C 3 s hows the internal and external data memory sp aces available on N78E366A . i nternal data memory can be divi ded into three blocks . they are the l ower 128 byte s of ram , the u pper 128 byte s of ram , and the 128 byte s of sfr space. internal data memory addresses are always 8 - bit wide, which implies an a d- dre ss space of only 256 byte s. direct address ing higher than 7fh will access the s pecial f unction r egister s ( sfr s) space and indirect address ing higher than 7fh will access the upper 128 byte s of ram . although the sfr space and the u pper 128 byte s of ram shar e the same logic address, 80h through ffh, a ctually they are physically separate entities. direct addressing to distinguish with the higher 128 bytes of ram can only a c cess these sfrs . sixteen addresses in sfr space are both byte and bit - addressable . the b it - addressable sfrs are those whose a d dress es end in 0h or 8h. the l ower 128 byte s of internal ram are present in all 8051 d e vices. the lowest 32 byte s are grouped into 4 banks of 8 registers. program instructions call these registers as r0 through r7. two bits rs0 and rs1 in the pr o gram status word (psw [ 3 :4] ) select which r egister b ank is use d . this benefits more efficien cy of code space, since register instructions are shorter than instructions that use direct a d dressing. the next 16 byte s above the regis ter bank s ( byte - address 20h through 2fh) form a block of bit - addressable memory space (bit - address 00h through 7fh) . the 8051 instruction set includes a wide selection of si n gle - bit instructions, and the 128 bits in this area can be directly addressed by t hese instructions. the bit addresses in this area are 00h through 7fh. all byte s in the l ower 128 - byte space can be accessed by either direct or indirect addressing . i ndirect addres s- ing can only access the upper 128 . another application implemented with t h e whole block of internal 256 - byte ram is for the stack. this area is selected by the stack pointer (sp), which stores the address of the top of the stack. whenever a j mp , call or interrupt is invoked, the return a d dress is placed on the stack. there is no restriction as to where the stack can begin in the ram. by default however , the stack pointer co n tains 07 h at reset. the user can then change this to any value d e sired. the sp will point to the last used value. therefore, the sp will be incremented and th en address saved onto the stack. co n versely, while popping from the stack the contents will be read first, and then the sp is decreased.
n78e366 a data sheet publication release date: march 11, 2011 - 18 - revision : v2.0 figure 5 C 3 . N78E366A data memory structur e figure 5 C 4 . 256 bytes internal ram addressing e x t e r n a l d a t a m e m o r y ( x r a m e n = 0 ) u p p e r 1 2 8 b y t e s i n t e r n a l r a m ( i n d i r e c t a d d r e s s i n g ) 0 0 h 7 f h 8 0 h f f h 1 k b y t e s a u x i l i a r y r a m ( x r a m e n [ 1 ] = 1 ) l o w e r 1 2 8 b y t e s i n t e r n a l r a m ( d i r e c t o r i n d i r e c t a d d r e s s i n g ) s f r ( d i r e c t a d d r e s s i n g ) [ 1 ] x r a m e n i s b i t 4 o f c h p c o n . x r a m i s e n a b l e d a f t e r a n y r e s e t . [ 2 ] i f x r a m e n i s 1 y e t t h e a d d r e s s o v e r 3 f f h , c p u w i l l u s e e x t e r n a l d a t a m e m o r y a b o v e 4 0 0 h . 0 0 0 h 3 f f h f f f f h 0 0 h [ 2 ] 0 0 0 0 h r e g i s t e r b a n k 0 r e g i s t e r b a n k 1 r e g i s t e r b a n k 2 r e g i s t e r b a n k 3 0 3 0 2 0 1 0 0 0 4 0 5 0 6 0 7 0 b 0 a 0 9 0 8 0 c 0 d 0 e 0 f 1 3 1 2 1 1 1 0 1 4 1 5 1 6 1 7 1 b 1 a 1 9 1 8 1 c 1 d 1 e 1 f 2 3 2 2 2 1 2 0 2 4 2 5 2 6 2 7 2 b 2 a 2 9 2 8 2 c 2 d 2 e 2 f 3 3 3 2 3 1 3 0 3 4 3 5 3 6 3 7 3 b 3 a 3 9 3 8 3 c 3 d 3 e 3 f 4 3 4 2 4 1 4 0 4 4 4 5 4 6 4 7 4 b 4 a 4 9 4 8 4 c 4 d 4 e 4 f 5 3 5 2 5 1 5 0 5 4 5 5 5 6 5 7 5 b 5 a 5 9 5 8 5 c 5 d 5 e 5 f 6 3 6 2 6 1 6 0 6 4 6 5 6 6 6 7 6 b 6 a 6 9 6 8 6 c 6 d 6 e 6 f 7 3 7 2 7 1 7 0 7 4 7 5 7 6 7 7 7 b 7 a 7 9 7 8 7 c 7 d 7 e 7 f d i r e c t o r i n d i r e c t a c c e s s i n g r a m i n d i r e c t a c c e s s i n g r a m 0 0 h 0 7 h 2 8 h 0 8 h 0 f h 1 0 h 1 7 h 1 8 h 1 f h 2 0 h 2 1 h 2 2 h 2 3 h 2 4 h 2 5 h 2 6 h 2 7 h 2 9 h 2 a h 2 b h 2 c h 2 d h 2 e h 2 f h 3 0 h 7 f h 8 0 h f f h 0 0 h f f h
publication release date: march 11, 2011 - 19 - revision : v 2.0 5.4 on - chip x ram N78E366A provides additional on - chip auxiliary ram called xram to enlarge ram space. t he 1024 bytes of xram (0 00 h to 3 ffh) are indirectly accessed by move external instruction movx . for detail s , see se c tion 8. " auxiliary ram (xram) " on page 28 . 5.5 external da ta memory access to external data memory can use either a 16 - bit address ( using ?movx @ dptr ? ) or an 8 - bit a d dress ( using ? movx @ri? , i = 0 or 1). for another 1k - byte xram exists, remember the bit xramen (chpcon.4) should be cleared as logic 0 in order to a ccess the range of 000h to 3ffh address of the external data memory. 16 - bit addresses are often used to access up to 64k byte s of external ram. whenever a 16 - bit address is used, p0, p2, p 3 .7 and p 3 .6 serve as the low byte address /data , the high byte addre ss , strobe and strobe signals respectively. meanwhile the pins listed above cannot be used as general purpose i/o during e x ternal data m emory access. 8 - bit addresses are often used in conjunction with one or more other i/o lines to page the ram . for e x ample, if a 1k - byte external ram is used , p ort 0 serves as a multiplexed address/data bus to the ram, and 2 pin s of port 2 are used to pag e the ram. the cpu generates and (alternate functions of p3.7 and p3.6) to strobe the memory. in 8 - bit addressing mode, p2 pins other than the two pins for ram paging are free for ge n- eral purpose i/o usage. this will facilitate p2 application. of course, the user may use any other i/o lines i n- stead of p2 to page the ram. in all case s , the low byte of the address is time - multiplexed with the data byte on port 0. ale (address latch enable) should be used to capture the address byte into an external latch. the address byte is valid at the negative transition of ale. then, in a write cycle, the data byte to be written appears on port 0 just before is activated, and remains there until after is deactivated. in a read cycle, the incoming byte is a c cepted at port 0 just before the read strobe is deactivated. during any access to external me m ory, the cpu writes 0ffh to the port 0 latch ( p0 in sfrs ), thus obliterating whatever information the port 0 sfr may have been holding. rd wr
n78e366 a data sheet publication release date: march 11, 2011 - 20 - revision : v2.0 figure 5 C 5 . data memory interface n 7 8 e 3 6 6 a l a t c h e x t e r n a l d a t a m e m o r y 8 8 8 p 0 p 2 a l e o e d a t a [ 7 : 0 ] a d d r e s s [ 7 : 0 ] a d d r e s s [ 1 5 : 8 ] r d w r w e
publication release date: march 11, 2011 - 21 - revision : v 2.0 6. special function reg ister (sfr ) the N78E366A uses special function registers (sfrs) to control and monitor peripherals and their m odes. the sfrs reside in the regi s ter locations 80 ~ ff h and are accessed by direct addressing only. some of the sfrs are bit - addressable . this is very useful in cases where users would like to modify a particular bit directly without changing other bits . t hose which are bit - addressable sfrs end their addresses as 0 h or 8 h . N78E366A contain s all the sfrs pr e sent ing in the standard 8051 . however some additional sfrs are built in . therefore, some of u n used byte s in the original 8051 have been given new functions. the sfrs is listed as below . ta ble 6 C 1 . N78E366A special function registers mapping f8 - - - - - - - - ff f0 b - - spcr spsr spdr - - f7 e8 - - - - - - - - ef e0 acc - - - - - - - e7 d8 p4 pwmp pwm0 pwm1 pwmcon 0 pwm2 pwm3 - df d0 psw - - - - - - - d7 c8 t2con t2mod rcap2l rcap2h tl2 th2 pwmcon 1 pwm4 cf c0 xicon - - - - - - ta c7 b8 ip - iph eiph eip eie - - bf b0 p3 - - - - - - - b7 a8 ie - wdcon p dcon pmc - isp fd isp cn af a0 p2 xramah - - isptrg - isp al isp ah a7 98 scon sbuf - - - - - chpcon 9f 90 p1 - - - - - rsr - 97 88 tcon tmod tl0 tl1 th0 th1 auxr - 8f 80 p0 sp dpl dph - - p0or pcon 87 in bold bit - addres s able - r e served note that the reserved sfr addresses must be kept in their own initial states. users should never change their va l ues.
n78e366 a data sheet publication release date: march 11, 2011 - 22 - revision : v2.0 table 6 C 2 . N78E366A s fr description s and reset value s symbol d efinition a ddress msb lsb [ 1 ] reset value [ 2 ] spdr s pi data f 5 h 0 0 0 0 0 0 0 0 b spsr s pi s tatus f 4 h spif wcol s piovf modf dismodf - - - 0000 0 0 0 0 b spcr s pi c ontrol f 3 h ssoe spien lsbfe mstr cpol cpha spr1 spr0 0 0 0 0 0 0 0 0 b b b register f0h (f7) (f6) (f5) (f4) (f3) (f2) (f1) (f0) 0 0 0 0 0 0 0 0 b acc accumulator e0h (e7) (e6) (e5) (e4) (e3) (e2) (e1) (e0) 0 0 0 0 0 0 0 0 b pwm 3 pwm3 duty deh 0 0 0 0 0 0 0 0 b pwm2 pwm2 duty ddh 0 0 0 0 0 0 0 0 b pwmcon 0 pwm co n trol 0 dch pwm3oe pwm2oe pwm3en pwm2en pwm1oe pwm0oe pwm1en pwm0en 0 0 0 0 0 0 0 0 b pwm1 pwm1 duty d b h 0 0 0 0 0 0 0 0 b pwm0 pwm 0 duty dah 0 0 0 0 0 0 0 0 b pwmp pwm period d9h 0 0 0 0 0 0 0 0 b p4 port 4 d8h ( df ) ( de ) ( dd ) ( dc ) ( db ) ( da ) ( d9 ) ( d8 ) 1 1 1 1 1 1 1 1 b psw program status word d0h (d7) cy (d6) ac (d5) f0 (d4) rs1 (d3) rs0 (d2) ov (d1) f1 (d0) p 0 0 0 0 0 0 0 0 b pwm4 pwm4 duty cfh 0 0 0 0 0 0 0 0 b pwmcon 1 pwm co n trol 1 ceh - - - - - pwm4oe - pwm4en 0 0 0 0 0 0 0 0 b th2 t imer 2 high byte cdh 0 0 0 0 0 0 0 0 b tl2 timer 2 low byte cch 0 0 0 0 0 0 0 0 b rcap2h timer 2 r e load/ capture high byte cbh 0 0 0 0 0 0 0 0 b rcap2l timer 2 r e load/ capture low byte cah 0 0 0 0 0 0 0 0 b t2mod timer 2 mode c9h - - - - - - t2oe - 0 0 0 0 0 0 0 0 b t2con timer 2 co n trol c8h (cf) tf2 (ce) exf2 (cd) rclk (cc) tclk (cb) exen2 (ca) tr2 (c9) (c8) 0 0 0 0 0 0 0 0 b ta timed a ccess p rote c tion c7h 0 0 0 0 0 0 0 0 b xicon external interrupt co n trol c0h (c7) px3 (c6) ex3 (c4) ie3 (c4) it3 (c3) px2 (c2) ex2 (c1) ie2 (c0) 1 it2 0 0 0 0 0 0 0 0 b e ie extensive i nterrupt en a- ble bdh - - - - - ebod e p dt espi 0000 0 0 0 0 b e ip extensive i nterrupt prior i- ty bch - - - - - pbov p p dt pspi 0 0 0 0 0 0 0 0 b e ip h extensive i nterrupt prior i- ty h igh bbh - - - - - pbodh p p dth pspih 0 0 0 0 0 0 0 0 b iph interrupt priority high bah px3 h px2 h pt2 h ps h pt1 h px1 h pt0 h px0 h 0 0 0 0 0 0 0 0 b ip interr upt priority b8h (bf) - (be) - (bd) pt2 (bc) ps (bb) pt1 (ba) px1 (b9) pt0 (b8) px0 00 00 0 0 0 0 b p3 port 3 b0h (b7) (b6) (b5) t1 (b4) t0 (b3) (b2) (b1) txd (b0) rxd 1 1 1 1 1 1 1 1 b isp cn isp flash control af h isp a17 isp a16 f oe n fcen f ctrl3 f ctrl2 f ctrl1 f ctrl0 00 00 0 0 0 0 b isp fd isp flash data ae h 0 0 0 0 0 0 0 0 b pmc [3] power monitoring co n trol ach boden - - borst bof [ 4 ] lpbod - bos [ 5 ] power - o n [ 6 ] , x x x x x 00 x b brown - out , xxxx 1 0 0 x b others , xxxx 0 00 x b p dcon power down wa k ing - up timer control ab h pdten p dtck pdtf - - pps2 pps1 pps0 00 00 0 0 0 0 b wdcon [3] watch d og timer c o n trol aa h wdten wdclr - widpd wdtrf wps2 wps1 wps0 power - on [ 6 ] , x 0 0 0 0 0 0 0 b watchdog , x 00 u 1 uuu b othe rs , x 00 u u uuu b ie interrupt enable a8h (af) ea (ae) - (ad) et2 (ac) es (ab) et1 (aa) ex1 (a9) et0 (a8) ex0 0 0 0 0 0 0 0 0 b isp ah isp address high byte a7 h 0 0 0 0 0 0 0 0 b isp al isp address low byte a6 h 0 0 0 0 0 0 0 0 b isptrg [3] isp trigger a4h - - - - - - - isp go 0 0 0 0 0 0 0 0 b xramah a uxiliary ram a d dress high byte a 1h - - - - - - xramah.1 xramah.0 0 0 0 0 0 0 0 0 b p2 port 2 a0h (a7) a15 (a6) a14 (a5) a13 (a4) a12 (a3) a11 (a2) a10 (a1) a9 (a0) a8 1 1 1 1 1 1 1 1 b 2 int 3 int 2 t / c 2 rl / cp rd wr 1 int 0 int
publication release date: march 11, 2011 - 23 - revision : v 2.0 table 6 C 2 . N78E366A s fr description s and reset value s symbol d efinition a ddress msb lsb [ 1 ] reset value [ 2 ] chpcon [3] chip c ontrol 9 fh swrst ispf ldue n xram en - - bs ispen software [ 6 ] , 000 1 00 u 0b others , 000 1 00 x 0b sbuf serial buffer 99h 0 0 0 0 0 0 0 0 b scon serial co n trol 98h (9f) sm0 (9e) sm1 (9d) sm2 (9c) ren (9b) tb8 (9a) rb8 (99) ti (98) ri 0 0 0 0 0 0 0 0 b rsr reset status register 96h - - - - - borf - sw rf power - on, 0000 0 0 0 0 b brown - out , 0 0 0 0 0 1 0 u b software, 0 0 0 0 0 u 0 1 b others , 0000 0 u 0 u b p1 port 1 90h (9 7 ) pwm 4 spclk (96) pwm3 miso (95) pwm2 mosi (94) pwm1 (93) pwm0 (92) (91) t2ex (90) t2 1 1 1 1 1 1 1 1 b auxr auxiliary register 8eh - - - - - - - aleoff 0 0 0 0 0 00 0 b th1 timer 1 high byte 8dh 0 0 0 0 0 0 0 0 b th0 timer 0 high byte 8ch 0 0 0 0 0 0 0 0 b tl1 timer 1 low byte 8bh 0 0 0 0 0 0 0 0 b tl0 timer 0 low byte 8ah 0 0 0 0 0 0 0 0 b tmod timer 0 and 1 mode 89h gate c/t m1 m0 gate c/t m1 m0 0 0 0 0 0 0 0 0 b tcon timer 0 and 1 control 88h (8f) tf1 (8e) tr1 (8d) tf0 (8c) tr0 (8b) ie1 (8a) it1 (89) ie0 (88) it0 0 0 0 0 0 0 0 0 b pcon power control 87h smod - - pof gf1 gf0 pd idl power - on, 00 0 1 0 0 0 0 b others , 00 0 u 0 0 0 0 b p0or p0 option regi s te r 86h - - - - - - - p0up 0 0 0 0 0 0 0 0 b dph data pointer high byte 83h 0 0 0 0 0 0 0 0 b dpl data pointer low byte 82h 0 0 0 0 0 0 0 0 b sp stack pointer 81h 0 0 0 0 0 1 1 1 b p0 port 0 80h (87) a7 (86) a6 (85) a5 (84) a4 (83) a3 (82) a2 (81) a1 (80) a0 1 1 1 1 1 1 1 1 b [ 1 ] ( ) item means the bit address in bit - addressable sfrs . [ 2 ] reset value symbol description. 0: logic 0 , 1 : logic 1 , u: u n changed , x : see [ 4 ] ~ [ 7 ] . [ 3 ] these sfrs have ta protected writing . [ 4 ] bof has different power - on reset value accord ing to cboden (config2.7) and cborst (config2.4). see table 21 C 1 . bof r eset v alue . [ 5 ] bos is a read - only flag decided by v dd level while brown - out detection is enabled. [ 6 ] these sfrs have bits which are initializ ed after specified reset by loa d ing certain bits in config bytes . see section 24. config bytes on page 114 for details. note that bits m arked in " - " must be kept in their own initial states. u s ers should never change their values. ss
n78e366 a data sheet publication release date: march 11, 2011 - 24 - revision : v2.0 7. general 80 c 51 system control a or acc C accumulator ( bit - addressable ) 7 6 5 4 3 2 1 0 acc.7 ac c.6 acc.5 acc.4 ac c.3 acc.2 acc.1 ac c.0 r/w r/w r/w r/w r/w r/w r /w r/w address: e 0 h reset value: 0000 0000b b it name description 7 :0 acc[7:0] accumulator . the a or acc register is the standard 8051 accumulator for arithmetic oper a tion . b C b register ( bit - addressable ) 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 r/w r/w r/w r/w r/w r/w r/w r/w address: f 0 h reset value: 0000 0000b b it name description 7 :0 b[7:0] b register . the b register is the other accumulator of the standard 8051 . it is used mainly for mul and div operations. sp C stack pointer 7 6 5 4 3 2 1 0 sp[7:0] r/w address: 81h reset value: 0000 0111b b it name description 7 :0 sp[7:0] stack pointer . the stack pointer stores the s cratch - pad ram address where the stack begins. it is incremented before data is stored during push or call instru c tions. note that the default value of sp is 07h. it causes the stack to begin at location 08h. dpl C data pointer low byte 7 6 5 4 3 2 1 0 dpl [7:0] r/w address: 8 2 h reset value: 0000 0 000 b b it name description 7 :0 dpl [7:0] data pointer low byte . this is the low byte of the standard 8051 16 - bit data pointer. dpl co m bined with dph serve as a 16 - bit data pointer dptr to address non - scratch - pad memory or program memory .
publication release date: march 11, 2011 - 25 - revision : v 2.0 dph C data pointer high byte 7 6 5 4 3 2 1 0 dph[7:0] r/w address: 83h reset value: 0000 0000b b it name description 7 :0 dph[7:0] data pointer high byte . this is the high byte of the standard 8051 16 - bit data pointer. dph co m bined with dpl serve as a 16 - bit data pointer dptr to address non - scratch - pad memory or program memory . psw C program s tatus word ( bit - addressable ) 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p r/w r/w r/w r/w r/w r/w r/w r address: d0 h reset value: 0000 0000 b b it name description 7 cy carry flag . for a adding or subtracting operation, cy will be set when the previous oper a tion resulted in a carry - out from or a borrow - in to the most significant bit , otherwise cleared. if the previous operation is mul or div, cy is always 0. c y is affected by da a instruction which indicates that if the original bcd sum is greater than 100 . f or a cjne branch, cy will be set if the first unsigned integer value is less than the second one. othe r wise, cy will be cleared. 6 ac auxiliary carry . set when the previous operation resulted in a carry - out from or a borrow - in to the 4 th bit of the low o r der nibble, otherwise cleared. 5 f0 user flag 0 . the g eneral purpose flag that can be set or cleared by the user. 4 rs1 register bank select ing bit s. these two bits select one of four banks in which r0 ~ r7 locate. rs1 rs0 register bank ram a d dress 0 0 0 00 ~ 07 h 0 1 1 08 ~ 0f h 1 0 2 10 ~ 17 h 1 1 3 18 ~ 1f h 3 rs0
n78e366 a data sheet publication release date: march 11, 2011 - 26 - revision : v2.0 b it name description 2 ov overflow flag . ov is used for a signed character operands. for a add or addc instruction, ov will be set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not bit 6. otherwise, ov is cleared. o v indicates a negative number produced as the sum of two positive operands or a positive sum from two negative ope r- ands. for a subb, ov is set if a borrow is needed into bit6 but not into bit 7, or into bit7 but not bit 6 . otherwise, ov is cleared. ov indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive nu m ber is subtracted from a negative number. for a mul, if the product is greater than 255 ( 0 0ffh), ov will be set. ot h erwise, it is cleared. for a div, it is normally 0. however, if b had originally contained 00h, the va l ues returned in a and b will be undefined. meanwhile, the ov will be set. 1 f1 user f lag 1 . the g eneral purpose flag that can be set or cleared by the user via software . 0 p parity flag . set to 1 to indicate an odd number of ones in the accumulator. cleared for an even number of ones. it performs even parity check. table 7 C 1 . inst ructions that affect flag settings instruction c y o v ac instruction c y o v ac add x [1] x x clr c 0 addc x x x cpl c x subb x x x anl c, bit x mul 0 x anl c, / bit x div 0 x orl c, bit x da a x orl c, / bit x rrc a x mov c, bit x rl c a x cjne x setb c 1 [1] x indicates the modification depends on the result of the i n struction.
publication release date: march 11, 2011 - 27 - revision : v 2.0 pcon C power control 7 6 5 4 3 2 1 0 smod - - pof gf1 gf0 pd idl r/w - - r/w r/w r/w r/w r/w address: 87h reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it name description 3 gf1 general purpose flag 1 . the g eneral purpose flag that can be set or cleared by the user. 2 gf0 general purpose flag 0. the g eneral purpose flag that can be set or cleared by the user.
n78e366 a data sheet publication release date: march 11, 2011 - 28 - revision : v2.0 8. auxiliary ram (xram) N78E366A provides additional on - chip 1k - byte ram called xram to enlarge the ram space. it occupies the address space from 000h through 3ffh. the xram is enable d after all resets. the 1024 bytes of xram are indirectly accessed by move external instruction movx @dptr or movx @ri along with xramah. (if xram is enabled, movx @ri cannot be used to access external ram anymore.) this block of xram shares the same logic address of 000h through 3ffh with the exte rnal ram. a dptr value given larger than 03ffh will map to the external ram no matter of the value of bit xramen (chpcon.4). if the user would like to access contents within 000h to 3ffh address of the o ff - chip external xram, the xramen bit should be clear ed as logic 0. (note that chpcon is a ta writing protected sfr.) when the xram is accessed, the a d dress fetching signal will not emit via p0, p2, , and . note that the stack pointer cannot locate in any part of x ram. chpcon C chip control ( ta protected ) 7 6 5 4 3 2 1 0 swrst ispf ldue n x ram en - - bs ispen w r /w r/w r/w - - r/w r /w address: 9fh reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it na me description 4 xram en x ram enable. 0 = disable on - chip xram. 1 = e nable on - chip xram . (the default value after all resets.) xramah C x ram address high byte 7 6 5 4 3 2 1 0 - - - - - - xramah.1 xramah.0 - - - - - - r/w r/w address: a1 h reset value: 0 000 0000b b it name description 7:2 - reserved. 1:0 xramah[1:0] x ram address high byte. to set the xram high byte address. this setting works along with mov @ri instructions. the demo codes are listed below. xram demo code: mov xramah,#01h ;write #5ah to xram with a d dress @0123h . mov r0,#23h mov a,#5ah movx @r0,a mov xramah,#01h ;read from xram with address @0123h . mov r0,#23h movx a,@r0 wr rd
publication release date: march 11, 2011 - 29 - revision : v 2.0 mov dptr,#0123h ;write #5bh to xram with a d dress @0123h . mov a,#5bh movx @dptr,a mov dptr,#0123h ;read from xram with address @0123h . movx a,@dptr
n78e366 a data sheet publication release date: march 11, 2011 - 30 - revision : v2.0 9. i/o port structure and o peration N78E366A has maxim um five 8 - bit width, bit - addressable ports p0~p4 . the configuration of p1~p4 is the qu a- si bi - directional i/o . this type rule s as both input and output. w hen the port outputs a logic high, it is weakly driven, a l lowing an external device to pull the pin low. when the pin is pulled low, it is driven strongly and able to sink a large current. in the quasi bi - directional i/o structure, t here are t hree pull - up transistors . each of them serve s different purposes. one of these pull - ups, called the very weak pull - up, is turned on whenever the port latch contains a logic 1. the very weak pull - up sources a very small current that will pull the pin hi gh if it is left floating. a second pull - up, called the weak pull - up, is turned on when the outside port pin itself is at a logic 1 level. this pull - up provides the pri mary source current for a quasi bi - directional pin that is outpu t ting a 1. if a pin th at has a logic 1 on it is pulled low by an external device, the weak pull - up turns off, and only the very weak pull - up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current (larger than i tl ) to ove r come the weak pull - up and make the voltage on the port pin below its input threshold (lower than v il ) . the third pull - up is the strong pull - up. this pull - up is used to speed up low - to - high transitions on a quasi bi - directional port pin when the por t latch changes from a logic 0 to a logic 1. when this occurs, the strong pull - up turns on for two - peripheral - clock time in order to pull the port pin high quickly. then it turns off and weak: pull - up continues remaining the port pin high . the quasi bi - di rectional port stru c ture is shown as below. figure 9 C 1 . quasi bi - direction i/o structure the default configuration of p0 is open - drain structure . to serve as an i/o port the exter nal pull - up resistor is always necessary. N78E366A also provide an internal p0 pull - up resistors for each pins. via setting p0up ( p0or.0 ) p0 will switch on its weak pull - up internally and behave the same as the quasi bi - directional i/o pins. p o r t p i n 2 - p e r i p h e r a l - c l o c k d e l a y i n p u t p o r t l a t c h p p p n v d d s t r o n g v e r y w e a k w e a k
publication release date: march 11, 2011 - 31 - revision : v 2.0 p0 and p2 also serve as a ddress/ d ata bus when external memory is running or is accessed by movc or movx instruction. in these cases, it h as strong pull - up and pull - down . in this application, there is no need of any external pull - up resistor . while external mode ex e cutio n, p0 and p2 cannot be used as general purpose i/o an y more. in standard 8051 instruction set, one kind of instructions, read - modify - write instructions, should be sp e cially taken care of. instead of the normal instructions, the read - modify - write instruction s read the internal port latch (p x in sfrs) rather than the external port pin state. this kind of instructions read the port sfr value, modify it and write back to the port sfr. read - modify - write instructions are listed as follows. in s truction description anl logical and . ( anl p x , a and anl px,direct ) orl logical or. (orl px,a and orl px,direct ) x rl logical exclusive or. ( xrl px,a and xrl px,direct ) jbc jump if bit = 1 and clear it. ( jbc px.y,label) cpl complemen t bit. ( cpl px.y) inc increment. ( inc p x) dec decrement. ( dec px) djnz decrem ent and jump if not zero. ( djnz px,label) mov px.y,c move carry bit to px.y. clr px.y clear bit px.y. setb px.y set bit px.y. the last three seems not obvious ly read - modify - write i n structions but actually they are. they read the entire port latch value , modify the changed bit, then write the new value back to the port latch. p0 C port 0 (bit - addressable) 7 6 5 4 3 2 1 0 p0 . 7 p0 . 6 p0 . 5 p0 . 4 p0 . 3 p0 . 2 p0 . 1 p0 . 0 r/w r /w r/w r /w r/w r /w r/w r /w address: 80 h reset valu e: 1111 1111 b b it name description 7:0 p0[7:0] port 0. p ort 0 is an 8 - bit open - drain port by default. via setting p0up ( p0or.0 ) p0 will switch as weakly pulled up internally. p0 has an alternative function as ad[7:0] while external memory accessing. du r- in g external program memory execution, sfr p0 ca n not be accessed .
n78e366 a data sheet publication release date: march 11, 2011 - 32 - revision : v2.0 p0or C p0 option register 7 6 5 4 3 2 1 0 - - - - - - - p0up - - - - - - - r /w address: 86 h reset value: 0000 0000b b it name description 7:1 - reserved. 0 p0up port 0 pull - up enable. 0 = dis able internal pull - up resistors of all 8 - bits of port 0 . 1 = e nable internal pull - up resistors of all 8 - bits of port 0 . p1 C port 1 (bit - addressable) 7 6 5 4 3 2 1 0 p1 . 7 p1 . 6 p1 . 5 p1 . 4 p1 . 3 p1 . 2 p1 . 1 p1 . 0 r/w r /w r/w r /w r/w r /w r/w r /w address: 90h reset value: 1111 1111 b b it name description 7:0 p1[7:0] port 1. p ort 1 is an 8 - bit quasi bi - directional i/o port. p2 C port 2 (bit - addressable) 7 6 5 4 3 2 1 0 p2 . 7 p2 . 6 p2 . 5 p2 . 4 p2 . 3 p2 . 2 p2 . 1 p2 . 0 r/w r /w r/w r /w r/w r /w r/w r /w address: a0h r eset value: 1111 1111 b b it name description 7:0 p2[7:0] port 2. p ort 2 is an 8 - bit quasi bi - directional i/o port. it has an alternative function as a[15:8] while external memory accessing . during external program memory ex e- cution, sfr p2 ca n not be accesse d . p3 C port 3 (bit - addressable) 7 6 5 4 3 2 1 0 p3 . 7 p3 . 6 p3 . 5 p3 . 4 p3 . 3 p3 . 2 p3 . 1 p3 . 0 r/w r /w r/w r /w r/w r /w r/w r /w address: b0h reset value: 1111 1111b b it name description 7:0 p3[7:0] port 3. p ort 3 is an 8 - bit quasi bi - directional i/o port.
publication release date: march 11, 2011 - 33 - revision : v 2.0 p 4 C port 4 (bit - addressable) 7 6 5 4 3 2 1 0 p4 . 7 p4 . 6 p4 . 5 p4 . 4 p4 . 3 p4 . 2 p4 . 1 p4 . 0 r/w r /w r/w r /w r/w r /w r/w r /w address: d8h reset value: 1111 1111b b it name description 7:0 p4[7:0] port 4. p ort 4 is an 8 - bit quasi bi - directional i/o port. it also possesses bit - addressable feature as p0~p3. note that a full 8 - bit p4 is just on lqpf - 48 package. plcc - 44 and pqfp - 44 just have low nibble 4 bits of p4. dip - 40 does not have this add i- tional p4 .
n78e366 a data sheet publication release date: march 11, 2011 - 34 - revision : v2.0 10. timers/counters N78E366A ha s t hree 16 - bi t programmable ti m er s /counters. 10.1 timer/counters 0 and 1 timer/counter 0 and 1 on N78E366A are two 16 - bit timer/counters. each of t hem has two 8 bit registers which form the 16 bit counting register. for timer/counter 0 they are th0, the upper 8 bits register, and tl0, the lowe r 8 bit register. similarly timer/counter 1 has two 8 bit registers, th1 and tl1. tcon and tmod can con figure modes of timer/counter 0 and 1 . the timer or counter function is selected by the bit in tmod. each timer/counter has its own s e l ection bit . tmod .2 selects the function f or timer/counter 0 and tmod .6 selects the function for timer/counter 1 when configured as a " timer " , the timer counts clock cycles. the timer clock is 1/ 6 of the peripheral clock (f periph ) . in the " counter " mode, th e register incr eas e s on the falling edge of the external input pin s t0 for timer 0 and t1 for timer 1. if the sampled value is high in one machine - cycle and low in the next, a valid 1 to 0 trans i tion on the pin is recognized and the count register incre ase s . in addition, each timer/counter can be set to operate in any one of four possible modes. bits m0 and m1 in tmod do the mode sele c tion . tmod C timer 0 and 1 mode 7 6 5 4 3 2 1 0 gate m1 m0 gate m1 m0 r/w r/w r/w r/w r/w r/w r/w r/w address: 89h reset value: 0000 0000b bit name description 7 gate timer 1 gate control . 0 = timer 1 will clock when tr1 = 1 regardless of logic level. 1 = timer 1 will clock only when tr1 = 1 and is logic 1 . 6 timer 1 counter/timer select. 0 = timer 1 is incremented by internal peripheral clocks. 1 = timer 1 is incremented by the falling edge of the external pin t1. 5 m1 timer 1 mode select. m 1 m 0 timer 1 mode 0 0 mode 0: 8 - bit timer/counter with 5 - bit pre - scalar (tl1[4:0]) 0 1 mode 1: 16 - bit timer/counter 1 0 mode 2 : 8 - bit timer/counter with auto - reload from th1 1 1 mode 3 : timer 1 halted 4 m0 t c/ t c/ 1 int 1 int t c/
publication release date: march 11, 2011 - 35 - revision : v 2.0 bit name description 3 gate timer 0 gate control. 0 = timer 0 will clock when tr 0 = 1 regardle ss of logic level. 1 = timer 0 will clock only when tr 0 = 0 and is logic 1 . 2 timer 0 counter/timer select. 0 = timer 0 is incremented by internal peripheral clocks. 1 = timer 0 is increment ed by the falling edge of the external pin t0. 1 m1 timer 0 mode select. m 1 m 0 timer 0 mode 0 0 mode 0: 8 - bit timer/counter with 5 - bit pre - scalar (tl0[4:0]) 0 1 mode 1: 16 - bit timer/counter 1 0 mode 2 : 8 - bit timer/counter with auto - reload from th0 1 1 mode 3 : tl0 as a 8 - bit timer/counter and th0 as a 8 - bit timer 0 m0 tcon C timer 0 and 1 control ( bit - addressable ) 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 r/w r /w r/w r /w r/w r /w r/w r /w address: 8 8 h reset value: 0000 0000b b it name descri ption 7 tf1 timer 1 overflow flag. this bit is set when timer 1 overflows. it is automatically cleared by hardware when the pr o gram executes the timer 1 interrupt service routine. software can also set or clear this bit. 6 tr1 timer 1 run control. 0 = ti mer 1 is halted. clearing this bit will halt timer 1 and the cu r rent count will be preserved in th1 and tl1. 1 = timer 1 is enabled. 5 tf0 timer 0 overflow flag. this bit is set when timer 0 overflows. it is automatically cleared via hardware when the pr o gram executes the timer 0 interrupt service routine. software can also set or clear this bit. 4 tr0 timer 0 run control. 0 = timer 0 is halted. clearing this bit will halt timer 0 and the cu r rent count will be preserved in th0 and tl0. 1 = timer 0 is enab led. tl0 C timer 0 low byte 7 6 5 4 3 2 1 0 tl0 [7:0] r/w address: 8 a h reset value: 0000 0000b b it name description 7 :0 tl0[7:0] timer 0 low byte . the tl0 register is the low byte of the 16 - bit timer 0. 0 int 0 int t c/
n78e366 a data sheet publication release date: march 11, 2011 - 36 - revision : v2.0 th0 C timer 0 high byte 7 6 5 4 3 2 1 0 th0[7:0 ] r/w address: 8ch reset value: 0000 0000b b it name description 7 :0 th0[7:0] timer 0 high byte . the t h 0 register is the high byte of the 16 - bit timer 0. tl1 C timer 1 low byte 7 6 5 4 3 2 1 0 tl1[7:0] r/w address: 8bh reset value: 0000 0000b b it nam e description 7 :0 tl1[7:0] timer 1 low byte . the tl 1 register is the low byte of the 16 - bit timer 1 . th 1 C timer 1 high byte 7 6 5 4 3 2 1 0 th1[7:0] r/w address: 8dh reset value: 0000 0000b b it name description 7 :0 th1[7:0] timer 1 high byte . the t h 1 register is the high byte of the 16 - bit timer 1 . 10.1.1 mode 0 (13 - bit timer ) in mode 0, the t imer / c ounter is a 13 - bit counter. the 13 - bit counter consists of thx and the five lower bits of tlx. the upper three bits of tlx are ignored. the t imer / c ounter is ena bled when trx is set and either gate is 0 or is 1 . gate = 1 allows the timer to calculate the pulse width on external input pin . when the 13 - bit value moves from 1fff h to 0000 h , the t imer overflow flag tfx is set and an interrupt occurs if enabled. note that the peripheral clock is f osc /2 in 12t mode and is f osc in 6t mode. see section 20. clock system on page 100 . intx intx
publication release date: march 11, 2011 - 37 - revision : v 2.0 figure 10 C 1 . timer/counters 0 and 1 in mode 0 10.1.2 mode 1 (16 - bit timer) mode 1 is similar to mode 0 except that the counting register s are fully used a s a 16 - b it counter. roll - over o c- curs when a count moves ffff h to 0000 h . the t imer overflow flag tfx of the relevant t imer /counter is set and an inte r rupt will occur s if enabled . figure 10 C 2 . timer/counters 0 and 1 in mode 1 10.1.3 mode 2 (8 - bit auto - r eload timer) in mode 2, the t imer / c ounter is in a uto - r eload m ode . in this mode, tlx acts as an 8 - bit count register whereas thx holds the reload value. when the tlx register overflows from ff h to 00 h , the tfx bit in tcon is set , tlx is reloaded with the contents of thx, and the counting process continues from here. the reload operation leaves the co n tents of the thx register unchanged. this feature is best suitab le for uart baud rate generator f or it runs without continuous software intervention. note that only timer1 can be the baud rate source for uart. coun t ing is enabled by the trx bit and proper setting of gate and pins. the functions of gate and pin s are just the same as mode 0 and 1. 0 1 t f 0 ( t f 1 ) t h 0 ( t h 1 ) t l 0 ( t l 1 ) t i m e r i n t e r r u p t t 0 = p 3 . 4 ( t 1 = p 3 . 5 ) c / t g a t e t r 0 ( t r 1 ) 1 / 6 f p e r i p h i n t 0 = p 3 . 2 ( i n t 1 = p 3 . 3 ) 0 4 7 0 7 0 1 t f 0 ( t f 1 ) t h 0 ( t h 1 ) t l 0 ( t l 1 ) t i m e r i n t e r r u p t c / t 1 / 6 f p e r i p h 0 7 0 7 t 0 = p 3 . 4 ( t 1 = p 3 . 5 ) g a t e t r 0 ( t r 1 ) i n t 0 = p 3 . 2 ( i n t 1 = p 3 . 3 ) intx
n78e366 a data sheet publication release date: march 11, 2011 - 38 - revision : v2.0 figure 10 C 3 . timer/counter 0 and 1 in mode 2 10.1.4 mode 3 ( two separate 8 - bit timers) mode 3 has different operating methods for the two t imer / c oun ters . for t imer / c ounter 1, m ode 3 simply freezes the counter. timer/ counter 0, however, configures tl0 and th0 as two separate 8 bit count registers in this mode. tl0 uses the timer/counter 0 control bits , gate, tr0, , and tf0. the tl0 also can be used as a 1 - to - 0 transition counter on pin t0 as determined by (tmod.2). th0 is forced as a clock c y cle counter and takes over the us age of tr1 and tf1 from timer/counter 1. mode 3 is used in case which an ex tra 8 bit timer is needed. if timer /counter 0 is configured in mode 3, timer/counter 1 can be turned on or off by switching it out of or into its own mode 3 . it can still be used in modes 0, 1 and 2 a l though its flexibility is restrict ed. i t no longer h as control over its ove r flow flag tf1 and the enable bit tr1. however timer 1 can still be used as a t imer/ c ounter and retains the use of gate and pin. it can be used as a baud rate gener a- tor for the serial port or other application not r equiring an inte r rupt. figure 10 C 4 . timer/counter 0 in mode 3 0 1 t f 0 ( t f 1 ) t h 0 ( t h 1 ) t l 0 ( t l 1 ) t i m e r i n t e r r u p t c / t 1 / 6 f p e r i p h 0 7 0 7 t 0 = p 3 . 4 ( t 1 = p 3 . 5 ) g a t e t r 0 ( t r 1 ) i n t 0 = p 3 . 2 ( i n t 1 = p 3 . 3 ) 0 int t c/ 1 int 0 1 t f 0 t h 0 t l 0 t i m e r 0 i n t e r r u p t c / t 1 / 6 f p e r i p h 0 7 0 7 t f 1 t i m e r 1 i n t e r r u p t t r 1 t 0 = p 3 . 4 g a t e t r 0 i n t 0 = p 3 . 2
publication release date: march 11, 2011 - 39 - revision : v 2.0 10.2 timer/counter 2 timer/counter 2 is a 16 - bit up counter, which is co n figured by the t2mod and t2con register s . the co unt stores in two 8 - bit ca s cade registers th2 and tl2. timer/counter 2 is additionally equipped with a capture or reload capability. it also can be configured as the baud rate generator for uart or a square wave ge n erator. the features listed above could b e achieved because of the addition timer/counter 2 capture registers rcap2h and rcap2l. as with the timer 0 and timer 1 counters, there exists considerable flexibility in selec t- ing and controlling the clock and in defining the operating mode. the clock sou rce for timer/counter 2 may be s e lected from either the external t2 pin ( (t2con.1) = 1) or the crystal oscillator ( = 0). the clock is then enabled when tr2 (t2con.2) is a 1, and disabled when tr2 is a 0. the following re g isters are related to timer/counters 2 fun c tion. t2con C timer 2 control ( bit - addressable ) 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 r/w r/w r/w r/w r/w r/w r/w r/w address: c8h reset value: 0000 0000b b it name de scription 7 tf2 timer 2 overflow flag. this bit is set when timer 2 overflows . if the timer 2 interrupt and the global inte r- rupt are enable, setting this bit will make cpu execute timer 2 interrupt service routine. this bit is not automatically cleared vi a hardware and must be cleared via software . tf2 will not be set while timer 2 is configured in the baud rate ge n erator or clock - out mode. 6 exf2 timer 2 external flag. this bit is s et via hardware when a 1 - to - 0 transition on the t2ex input pin occurs and exen2 is logic 1. when the timer 2 interrupt is enabled, setting this bit cau s- es the cpu to execute the timer 2 interrupt service routine. this bit is not aut o- matically cleared via hardware and must be cleared via software . 5 rclk receive clock flag. thi s bit s elects which t imer is used for the uart's receive clock in serial m ode 1 or 3. 0 = timer 1 overflows is used for uart receive baud rate clock. 1 = timer 2 overflows is used for uart receive baud rate clock. 4 tclk transmit clock flag. this bit s ele cts which t imer is used for the uart's transmit clock in serial m ode 1 or 3. 0 = timer 1 overflows is used for uart transmit baud rate clock. 1 = timer 2 overflows is used for uart transmit baud rate clock. 2 t c/ 2 rl cp/
n78e366 a data sheet publication release date: march 11, 2011 - 40 - revision : v2.0 b it name de scription 3 exen2 timer 2 external enable . this bit e nable s 1 - to - 0 transitions on t2ex trigger. 0 = 1 - to - 0 transitions on t2ex is ignored. 1 = 1 - to - 0 transitions on t2ex will set exf2 logic 1. if timer 2 is configured in capture or auto - reload mode, the 1 - to - 0 transitions on t2ex will cause ca p- ture or reload even t. 2 tr2 timer 2 run control. 0 = timer 2 is halted. clearing this bit will halt timer 2 and the cu r rent count will be preserved in th2 and tl2. 1 = timer 2 is enabled. 1 timer 2 counter/timer select. 0 = timer 2 is incremented by inter nal peripheral clocks. 1 = timer 2 is incremented by the falling edge of the external pin t2. if timer 2 would like to be set in clock - out mode, must be 0. 0 timer 2 capture or reload select. this bit selects whether ti mer 2 functions in capture or auto - reload mode. exen2 must be logic 1 for 1 - to - 0 transitions on t2ex to be recognized and used to tri g ger captures or reloads. if rclk or tclk is set, this bit is ignored and timer 2 will function in auto - reload mode. 0 = au to - reload on timer 2 overflow or 1 - to - 0 transition on t2ex pin . 1 = capture on 1 - to - 0 transition at t2ex pin . t2mod C timer 2 mode 7 6 5 4 3 2 1 0 - - - - - - t2oe - - - - - - - r/w - address: c9h reset value: 0000 0000b b it name description 7:2 - res erved. 1 t2oe timer 2 clock - out enable. 0 = disable timer 2 clock - out function. t2 pin functions either as a standard port pin or as a counter input for timer 2. 1 = enable timer 2 clock - out function. timer 2 will drive t2 pin with a clock output if is 0. 0 - reserved. rcap2l C timer 2 reload/ capture low byte 7 6 5 4 3 2 1 0 rcap2l[7:0] r/w address: cah reset value: 0000 0000b b it name description 7 :0 rcap2l[7:0] timer 2 reload/ capture low byte . th is register captures and stores the low byte of timer 2 when timer 2 is co n- figured in capture mode. when timer 2 is in auto - reload mode , baud rate generator mode, or clock - out mode , it holds the low byte of the reload value. 2 t c/ 2 t c/ 2 rl cp/ 2 t c/
publication release date: march 11, 2011 - 41 - revision : v 2.0 rcap2h C timer 2 reload/ capture high byte 7 6 5 4 3 2 1 0 rcap2h [7:0] r/w address: cbh reset value: 0000 0000b b it name description 7 :0 rcap2h[7:0] timer 2 reload/ capture high byte . th is register captures and stores the high byte of timer 2 when timer 2 is configured in capture mode. when timer 2 is in auto - reload m ode , baud rate gen e rator mode, or clock - out mode , it holds the high byte of the reload value. tl2 C timer 2 low byte 7 6 5 4 3 2 1 0 tl2[7:0] r/w address: cch reset value: 0000 0000b b it name description 7 :0 tl2[7:0] timer 2 low byte . the tl 2 register is the low byte of the 16 - bit timer 2 . th2 C timer 2 high byte 7 6 5 4 3 2 1 0 th2[7:0] r/w address: cdh reset value: 0000 0000b b it name description 7 :0 th2[7:0] timer 2 high byte . the t h2 register is the high byte of the 16 - bit timer 2 . timer/cou nter 2 provides four operating mode which can be s e lected by control bits in t 2 con and t 2 mod as shown in table below. note that the th2 and tl2 are accessed sep a rately . it is strongly recommended that the user stop timer 2 temporally for a reading from or writing to th2 and tl2. the free - running reading or writing may cause unpredic t able situation.
n78e366 a data sheet publication release date: march 11, 2011 - 42 - revision : v2.0 table 10 C 1 . timer 2 operating modes timer 2 mode rclk (t2con.5) o r tclk (t2con.4) (t2con.0 ) t2oe (t 2 mod.1) 16 - bit capture [1] 0 1 0 16 - bit auto - reload 0 0 0 b aud rate generator 1 x 0 clock - out [2] 0 0 1 [1] the capture is valid while exen2 (t2con.3) is a 1. or timer/counter 2 behaves just like a 16 - bit timer/counter. [2] (t 2con.1) must be 0. 10.2.1 capture mode the capture mode is enabled by setting the bit in the t2con register to 1. in the capture mode, ti m- er/counter 2 serves as a 16 bit up counter. when the counter rolls over from ffff h to 0000 h , the tf2 bit is set, which will generate an timer 2 interrupt request. if the exen2 bit is set, then a negative transition of t2ex pin (alternative function of p1.1) will cause the value in the tl2 and th2 register to be captured by the rcap2l and rcap2h registers. the t h2 and tl2 keeps on counting while this capture event occurs. this capture action also causes the exf2 (t2con.6) bit set, which will also generate an timer 2 inte r rupt. if timer 2 interrupt enabled, both tf2 and e xf2 flags will generate interrupt vectoring to the same location. the user should check which one triggers the timer 2 interrupt in the interrupt service routine. figure 10 C 5 . timer/counter 2 in capture mode 10.2.2 auto - r eload m ode the auto - reload mode is enabled by clearing the bit in the t2con register. in this mode, ti m- er/counter 2 is a 16 bit up counter. when the counter rolls over from ffff h , tf2 (t2con.7) is set as 1 and a reload is generated that causes t he contents of the rcap2l and rcap2h registers to be reloaded into the tl2 and th2 registers respectively . if the exen2 bit is set, then a negative transition on t2ex pin will also cause a reload. this a c tion also sets the exf2 bit in t2con. 2 rl cp/ rl2 cp/ 2 t c/ 0 1 t f 2 r c a p 2 l t l 2 t i m e r 2 i n t e r r u p t t 2 = p 1 . 0 c / t 2 t r 2 1 / 6 f p e r i p h 0 7 0 7 t h 2 0 7 r c a p 2 h 0 7 t 2 e x = p 1 . 1 e x e n 2 e x f 2
publication release date: march 11, 2011 - 43 - revision : v 2.0 figure 10 C 6 . timer/counter 2 in auto - reload mode 10.2.3 baud rate generator mode the t i mer 2 can generate the baud rate for uart in its mode 1 and 3. the baud rate generator mode is en a- bled by settin g either the rclk or tclk bits in t2con register. while in the baud rate generator mode, ti m- er/counter 2 is a 16 bit counter with auto - reload when the count rolls over from ffff h . ho w ever, rolling over is used to generate the shift clock for uart data rath er than to set the tf2 bit. if exen2 bit is set, then a ne g- ative transition of the t2ex pin will set exf2 bit in the t2con register and cause an i n terrupt request. it simply provides a external interrupt. n o te that tclk and rclk are selected individually, the serial port tran s mit rate can be different from the receive rate. for example the transmit clock can be generated f ro m timer 2 by se t ting tclk and the receive clock f rom timer 1 by clearing rclk. figure 10 C 7 . timer/counter 2 in baud rate generator mode 0 1 t f 2 r c a p 2 l t l 2 t i m e r 2 i n t e r r u p t c / t 2 t r 2 1 / 6 f p e r i p h 0 7 0 7 t h 2 0 7 r c a p 2 h 0 7 e x e n 2 e x f 2 t 2 = p 1 . 0 t 2 e x = p 1 . 1 0 1 r c a p 2 l t l 2 t i m e r 2 i n t e r r u p t c / t 2 t r 2 f p e r i p h 0 7 0 7 t h 2 0 7 r c a p 2 h 0 7 e x e n 2 e x f 2 1 1 0 0 r c l k t c l k 0 1 t i m e r 1 o v e r f l o w s m o d ( p c o n . 7 ) r x c l o c k t x c l o c k 1 / 2 t i m e r 2 o v e r f l o w 1 / 1 6 1 / 1 6 t 2 = p 1 . 0 t 2 e x = p 1 . 1
n78e366 a data sheet publication release date: march 11, 2011 - 44 - revision : v2.0 10.2.4 clock - o ut mode timer 2 is equipped with a clock - out feature, which outputs a 50% duty cycle clock on p1.0. it can be invoked as a programmable clock generator. to configure time r 2 with clock - out mode, software must initiate it by se t- ting bit t2oe (tmod.1) = 1, = 0 and = 0. setting bit tr2 will start the clock output . this mode is similar to the baud rate generator mode which does not generat e an interrupt while timer 2 overflow. sim i lar with the baud rate generator mode, t2ex can also be configured as a simple external interrupt. the clock - out frequency follows the equation . in this formula , en6t is bit 6 of config3 . whi le en6t = 0, the clock system runs under 6t mode and the clock - out frequency will be double of that in 12t mode . (rcap2h,rcap2l) in the formula means . figure 10 C 8 . timer/counter 2 in clock - o ut mode 2 t c/ 2 rl cp/ ? ? ? ? l 2 rcap , h 2 rcap 65536 2 2 f t 6 en osc ? ? ? rcap2l rcap2h 256 ? ? r c a p 2 l t l 2 t i m e r 2 i n t e r r u p t t r 2 f p e r i p h 0 7 0 7 t h 2 0 7 r c a p 2 h 0 7 e x e n 2 e x f 2 1 / 2 t 2 = p 1 . 0 t 2 e x = p 1 . 1
publication release date: march 11, 2011 - 45 - revision : v 2.0 11. watchdog timer 11.1 function description of watchdog timer N78E366A provides one watchdog timer to serve as a system monitor , which improve the reliability of the system. watchdog timer is useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. the watchdog timer is basic a set ting of dividers that divide the peripheral clock. the divider ou t put is selectable and determines the time - out interval. when the time - out interval is fulfi lled, a direct system reset will o c cur . figure 11 C 1 . watchdog timer block diagram the watchdog t imer should first be res et 00h by using wdclr ( wdcon .6) to ensure that the timer s t arts from a known state. the wdclr bit is used to res et the watchdog timer. t his bit is self - cleared thus the user doesn ? t need to clear it. a fter wri t ing a 1 to wdclr , the hardware will automatically clear it. after wdten set as 1, t he watchdog timer star t s count ing . the time - out interval is selected by the three bits wps2 , w ps 1 , and w ps 0 ( wdcon [2:0] ). when the selected time - out occurs, the watchdog timer will reset the system directly . once a reset due to watc h dog timer occurs , the watchdog timer reset fl ag w dt rf ( wdcon . 3 ) will be set . this bit keeps unchang ed after any re set other than a power - on reset. the user may clear wdtrf via sof t- ware . in general, software should restart the counter to put it into a known state by setting wdclr. the watchdog t i mer a lso provides an widpd bit (wdcon.4) to allow the watchdog timer continuing running a f- ter the system enters into idle or power down ope r ating mode. wdt counter should be specially taken care. the hardware automatically clear s wdt counter after entering into or b e ing woken - up from idle or power down mode. it prevents unconscious system reset. 1 0 k h z i n t e r n a l r c f l o s c i d l ( p c o n . 0 ) p d ( p c o n . 1 ) w i d p d w d t e n w d c l r c l o c k d i v i d e r w p s [ 2 : 0 ] w d t c o u n t e r ( 6 - b i t ) c l e a r o v e r f l o w w a t c h d o g t i m e r r e s e t w d t r f
n78e366 a data sheet publication release date: march 11, 2011 - 46 - revision : v2.0 config3 7 6 5 4 3 2 1 0 cwdten en6t rog ckf in t oscfs - fosc - r/w r/w r/w r/w r/w - r/w - unprogrammed value: 1111 1111 b b it name description 7 cwdten config watchd og timer enable . 1 = dis able watchdog timer after all resets . 0 = en able watchdog timer after all resets . wdcon C watchdog timer control ( ta protected ) 7 6 5 4 3 2 1 0 wdten [1] wdclr - widpd [ 2 ] wdtrf [ 3 ] wps2 [ 2 ] wps1 [ 2 ] wps0 [ 2 ] r/w w - r/w r/w r/w r/w r/ w address: aah reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it name description 7 wdten watchdog timer enable. 0 = disable watchdog t i mer. 1 = enable watchdog t i mer. the wdt counter sta rts running. 6 wdclr watchdog timer clear. setting this bit will reset the watchdog timer count to 00h. it put s the counter in a known state and prohibit the system from reset . note that this bit is written - only and has no need to be clear ed via software . 5 - reserved . 4 widpd watchdog t i mer running in idle and power down mode. this bit decides whether watchdog t i mer runs in idle or power down mod e. 0 = wdt counter is halted while cpu is in idle or power down mode. 1 = wdt keeps running while cpu is in i dle or power down mode. 3 wdtrf watchdog timer reset flag. when the cpu is reset by watchdog timer time - out event, this bit will be set via hardware . this flag is recommended to be cleared via software . 2 wps2 watchdog t i mer clock pre - scalar select. thes e bits determine the scale of the clock divider for wdt counter . the scale is from 1/1 through 1/256. see table 11 C 1 . 1 wps1 0 wps0 [1] wdten is initialized by the inversed value of cwdten ( config3 .7) a fter al l resets . [ 2 ] widpd and wps [ 2 :0] are cleared a fter power - on reset, and keep unchanged a fter any other r e sets. [ 3 ] wdtrf will be cleared after power - on reset, be set after watchdog timer reset, and remain s unchanged after any ot h- er resets. the watchdog tim e - out interval is determined by the fo r mula . where f ilrc is the frequency of internal 10khz rc . the following table shows an example of t he watchdog time - out interval under different f wck and pre - scalars . 64 scalar divider clock f 1 losc ? ?
publication release date: march 11, 2011 - 47 - revision : v 2.0 table 11 C 1 . watchdog timer - out interval under different pre - scalars wps2 wps1 wps 0 clock d i vider s cal e typical watchdog time - out i n terval ( f ilrc ~ = 10 k hz ) 0 0 0 1/1 6.4 0 ms 0 0 1 1/2 12.8 0 ms 0 1 0 1/8 51.2 0 ms 0 1 1 1/16 102.40ms 1 0 0 1/32 204.80ms 1 0 1 1/64 409.60ms 1 1 0 1/128 819.20ms 1 1 1 1/256 1.638s 11.2 applications of watchdog timer the main application of the watchdog timer is for the system mon i tor. this is important in real - time control applications. in case of some power glitches or electro - magnetic interference, the processor may begin to ex e- cute err oneous code s and operate in an u n predictable state . if this is left unchecked the entire system may crash. using the watc h dog timer during software developm ent will require the user to select ideal watchdog reset locations for insert ing instructions to reset the watchdog timer . by inserting the instruction setting w d clr , it will allow the code to run without any watchdog timer reset . however if any err oneous code ex e- cut es by any power of other interference, the instructions to clear the watchdog timer counter will not be ex e- cuted at the required instants . thus the watchdog timer reset will occur to reset the system start from an err o- neously executing condition . the user should re member that wdcon r e quire s a timed a ccess writing .
n78e366 a data sheet publication release date: march 11, 2011 - 48 - revision : v2.0 12. power down waking - up timer 12.1 function description of power down waking - up timer N78E366A provides another free - running timer , power down wa k ing - up timer which serve s as a event timer or a durational system supervisor in a monitoring system which generally operates in idle or power down modes . it is basic a set ting of dividers that divide the peripheral clock. the divider output is selectable and d e- termines the time - out interval. when the t ime - out interval is fulfilled , it will wake the system up from idle or power down mode and a n i n terrupt event will occur . figure 12 C 1 . power down waking - up timer block diagram th e power down waking - up timer should first be res et 00h by using p dclr ( pdcon. 6) to ensure that the ti m- er starts from a known state. the p dclr bit is used to restart the power down waking - up timer . this bit is self - clear ed thus the user doesn ? t need to clear it. a fter writing a 1 to p dclr , the hardware will automatically clear it. after p dten set as 1, t he power down waking - up timer will start count ing clock cycles. the time - out interval is selected by the three bits p ps2 , p ps 1 , and p ps 0 ( p dcon [2:0] ). when th e selected time - out o c- curs, the power down waking - up timer will set the interrupt flag pdtf ( p dcon . 5 ) . the power down waking - up timer inte r rupt enable bit locates at bit 1 in eie . in general, software should restart the counter to put it into a known state by setting wdclr. p dcon C power down waking - up timer control 7 6 5 4 3 2 1 0 pdten pdclr pdtf - - pps2 pps1 pps0 r/w w r/w - - r/w r/w r/w address: abh reset value: 0000 0000b b it name description 7 p dten power down w aking - up t imer enable. 0 = disable power down w aking - up t i mer. 1 = enable power down w aking - up t i mer. the pdt counter starts running. 6 p dclr power down w aking - up t imer clear. setting this bit will reset the power down w aking - up timer count to 00h. it put the counter in a known state. thi s bit is written - only and has no need to be clear ed via software . 1 0 k h z i n t e r n a l r c f l o s c p d t e n p c l r c l o c k d i v i d e r p p s [ 2 : 0 ] p d t c o u n t e r ( 6 - b i t ) c l e a r o v e r f l o w p o w e r d o w n w a k i n g - u p t i m e r i n t e r r u p t p d t f e p d t
publication release date: march 11, 2011 - 49 - revision : v 2.0 b it name description 5 pdt f power down w aking - up t imer interrupt flag . this bi t will be set via hardware when p dt counter overflows. this bit must be cleared via software . 4: 3 - reserved . 2 p ps2 power down w a king - up t i mer clock pre - scalar select. these bits determine the scale of the clock divider for p dt counter. the scale is from 1/1 through 1/ 1024 . see table 12 C 1 . 1 p ps1 0 p ps0 the power down waking - up time - ou t interval is determined by the formula where f ilrc is the frequency of inte r nal 10khz rc. the following table shows an example of t he power down waking - up time - out interval under di f ferent pre - scalars. table 12 C 1 . power down waking - up timer - out interval under different pre - scalars p ps2 p ps1 p ps 0 clock d i vider s cal e typical power down waking - up time - out interval ( f ilrc ~ = 10 k hz ) 0 0 0 1/1 6.4 0 ms 0 0 1 1/ 4 25 . 60 ms 0 1 0 1/8 51.2 0 ms 0 1 1 1/ 32 204.80ms 1 0 0 1/ 64 409.60ms 1 0 1 1/ 256 1.638s 1 1 0 1/ 512 3 . 277 s 1 1 1 1/ 1024 6.554 s 12.2 applications of power down waking - up timer the main application of the power down w aking - up t imer is a si m ple timer. the pdt f fla g will be set while the power down w aking - up t imer completes the selected time interval. the software polls the pdtf flag to detect a time - out and the p d clr allows software to restart the timer. the power down w aking - up t imer can also be used as a very lon g timer. every time the time - out occurs , an inte r rupt will occur if the individual interrupt epdt (eie.1) and global i n terrupt enable ea is set. in some application of low power consumption, the cpu usually stays in idle mode when nothing needs to be serve d to save power consumption. after a while the cpu will be woken up to check if anything needs to be served at an i n terval of programmed period implemented by timer 0, 1 or 2. however, the current consumption 64 scalar divider clock f 1 losc ? ?
n78e366 a data sheet publication release date: march 11, 2011 - 50 - revision : v2.0 of i dle mode still keeps at a ma level. to fu rther reduc ing the current consumption to a level, the cpu should stay in power down mode when nothing needs to be served, and has the ability of waking up at a pr o- grammable interval. N78E366A is equipped with this useful function. it provides a very lo w power internal rc 10khz. along with the low power consumption application, the power down waking - up t imer needs to count under idle and power down mode and wake cpu up from idle or power down mode. the demo code to a c- complish this feature is shown b e low. the demo code of power down w aking - up t imer waking up cpu from power down. org 0000h ljmp start org 004bh ljmp p dt _isr org 0100h p dt _isr: orl p dcon ,#01000000b ;clear power down wa k ing - up t imer counter anl p dcon ,#11011111b ;clear power down wa k i ng - up t imer interrupt flag reti start: orl p dcon ,# 000 00 111b ; choose interval length orl eie ,#00000010b ;enable power down wa k ing - up t imer interrupt setb ea orl p dcon ,#10000000b ;enable power down wa k ing - up t imer to run ;************************** ****************************************** ;enter into power down m od e ;******************************************************************** loop: orl pcon,#02h ljmp loop
publication release date: march 11, 2011 - 51 - revision : v 2.0 13. serial port N78E366A includes one enhanced full duplex serial port . the serial por t supports three modes of full duplex uart (universal asy n chronous receiver and transmitter) in mode 1, 2 , and 3. this means it c an transmit and receive simultaneously. the serial port is also receive - buffered, meaning it can commence reception of a s e- cond byte before a previously received byte has been read from the register. the serial port receive and transmit registers are both accessed at sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register . there are four operation mode s in serial port. in all four modes, transmission initia tes by any instruction that uses sbuf as a destination register. note that before s e- rial port function works, the port latch bits of p3.0 and p3.1 (for rxt and txd pins) have to be set to 1. scon C serial port control ( bit - addressable ) 7 6 5 4 3 2 1 0 sm0 sm1 sm2 ren tb8 rb8 ti ri r/w r/w r/w r/w r/w r/w r/w r/w address: 98h reset value: 00 00 0000b b it name description 7 sm0 serial port mode select. see table 13 C 1 . serial port mode description for details. 6 sm1 5 sm2 multiprocessor c ommunication mode e nable. the function of this bit is dependent on the serial port mode. mode 0: this bit has no effect. mode 1: this bit c heck s valid stop bit. 0 = reception is always valid no matter the l ogic level of stop bit . 1 = reception is ignored if the received stop bit is not logic 1. mode 2 or 3: for multiprocessor communication. 0 = reception is always valid no matter the l ogic lev el of the 9 th bit . 1 = reception is ignored if the received 9 th bit is not logic 1. 4 ren receive enable. 0 = disable s erial port reception . 1 = enable s erial port reception in mode 1,2, and 3. in mode 0, clea r ing and then s etting ren initiate s one - byte reception . after reception is complete, this bit will not be cleared via hardware . the user should clear and set ren again via software to triggering the next byte reception. 3 tb8 9 th t ransmi t bit. this bit defines the state of the 9 th transmission bit i n serial port mode 2 and 3. it is not used in mode0 and 1.
n78e366 a data sheet publication release date: march 11, 2011 - 52 - revision : v2.0 b it name description 2 rb8 9 th r eceive bit. the bit identifies the logic level of the 9 th received bit in modes 2 and 3. in mode 1, if sm2 0, rb8 is the logic level of the received stop bit. rb8 is not used in mode 0. 1 ti transmission interrupt flag. this flag is s et via hardware when a byte of data has been transmitted by the uart after the 8 th bit in mode 0 or the last bit of data in other modes. when the uart interrupt is enabled, setting this bit causes the cpu t o execute the uart inte r rupt service routine. this bit must be cleared manually via software . 0 ri receiving interrupt flag. this flag is set via hardware when a 8 - bit or 9 - bit data has been received by the uart after the 8 th bit in mode 0 , after sampling the stop bit in mode 1, or after sampling the 9 th bit in mode 2 and 3. sm2 bit has restriction for exception. when the uart interrupt is enabled, setting this bit causes the cpu to execute to the uart interrupt se r vice routine. this bit must be cleared ma nually via software . table 13 C 1 . serial port mode description mode sm0 sm1 description data bits baud rate 0 0 0 synchronous 8 f osc divided by 12 for 12t mode, by 6 for 6t mode 1 0 1 asynchronous 10 timer 1 overflow rate divided by 16 or divided by 32 [ 1 ] , or timer 2 ove r flow rate divided by 16 2 1 0 asynchronous 11 f osc divided by 32 or 64 [1] for 12t mode, by 16 or 32 [1] for 6t mode 3 1 1 asynchronous 11 timer 1 overflow rate divided by 16 or divided by 3 2 [ 1 ] , or timer 2 ove r flow rate divided by 16 [1] while smod (pcon.7) is logic 0 . pcon C power control 7 6 5 4 3 2 1 0 smod - - pof gf1 gf0 pd idl r/w - - r/w r/w r/w r/w r/w address: 87h reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it name description 7 smod serial port double baud rate enable. setting this bit doubles the serial port baud rate in uart mode 2 and mode 1 or 3 only if timer 1 overflow is used as the baud rate source. s ee table 13 C 1 . serial port mode description in d e tails.
publication release date: march 11, 2011 - 53 - revision : v 2.0 sbuf C serial data buffer 7 6 5 4 3 2 1 0 sbuf[7:0] r/w address: 99h reset value: 0000 0000b b it name description 7:0 sbuf[7:0] serial data buffer. this byte actually consists two separate registers . one is the receive resister, and the other is the transmit buffer. when data is moved to sbuf, it goes to the tran s mit buffer and is shifted for serial transmission . when data is moved from sbuf, it comes from the receive buffer. the transmission is initiated through m oving a byte to sbuf . 13.1 m ode 0 mode 0 provides synchronous communication with external devices. serial data enters and exits through r x d pin . t x d outputs the shift clock. 8 bits are transmitted or received. mode 0 therefore provides half - duplex communication because the transmitting or receiving data is via the same data line rxd. the baud rate is fixed at 1/12 the oscillator frequency in 12 t m ode or 1/6 the oscillator frequency in 6t mode . note tha t whe n- ever transmitting or receiving, the serial clock is always generated by the microcontroller. thus any device on the serial port in mode 0 must accept the microcontroller as the m aster . figure 13 C 1 shows a sim plified fun c- tional diagram of the serial port in mode 0 and assoc i ated timing. note that the peripheral clock is f osc /2 in 12t mode and is f osc in 6t mode. see section 20. clock system on page 100 .
n78e366 a data sheet publication release date: march 11, 2011 - 54 - revision : v2.0 figure 13 C 1 . serial port mode 0 function block and timing diagram
publication release date: march 11, 2011 - 55 - revision : v 2.0 as shown there is one bi - direction data line (rxd) and one shift clock line (tx d). the shift clock is used to shift data in or out of the serial port controller bit by bit for a serial co m munication. data bits enter or exit lsb first. the band rate is equal to the shift clock fr e quency. transmission is initiated by any instruction wr ites to sbuf . the c ontrol block will then shift out the clock and begin to transfer data until all 8 bit s are complete. then the transmitted flag ti (scon.1) will be set 1 to ind i- cate one byte transmitting complete. reception is initiated by the condition ren (scon.4) = 1 and ri (scon.0) = 0. this condition tells the serial port controller that there is data to be shifted in. this process will continue until 8 bits have been received. then the received flag ri will be set as 1. the user can clear ri to trig ger the next byte reception. 13.2 m ode 1 mode 1 supports asynchronous, full duplex serial commun i cation. the asynchronous mode is commonly used for communication with pcs, modems or other similar inte r faces. in mode 1, 10 bits are transmitted (through t x d) or r eceived (through r x d) including a start bit ( logic 0), 8 data bits (lsb first) and a stop bit ( logic 1) . the baud rate is determined by the timer 1 or timer 2 overflow rate a c cording to rclk and tclk bits in t2con. smod (pcon.7) setting 1 makes the baud ra te double while timer 1 is selected as the clock source. figure 13 C 2 shows a simplified functional diagram of the serial port in mode 1 and associated timings for transmit and r e ceive.
n78e366 a data sheet publication release date: march 11, 2011 - 56 - revision : v2.0 figure 13 C 2 . serial port mode 1 function block and timing diagram
publication release date: march 11, 2011 - 57 - revision : v 2.0 transmission is initiated by any writing instruction s to sbuf. transmission takes place on txd pin. first the start bit comes out , the 8 - bit data follow s to be shifted o ut and then ends with a stop bit. after the stop bit a p- pears, ti (scon.1) will be set to indicate one byte transmission complete. all bits are shifted out depending on the rate determined by the baud rate generator. once the baud rate generator is activate d and ren (scon.4) is 1, the reception can begin at any time. r e- ce p tion is initiated by a d e tected 1 - to - 0 transition at r x d . data wil l be sampled and shifted in at the selected baud rate. in the midst of the stop bit, certain conditions must be met to load sbuf with the r e ceived data: 1. r i (scon.0) = 0, and 2. either sm2 (scon.5) = 0, or the received stop bit = 1 while sm2 = 1 . if these conditions are met, then the sbuf will be loaded with the received data, the rb8 (scon.2) with stop bit , and ri will be s et. if these conditions fail, there will be no data load ed and ri will remain 0 . after above r e- ceiving progress, the serial control will look forward another 1 - 0 transition on rxd pin in order to start next data rece p tion. 13.3 m ode 2 mode 2 supports asynchrono us, full duplex serial commun i cation. different from mode1, there are 1 1 bits to be transmitted or received . they are a start bit ( logic 0), 8 data bits (lsb first) , a pr o grammable 9 th bit tb8 or rb8 bit and a stop bit ( logic 1). the most common use of 9 th bit is to put the parity bit in it. the baud rate is fixed as 1/32 or 1/64 the oscillator frequency depending on smod bit. (this is under 12t mode. under 6t mode, the baud rate will be 1/16 or 1/32 the oscillator frequency.) figure 13 C 3 shows a simpl i fied functional diagram of the serial port in mode 2 and associated timings for transmit and r e ceive .
n78e366 a data sheet publication release date: march 11, 2011 - 58 - revision : v2.0 figure 13 C 3 . serial port mode 2 function block and timing diagram
publication release date: march 11, 2011 - 59 - revision : v 2.0 transmission is initiated by any writing instruction s to sbuf. transmission takes place on txd pin. first the start bit comes out, the 8 - bit data and bit tb8 (scon.3) follow s to be shifted out and then ends with a stop bit. after t he stop bit appears, ti w ill be set to indicate the transmission co m plete . while ren is set, the reception is allowed at any time. a falling edge of a start bit on rxd will initiate the r e- ce p tion progress . data will be sampled and shifted in at the selected baud rate. in the midst of the 9 th bit, ce r- tain conditions must be met to load sbuf with the received data: 1. r i (scon.0) = 0, and 2. either sm2 (scon.5) = 0, or the received 9 th bit = 1 while sm2 = 1 . if these conditions are met, then the sbuf will be loaded with the received d ata, the rb8(scon.2) with tb8 bit and ri will be set. if these conditions fail, there will be no data load ed and ri will remain 0 . after above r e- ceiving progress, the serial control will look forward another 1 - 0 transition on rxd pin in order to start next data rece p tion. 13.4 m ode 3 mode 3 has the same operation as mode 2, except its baud rate clock source. as shown is figure 13 C 4 , mode 3 uses timer 1 or timer 2 overflow as its baud rate clock.
n78e366 a data sheet publication release date: march 11, 2011 - 60 - revision : v2.0 figure 13 C 4 . serial port mode 3 function block and timing diagram
publication release date: march 11, 2011 - 61 - revision : v 2.0 13.5 baud rate table 13 C 2 . uart baud rate formulas uart mode baud rate clock source en6t ( config3 . 6 ) value 1 (12t mod e) 0 (6t mode) 0 oscillator 2 oscillator 1 or 3 timer/counter 1 ove r flow [1] timer/counter 2 ove r flow [2] [ 3 ] [1] timer 1 is configured as a timer in auto - reload mode (mode 2) . [2] timer 2 is configured as a timer in baud rate generator mode . [3] (rcap2h,rcap2l) in the fo r mula mea n s . note that in using timer 1 as the baud rate generator, the interrupt should b e disabled . in using timer 2, the interrupt is automatically switched off. the timer itself can be configured for either t imer or c ounter oper a- tion . a nd timer 1 can be in any of i ts 3 running modes. in the most typical applicat ions, it is configured for t imer operation, in the auto - reload mode (mode2) . if timer 1 is used as the baud rate generator, the reloa d- ed value is stored in th1. therefore the baud rate is determined by th1 value. if timer 2 is used, the user should configure it in baud rate generator mode (rclk or tclk in t2con is logic 1) and give 16 - bit reloaded value in rcap 2 h and rcap 2 l. table 13 C 3 list s various commonly used bau d rates and how they can be obtained from timer 1. in this mode, timer 1 as an auto - reload t imer operates in 12t mode and smod (pcon.7) is 0. table 13 C 4 is for timer 2 as the baud rate generator. timer 2 operates in b aud rate gener a tor mode in 12 t mode. in 6t mode, the baud rate generated from both timer 1 and timer 2 overflows will be do u bled. table 13 C 3 . timer 1 generated commonly used baud rates th1 reload value osc illator frequency (mhz) 11.0592 14.7456 18.432 22.1184 36.864 baud rate 57600 ffh 12 / f osc 6 / f osc osc smod f 64 2 ? osc smod f 32 2 ? ? ? 1 th 256 12 f 32 2 osc smod ? ? ? ? ? 1 th 256 12 f 16 2 osc smod ? ? ? ? ? ? ? l 2 rcap , h 2 rcap 65536 32 f osc ? ? ? ? ? ? l 2 rcap , h 2 rcap 65536 16 f osc ? ? l 2 rcap h 2 rcap 256 ? ?
n78e366 a data sheet publication release date: march 11, 2011 - 62 - revision : v2.0 th1 reload value osc illator frequency (mhz) 11.0592 14.7456 18.432 22.1184 36.864 baud rate 38400 ffh 19200 feh fdh fbh 9600 fdh fch fbh fah f6h 4800 fah f8h f6h f4h ech 2400 f4h f0h ech e8h d8h 1200 e8h e0h d8h d0h b0h 300 a0h 80h 60h 40h table 13 C 4 . timer 2 generated commonly used baud rates rcap2h, rcap2l reload value oscillator frequency (mhz) 11.0592 14.7456 18.432 22.1184 36.864 baud rate 115200 ffh, fdh ffh, fch ffh, fbh ffh, fah ffh, f6h 57600 ffh, fah ffh, f8h ffh, f6h ffh, f4h ffh, ech 38400 ffh, f7h ffh, f4h ffh, f1h ffh, eeh ffh, e2h 19200 ffh, eeh ffh, e8h ffh, e2h ffh, dch ffh, c4h 9600 ffh, dch ffh, d0h ffh, c4h ffh, b8h ffh, 88h 4800 ffh, b8h ffh, a0h ffh, 88h ffh , 70h ffh, 10h 2400 ffh, 70h ffh, 40h ffh, 10h feh, e0h feh, 20h 1200 feh, e0h feh, 80h feh, 20h fdh, c0h fch, 40h 300 fbh, 80h fah, 00h f8h, 80h f7h, 00h f1h, 00h 13.6 multiprocessor communication N78E366A multiprocessor communication feature of uart let s a m aster device send a multiple frame serial message to a s lave d e vice in a multi - slave configuration. it does this without interrupting other slave devices that may be on the same serial line. this fe a ture can be used only in uart mode 2 or 3 mode. after 9 data bits are received. the 9 th bit value is written to rb8 ( s con.2). the user can enable this function by setting sm2 (scon.5) as a logic 1 so that when the stop bit is received, the serial interrupt will be gene r ated only if rb8 is 1. when the sm2 bit is 1 , serial data frames that are received with the 9 th bit as 0 do not generate an interrupt. in this case, the 9 th bit simply sep a rates the address from the serial data. when the m aster device wants to transmit a block of data to one of several slaves on a serial line, it first sen d s out an address byte to identify the target slave. note that in this case, an address byte differs from a data byte:
publication release date: march 11, 2011 - 63 - revision : v 2.0 in an a d dress byte, the 9 th bit is 1 and in a data byte, it is 0 . the address byte interrupts all slaves so t hat each slave can examine the received byte and see if it is being a d dressed. the addressed slave then clears its sm2 bit and prepares to receive incoming data bytes. the s m 2 bits of slaves that were not addressed remain set, and they continue operating n ormally while igno r ing the incoming data bytes. follow these steps to configure multiprocessor communic a tions: 1. set all devices ( m asters and s laves) to uart mode 2 or 3 . 2. write the sm2 b it of all the s lave devices to 1 . 3. the m aster device's transmiss ion protocol is: C first byte: the address , identifying the target slave d e vice , ( 9 th bit = 1) . C next bytes: data , ( 9 th bit = 0 ) . 4. when the target s lave receives the first byte, all of the s laves are interrupted because the 9 th data bit is 1. the targeted s lave compares the address byte to its own address and then clears its sm2 bit in order to r e- ceive incoming data. the other slaves co n tinue operating normally. 5. after all data bytes have been received, set sm2 back to 1 to wait for next address. sm2 has n o effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. for mode 1 r e- ception, if sm2 is 1, the receive interrupt will not be issue unless a valid stop bit is received.
n78e366 a data sheet publication release date: march 11, 2011 - 64 - revision : v2.0 14. serial peripheral in terface (spi ) 14.1 features N78E366A exists a serial peripheral interface (spi) block to su p port high speed serial communication. spi is a full - duplex, high speed, synchronous communication bus b e tween mcus or other peripheral devices such as serial eeprom , lcd driver, or d/a con verter . it provides either master or slave mode, high speed rate up to f periph / 16 f or master mode and f periph /4 for slave mode , transfer complete and write collision flag. for a multi - m aster sy s tem, spi supports master mode fault to protect a multi - master conflict. 14.2 function d escription figure 14 C 1 . spi b lock d iagram d i v i d e r / 1 6 , / 3 2 , / 6 4 , / 1 2 8 s e l e c t 8 - b i t s h i f t r e g i s t e r r e a d d a t a b u f f e r m s b l s b p i n c o n t o r l l o g i c m i s o m o s i s p c l k s s s p i s t a t u s c o n t r o l l o g i c s p i s t a t u s r e g i s t e r s p i c o n t r o l r e g i s t e r c l o c k l o g i c s m m s c l o c k s p i f w c o l s p i o v f m o d f d i s m o d f s p i i n t e r r u p t r e q u e s t s p i e n m s t r m s t r s s o e d i s m o d f s p r 0 s p r 1 s p r 0 s p r 1 c p h a c p o l m s t r l s b f e s p i e n s s o e s p i e n i n t e r n a l d a t a b u s f p e r i p h
publication release date: march 11, 2011 - 65 - revision : v 2.0 figure 14 C 1 shows spi block diagram. it provide s an overview of spi architecture in this device . the main blocks of spi are the spi control register logic , spi status logic, clock rate control logic, and pin control logic . for a serial data transfer or receiving, the spi block exists a shift register and a read data buffer. it is single buf f ered in the transmit direction and double buffered in the receiv ing direction. transmit data cannot be written to the shifter until the previous transfer is complete. receiv ing logic consist s of parallel read data buffer so the shift r egister is free to accept a s econd data, as the first received data will be transferred to the read data buf f- er. the four pins of spi interface are master - in/slave - out (miso), master - out/slave - in (mosi), shift clock (s pcl k), and slave s e lect ( ). the mosi pin is used to transfer a 8 - bit data in series from the master to the slave. therefore, mosi is an output pin for master device and a input for slave. respectively , the miso is used to receive a serial dat a from the slave to the master. the s pclk pin is the clock output in master mode, but is the clock input in slave mode. the shift clock is used to synchronize the data movement both in and out of the d e vices through their mosi and miso pins. the shift clock is driven by the master mode device for eight clock cycl es which exchanges one byte data on the serial lines. for the shift clock is always produced out of the master d e vice, the system should never exist more than one device in master mode for avoiding device conflict. each slave peripheral is selected by one slave select pin ( ). the signal must stay low for any slave a c- cess. when is driven high, the slave device will be inactivated. if the system is multi - slave, there should be only one slave device selected at th e same time. in the master mode mcu , the pin does not function and it can be configured as a ge n eral purpose i/o. however, can be used as master mode fault detection (s ee section 14.7 mode fault detection on page 73 ) via software setting if multi - master environment exists. N78E366A also provides auto - activating fun c tion to toggle between each byte - transfer. ss ss
n78e366 a data sheet publication release date: march 11, 2011 - 66 - revision : v2.0 figure 14 C 2 . spi m ulti - master , multi - slave interconnection figure 14 C 2 shows a typical interconnec tion of spi devices. the bus generally connects devices together through three signal wires, mosi to mosi, miso to miso, and s p c l k to s p c l k. the master devices select the individual slave devices by using four pins of a parallel port to control the four pins. mcu1 and mcu2 play either master or slave mode. the should be configured as master mode fault detection to avoid mu l- ti - master conflict. figure 14 C 3 . spi s ingle - master , s ingle - slave i nterconnection figure 14 C 3 shows the simplest spi system interconne c tion, single - master and signal - slave. during a transfer, the master shifts data out to the slave via mosi line. while s i multaneously, the master shifts data in from the slave via miso line. the two shift registers in the master mcu and the slave mcu can be considered as one 16 - bit circular shift register. therefore, while a transfer data pushed from master into slave, the data in slave will also be pulled in master device r espectively . the transfer effectively e x changes the data which was in the spi shift registers of the two mcu s . ss m i s o m o s i s p c l k s s i / o p o r t 0 1 2 3 i / o p o r t 0 1 2 3 s o s i s c k s s s l a v e d e v i c e 1 m a s t e r / s l a v e m c u 1 m i s o m o s i s p c l k s s m a s t e r / s l a v e m c u 2 s o s i s c k s s s l a v e d e v i c e 2 s o s i s c k s s s l a v e d e v i c e 3 s p i c l o c k g e n e r a t o r m i s o m i s o m o s i m o s i s p c l k s p c l k v s s s s s s 7 6 5 4 3 2 1 0 s p i s h i f t r e g i s t e r 7 6 5 4 3 2 1 0 s p i s h i f t r e g i s t e r m a s t e r m c u s l a v e m c u * * s s c o n f i g u r a t i o n f o l l o w s d i s m o d f a n d s s o e b i t s .
publication release date: march 11, 2011 - 67 - revision : v 2.0 by default , spi data is transferred msb first. if the lsbfe (sp cr.5) is set, spi data shifts lsb first. this bit does not affect the position of the msb and lsb in the data register. note that all following descriptions and figures are under the condition of lsbfe logic 0. msb is transmitted and received first. 14.3 contro l registers of spi there are three spi registers to support its operations, they are spi control register (spcr) , spi status regi s- ter (spsr) , and spi data register (spdr) . these registers provide control, status, data storage functions , and clock rate sele ction. the following regi s ters relate to spi function. spcr C serial peripheral control register 7 6 5 4 3 2 1 0 ssoe spien lsbfe mstr cpol cpha spr1 spr0 r/w r/w r/w r/w r/w r/w r/w r/w address: f3 h reset value: 00 00 0000b bit name description 7 ssoe slave select output enable. this bit is used in combination with the dismodf (spsr.3) bit to d e termine the feature of pin as shown in table 14 C 1 . slave select pin c onfigurations . this bit ta kes effect only under mstr = 1 and dismodf = 1 condition. 0 = functions as a general purpose i/o pin. 1 = automatically goes low for each transmission when selecting external slave device and goes high during each idle state to de - select the slave d e- vice. 6 spien spi enable. 0 = disable spi function. 1 = enable spi function. 5 lsbfe lsb first enable. 0 = the spi d ata is transferred msb first . 1 = the spi d ata is transferred lsb first . 4 mstr master mode ena ble. this bit switches the spi operating between master and slave modes. 0 = the spi is configured as slave mode . 1 = the spi is configured as master mode . 3 cpol spi clock polarity select. cpol bit determines the idle state level of the spi clock. see figure 14 C 4 . spi clock forma ts . 0 = the spi clock is low in idle state. 1 = the spi clock is high in idle state. 2 cpha spi clock phase select. cpha bit determines the data sampling edge of the spi clock. see figure 14 C 4 . spi clock forma ts . 0 = the data is sampled on the first edge of the spi clock. 1 = the data is sampled on the second edge of the spi clock. ss ss ss
n78e366 a data sheet publication release date: march 11, 2011 - 68 - revision : v2.0 bit name description 1 spr1 spi clock rate select. these two bits select four grades of spi clock divider. spr 1 spr 0 divider spi clock rate 0 0 16 1.25m bit/s 0 1 32 625k bit/s 1 0 64 312k bit/s 1 1 128 156k bit/s the clock rates above are illustrated under f periph = 20mhz condition. 0 spr0 table 14 C 1 . slave select pin c onfigurations dismodf ssoe master mode (mstr = 1) slave mode (mstr = 0) 0 x input for mode fault input for slave s e lect 1 0 general purpose i/o 1 1 au tomatic output spsr C serial peripheral status register 7 6 5 4 3 2 1 0 spif wcol spiovf modf dismodf - - - r/w r/w r/w r/w r/w - - - address: f4h reset value: 0000 0000b bit name description 7 spif spi complete flag. this bit is set to logic 1 via hardware while an spi data transfer is complete or an receiving data has been moved into the spi read buffer . if espi ( eie .0) and ea are enabled, an spi interrupt will be required. this bit must be cleared via sof t- ware . attempting t o write to spdr is i n hibited if spif is set. 6 wcol write collision error flag. this bit indicates a write collision event. once a write collision event occurs, this bit will be set. it must be cleared via software . 5 spiovf spi overrun error flag. this bit indicates an overrun event. once an overrun event occurs, this bit will be set. if espi and ea are e n abled, an spi interrupt will be required. this bit must be cleared via software . 4 modf mode fault error flag. this bit indicates a mode fault error e vent. if pin is configured as mode fault input (mstr = 1 and dismodf = 0) and is pulled low by external d e- vices, a mode fault error occurs. instantly modf will be set as logic 1. if espi and ea are enabled, a n spi interrupt will be required. this bit must be cleared via software . ss ss ss ss ss
publication release date: march 11, 2011 - 69 - revision : v 2.0 bit name description 3 dismodf disable mode fault error detection. this bit is used in combination with the ssoe (spcr.7) bit to determine the fe a- ture of pin as shown in table 14 C 1 . slave select pin c onfigurations . dismodf affects only in master mode (mstr = 1). 0 = mode fault detection is not disabled. serves as input pin for mode fault de tection disregard of ssoe. 1 = mode fault detection is disabled. the feature of follows ssoe bit. 2:0 - reserved. spdr C serial peripheral data register 7 6 5 4 3 2 1 0 spdr[7:0] r/w address: f5h reset value: 0000 0000b b it name description 7:0 spdr[7:0 ] serial peripheral data. this byte is used of transmitting or receiving data on spi bus. a write of this byte is a write to the shift register. a read of this byte is actually a read of the read data buffer . in master mode, a write to this register initia te s t ransmission and reception of a byte simult a neously. 14.4 operating modes 14.4.1 master mode the spi can operate in master mode while mstr (spcr.4) is set as 1. only one m aster spi device can init i- ate transmission s . a transmission always begins by master through writing to spdr. the byte written to spdr begin s shifting out on mosi pin under the control of spclk. simultan e ously, another byte shifts in from the slave on the miso pin. after 8 - bit data transfer complete, spif (spsr.7) will automatically set via har d wa re to indicate one byte data transfer complete. at the same time, the data received from the slave is also transferred in spdr. the user can clear spif and read data out of spdr. 14.4.2 slave mode when mstr is 0, the spi operates in slave mode. t he spclk pin bec omes input and it will be clock ed by another m aster spi device. the pin also becomes input. the master device cannot e x change data with the slave device until t he pin of the s lave device is externally pulled low . b efore data transmissions o c- curs, the of the slave d e vice must be pulled and remain low until the transmission is complete. if goes ss ss ss ss
n78e366 a data sheet publication release date: march 11, 2011 - 70 - revision : v2.0 high, the spi is forced into idle state. if the is force to high at the middle of transmission , the transmission will be aborted and the rest bits of the recei v ing shifter buffer will be high and goes into idle state. in slave mode, d ata flows from the m aster to the s lave on mosi pin and flows from the s lave to the m aster on miso pin. the data enters the shift register under the control of the spclk from the master device. after one byte is r e ceived in the shift register, it is immediately moved into the read data buffer and the spif bit is set. a read of the spdr is actually a read of the read data buffer. to prevent an overrun and the loss of the byte that caused by the overrun, the slave must read spdr out and the first spif must be cleared before a second transfer of data from the master device comes in the read data buffer . 14.5 clock formats and data transfer to accommodate a wide variety of synchronous serial peripherals, the spi has a clock polarity bit cpol (spcr.3) and a clock phase bit cpha (spcr.2) . figure 14 C 4 . spi clock forma ts shows that cpol and cpha compose four different clock formats. the cpol bit denotes the spclk line level in spi idle state . the cpha bit d e fines the edge on which the mosi and miso lines are sampled. the cpol and cpha should be iden tical for the master and slave devices on the same system. to communicat e in d i f ferent data formats with one another will result undete r mined result. figure 14 C 4 . spi clock forma ts in spi, a master device always initiates the transfer . if spi is selected as master mode (mstr = 1) and en a- bled (spien = 1), wri t ing to the spi data register (spdr) by the master device starts the spi clock and data transfer. after shifting one byte out and recei v ing o ne byte in, the spi clock stops and spif (spsr.7) in both master and slave are set. if spi interrupt enable bit espi ( eie .0) is set 1 and global interrupt is enabled (ea = 1), the interrupt service routine (isr) of spi will be executed. ss c p h a = 0 c p h a = 1 s a m p l e c p o l = 0 c p o l = 1 c l o c k p h a s e ( c p h a ) c l o c k p o l a r i t y ( c p o h ) s a m p l e s a m p l e s a m p l e
publication release date: march 11, 2011 - 71 - revision : v 2.0 con cerning the slave mode, the signal needs to be taken care . as shown in figure 14 C 4 . spi clock fo r- ma ts , when cpha = 0, the first spclk edge is the sampling strobe of msb (for an example of ls bfe = 0, msb first). therefore, the slave must shift its msb data before the first spclk edge. t he falling edge of is used for preparing the msb on miso line. the pin therefore must toggle high and then low b etween each successive serial byte . furthermore , if the slave writes data to the spi data regi s ter (spdr) while is low, a write collision e r ror occurs. when cpha = 1, the sampling edge thus locates on the second edge of spclk clock. the slave uses the first spclk clock to shift msb out rather than the falling edge. therefore, the line can remain low between successive transfers. this format may be preferred in systems having single fixe d master and single fixed slave. the line of the unique slave device can be tied to v ss as long as only cpha = 1 clock mode is used. note: the spi should be configured before it is enabled (spien = 1) , or a change of lsbfe, mstr, cp ol, cpha and spr[1:0] will abort a transmission in progress and force the spi system into idle state. prior to any co n figuration bit changed, spien must be disabled first . figure 14 C 5 . spi clock and data format with c ph a = 0 ss s p c l k c y c l e s s p c l k ( c p o l = 0 ) m o s i s s o u t p u t o f m a s t e r [ 2 ] s p i f ( m a s t e r ) 1 2 3 4 5 6 7 8 s p c l k ( c p o l = 1 ) t r a n s f e r p r o g r e s s [ 1 ] ( i n t e r n a l s i g n a l ) m s b m i s o 6 5 4 3 2 1 l s b m s b i n p u t t o s l a v e s s l s b 6 5 4 3 2 1 s p i f ( s l a v e ) [ 1 ] t r a n s f e r p r o g r e s s s t a r t s b y a w r i t i n g s p d r o f m a s t e r m c u . [ 2 ] s s a u t o m a t i c o u t p u t a f f e c t s w h e n m s t r = d i s m o d f = s s o e = 1 . s p c l k c y c l e s
n78e366 a data sheet publication release date: march 11, 2011 - 72 - revision : v2.0 figure 14 C 6 . spi clock and data format with c ph a = 1 14.6 slave select pin configuration N78E366A spi gives a flexible pin feature for different system requirements. when the spi operates as a slave, pin always rules as slave select input. when the master mode is enabled, has three different functions according to dismod f (spsr.3) and ssoe (spcr.7). by default, dismodf is 0. it means that the mode fault detection act i vate s . is configured as a input pin to check if the mode fault appears. on the contrary, if dismodf is 1, mode fault is inactivated a nd the ssoe bit takes over to control the function of the pin. while ssoe is 1, it means the slave s e lect signal will generate automatically to select a slave device. the as output pin of the master usually c onnect s with the input pin of the s lave device. the ou t- put automatically goes low for each transmission when selecting external slave device and goes high during each idl e state to de - select the slave device. while ssoe is 0 and dismodf is 1, is no more used by the spi and r e verts to be a general purpose i/o pin. ss t r a n s f e r p r o g r e s s [ 1 ] ( i n t e r n a l s i g n a l ) s p c l k c y c l e s s p c l k ( c p o l = 0 ) m o s i s s o u t p u t o f m a s t e r [ 2 ] s p i f ( m a s t e r ) 1 2 3 4 5 6 7 8 s p c l k ( c p o l = 1 ) m s b m i s o 6 5 4 3 2 1 l s b m s b i n p u t t o s l a v e s s l s b 6 5 4 3 2 1 s p i f ( s l a v e ) [ 1 ] t r a n s f e r p r o g r e s s s t a r t s b y a w r i t i n g s p d r o f m a s t e r m c u . [ 2 ] s s a u t o m a t i c o u t p u t a f f e c t s w h e n d i s m o d f = s s o e = m s t r = 1 . [ 3 ] i f s s o f s l a v e i s l o w , t h e m i s o w i l l b e t h e l s b o f p r e v i o u s d a t a . o t h e r w i s e , m i s o w i l l b e h i g h . [ 4 ] w h i l e s s s t a y s l o w , t h e l s b w i l l l a s t i t s s t a t e . o n c e s s i s r e l e a s e d t o h i g h , m i s o w i l l s w i t c h t o h i g h l e v e l . [ 3 ] [ 4 ] s p c l k c y c l e s ss
publication release date: march 11, 2011 - 73 - revision : v 2.0 14.7 mode fault detection the mode fault detection is useful in a system where more than one spi devices might become masters at t he same time. it may induce data contention . when the spi device is configured as a m aster and the input line is configured for mode fault input depending on table 14 C 1 . slave select pin c onfigurations , a m ode f ault error occur s once the is pulled low by others. it indicates that some other spi device is trying to a d- dress this master as if it is a slave. instantly t he mstr and spien control bits in the spcr are cleared via hardware to disable spi , mode fault flag modf (spsr.4) is set and an interrupt is generated if espi ( eie .0 ) and ea are enabled. 14.8 write collision error the spi is signal buffered in the transfer direc tion and double buffered in the receiving direction. new data for transmission cannot be written to the shift register until the previous transaction is co m plete. write collision occurs while an attempt was made to write data to the spdr while a transfer was in progress. spdr is not double buffered in the t ransmit direction . a ny writ ing to spdr cause data to be written directly into the spi shift register . once a write collision error is generated , wcol (spsr.6) will be set as a 1 via hardware to ind i cate a write collision . in this case, t he current transfer ring data continues its transmission. ho w ever the new data that caused the collision will be lost . a lthough the spi logic can d etect write collisions in both m aster and s lave modes, a write collision is normally a s lave error because a s lave has no indicat or when a m aster init i ates a transfer. during the receive of slave, a write to spd r causes a write collision under slave mode. wcol flag needs to be clear ed via sof t ware . 14.9 overrun error for receiving data, the spi is double buffered in the receiving dire c ti on. t he received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial byte . however, the received data must be read from spdr before the next data has been completely shifted in. as long as the first byte is read out of the read data buffer and spif is cleared before the next byte is ready to be transferred, no o verrun error cond i- tion occurs . otherwise t he overrun error occurs. in this condition, the s econd byte data will not be successfully received into the read data re g ister and the previous data will remains. if overrun occur, spiovf (spsr.5) will be set via hardware . this will also require an interrupt if enabled. figure 14 C 7 . spi overrun waveform shows the relati onship between the data recei v ing and the overrun error. ss
n78e366 a data sheet publication release date: march 11, 2011 - 74 - revision : v2.0 figure 14 C 7 . spi overrun waveform 14.10 spi i nterrupt s three spi status flags , spif, modf, and spiovf, can generate a n spi event interrupt requests. all of them locate in spsr. spif will be set after completion of data transfer with external device or a new data have been received and copied to spdr. modf b e comes set to indicate a low level on causing the mo de fault state. spiovf denotes a receiving overrun error. if spi interrupt mask is enable d via setting espi ( eie .0 ) and ea is 1 , cpu will ex e cutes the spi interrupt service routine once any of these three flags is set. the user needs to check flags to dete rmine what event caused the interrupt. these three flags are software clear ed . figure 14 C 8 . spi i nterrupt r equest s h i f t i n g d a t a [ n ] i n s h i f t i n g d a t a [ n + 1 ] i n s p i f d a t a [ n ] d a t a [ n ] r e a d d a t a b u f f e r s h i f t r e g i s t e r s h i f t i n g d a t a [ n + 2 ] i n s p i o v f d a t a [ n + 2 ] d a t a [ n ] r e c e i v i n g b e g i n s d a t a [ n + 1 ] r e c e i v i n g b e g i n s d a t a [ n + 2 ] r e c e i v e i n g b e g i n s [ 1 ] w h e n d a t a [ n ] i s r e c e i v e d , t h e s p i f w i l l b e s e t . [ 2 ] i f s p i f i s n o t c l e a r b e f o r e d a t a [ n + 1 ] p r o g r e s s d o n e , t h e s p i o v f w i l l b e s e t . d a t a [ n ] w i l l b e k e p t i n r e a d d a t a b u f f e r b u t d a t a [ n + 1 ] w i l l b e l o s t . [ 3 ] s p i f a n d s p i o v f m u s t b e c l e a r e d b y s o f t w a r e . [ 4 ] w h e n d a t a [ n + 2 ] i s r e c e i v e d , t h e s p i f w i l l b e s e t a g a i n . [ 1 ] [ 2 ] [ 3 ] [ 3 ] [ 4 ] s p i f d i s m o d f m s t r e s p i ( e i e . 0 ) s p i i n t e r r u p t r e q u e s t s p i o v f m o d e f a u l t d e t e c t i o n s s m o d f e a ss
publication release date: march 11, 2011 - 75 - revision : v 2.0 15. pulse width modulat or (pwm) N78E366A provides five pulse width mo dulated (pwm) ou t put channels to generate pulses of programmable length and interval. five pwm channels, pwm0~4, shares the same pins with p1.3~p1.7. the pwm period is defined by an 8 - bit pre - scal a r pwmp, which supplies the clock of the pwm counter. the pr e - scal a r is common for all pwm channels. the duty of each pwm channel is determined by t he value of five registers , pwm0, pwm1, pwm2, pwm3 , and pwm4. if the contents o f these registers are equal to or less than the 8 - bit counter value, the output will be 0 . else the output will be 1 if these registers value are larger th an the counter . set pwm x en (in pwmcon 0 [0,1,4,5] and pwmcon 1 .0) will enable to run or disable to stop each pwm channel respectively . in addition, the pwmxom (in pwmcon 0 [2,3,6,7] and pwmcon 1 .2 ) must set 1 to output the internal pwm signal to port pins. without setting pwmxom, the pins which share with alternative pwm fun c- tion will be normal general purpose i/o of p1.3~p1.7 even though pwm is enabled . the following registers relate to pwm functi on. pwmcon0 C pwm control 0 7 6 5 4 3 2 1 0 pwm3oe pwm2oe pwm3en pwm2en pwm1oe pwm0oe pwm1en pwm0en r/w r/w r/w r/w r/w r/w r/w r/w address: dc h reset value: 0000 0000b b it name description 7 pwm3oe pwm3 output enable. 0 = p1.6 serves as general purpos e i/o. 1 = p1.6 serves as output pin of pwm3 signal. 6 pwm2oe pwm2 output enable. 0 = p1.5 serves as general purpose i/o. 1 = p1.5 serves as output pin of pwm2 signal. 5 pwm3en pwm3 enable. 0 = pwm3 is disabled and stops. 1 = pwm3 is enabled and runs . 4 pwm2en pwm2 enable. 0 = pwm2 is disabled and stops. 1 = pwm2 is enabled and runs . 3 pwm1oe pwm1 output enable. 0 = p1.4 serves as general purpose i/o. 1 = p1.4 serves as output pin of pwm1 signal. 2 pwm0oe pwm0 output enable. 0 = p1.3 serves as general purpose i/o. 1 = p1.3 serves as output pin of pwm0 signal. 1 pwm1en pwm1 enable. 0 = pwm1 is disabled and stops . 1 = pwm1 is enabled and runs .
n78e366 a data sheet publication release date: march 11, 2011 - 76 - revision : v2.0 b it name description 0 pwm0en pwm0 enable. 0 = pwm0 is disabled and stops . 1 = pwm0 is enabled and runs . pwmcon1 C pwm control 1 7 6 5 4 3 2 1 0 - - - - - pwm4oe - pwm4en - - - - - r/w - r/w address: ce h reset value: 0000 0000b b it name description 7:3 - reserved. 2 pwm4oe pwm4 output enable. 0 = p1.7 serves as general purpose i/o. 1 = p1.7 serves as output pin of pwm4 signal. 1 - reserved. 0 pwm4en pwm0 enable. 0 = pwm 4 is disabled and stops . 1 = pwm 4 is enabled and runs . pwmp C pwm period 7 6 5 4 3 2 1 0 pwmp[7:0] r/ w address: d9 h reset value: 0000 0000b b it name description 7:0 pwmp[7:0] pwm period. this byte controls th e period of the pwm outp ut of pwm0~ pwm4 channels . pwm0 C pwm0 d uty 7 6 5 4 3 2 1 0 pwm0[7:0] r/ w address: da h reset value: 0000 0000b b it name description 7:0 pwm0[7:0] pwm0 duty. this byte controls the duty of the pwm0 output.
publication release date: march 11, 2011 - 77 - revision : v 2.0 pwm1 C pwm1 d uty 7 6 5 4 3 2 1 0 pwm1[7:0] r/ w address: db h reset value: 0000 0000b b it name description 7:0 pwm1[7:0] pwm1 duty. this byte controls the duty of the pwm1 output. pwm 2 C pwm 2 d uty 7 6 5 4 3 2 1 0 pwm2[7:0] r/ w address: dd h reset value: 0000 0000b b it name description 7:0 pwm2[7:0] pwm2 duty. this byte controls the duty of the pwm2 output. pwm3 C pwm3 d uty 7 6 5 4 3 2 1 0 pwm3[7:0] r/ w address: de h reset value: 0000 0000b b it name description 7:0 pwm3[7:0] pwm3 duty. this byte controls the duty of the pwm3 output. pwm4 C pwm4 d uty 7 6 5 4 3 2 1 0 pwm4[7:0] r/ w address: c f h reset value: 0000 0000b b it name description 7:0 pwm4[7:0] pwm4 duty. this byte controls the duty of the pwm4 output. the repetition frequency of pwm , f pwm is given by , , p re - scal ar division factor = pwm + 1 . pwm high duty of pwmx = . 255 ) 1 pwmp ( f f periph pwm ? ? ? 255 pwmx
n78e366 a data sheet publication release date: march 11, 2011 - 78 - revision : v2.0 this gives a repetition frequency range of 12 2 hz to 31. 25 k hz ( f periph = 16mhz). by loading the pwm x regi s- ters with either 00h or ffh, the pwm channels will generate a constant low or high level output , respectively . when a compare register pwm x is loaded with a new value, the associated output updated immediately. it does not have to wait u n til the end of the current counter period . figure 15 C 1 . pwm function block p wm demo code , mov pwmp , # 128 ; determine pwm p e riod mov pwm0 , # 0h ;duty = 0% mov pwm1 , # 40h ;duty = 25% mov pwm 2,# 80h ;duty = 50% mov pwm 3,# 0c0h ;duty = 75 % mov pwm 4,# 0ffh ;duty = 100% orl pwmcon 0 , #00110011b ;enable pwm0~3 orl pwmcon 1 , #00000 0 01b ;enable pwm 4 orl pwmcon 0 ,# 11001100 b ;output e n able pwm0~3 orl pwmcon 1 ,# 00000100 b ;output e n able pwm4 + - + - + - + - + - p w m 0 o e p w m 1 o e p w m 2 o e p w m 3 o e p w m 4 o e 8 - b i t u p - c o u n t e r p w m 0 p w m 2 p w m 3 p w m 1 p w m 4 p w m 0 ( p 1 . 3 ) p w m 1 ( p 1 . 4 ) p w m 2 ( p 1 . 5 ) p w m 3 ( p 1 . 6 ) p w m 4 ( p 1 . 7 ) p r e - s c a l a r f p e r i p h p w m p p w m 0 e n p w m 1 e n p w m 2 e n p w m 3 e n p w m 4 e n
publication release date: march 11, 2011 - 79 - revision : v 2.0 16. timed access protect ion (ta) N78E366A has several fea tures lik e the watchdog t i mer, the isp function, boot select control, etc. are cr u cial to proper operation of the system. if le aving these control registers unprotected, errant code may write und e- termined value into them, it result s in incorrect operation and loss of control. in order to prevent this risk , the N78E366A has a pr o tection scheme which limits the write access to critical sfr s. this protection scheme is done using a timed a c cess . the following registers are related to ta process . ta C timed acce ss 7 6 5 4 3 2 1 0 ta[7:0] w address: c7 h reset value: 0000 0000b b it name description 7:0 ta[7:0] timed access. the t imed a ccess register controls the access to protected sfrs. to access pr o- tected bits, the user must first write aah to the ta and imme diately followed by a write of 55h to ta. after these two step s , a writing permission window is opened for three machine - cycles during which the user may write to protected sfrs. in timed access method, the bits, which are protected, have a timed write e nable window. a write is su c cessful only if this window is active, otherwise the write will be discarded. when the software writes aa h to ta, a cou n ter is started. this counter waits for three machine - cycles looking for a write of 55 h to ta. if the second write of 55 h occurs within three machine - cycles of the first write of aa h , then the timed access window is opened. it remains open for three machine - cycles during which the user may write to the pr o tected bits. after three machine - cycle s, this window autom atically closes. once the window closes , the procedure must be r e- peated to access the other protected bits. not that the ta protected sfrs are required timed access for wri t- ing. but the reading is not protected. the user may read ta protected sfr with out g iving aa h and 55 h to ta . t he suggest ion code for opening the timed access window is shown below. ( clr ea ) ;if any interrupt is enabled, disable temporally mov ta,#0aa h mov ta,#55 h (instruction that writes a ta protected register) (setb ea) ;resume interrupts enabl e d the writings of aah , 55h to ta register and the writing - protection register must occur within 3 machine - cycles of each other. any enabled i nterrupt should be disabled during this procedure to avoid delay between the se three writings . i f there is no interrupt enabled, the clr ea and setb ea instructions can be left out. once the timed access window closes , the procedure must be r e peated to access the other protected bits.
n78e366 a data sheet publication release date: march 11, 2011 - 80 - revision : v2.0 examples of t imed a ssessing are shown to i llustrate correct or inc orrect writing process es . example 1, mov ta,#0aah ; 2 machine - cycles . mov ta,#55h ; 2 machine - cycles . orl chpcon,#data ;2 machine - cycles . example 2, mov ta,#0aah ;2 machine - cycles . mov ta,#55h ;2 machine - cycles . nop ;1 machine - cycle . nop ; 1 machine - cycle . anl isptrg,#data ;2 machine - cycles . example 3 , mov ta,#0aah ;2 machine - cycles . nop ;1 machine - cycle . mov ta,#55h ;2 machine - cycles . mov wdcon ,# data1 ; 2 machine - cycles . orl pmc ,# data2 ; 2 machine - cycles . example 4 , mov ta,#0 aah ;2 machine - cycles . nop ;1 machine - cycle . nop ;1 machine - cycle . mov ta,#55h ;2 machine - cycles . an l wdcon ,# data ; 2 machine - cycles . in the first examples, the writing to the pro tected bits is done before the three - machine - cycle window closes . in e x ample 2 , however, the writing to isptrg does not complete during the window opening, there will be no change of the value of isptrg . in example 3 , the wdcon is successful written but the pmc access is out of the three - machine - cycle window. therefore pmc value will not change either. in example 4 , the se c ond write 55h to ta completes after three machine - cycles of the first write ta of aah , therefore the timed access wi n- dow in not opened at all, and the write to the pr o tected bit fails. in N78E366A , th e ta protected sfrs includes chpcon (9fh), isptrg (a4h), pmc (ach), and wdcon (aah).
publication release date: march 11, 2011 - 81 - revision : v 2.0 17. interrupt system the purpose of the interrupt is to make the software deal with unscheduled or asynchronous events. N78E366A has a four - priority - level interrupt structure with 11 interrupt sources. each of the inte r rupt sources has an individual priority bit, flag, interrupt vector and enable bit. in addition, the interrupts can be globally en a- bled or disabled. when an interrupt occurs , the cpu is expected to service the in terrupt. this service is spec i- fied as an interrupt service routine (isr). the isr resides at a predetermined address as shown in table 17 C 1 . N78E366A i nterrupt v ecto r s . when the interrupt occurs if enabled , the cpu will vector to the appr o priate location. it will execute the code at this location, staying in an interrupt service state until done with the isr. once an isr has begun, it can be inter rupted o nly by a higher priority interrupt. the isr is terminated by a r e- turn from interrupt instruction reti. this instruction will force the cpu return to the instruction that would have been ne xt when the interrupt o c curred. table 17 C 1 . N78E366A i nterrupt v ecto r s source vecto r a d dress vector number source vector a d dress vector number external interrupt 0 0003 h 0 timer 0 overflow 000b h 1 external interrupt 1 0013 h 2 timer 1 overflow 001b h 3 serial port interrupt 0023 h 4 timer 2 o verflow / c a p ture / r eload 002b h 5 external interrupt 2 0033 h 6 external interrupt 3 003b h 7 spi i nterrupt 0043h 8 power down waking - up timer inte r rupt 00 4 b h 9 brown - out detection inte r rupt 0053h 10 the sfrs associated with the se interrupt s are listed below. ie C interrupt enable ( bit - addre ssable ) 7 6 5 4 3 2 1 0 ea - et2 es et1 ex1 et0 ex0 r/w - r/w r/w r/w r/w r/w r/w address: a8h reset value: 0000 0000b bit name description 7 ea enable all interrupt. this bit globally enables/disables all interrupts. it overrides the individual inte r r upt mask settings. 0 = disable all interrupt sources. 1 = enable each interrupt depending on its individual mask setting. individual i n- terrupts will occur if enabled. 6 - reserved.
n78e366 a data sheet publication release date: march 11, 2011 - 82 - revision : v2.0 bit name description 5 et2 enable timer 2 interrupt. 0 = disable all timer 2 interrupt s . 1 = e nable interrupt generated by tf2 (t2con.7) or exf2 (t2con.6) . 4 es enable serial port (uart) interrupt. 0 = disable all uart interrupt s . 1 = enable interrupt generated by ti ( scon.1 ) or ri ( scon.0). 3 et1 enable timer 1 interrupt. 0 = disable timer 1 int errupt 1 = enable interrupt generated by tf1 ( tcon.7 ) . 2 ex1 enable external interrupt 1. 0 = disable external interrupt 1. 1 = enable interrupt generated by pin (p3.3). 1 et0 enable timer 0 interrupt. 0 = disable timer 0 interrup t 1 = enable interrupt generated by tf0 ( tcon.5 ) . 0 ex0 enable external interrupt 0. 0 = disable external interrupt 0. 1 = enable interrupt generated by pin (p3.2). e ie C extensive interrupt enable 7 6 5 4 3 2 1 0 - - - - - ebod e p dt espi - - - - - r/w r/w r/w address: bd h reset value: 0000 0000b b it name description 7:3 - reserved. 2 ebod enable brown - out detection interrupt. 0 = disable brown - out detection interrupt. 1 = enable interrupt generated by bof (pmc.3). 1 e p dt ena ble power down w aking - up timer interrupt. 0 = disable power down w aking - up timer interrupt 1 = enable interrupt generated by pdtf ( p dcon .5 ) . 0 espi enable spi interrupt. 0 = disable spi interrupt. 1 = enable interrupt generated by spif (spsr.7) , spiovf (s psr.5) , or modf (spsr.4). ip C interrupt priority ( bit - addressable ) [1] 7 6 5 4 3 2 1 0 - - pt2 ps pt1 px1 pt0 px0 - - r/w r/w r/w r/w r/w r/w address: b8h reset value: 0000 0000b b it name description 7:6 - reserved. 1 int 0 int
publication release date: march 11, 2011 - 83 - revision : v 2.0 b it name description 5 pt2 timer 2 interrupt priority l ow bit. 4 ps serial port (uart) interrupt priority low bit. 3 pt1 timer 1 interrupt priority low bit. 2 px1 external interrupt 1 priority low bit. 1 pt0 timer 0 interrupt priority low bit. 0 px0 external interrupt 0 priority low bit. [1] ip is used i n combination with the iph to determine the priority of each interrupt source. see table 17 C 2 . i nterr upt p rio r- ity l evel setting for co r rect interrupt priority configuration. iph C interrupt priority high 7 6 5 4 3 2 1 0 px3h [ 2 ] px2h [ 2 ] pt2h [ 3 ] psh [ 3 ] pt1h [ 3 ] px1h [ 3 ] pt0h [ 3 ] px0h [ 3 ] r/w r/w r/w r/w r/w r/w r/w r/w address: bah reset value: 0000 0000b b it name description 7 px3h external interrupt 3 priority high bit. 6 px2h external interrupt 3 priority high bit . 5 pt2h timer 2 interrupt priority high bit. 4 psh serial port (uart) interrupt priority high bit. 3 pt1h timer 1 interrupt priority high bit. 2 px1h external interrupt 1 priority high bit. 1 pt0h timer 0 interrupt priority high bit. 0 px0h external interrupt 0 priority high bit. [ 2 ] px2h and px3h are used in combination with the px2 ( xicon . 3 ) and px3 ( xicon .7) respectively to determine the priority of external interrupt 2 and 3 . see table 17 C 2 . i nterr upt p riority l evel setting for correct interrupt priority config u- ration. [ 3 ] these bits is used in combination with the ip respectively to d e termine the priority of each interrupt source. see table 17 C 2 . i nterr upt p riority l evel setting for correct interrupt priority config u ration. e ip C extensive interrupt priority [ 4 ] 7 6 5 4 3 2 1 0 - - - - - pbo d p p dt pspi - - - - - r/w r/w r/w address: bch reset value: 0000 0000b b it name description 7:3 - reserved. 2 pbo d brown - out detection interrupt priority low bit. 1 ppdt power down w aking - up t imer interrupt priority low bit. 0 pspi spi interrupt priority low bit.
n78e366 a data sheet publication release date: march 11, 2011 - 84 - revision : v2.0 [ 4 ] eip is used in combination with the eiph to determine the pr i ority of each interrupt source. see table 17 C 2 . i nterr upt p riority l evel setting for correct interrupt priority configuration. eiph C extensive interrupt priority high [1] 7 6 5 4 3 2 1 0 - - - - - pbo d h p p dt h pspi h - - - - - r/w r/w r/w address: bbh reset value: 0000 0000b b it name description 7:3 - reserved. 2 pbo d h brown - out detection interrupt priority high bit. 1 p p dth power down w aking - up t imer interrupt priority high bit. 0 pspih spi interrupt priority high bit. [1] eiph is used in combination w ith the eip to determine the pr i ority of each interrupt source. see table 17 C 2 . i nterr upt p riority l evel setting for correct interrupt priority configuration. tcon C timer 0 and 1 control ( bit - addressable ) 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 r/w r /w r/w r /w r/w r /w r/w r /w address: 88h reset value: 0000 0000b bit name description 3 ie1 external interrupt 1 edge flag. this flag is set via hardware when an edge/level of type defined by it1 is detec t- ed. if it1 = 1, this bit will remain set until cleared via software or at the begi n ning of the external interrupt 1 service routine. if it1 = 0, this flag is the i n verse of the input signal's logic level. 2 it1 external interrupt 1 ty pe select . this bit selects whether the pin will detect falling edge or low level tri g gered interrupts. 0 = is low level triggered. 1 = is falling edge triggered. 1 ie0 external inter rupt 0 edge flag. this flag is set via hardware when an edge/level of type defined by it0 is detec t- ed. if it0 = 1, this bit will remain set until cleared via software or at the begi n ning of the external interrupt 0 service routine. if it0 = 0, this flag is the i n verse of the input signal's logic level. 0 it0 external interrupt 0 type select . this bit selects whether the pin will detect falling edge or low level tri g gered interrupts. 0 = is low level triggered. 1 = is falling edge triggered. 1 int 1 int 1 int 1 int 0 int 0 int 0 int 0 int
publication release date: march 11, 2011 - 85 - revision : v 2.0 xicon C external interrupt control ( bit - addressable ) 7 6 5 4 3 2 1 0 px3 [1] ex3 ie3 it3 px2 [1] ex2 ie2 it2 r/w r /w r/w r /w r/w r /w r/w r /w address: c0h reset value: 0000 0 000b bit name description 7 px3 external interrupt 3 priority low bit. 6 ex3 enable external interrupt 3. 0 = disable external interrupt 3. 1 = enable interrupt generated by pin (p4.2). 5 ie3 external interrupt 3 edge flag. this flag is set via hardware when an edge/level of type defined by it3 is detec t- ed. if it3 = 1, this bit will remain set until cleared via software or at the begi n ning of the external interrupt 3 service routine. if it3 = 0, this flag is the i n verse of the input signal's logic level. 4 it3 external interrupt 3 type select . this bit selects whether the pin will detect falling edge or low level tri g gered interrupts. 0 = is low level triggere d. 1 = is falling edge triggered. 3 px2 external interrupt 2 priority low bit. 2 ex2 enable external interrupt 2. 0 = disable external interrupt 2. 1 = enable interrupt generated by pin (p4.3). 1 ie2 exter nal interrupt 2 edge flag. this flag is set via hardware when an edge/level of type defined by it2 is detec t- ed. if it2 = 1, this bit will remain set until cleared via software or at the begi n ning of the external interrupt 2 service routine. if it2 = 0, thi s flag is the i n verse of the input signal's logic level. 0 it2 external interrupt 2 type select . this bit selects whether the pin will detect falling edge or low level tri g gered interrupts. 0 = is low level triggered. 1 = is falling edge triggered. [1] px2 and px3 are used in combination with the px2h (iph.6) and px3h (iph.7) respectively to determine the priority of external interrupt 2 and 3 . see table 17 C 2 . i nterr upt p riority l evel setting for correct interrupt prio r ity configuration. the external interrupts and can be either edge or level triggered depen d ing on bits it 0 (tcon.0) and it1 (tcon.2) . the bits ie0 (tcon.1) and ie1 (tcon.3) are the flags which are checked to generate the interrupt. in the edge triggered mode, the or inputs are sampled in every machine - cycle . if the sample is high in one cycle and low in the next, then a high to low transition is detected and the interrupts r e- quest flag ie 0 or ie1 will be set. since the external interrupts are sampled every machine - cycle , they have to be held high or low for at le ast one complete machine - cycle . the ie 0 and ie1 are automat i cally cleared when the interrupt service routine is called. if the level tri g gered mode is selected, then the requesting source has to 3 int 3 int 3 int 3 int 3 int 2 int 2 int 2 int 2 int 2 int 0 int 1 int 0 int 1 int
n78e366 a data sheet publication release date: march 11, 2011 - 86 - revision : v2.0 hold the pin low till the interrupt is serviced. the ie 0 and ie1 will not be cleared by the hardware on e n tering the service routine. in the level triggered mode, ie0 and ie1 follows the inverse value of and pins. if interrupt pins continue to be held low even after th e service routine is completed, the processor will acknowledge another interrupt request from the same source. N78E366A ( on plcc - 44, pqfp - 44 , and lqfp - 48 packages) possessed other two external interrupts and . their setting and operation are just the same as interrupt 0 and 1. all c onfiguring bits locate in xicon . t he individual interrupt flag corresponding to external interrupt 2 to 3 will also be automatically cleared via hardware once its own interrupt servi ce routine is ex e cuted. the timer 0 and 1 interrupts are generated by the tf0 and tf1 flags. these flags are set by the ove r flow in the timer 0 and timer 1 and automatically cleared by the hardware when the timer inte r rupt is serviced. tf2 or exf2 flag ge n erate s the timer 2 interrupt . these flags are set by overflow , capture , or reload events in the t imer 2 operation. the hardware will not clear these flags when a t imer 2 interrupt service routine execut es . software has to resolve the cause of the interrup t between tf2 and exf2 and clear the a p propriate flag. the s erial port can generate interrupts on reception or transmission. there are two interrupt sources from the s erial port block, which are obtained by the ri and ti bits in the scon. these bits are no t automatically cleared by the hardware . t he user ha s to clear these bits via software . the power down waking - up t imer can be used as a simple timer . the power down waking - up t imer inte r rupt flag pdtf ( p dcon . 5 ) i s set once an overflow occurs . if the interr upt is enabled by the enable bit epdt ( eie . 1 ) , then an interrupt will o c cur. brown - out detect ion , if enabled, can cause brown - out flag bof (pmc.3) to be asserted if power voltage drop below brown - out vol t age level. the i nterrupt will occur if borst ( pmc . 4 ) is 0 and ebod ( eie . 2 ) is 1 . spi asserts interrupt flag spif (spsr.7) on completion of data transfer with a n external device. if spi interrupt enable bit espi ( eie .0 ), a serial peripheral interrupt generate s . spif flag is sof t ware clear. modf (spsr.4) and spiovf (spsr.5) will also gene r ate spi interrupt. they share the same vector address with spif. when interrupt is gene r ated, the user should tell which flag requires the interrupt. all the bits that generate interrupts can be set or reset via har d ware , and thereby software initiated interrupts can be generated. each of the individual interrupts can be enabled or disabled by setting or clearing its contro l- ling bit in the ie or eie . ie also has a global enable bit ea (ie.7) which can be cleared to disable all the inte r- rupts at once . it is set to enable all individually enabled inte r rupt. note that every interrupts, if enabled, is generated by a setting as a logic 1 of its interrupt flag no mat ter by hardware or software. the user should take care of each inter rupt flag in its own interrupt ser vice ro u tine (isr). 0 int 2 int 3 int 1 int
publication release date: march 11, 2011 - 87 - revision : v 2.0 most of interrupt flags must be cleared by writing it as a logic 0 via software. without clearing the flag, the isr of corresponding interrupt source will ex e cute again and again non - stopped . 17.1 priority l evel structure there are four priority levels for the interrupts, highest, high, low , and lowest. the interrupt sources can be i n- dividually set to one of four priority levels by setting their own priority bits. table 17 C 2 lists four priority setting. naturally , a low priority interrupt can itself be interrupted by a high prio r ity interrupt, but not by another same level interrupt or lower level . a highest priority can ? t be interrupted by any other interrupt source. in addition, there exists a pre - defined hiera r chy among the interrupts themselves. this hierarchy comes into play when the interrupt controller has to resolve simultaneous requests having the same priority level. this hierarchy is d e- fined as shown on table 17 C 3 . it also summarizes the interrupt sources, flag bits, vector addresses, e n able bits, priority bits, natural priority and the permission to wake up the cpu from power down mode. for details of waking cpu up fr om power down mode, please s ee se c tion 19.2 power d own mode on page 99 . table 17 C 2 . i nterr upt p riority l evel setting interrupt priority control bits interrupt priority le v el ip h / eiph ip / eip / xicon [ 7 ,3] 0 0 level 0 (lowes t ) 0 1 level 1 1 0 level 2 1 1 level 3 (highest) table 17 C 3 . chara cteristics of each interrupt source source vector a d dress flag enable b it natural p rio r ity priority c o n trol b its power d own w ak ing up external i nte r rupt 0 0003h ie0 [1] ex0 1 px0, px0h yes timer 0 o verflow 000bh tf0 [2] et0 2 pt0, pt0h no external i nte r r upt 1 0013h ie1 [1] ex1 3 px1, px1h yes timer 1 o verflow 001bh tf1 [2] et1 4 pt1, pt1h no serial p ort (uart) 0023h ri + ti es 5 ps, psh no timer 2 o verflow / c a p- ture / r eload 002bh tf2 [2] + exf2 et2 6 pt2, pt2h no external i nte r rupt 2 0033h ie2 [1] ex2 7 px2, px2h yes external i nte r rupt 3 003bh ie3 [1] ex3 8 px 3 , px 3 h yes
n78e366 a data sheet publication release date: march 11, 2011 - 88 - revision : v2.0 source vector a d dress flag enable b it natural p rio r ity priority c o n trol b its power d own w ak ing up spi interrupt 0043 h spif (spsr.7) + modf (spsr.4) + spiovf (spsr.5) espi ( eie .0) 9 pspi ( eip .0), pspih ( eiph .0) n o power down wa k ing - up t imer i nte r rupt 00 4 b h pdtf ( p dcon .5) e p dt ( eie .1) 10 p p dt ( eip .1), p p dth ( eiph .1) yes brown - out i nte r rupt 0053 h bof (pmc.3) ebod ( eie .2) 11 pbod ( eip .2), pbodh ( eiph .2) yes [1] while the external interrupt pin is set as edge trigger e d (itx = 1), its own flag iex will be automatically cleared if the i n- terrupt service routine (isr) is executed. while as level triggered (itx = 0), iex follows the inverse of respective pin state. it is not co n trolled via software . [2] tf0 and tf1 will be automatically cleared if the interrupt se r vice routine (isr) is exe cuted. but be aware that tf2 will not. the interrupt flags are sampled every machine - cycle . in the same machine - cycle , the sampled interrupts are polled and their priority is resolved. if certain conditions are met then the hardware will ex e cute an intern ally generated lcall instruction which will vector the process to the appropriate interrupt vector address. the conditions for generating the lcall are , 1. an interrupt of equal or higher priority is not currently being se r viced. 2. the current polling cyc le is the last machine - cycle of the instru c tion currently being executed. 3. the current instruction does not involve a write to any enable or priority setting bits and is not a reti. if any of these conditions are not met, then the lcall will not be gener ated. the polling cycle is repeated ev e- ry machine - cycle . if an interrupt flag is active in one cycle but not responded to for the above cond i tions are not met, if the flag is not still active when the blocking condition is removed, the denied interrupt wil l not be se r- viced. this means that the interrupt flag was once active but not serviced is not remembered . e very polling c y cle is new. the processor responds to a valid interrupt by executing an lcall instruction to the appropriate service ro u- tine. this may or may not clear the flag, which caused the interrupt according to different i n terrupt source. the hardware lcall behaves exactly like the software lcall instruction. this instruction saves the program counter contents onto the stack ram but does not save the pr o gram status word ( psw ) . the pc is reloaded with the vector address of that interrupt which caused the lcall. execution continues from the vectored a d- dress till an reti instruction is ex e cuted. on execution of the reti instruction the processor pops the stack and loads the pc with the contents at the top of the stack. the user must take care that the status of the stack is restored to what i t was after the hardware lcall . i f the execution is to return to the interrupted pr o gram , t he processor does no t notice anything if the stack contents are modified and will proceed with execution from the address put back into pc. note that a simple ret i n struction would perform exactly the same process as a
publication release date: march 11, 2011 - 89 - revision : v 2.0 reti instruction, but it would not inform the interrupt c o n troller that the interrupt service routine is completed . ret would leave the controller still thinking that the service routine is underway , making future interrupts i m- possible. 17.2 interrupt latency the response time for each interrupt source depends on sev eral factors, such as the nature of the interrupt and the instruction underway. in the case of external interrupts and , they are sampled at every machine - cycle and then their corresponding inte r rupt flags ie 0 or ie1 will be set or reset. the value are not actually polled by the circuit until the next machine - cycle . if a request is a c tive and all three previous conditions are met, then the hardware generated lcall is executed. this lcall itself takes 2 machine - cycle s to be completed. thus there is a minimum time of 3 machine - cycle s between the interrupt flag being set and the i n- terrupt service routine being executed. a longer response time should be anticipated if any of the three conditions are not met. if a hi gher or equal pr i- ority is being serviced, then the interrupt latency time obviously depends on the n a ture of the service routine currently being executed. if the polling cycle is not the last machine - cycle of the instruction being ex e cuted, then an additio nal delay is introduced. the maximum response time (if no other inte r rupt is in service) occurs if the device is performing a write to ie, ip and then executes a mul or div instruction. from the time an inte r- rupt source is activated, the longest reaction t ime is 9 m a chine - cycle s. this includes 1 machine - cycle to detect the interrupt, 2 machine - cycle s to complete the ie, eie , ip , iph, eip , or eiph access, 4 machine - cycle s to complete the mul or div instruction and 2 machine - cycle s to complete the hardware lc all to the interrupt vector l o cation. thus in a single - interrupt system the interrupt response time will a l ways be more than 3 machine - cycle s and not more than 9 m a chine - cycle s . 1 int 0 int
n78e366 a data sheet publication release date: march 11, 2011 - 90 - revision : v2.0 18. i n system programming ( isp ) the internal program memory support s both hardware programming and in system programming ( isp ) . har d- ware programming mode uses gang - writers to reduc e programming costs and time to market while the pro d- ucts enter into the mass production state . however , if the product is just under development or the end p roduct needs firmware updating in the hand of an end user , the hardware programming mode will make repeated pr o- gramming difficult and i n convenient . isp method makes it easy and possible. N78E366A supports isp mode al low ing a device to be reprogrammed under software control. furthermore, t he capability to update the appl i- cation firmware makes wide range of appl i cations possible. isp is performed without removing the microcontroller from the sy s tem. the most common method to perform isp is via uart along with the firmware in ldrom. general speaking , pc transfers the new aprom code through serial port . then ldrom firmware r e ceives it and re - programs into aprom through isp commands. nuvoton provides isp firmware , usb isp writer and pc application program for n78 e366a . it makes users quite easy perform isp through nuvoton standard isp tool . please explore nuvoton 8 - bit microcontroller we b- site: nuvoton 80c51 microcontroller development tool . 18.1 isp procedure unlike ram ? s re al - time operation, to update flash data often takes long time. furthermore, it is a quite complex timing procedure to erase, program , or read flash data. f ortunately, N78E366A c arried out the flash operation with convenient mechanism to help the user update the flash content. after isp enabled by setting ispen (chpcon.0 with ta protect ed ), t he user can easily fill the 16 - bit target a d dress in ispah and ispal , data in ispfd and co mmand in ispcn. then the isp is ready to begin by setting a trigge r ing bit ispgo (isptrg.0). note that isptrg is also ta protected. at this moment, the cpu holds the program counter and the built - in isp automation takes over to control the internal charge - pump for high voltage and the detail signal timing. a f- ter isp action completed , the program counter continues to run the following instructions . the ispgo bit will be automatically cleared. the user may repeat steps above for next isp action if necessary. through this pr o- gress, the user can easily erase, program , and verify the embedded flash by just taking care of the pure sof t- ware . the following registers relate to isp processing.
publication release date: march 11, 2011 - 91 - revision : v 2.0 chpcon C chip control ( ta protected ) 7 6 5 4 3 2 1 0 swrst ispf ldue n xram en - - bs ispen w r /w r/w r/w - - r/w r /w address: 9fh reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it name description 6 ispf isp fault flag. the hardware will set this bit when any o f the following condition is met: 1. the accessing area is illegal, such as, (a) erasing or programming aprom itself when aprom code runs . (b) erasing or programming ldrom when aprom code runs but ldue n is 0. (c) erasing , programming , or reading config byt es when aprom code runs . (d) erasing or programming ldrom itself when ld rom code runs . (e) accessing oversize. 2. the isp operating runs from internal program memory into e x ternal one. this bit should be cleared via software . 5 ldue n u pdating ldrom enable . 0 = the ldrom is inhibited to be erased or programmed when aprom code runs. ldrom remains read - only. 1 = the ldrom is allowed to be fully accessed when aprom code runs. 0 ispen isp enable. 0 = enable isp function. 1 = disable isp function. to enable isp function will start the internal 22.1184 mhz rc oscillator for timing control. to clear ispen should always be the last instruction after isp operation in order to stop internal rc for redu c ing power consumption. ispcn C isp control 7 6 5 4 3 2 1 0 isp a . 17 isp a . 16 foen fcen fctrl.3 fctrl.2 fctrl.1 fctrl.0 r/w r /w r/w r/w r/w r/w r/w r /w address: afh reset value: 0000 0000b b it name description 7:6 ispa[17:16] isp control. this byte is for isp controlling command to decide isp destinations and a c- tions. for details, see table 18 C 1 . isp modes and command c odes . 5 foen 4 fcen 3:0 fctrl[3:0]
n78e366 a data sheet publication release date: march 11, 2011 - 92 - revision : v2.0 ispah C isp address high byte 7 6 5 4 3 2 1 0 ispa [ 15 : 8 ] r/ w address: a 7 h reset value: 0000 0000b b it name descriptio n 7:0 ispa[15:8] isp address high byte. ispah contains address ispa[15:8] for isp operations. ispal C isp address low byte 7 6 5 4 3 2 1 0 ispa[7:0] r/ w address: a 6 h reset value: 0000 0000b b it name description 7:0 ispa[7:0] isp address low byte. isp al contains address ispa[7:0] for isp operations. ispfd C isp flash data 7 6 5 4 3 2 1 0 ispfd[7:0] r/ w address: a e h reset value: 0000 0000b b it name description 7:0 ispfd[7:0] isp flash data. this byte contains flash data which is read from or is goi ng to be written to the flash memory. the user should w rite data into ispfd for program mode before triggering isp processing and read data from ispfd for read /verify mode after isp pro c essing is finished. isptrg C isp trigger ( ta protected ) 7 6 5 4 3 2 1 0 - - - - - - - ispgo - - - - - - - w address: a 4 h reset value: 0000 0000b b it name description 0 ispgo isp go. isp begin s by setting this bit as a logic 1 . a fter this instruction, the cpu holds the program counter (pc) and the isp hardware automation takes over to co n- trol the progress . after isp action completed, the program counter continues to run the following instructions. the ispgo bit will be aut o matically cleared and always read as logic 0.
publication release date: march 11, 2011 - 93 - revision : v 2.0 18.2 isp commands N78E366A provides a wide application to perform isp to aprom or ldrom . the isp action mode and the destination of the flash block are defined by isp control register ispcn . table 18 C 1 . isp modes and command c odes isp mode ispcn ispah, ispal isp a [15: 0] ispfd[7:0] isp a . 17, isp a . 16 foen fcen fctrl[3:0] standby x , x [1] 1 1 x x x aprom page erase 0, 0 1 0 0010 a ddress i n [ 2 ] x ldrom page erase 0, 1 1 0 0010 a ddress i n [ 2 ] x aprom pr o gram 0, 0 1 0 0001 a ddress i n data in ldrom program 0, 1 1 0 0001 a ddress i n data in aprom read 0, 0 0 0 0000 a ddress i n data out ldrom read 0, 1 0 0 0000 a ddress i n data out all config bytes erase 1, 1 1 0 0010 00 xx h x config program 1, 1 1 0 0001 config0: 0000h config 2 : 000 2 h config 3 : 000 3 h data in config read 1, 1 0 0 0000 config0: 0000h config2: 0002h config3: 0003h data out [1] x means d on ? t c are . [ 2 ] each page is 256 - byte size . therefore , the address for page erase should be 0000h, 0100h, 0200h, 0300h, etc. , which is incremented by one of high byte address . 18.3 u ser guide of isp isp facilitates the updating flash contents in a convenient way; however, the user should follow some r e stricted laws in order that the isp operates correct ly . without notic ing warnings will possible cause undetermined r e- sults even s e ri ous damages of devices. be attention of these notices. furthermore, t his paragraph will also support useful sugge s tions during isp procedures. (1) if no more isp operation need s , the user must c lear ispen (chpcon.0 ) to zer o. it will make the system void to trigger isp unaware. furthermore, isp requires internal 22.1184 mhz rc oscillator running. if the e x- ternal clock source is chosen, disabling isp will stop internal 22.1184 mhz rc for sav ing power consumption. note that a write to ispen is ta protect ed . (2 ) if the loader code, which controls the isp procedure, l o cates in the external program memory or runs from the internal into the e x ternal , the isp will not work anymore and set error indicator ispf for data security.
n78e366 a data sheet publication release date: march 11, 2011 - 94 - revision : v2.0 (3 ) config byte s can be isp fully access ed only when loader code executing in ldrom. new config byte s other than cbs bit activate after all resets . new cbs bit act i vates after resets other than software reset. ( 4 ) when the lock bit ( config0 .1 ) is activated, isp reading, wri t ing, or erasing can s till be valid . ( 5 ) isp erasing or programming works from v dd 3.0 v through 5.5v. (6) aprom and ldrom can read itself through isp method. during isp progress, interrupts (if enabled) should be disabled temporally by clearing ea bit for i m- plement limitation. note that if the user would like to develop your own isp pr o gram, remember always erase and program config bytes at the last step for data security. 18.4 isp demo codes ;******************************************************************** ********** ; this code illustrates how to do aprom and config isp from ldrom. ; aprom are re - programmed by the code to output p1 as 55h and p2 as aah. ; the config3 is also updated to 6t mode. ; the user should p ut this code in ldrom and boot from ldrom. ;*********************** ********************************************* ********** page_erase_ap equ 00100010b byte_program_ap equ 00100001b byte_read_ap equ 00000000 b byte_read_config equ 11000000b byte_program_config equ 11100001b all_erase_config equ 11100010b org 0000h call enable_isp clr ea ;disable all interrupts call erase_ap ; e rase ap data call erase_ap_verify ; v erify erase ap data call program_ap ; p rogramming ap data call program_ap_verify ; v erify programmed ap data call read_config ; r ead b ack config3 call erase_config ; e rase config bytes call program_config ; p rogramming config3 with new data call program_config_verify ; v erify programmed config3 call disable_isp mov ta,#0aah ;ta protection mov ta,#55h ; anl chpcon,#0fdh ;bs = 0, reset to aprom mov ta,#0aah mov ta,#55h orl chpcon,#80h ; s oftware reset and reboot from aprom sjmp $
publication release date: march 11, 2011 - 95 - revision : v 2.0 ;******************************************************************** ; isp function ;************************************************** ****************** enable_isp: mov ta, #0aah ;chpcon is ta protected mov ta,#55h orl chpcon,#0000000 1b ;ispen = 1, enable isp mode ret disable_isp: mov ta, #0aah ;chpcon is ta protected mov ta,#55h anl chpcon,#11111110 b ;ispen = 0, disable isp m ode ret trigger_isp: mov ta,#0aah mov ta,#55h orl isptrg,#00000001b ;write '1' to ispgo to trigger isp process ret ;******************************************************************** ; isp ap function ;********************************************* *********************** erase_ap: mov ispcn,#page_erase_ap mov ispal,#00h mov r0,#00h erase_ap_loop: mov ispah,r0 call trigger_isp inc r0 cjne r0,#0,erase_ap_loop ret erase_ap_verify: mov ispcn,#byte_read_ap mov ispah,#00h mov ispal,#00h erase_a p_verify_loop: mov ispfd,#00h ; c lear ispfd data call trigger_isp mov a,ispfd cjne a,#0ffh,erase_ap_verify_error inc ispal mov a,ispal cjne a,#0,erase_ap_verify_loop inc ispah mov a,ispah cjne a,#0,erase_ap_verify_loop ret erase_ap_verify_error : call disable_isp mov p0,#00h sjmp $ program_ap: mov ispcn,#byte_program_ap mov ispah,#00h mov ispal,#00h mov dptr,#ap_code program_ap_loop: mov a,#0 movc a,@a+dptr mov ispfd,a
n78e366 a data sheet publication release date: march 11, 2011 - 96 - revision : v2.0 call trigger_isp inc dptr inc ispal mov a,ispal cjne a,#8,progr am_ap_loop ret program_ap_verify: mov ispcn,#byte_read_ap mov ispah,#00h mov ispal,#00h mov dptr,#ap_code program_ap_verify_loop: mov ispfd,#00h ; c lear ispfd data call trigger_isp mov a,#0 movc a,@a+dptr mov b,a mov a,ispfd cjne a,b,program_a p_verify_error inc dptr inc ispal mov a,ispal cjne a,#8,program_ap_verify_loop ret program_ap_verify_error: call disable_isp mov p0,#00h sjmp $ ;******************************************************************** ; isp config function ;********* *********************************************************** erase_config: mov ispcn,#all_erase_config mov ispah,#00h call trigger_isp ret read_config: mov ispcn,#byte_read_config mov ispah,#00h mov ispal,#03h call trigger_isp mov a,ispfd ret pro gram_config: mov ispcn,#byte_program_config mov ispah,#00h mov ispal,#03h anl a,#10111111b mov ispfd,a ; s witch to 6t mode mov r0,a ;temp data call trigger_isp ret program_config_verify: mov ispcn,#byte_read_config mov ispah,#00h mov ispal,# 03h mov ispfd,#00h ; c lear ispfd data call trigger_isp mov b,r0 mov a,ispfd
publication release date: march 11, 2011 - 97 - revision : v 2.0 cjne a,b,program_config_verify_error ret program_config_verify_error: call disable_isp mov p0,#00h sjmp $ ;*************************************************************** ***** ; aprom code ;******************************************************************** ap_code: db 75h, 90h, 55h ;opcode s of "mov p1,#55h" db 75h,0a0h,0aah ;opcode s of "mov p2,#0aah" db 80h,0feh ;opcode s of "sjmp $ " end
n78e366 a data sheet publication release date: march 11, 2011 - 98 - revision : v2.0 19. power saving modes N78E366A has several features that help the user to control the power consumption of the device. the power saved features have the power down mode and the i dle mode of operation. for a stable current consum p tion, states of p0 pin s should be taken care of. p0 should be set as 0 if floating or external pull - downs exist. or p0 should be set as 1 if external pull - ups exist or internal pull - ups are enabled by p0up ( p0or.0 ). in system power saving modes, the watchdog timer should be spe cially taken care. the hardware will clear wdt counter aut o matically after entering into or being woken - up from idle or power down mode. it prevents unconscious system reset. pcon C power control 7 6 5 4 3 2 1 0 smod - - pof gf1 gf0 pd idl r/w - - r/w r/ w r/w r/w r/w address: 87h reset value: s ee table 6 C 2 . N78E366A s fr description s and reset value s b it name description 1 pd power down mode. setting this bit puts mcu into power down mode. under this mode, both c pu and peripheral clocks stop and program counter (pc) suspends. it provides the lowest power consumption. after cpu is woken up from power down, this bit will be a u- tomatically cleared via hardware and the program continue executing the interrupt service r outine (isr) of the very interrupt source that woke the sy s tem up before. after return from the isr, the device continues execution at the instruction which follows the instruction that put the system into power down mode. note that if idl bit and pd bit a re set simultaneously, the mcu will enter into power down mode. then it does not go to idle mode after exiting power down. 0 idl idle mode. setting this bit puts mcu into idle mode. under this mode, the cpu clock stops and program counter (pc) suspends. a fter cpu is woken up from idle, this bit will be automatically cleared via hardware and the program continue executing the isr of the very interrupt source that woke the system up before. after return from the isr, the device continues execution at the ins truction which follows the i n- struction that put the system into idle mode. 19.1 idle mode idle mode suspends cpu processing by holding the program c ounter. no program code are fetched and run in idle mode. this fo rces the cpu state to be frozen . t he program c o unter (pc) , the stack pointer (sp) , the program status word (psw) , the accum u lator (acc) , and the other registers hold their contents during idle mode . the port pins hold the logical states they had at the time idle was activated. generally, it saves consi d- erable power of typical ha lf of the full operating power.
publication release date: march 11, 2011 - 99 - revision : v 2.0 since the clock provided for peripheral function logic circuit like timer or serial port still remain in idle mode , the cpu can be released from the idle mode using any of the interrupt sources if e n abled. the user can put the device into i dle mode by writing 1 to the bit idl ( pcon.0 ) . the instruction that sets the idl bit is the last i n- struction that will be executed before the device goes into idle m ode. the idle mode can be terminated in two ways . first, any interrupt if enabled will cause an exit. this will aut o- matically clear the i dl bit, terminate the idle mode , and the i nterrupt s ervice r outine (isr) will be executed. after using the reti instruction to jump out of the isr, execution of the pr ogram will be the one following the instruction which put the cpu into idle mode. the second way to terminate the idle mode is wit h any reset ot h- er than software reset. r e member that if watchdog reset is used to exit idle mode, the widpd ( wdcon .4) needs to be set 1 to let watchdog timer keep running in idle mode. 19.2 power d own mode power down mode is the lowest power state that N78E366A can enter. it remain the power consumption as a a level. this is achieved by stopping the system clock no matter internal rc clock or external crystal . both of cpu and peripheral functions like timers or uart are frozen . flash memory stop s . all activity is completely stopped and the power consumption is reduced to the lowest poss i ble value. the device can be put into power do wn mode by writing 1 to bit pd ( pcon.1 ) . the instruction that does this action will be the last instruction to be executed before the device goes into power down mode. in the power down mode, ram maintains its co n- tent. t he port pins output the values held by their respective . there are two ways to exit N78E366A from the power down mode . first is with all resets except software r e- set. brown - out reset will also wake up cpu from power down mode. be s ure that brown - out detection is en a- bled before the system ent ers into power down. but for a principle of least power consumption, it is u n common to enable brown - out detection in power down mode. it is not a recommended application. of course the rst pin reset and power - on reset will remove the power down status. aft er rst pin reset or power - on reset. the cpu is in i tialized and start executing program code from the beginning. N78E366A can be woken up from the power down mode by forcing an external interrupt pin activated, provi d- ing the corresponding i n terrupt enabled and the global enable ea bit (ie.7) is set . if these conditions are met, then the trigger on the external pin will asynchronously restart the system clock . then device executes the i n- terrupt service routine (isr) for the corresponding external interrupt. a fter the isr is completed, the program ex e cution returns to the instruction after the one which put the device into power down mode and continues. the power down waking - up t imer interrupt is also allowed to wake up power down. it is usually applied as a lo ng period timer to mon i toring a static behavior. for detail application, please see section 12.2 applications of power down waking - up timer on page 49 . brown - out interrupt is another source to wake up cpu from power down. as mentioned before the user will endure the large current of brown - out detection c ircui t. it is not a typ i cal application .
n78e366 a data sheet publication release date: march 11, 2011 - 100 - revision : v2.0 20. clock system N78E366A provide s three options of the system clock source . it is configure d by fosc ( config3 .1) . it switches the system clock from crystal/ resonator , on - chip rc oscillator , or e xternal c lock from xtal1 pin. N78E366A embed s an on - chip rc oscillator of 22 .1184 mhz /11.0592mhz selected by conf ig setting, factory trimmed to 1 % at room temperature . if the external clock source is f ro m t he c rystal , the frequency support s from 4mhz to 40 mhz. figure 20 C 1 . clock system bl ock diagram 20.1 12t/ 6t mode the clock for the entire circuit and peripherals is normally divided by 2 before being used by the cpu core and peripherals. in 6t mode, this divider is bypassed. this facility provides the same perfor m ance when operating with a 24m hz oscillator in 12t mode as with a 12mhz oscillator in 6t mode , for example. the user may choose a divided - by - 2 frequency oscillator in 6t mode to reach the same pe r formance as in the original 12t mode. therefore, it reduces emi and power consumption if 6 t mode is used . f c p u o s c i l l a t i n g c i r c u i t i n t e r n a l r c o s c i l l a t o r ( 2 2 . 1 1 8 4 m h z ) x t a l 1 x t a l 2 e x t e r n a l c r y s t a l 1 / 2 c f o s c ( c o n f i g 3 . 1 ) i n o s c f s ( c o n f i g 3 . 3 ) i s p e n ( c h p c o n . 0 ) 1 : 1 2 t m o d e 0 : 6 t m o d e 1 : t u r n o n 0 : t u r n o f f f o s c 1 0 1 0 1 / 2 0 1 8 0 c 5 1 c p u t i m e r s s e r i a l p o r t ( u a r t ) s p i p w m w a t c h d o g t i m e r b r o w n - o u t d e t e c t i o n i n t e r n a l r c o s c i l l a t o r ( ~ 1 0 k h z ) f p r i p h l p b o d ( p m c . 2 ) i s p e n 6 t ( c o n f i g 3 . 6 ) f l a s h p o w e r d o w n w a k i n g - u p t i m e r f i h r c f i l r c
publication release date: march 11, 2011 - 101 - revision : v 2.0 config3 7 6 5 4 3 2 1 0 cwdten en6t rog ckf in t oscfs - fosc - r/w r/w r/w r/w r/w - r/w - unprogrammed value: 1111 1111 b b it name description 6 en6t enable 6t mode. this bit switches mcu between 12t and 6t mode. see figure 20 C 1 . clock system bl ock diagram for definitions in details. 1 = mcu runs at 12t mode. each machine - cycle is equal to 12 clocks of sy s tem oscillator. the operating mode is the same as a standard 8051 mcu. (f cpu and f periph is a half of f osc .) 0 = mcu runs at 6t mode. each machine - cycle is equal to 6 clocks of system oscillator. this mode doubles the whole chip operation compared with the standard 8051 . (f cpu and f periph is equal to f osc .) 5 rog reducing oscillator gain. 1 = us e normal gain for crystal oscillating. the crystal frequency can be up to 40 mhz. 0 = use reduced gain for crystal oscillating. the crystal frequency should be lower than 24mhz. in reduced gain mode, it will also help to decrease emi. 4 ckf clock filter en able. 1 = enable clock filter. it increases noise immun ity and emc capa c ity. 0 = disable clock filter . 3 intoscfs internal rc oscillator frequency select. 1 = select 22.1184mhz as the system clock if internal rc oscillator mode is used. it b ypass es the di vided - by - 2 path of internal oscillator to select 22.1184mhz output as the system clock source. 0 = select 11.0592mhz as the system clock if internal rc oscillator mode is used. the internal rc divided - by - 2 path is selected. the internal oscillator is equiv alent to 11.0592mhz output used as the system clock. 2 - reserved. 1 fosc o scillator selection bit. this bit selects the source of the system clock. 1 = crystal, resonator, or external clock input. 0 = internal rc oscillator. 0 - reserved.
n78e366 a data sheet publication release date: march 11, 2011 - 102 - revision : v2.0 chpcon C chi p control ( ta protected ) 7 6 5 4 3 2 1 0 swrst ispf ldue n x ram en - - bs ispen w r /w r/w r/w - - r/w r /w address: 9fh reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it name description 0 ispen isp enable. 0 = enable isp function. 1 = disable isp function. to enable isp function will start the internal 22.1184 mhz rc oscillator for timing control. to clear ispen should always be the last instruction after isp o p eration in order to stop inte rnal rc for reducing power consumption. p mc C power monitoring control ( ta protected ) 7 6 5 4 3 2 1 0 boden - - borst bof lpbod - bos r/w - - r/w r/w r/w - r address: ac h reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it name description 3 lpbod low power brown - out detection enable. this bit switches the brown - out detection into a power saving mode. this bit is only effective while boden = 1. 0 = disable brown - out power saving mode. bro wn - out detection operates in no r- mal mode if enabled . the detection is always on. 1 = enable brown - out power saving mode. brown - out detection o p erates in power saving mode if enabled . enable this bit will switch on internal 10khz rc to be a timer for about 12.8ms interval of detection. the discrete detection will save much power but the hysteresis feature disappears . 20.2 external clock source the system clock source can be from external xtal1 pin . when xtal1 pin is driven by an external clock source, xtal2 shou ld be left floating. xtal1 and xtal2 are the input and output, respe c tively, of an internal inverting amplifier. a crystal or resonator can be used by connecting between xtal1 and xtal2 pins. the cry s tal or resonator frequency from 4m hz up to 40 mhz is allo wed . while an external crystal or resonator is used, rog ( config3 . 5 ) is for half gain selection of the inverting amplifier. when the system clock is lower than 24mhz and rog is configured as a 0, the sy s tem emi can be reduced. ckf ( config3 . 4 ) is the contro l bit of clock fi l ter circuit of xtal1 input pin . 20.3 on - c hip rc oscillator the o n - c hip rc o scillator is enabled while fosc (config3.1) is 0. setting intoscfs ( config3 . 3 ) logic 0 will switch to a divided - by - 2 path. note that a 0.1f capacitor is recommended to be added on xtal1 pin to gain the more precise frequency of the internal rc oscillator frequency if it is selected as the system clock source.
publication release date: march 11, 2011 - 103 - revision : v 2.0 21. power monitoring in order to prevent incorrect execution during power up and power drop, N78E366A provide s three power mo n- itor function s, p ower - o n d etect ion , brown - out d etect ion , and low power detection . 21.1 power - o n detect ion the p ower - o n d etect ion function is design ed for detect ing power up after power voltage reaches to a level about 2.0v where the system can work . a fter power - on detect ed , the po f (pcon. 4) will be set 1 to indicate a cold reset, a power - on reset co m plete. the p of flag can be cleared via software. 21.2 brown - out detect ion the other power monitoring function, brown - out d etection circuit is for monitoring the v dd level during exec u- tion. the re are four programmable brown - out trigger levels available for wide voltage appl i cations . t h e four nominal levels are 2. 2 v, 2. 7 v, 3.8v , and 4.5v selected via setting c bov [ 1 : 0 ] i n config2 . when v dd drops to the selected brow n - out trigger level (v bo d ), the brown - out detection logic will either reset the cpu or request a brown - out interrupt. the use r may determine brown - out reset or interrupt enable according to different applic a- tion system s . the brown - out detect ion will reques t the interrupt while v dd drops below v bod while borst (pmc.4) is 0. in this case, bof (p m c.3) will set as a 1. after the user cleared this flag whereas v dd remains below v bo d , bof will not set again. bof just acknowledge the user a power drop occurs. the bof will set 1 after v dd goes higher than v bo d to indicate a power resuming . the brown - out circuit provide s an useful status indicator bos (pmc.0) , which is helpful to tell a brown - out event or power resuming event occurrence . if bors t bit is set, this wil l enable brown - out reset function. after a brown - out reset, borf (rsr.2) will set 1 via har d ware . it will not be altered by reset other than power - on . software can clear this bit . v bod has a hy s teresis of 2 0~ 20 0mv. the brown - out detection circuit also prov ides a low power brown - out detection m ode for power saving. when lp bod is set 1 , the brown - out detection repeat ed ly senses the power voltage about e very 12.8ms . for the interval counting, the internal 10khz rc oscillator will turn on in brown - out low power mode. note that the hy s- teresis feature will disappear in low power brown - out detection mode.
n78e366 a data sheet publication release date: march 11, 2011 - 104 - revision : v2.0 figure 21 C 1 . brown - out detect ion block di a gram fi g ure 21 C 2 . power monitoring timing diagram c b o v 1 c b o v 0 b o r s t c h i p r e s e t b o f b r o w n o u t i n t e r r u p t b r o w n o u t d e t e c t i o n 1 : o n 0 : o f f v d d + - 4 v b o d t h r e s h o l d v o l t a g e s e l e c t b o d e n 1 0 a l w a y s o n o n / o f f i n t e r v a l c o u n t e r i n t e r n a l 1 0 k h z r c l p b o d o r b o s b o r f v b o d n v p o r v s s v d d p o f b o f [ 2 ] r e s e t s t a t u s p o w e r [ 1 ] p o f a n d b o f a r e b o t h c l e a r e d b y s o f t w a r e . [ 2 ] b r o w n - o u t r e s e t i s d i s a b l e d . w h i l e t h e w h o l e b r o w n - o u t d e t e c t i o n c i r c u i t d i s a b l e d , b o s a n d b o f w i l l k e e p 0 . [ 3 ] t b o r ~ = 8 m s p o w e r - o n b r o w n - o u t e v e n t p o w e r f a i l e v e n t 1 = r e s e t s t a t e 0 = f r e e r u n n i n g [ 1 ] [ 1 ] - - - - - - b r o w n o u t r e s e t d i s a b l e d b r o w n o u t r e s e t e n a b l e d t b o r t b o r [ 3 ] b o s [ 2 ]
publication release date: march 11, 2011 - 105 - revision : v 2.0 config2 7 6 5 4 3 2 1 0 cboden cbov1 cbov0 cborst - - - - r/w r/w r/w r/w - - - - unprogrammed value: 1111 1111 b b it name description 7 cboden config brown - out detec t enable . 1 = enable brown - out detection . 0 = disable brown - out detection . 6 cbov1 config brown - out voltage select. these two bits select one of four brown - out voltage level. cbov 1 cbov 0 brown - out vol t age 1 1 2.2 v 1 0 2.7 v 0 1 3.8 v 0 0 4.5 v 5 cbov0 4 cborst config brown - out reset enable. this bit decides if a brown - out reset is caused after a brown - out event. 1 = enable brown - out reset when v dd drops below v bod . 0 = disable brown - out reset when v dd drops below v bod . p mc C power monitoring control ( ta protected ) 7 6 5 4 3 2 1 0 boden [1] - - borst [1] bof lpbod - bos r/w - - r/w r/w r/w - r address: a c h reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it name description 7 boden bro wn - out detect enable . 0 = disable brown - out detection . 1 = enable brown - out detection . 6:5 - reserved. 4 borst brown - out reset enable. this bit decides if a brown - out reset is caused after a brown - out event. 0 = disable brown - out reset when v dd drops bel ow v bod . 1 = enable brown - out reset when v dd drops below v bod . 3 bof brown - out flag. this flag will be set as a logic 1 via hardware after a v dd dropping below or rising above v bod event occurs. if both ebod ( eie .2) and ea (ie.7) are set, a brown - out inte rrupt requirement will be gene r ated. this bit must be cleared via software. 3 lpbod low power brown - out detection enable. this bit switches the brown - out detection into a power saving mode. this bit is only effective while boden = 1. 0 = disable brown - out power saving mode. brown - out detection operates in no r- mal mode if enabled. the d e tection is always on. 1 = enable brown - out power saving mode. brown - out detection o p erates in power saving mode if enabled. enable this bit will switch on internal 10khz rc t o be a timer for about 12.8ms interval of detection. the discrete detection will save much power but the hysteresis feature disappears .
n78e366 a data sheet publication release date: march 11, 2011 - 106 - revision : v2.0 b it name description 1 - reserved. 0 bos brown - out status. this bit indicates the v dd voltage level comparing with v bod while brown - out ci r- cuit is enabled. it is helpful to tell a brown - out event or power resuming event o c- currence . t his bit is read - only and keeps 0 if brown - out detection is not e n abled. 0 = v dd voltage level is higher than v bod . 1 = v dd voltage level is lower than v bod . [1] boden and borst will be directly loaded from config2 bit 7 and bit 4 a fter all resets . table 21 C 1 . bof r eset v alue reset source cboden (config2.7) cborst (config2.4) v dd stable level bof brown - out reset 1 1 > v bod always 1 other resets 1 1 > v bod always 1 1 0 > v bod 1 1 0 < v bod 0 0 x x 0 note that if bof is 1 after chip reset, it is strongly recommended to initialize the user s program by clearing bof. pcon C power control 7 6 5 4 3 2 1 0 smod - - pof gf1 gf0 pd idl r/w - - r/w r/w r/w r/w r/w address: 87h reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it name description 4 pof power - on reset flag. this bit will be set as 1 after a power - on reset. it indicate s a cold reset, a power - on reset complete. this bit remains its value after any other resets. this flag is recommended to be cleared via sof t ware.
publication release date: march 11, 2011 - 107 - revision : v 2.0 22. reset conditions N78E366A has several options to place device in reset conditio n. it also offers the software flags to indicate the source, which cause s a reset. in general, most sfrs go to their reset value irrespective of the reset cond i- tion, but there are several reset source indicating flags whose state depends on the s ource of r eset. the user can read back these flags to determine the cause of reset using software. t here are 5 ways of putting the d e- vice into reset state. they are power - on reset, rst pin reset , software reset, watchdog timer reset , and brown - out reset. rsr C reset status register 7 6 5 4 3 2 1 0 - - - - - borf - swrf - - - - - r/w - r/w address: 96 h reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it name description 7:3 - reserved. 2 borf brown - out reset flag. when the mcu is reset by brown - out reset, this bit will be set via hardware. this flag is recommended to be cleared via sof t ware. 1 - reserved. 0 swrf software reset flag. when the mcu is reset via software reset, this bit will be set via hardware. this flag is recommended to be cleared via software. pcon C power control 7 6 5 4 3 2 1 0 smod - - pof gf1 gf0 pd idl r/w - - r/w r/w r/w r/w r/w address: 87h reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it name description 4 pof power - on reset flag. this bit will be set as 1 after a power - on reset. it indicate s a cold reset, a power - on reset complete. this bit remains its value after any other resets. this flag is recommen ded to be cleared via sof t ware.
n78e366 a data sheet publication release date: march 11, 2011 - 108 - revision : v2.0 wdcon C watchdog timer control ( ta protected ) 7 6 5 4 3 2 1 0 wdten wdclr - widpd wdtrf wps2 wps1 wps0 r/w w - r/w r/w r/w r/w r/w address: aah reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it name description 3 wdtrf watchdog timer reset flag. when the cpu is reset by watchdog timer time - out event, this bit will be set via hardware. this flag is recommended to be cleared via software. 22.1 power - o n reset n7 8e366a incorporate an internal voltage reference . during a power - on process of rising power supply voltage v dd , this voltage reference will hold the cpu in power - on reset mode when v dd is lower than t he voltage refe r- ence threshold. this design make s cpu no t access program flash while the v dd is not adequate performing the flash reading. if a und e termined operating code is read from the program flash and executed, this will put cpu and even the whole system in to a erroneous state. after a while, v dd rises a bove the reference threshold where the system can work , the selected oscillator will star t and then program code will be executed from 0000h. at the same t ime, a power - on flag pof (pcon.4) will be set 1 to indicate a cold reset, a power - on r e- set complete. note that the contents of internal ram will be undetermined after a power - on. the user is re c- ommended to give initial value s for the ram block. t he pof is recommended to be cleared to 0 via software in order to check if a cold reset or warm reset pe r- formed after the next r e set occurs. if a cold reset caused by power off and on, pof will be set 1 again. if the reset is a warm reset caused by other reset sources, pof will remain 0. the user may take a different course to check other reset flag s and deal with the warm reset event . 22.2 brown - out reset brown - out d etection circuit is for monitoring the v dd level during execution. when v dd drops to the selected brown - out trigger level (v bo d ), the brown - out detection logic will reset the cpu if borst (pmc.4) setting 1. after a brown - out reset, borf (rsr.2) will set 1 via hardware. it will not be altered by any reset other than a power - on reset. software can clear this bit. 22.3 rst p in reset the hardware reset input is rst pin which is the input with a schmitt trigger. a hard ware reset is accomplished by holding t he rst pin high for at least two machine - cycle s to ensure detection of a valid hardware reset si g-
publication release date: march 11, 2011 - 109 - revision : v 2.0 nal . the reset circuitry then synchronously applies the internal reset signal. thus the reset is a synchr o nous operation and requires the clock to be running to cause an e x ternal reset. once the device is in reset condition, it will remain so as long as rst pin is 1 . a fter the rst high is remov ed, the cpu will exit the reset state with in two machine - cycle s and begin code e xecuti ng from address 0000 h . there is no flag associated with the rst pin reset condit ion. however since the other reset sources have flags, the e x ternal reset can be considered a s the default reset if those reset flags are cleared. if a rst pin reset appl ie s while cpu is in power down mode, the way to trigger a hardware reset is slightly different. since the power down mode stops system clock, the reset signal will asynchronously cause the sy s- tem clock resuming . after the system clock is stable, cpu will e nter into the reset state. 22.4 watchdog timer reset the watchdog t imer is a free running timer with programmable time - out intervals. the user can clear the watchdog timer at any time, causing it to restart the count. when the selected time - out occurs, the watc hdog timer will reset the system directly . the reset condition is maintained via hardware for two machine - cycle s. a f ter the reset is removed, the device will begin execution from 0000 h . once a reset due to watchdog timer occurs the watchdog timer reset fla g wdtrf (wdcon. 3 ) will be set . this bit keep s unchanged after any reset other than a power - on reset. the user may clear wdtrf via sof t- ware. 22.5 software reset N78E366A is enhanced with a software reset. this allows the program code to reset the whole system in sof t- ware approach. it is quite useful in the end of an isp progress. for example , if an ldrom updating aprom isp finishes and the code in aprom is correctly updated, a software reset can be asserted to reboot cpu from the aprom in order to check the resul t of the updated aprom program code immediately. writing 1 to swrst (chpcon.7) will trigger a software reset. note that this bit is timed access protection. see demo code below. after a software reset the swrf (rsr.0) will be automatically set via hardware . this bit will be pr e- served its value after all resets except power - on reset. swrf can also be cleared via software.
n78e366 a data sheet publication release date: march 11, 2011 - 110 - revision : v2.0 chpcon C chip control ( ta protected ) 7 6 5 4 3 2 1 0 swrst ispf ldue n xramen - - bs ispen w r /w r/w r/w - - r/w r /w address: 9fh reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it name description 7 swrst software reset. to set this bit as a logic 1 will cause a software reset. it will automatically be cleared via har d ware after reset in finished. the software demo code are listed below. m ov ta,#0aah ;ta protection. m ov ta,#55h ; anl chpcon,#0fdh ;bs = 0, reset to aprom. m ov ta,#0aah m ov ta,#55h orl chpcon,# 8 0 h ;software reset 22.6 boot select figure 22 C 1 . boot selecting diagram N78E366A provides user s a flexible boot selection for variant application. the sfr bit bs in chpcon.1 d e- termines cpu boot ing from ap rom or ld rom after any so urce of reset . if reset occurs and bs is 0 , cpu will re boot from ap prom . else, the cpu will re boot from ld rom . r s t - p i n r e s e t b r o w n o u t r e s e t s o f t w a r e r e s e t p o w e r - o n r e s e t l o a d r e s e t a n d b o o t f r o m l d r o m r e s e t a n d b o o t f r o m a p r o m c o n f i g 0 . 7 c h p c o n . 1 w a t c h g o d t i m e r r e s e t b s c b s b s = 0 b s = 1
publication release date: march 11, 2011 - 111 - revision : v 2.0 config0 7 6 5 4 3 2 1 0 cbs - - - - movcl lock - r /w - - - - r/w r/w - unprogrammed value: 1111 1111b b it name description 7 cbs config boot select. this bit defines from which block mcu boots after all resets except software r e set . 1 = mcu will boot from aprom after all resets except software r e set . 0 = mcu will boot from ldrom after all resets except software r e set . chpcon C chip control ( t a protected ) 7 6 5 4 3 2 1 0 swrst ispf ldue n xram en - - bs [1] ispen w r /w r/w r/w - - r/w r /w address: 9fh reset value: see table 6 C 2 . N78E366A s fr description s and reset value s b it name description 1 bs boot select. there are different meanings of writing to or reading from this bit. writing : it defines from which block mcu boots after all resets . 0 = the next re booting will be from aprom. 1 = the next re booting will be from ldrom. reading : it indicates from which block mcu booted after previous reset. 0 = the previous re booting is from aprom. 1 = the previous re booting is from ldrom. [1] note that this bit is initialized by being loaded from the inverted value of cbs bit in config0.7 at all resets except sof t- ware reset . it keeps u n changed after software reset. note that after the cpu is released from all reset state, the hardware will always check the bs bit i n- stead of the cbs bit to determine from aprom or ldrom that the device re boots. 22.7 reset state the r eset state does not affect the on - chip ram. the data in the ram will be preserved during the reset. note that t he ram contents may be lost if the v dd falls below approx i mately 1.2 v . t his is the minimum voltage level required for ram data retention . therefo re , after the power - on reset the ram contents will be in determinate. during a power fa il condi tion . if the power falls below the data retention minimum voltage , the ram contents will also los e . after a reset, most of sfrs go to their initial value s except bits which are affected by different reset events. see the note s of table 6 C 2 . N78E366A s fr description s and reset value s . the program counter is forced to
n78e366 a data sheet publication release date: march 11, 2011 - 112 - revision : v2.0 0000 h and held as long as the reset condition is applied. note that t he s tack p ointer is also reset to 07 h , therefore the stack contents may be e f fectively lost during the reset event even though the ram contents are not altered. after a r eset, i nterrupts and timers are disabled. the i/o port sfrs have ff h writte n into them which puts the port pins in a high state.
publication release date: march 11, 2011 - 113 - revision : v 2.0 23. auxiliary features ale is used to enable the address latch that separates the address from the data on port 0. ale runs at 1/6 of the fosc in 12t mode . an ale pulse is omitted always. the u ser can turn ale signal off via setting ale off to reduce emi. aleoff enable will just make ale activating during external memory access through a movc or movx i n struction . ale will stay high in other conditions. auxr C auxiliary register 7 6 5 4 3 2 1 0 - - - - - - - aleoff - - - - - - - r /w address: 8eh reset value: 0000 0000b b it name description 7:1 - reserved. 0 aleoff ale output off. 0 = ale is emitted always. 1 = ale is off normally and active only during external memory a c cess through a movx or movc instruct ion.
n78e366 a data sheet publication release date: march 11, 2011 - 114 - revision : v2.0 24. config bytes N78E366A has several hardware configuration bytes , called config bytes, those are used to configure the hardware option s such as the security bits, system clock source , and so on. these hardware options can be re - configured through the programmer/writer or isp modes. N78E366A has three config bytes those are config0, 2 and 3 . several functions which are defined by certain config bits are also available to be re - configured by certain sfr bits. therefore, there is a need to load such confi g bits into respective sfr bits. such loading will occurs after reset s . (software reset will reload all config bytes except cbs bit in config0 .) these sfr bits can be continuously controlled via user ? s software. note that config bits marked as " - " should a lways keep unprogrammed. config0 7 6 5 4 3 2 1 0 cbs - - - - movcl lock - r /w - - - - r/w r/w - unprogrammed value: 1111 1111 b b it name description 7 cbs config boot select. this bit defines from which block mcu boots after all resets except software r e set. 1 = mcu will boot from aprom after all resets except software r e set. 0 = mcu will boot from ldrom after all resets except software r e set. 6 :3 - reserved. 2 movcl movc lock enable. this bit determines movc instruction is inhibited or not when readi ng internal program memory by executing on the external pr o gram memory. this mechanism is for data security. 1 = movc has no restriction. 0 = movc is restricted . the external program memory code is inhibited to read i n ternal aprom or ldrom contents through movc instruction. 1 lock chip lock enable. 1 = chip is unlocked. all of aprom and ldrom are not locked . their contents can be read out through a parallel progra m mer/writer. 0 = chip is locked. aprom and ldrom are locked. their co n tents read through paral lel programmer/writer will become ff h. note that config bytes are always un locked and can be read. hence, once the chip is locked, the config bytes cannot be erased or programmed individually . the only way to disable chip lock is to use the whole chip eras e mode . however, all data within aprom, ldrom, and other config bits will be erased when this procedure is ex e cuted. if the chip is locked, it does not alter the isp function. 0 - reserved.
publication release date: march 11, 2011 - 115 - revision : v 2.0 figure 24 C 1 . config0 reset reload ing except software r e set config2 7 6 5 4 3 2 1 0 cboden cbov1 cbov0 cborst - - - - r/w r/w r/w r/w - - - - unprogrammed value: 1111 1111 b b it name description 7 cboden config brown - out detect enable . 1 = enable brown - out detection . 0 = disable brown - out detection . 6 cbov1 config brown - out voltage select. these two bits select one of four brown - out voltage level. cbov 1 cbov 0 brown - out vol t age 1 1 2.2 v 1 0 2.7 v 0 1 3.8 v 0 0 4.5 v 5 cbov0 4 cborst config brown - out reset enable. this bit decides if a brown - out reset is caused after a brown - out event. 1 = enable brown - out reset when v dd drops below v bod . 0 = disable brown - out reset when v dd drops below v bod . 3:0 - reserved. figure 24 C 2 . config2 reset reload ing c h p c o n c o n f i g 0 c b s 7 - 6 - 5 - 4 - 3 m o v c l 2 l o c k 1 - 0 s w r s t 7 i s p f 6 l d u e 5 a u x r a m 4 - 3 - 2 b s 1 i s p e n 0 p m c c o n f i g 2 c b o d e n 7 c b o v 1 6 c b o v 0 5 c b o r s t 4 - 3 - 2 - 1 - 0 b o d e n 7 - 6 - 5 b o r s t 4 b o f 3 l p b o d 2 - 1 b o s 0
n78e366 a data sheet publication release date: march 11, 2011 - 116 - revision : v2.0 config3 7 6 5 4 3 2 1 0 cwdten en6t rog ckf in t oscfs - fosc - r/w r/w r/w r/w r/w - r/w - unprogrammed value: 1111 1111 b b it name description 7 cwdten config watchdog timer enable . 1 = dis able watchdog timer after all resets . 0 = en able watchdog timer after all resets . 6 en6t enable 6t mode. this bit switches mcu between 12t and 6t mode. see figure 20 C 1 . clock system bl ock diagram for definitions in details. 1 = mcu runs at 12t mode. each machine - cycle is equal to 12 clocks of system o s cillator. the operating mode is the same as a standard 8051 mcu. (f cpu and f periph is a half of f osc .) 0 = mcu runs at 6t mode. each mac hine - cycle is equal to 6 clocks of system osci l- lator. this mode doubles the whole chip operation compared with the standard 8051 . (f cpu and f periph is equal to f osc .) 5 rog reducing oscillator gain. 1 = use normal gain for crystal oscillating. the frequen cy can be up to 40 mhz. 0 = use reduced gain for crystal oscillating. the frequency should be lower than 24mhz. in reduced gain mode, it will also help to decrease emi. 4 ckf clock filter enable. 1 = enable clock filter. it increases noise immun ity and emc capa c ity. 0 = disable clock filter . note that the clock filter should be always disabled if the crystal frequency is above 24mhz. 3 intoscfs internal rc oscillator frequency select. 1 = select 22.1184mhz as the system clock if internal rc oscillator mod e is used. it bypasses the divided - by - 2 path of internal oscillator to select 22.1184mhz output as the system clock source. 0 = select 11.0592mhz as the system clock if internal rc oscillator mode is used. the internal rc divided - by - 2 path is selected. the internal oscillator is equiv a- lent to 11.0592mhz output used as the system clock. 2 - reserved. 1 fosc o scillator selection bit. this bit selects the source of the system clock. 1 = crystal, resonator, or external clock input. 0 = internal rc oscillator. 0 - reserved. figure 24 C 3 . config3 reset reload ing w d c o n c o n f i g 3 c w d t e n 7 e n 6 t 6 r o g 5 c k f 4 i n t o s c f s 3 - 2 f o s c 1 - 0 w d t e n 7 w d c l r 6 - 5 w i d p d 4 w d t r f 3 w p s 2 2 w p s 1 1 w p s 0 0
publication release date: march 11, 2011 - 117 - revision : v 2.0 25. instruction set N78E366A execute s all the instructions of the standard 8051 family. all instructions are coded wi thin an 8 - bit field called an opcode . this single byte must be fetched from program memory . the opcode is d e coded by the cpu. it determines what action the microcontroller will take and whether more operation data is needed from memory. if no other data is needed , then only one byte was required. thus the instruction is called a one byte instruction. in some cases, more data is needed. these will be two or three byte instructions. table 25 C 1 lists all instructions in details . note of the i n str uction set and addressing modes are shown below. rn (n = 0~ 7) register r0 ~ r7 of the currently selected register bank. direct 8 - bit internal data location ? s address. this could be an internal data ram location (0 ~ 127) or a sfr (e.g . , i/ o p o r t, control register, status register, etc. (128 ~ 255)) . @ri (i = 0, 1) 8 - bit internal data ram location (0 ~ 255) addressed indirectly through register r0 or r1. #data 8 - bit constant included in the instru c tion. #data16 16 - bit constant include d in the instruction. addr16 16 - bit destination address. used by lcall and ljmp. a branch can be anywhere within the 64k - byte program memory address space. addr11 11 - bit destination address. used by acall and ajmp. the branch will be within the s ame 2k - byte page of program memory as the first byte of the following instruction. rel signed (2 ? s complement) 8 - bit offset byte. used by sjmp and all co n ditional branches. r ange is - 128 to +127 bytes relative to first byte of the following instructio n. bit direct addressed bit in internal data ram or sfr. table 25 C 1 . instruction set for N78E366A instruction opcode bytes clock c y cles in 12t m ode clock c y cles in 6t mode nop 00 1 12 6 add a, r n 28 ~ 2f 1 12 6 add a, @ri 26 , 27 1 12 6 add a, direct 25 2 12 6 add a, #data 24 2 12 6 addc a, r n 38 ~ 3f 1 12 6 addc a, @ri 36 , 37 1 12 6 addc a, direct 35 2 12 6 addc a, #data 34 2 12 6 subb a, r n 98 ~ 9f 1 12 6 subb a, @ri 96 , 97 1 12 6 subb a, direct 95 2 12 6 subb a, #data 94 2 12 6
n78e366 a data sheet publication release date: march 11, 2011 - 118 - revision : v2.0 table 25 C 1 . instruction set for N78E366A instruction opcode bytes clock c y cles in 12t m ode clock c y cles in 6t mode inc a 04 1 12 6 inc r n 08 ~ 0f 1 12 6 inc @ri 06 , 07 1 12 6 inc direct 05 2 12 6 inc dptr a3 1 24 12 dec a 14 1 12 6 dec r n 18 ~ 1f 1 12 6 dec @ri 16 , 17 1 12 6 dec direct 15 2 12 6 mul ab a4 1 48 24 div ab 84 1 48 24 da a d4 1 12 6 anl a, r n 58 ~ 5f 1 12 6 anl a, @ri 56 , 57 1 12 6 anl a, direct 55 2 12 6 anl a, #data 54 2 12 6 anl direct, a 52 2 12 6 anl direct, #data 53 3 24 12 orl a, r n 48 ~ 4f 1 12 6 orl a, @ri 46 , 47 1 12 6 orl a, direct 45 2 12 6 orl a, #dat a 44 2 12 6 orl direct, a 42 2 12 6 orl direct, #data 43 3 24 12 xrl a, r n 68 ~ 6f 1 12 6 xrl a, @ri 66 , 67 1 12 6 xrl a, direct 65 2 12 6 xrl a, #data 64 2 12 6 xrl direct, a 62 2 12 6 xrl direct, #data 63 3 24 12 clr a e4 1 12 6 cpl a f4 1 12 6 rl a 23 1 12 6 rlc a 33 1 12 6 rr a 03 1 12 6 rrc a 13 1 12 6 swap a c4 1 12 6 mov a, r n e8 ~ ef 1 12 6 mov a, @ri e6 , e7 1 12 6 mov a, direct e5 2 12 6
publication release date: march 11, 2011 - 119 - revision : v 2.0 table 25 C 1 . instruction set for N78E366A instruction opcode bytes clock c y cles in 12t m ode clock c y cles in 6t mode mov a, #data 74 2 12 6 mov r n , a f8 ~ ff 1 12 6 mov r n , direct a8 ~ af 2 24 12 mov r n , #data 78 ~ 7f 2 12 6 mov @ri , a f6 , f7 1 12 6 mov @ri , direct a6 , a7 2 24 12 mov @ri , #data 76 , 77 2 12 6 mov direct, a f5 2 12 6 mov direct, r n 88 ~ 8f 2 24 12 mov direct, @ri 86 , 87 2 24 12 mov direct, d i rect 85 3 24 12 mov direct, #data 75 3 24 12 mov dptr, # data16 90 3 24 12 movc a, @a+dptr 93 1 24 12 movc a, @a+pc 83 1 24 12 movx a, @ri e2 , e3 1 24 12 movx a, @dptr e0 1 24 12 movx @ri , a f2 , f3 1 24 12 movx @dptr, a f0 1 24 12 push direct c0 2 24 12 pop direct d0 2 24 12 xch a, r n c8 ~ cf 1 12 6 xch a, @ri c6 , c7 1 12 6 xch a, direct c5 2 12 6 xchd a, @ri d6 , d7 1 12 6 clr c c3 1 12 6 clr bit c2 2 12 6 setb c d3 1 12 6 setb bit d2 2 12 6 cpl c b3 1 12 6 cpl bit b2 2 12 6 anl c, bit 82 2 24 12 anl c, /bit b0 2 24 12 orl c, bit 72 2 24 12 or l c, /bit a0 2 24 12 mov c, bit a2 2 12 6 mov bit, c 92 2 24 12 acall addr11 11, 31, 51, 71, 91, b1, d1, f1 [ 1 ] 2 24 12 lcall addr16 12 3 24 12
n78e366 a data sheet publication release date: march 11, 2011 - 120 - revision : v2.0 table 25 C 1 . instruction set for N78E366A instruction opcode bytes clock c y cles in 12t m ode clock c y cles in 6t mode ret 22 1 24 12 reti 32 1 24 12 ajmp addr 11 01, 21, 41, 61, 81, a1, c1, e1 [2] 2 24 12 ljmp addr16 02 3 24 12 jmp @a+dptr 73 1 24 12 sjmp rel 80 2 24 12 jz rel 60 2 24 12 jnz rel 70 2 24 12 jc rel 40 2 24 12 jnc rel 50 2 24 12 jb bit, rel 20 3 24 12 jnb bit, rel 30 3 24 12 jbc bit, rel 10 3 24 12 cjne a, direct, rel b5 3 24 12 cjne a, #data, rel b4 3 24 12 cjne @ri , #data, rel b6 , b7 3 24 12 cjne r n , #data, rel b8 ~ bf 3 24 12 djnz r n , rel d8 ~ df 2 24 12 djnz direct, rel d5 3 24 12 [ 1 ] the most three significant bits in the 11 - bit address [a10:a8] decide the acall hex code. the code will be [a10,a9, a8,1,0,0,0,1] . [ 2 ] the most three sig nificant bits in the 11 - bit address [a10:a8] decide the ajmp hex code. the code will be [a10,a9,a8, 0 ,0,0,0,1] .
publication release date: march 11, 2011 - 121 - revision : v 2.0 26. electrical character istics 26.1 absolute maximum ratings parameter rating u nit operating temperature under bias - 40 to +85 ? c storage temperature range - 55 to +150 ? c voltage on vdd pin to v ss - 0. 3 to +6.5 v voltage on any other pin to v ss - 0. 3 to (v dd + 0. 3 ) v stresses at or above those listed under absolute maximum ratings m a y cause permanent damage to the de vice. this is a stress rating o nly and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute ma x- imum rating conditions may affect dev ice reliability. 26.2 dc electrical characteristics temperatur e = - 40 ~85 ; v ss = 0v ; v dd = 4.5 v to 5.5v @ f = 0 to 40 mhz (12t mode), f = 0 to 33 mhz (6t mode) v dd = 2.4v to 5.5v @ f = 0 to 27 mhz (12t mode), f = 0 to 20 mhz (6t mode) v dd = 3.0 v to 5.5v for isp erasing or programming . table 26 C 1 . dc characteristics sym bol parameter condition min . typ . max . unit v il input l ow v oltage 0.2v dd - 0.1 v v ih input h igh v oltage (ports 0 ~ 4, ) 0.2v dd + 0.9 v v ih1 input h igh v oltage ( rst, xtal1) 0.7v dd v v ol output l ow v oltage [ 1 ] v dd = 4.5v, i ol = 8. 2 ma v dd = 3.0 v, i o l = 5.8m a v dd = 2.4v, i ol = 4.4 ma 0.4 v v oh output h igh v oltage (ports 1 ~ 4 and port 0 with i n ternal pull - up enabled ) v dd = 4.5v, i oh = - 3 0 0 a v dd = 3.0 v, i oh = - 75 a v dd = 2.4v, i oh = - 35 a 2.4 2.4 2.0 v v oh 1 output h igh v oltage (ports 0 and 2 in e x ternal bus mode, ale, ) v dd = 4.5v, i oh = - 9 m a v dd = 3.0 v, i oh = - 2.4 m a v dd = 2.4v, i oh = - 1. 3 m a 2.4 2.4 2.0 v ea psen
n78e366 a data sheet publication release date: march 11, 2011 - 122 - revision : v2.0 sym bol parameter condition min . typ . max . unit i il lo gical 0 i nput c u r rent (ports 1 ~ 4 and port 0 with i n ternal pull - up enabled ) v dd = 5.5v, v in = 0.4v v dd = 3.6 v, v in = 0.4v - 50 - 20 a i tl logical 1 - to - 0 t ransition c u r- rent [ 2 ] (ports 1~4 and port 0 with internal pull - up enabled ) v dd = 5.5v v dd = 3.6 v - 5 7 0 - 240 - 65 0 - 290 a i li input l eakage c u r rent (port 0) 0 < v in < v dd 10 a i dd supply c urrent [3] v dd = 5 .0 v, external clock, 12t 0. 21 f + 3. 5 ma v dd = 3. 3 v , external clock, 12t 0.1 5 f + 2 .9 ma v dd = 5 .0 v, external clock, 6t 0. 35 f + 3.3 ma v dd = 3. 3 v , external clock, 6t 0. 3 2 f + 2.3 ma v dd = 5 .0 v, internal 22.1184mhz, 12t 5.8 ma v dd = 3. 3 v , internal 11.0592mhz, 12t 3.9 ma v dd = 5 .0 v, internal 22.1184mhz, 6t 8.6 ma v dd = 3. 3 v , internal 11.0592mhz, 6t 5.1 ma i i d idle m o de c urrent v dd = 5 .0 v, external clock, 12t 0. 11 f + 2.0 ma v dd = 3. 3 v , external clock, 12t 0.0 9 f + 0. 9 ma v dd = 5 .0 v, external clock, 6t 0. 15 f + 1. 7 ma v dd = 3. 3 v , external clock, 6t 0. 14 f + 0. 7 ma v dd = 5 .0 v, internal 22.1184mhz, 12t 2.0 ma v dd = 3. 3 v , internal 11.0592mhz, 12t 1.4 ma v dd = 5 .0 v, internal 22.1184mhz, 6t 2.5 ma v dd = 3. 3 v , internal 11.0592mhz, 6t 1.8 ma i p d power d own m ode c urrent 2 35 a r rst rst pin i nternal p ull - down r e sistor 2.4 < v dd < 5.5v 45 80 0 k v bod 0 brown - out t hreshold 2.2v 2.05 2.2 2.3 v v bod 1 brown - out t hreshold 2.7v 2.6 2.7 2.85 v v bod 2 brown - out t hreshold 3.8v 3.65 3.8 4.0 v v bod 3 brown - out t hreshold 4.5v 4.35 4.5 4.75 v v bodhys brown - out h ysteresis 20 200 mv v por power - on r eset t hres h old 2.0 v [ 1 ] under steady state (non - transient) conditions, i ol must b e externally limited as follows, maximum i ol per port pin: 20ma maximum i ol per 8 - bit port : 40ma maximum total i ol for all outputs: 100ma [ 2 ] pins of ports 1~4 a nd port 0 with internal pull - up enabled will source a transition current when they are being externally driven from 1 t o 0. th e tra n sition current reaches its maximum value w hen v in is approximately 1.5v ~ 2.5 v. [3] it is measured while mcu keeps in runni ng sjmp $ loop co n tinuously. p0 is externally or internally pulled - up.
publication release date: march 11, 2011 - 123 - revision : v 2.0 figures below shows supply and idle mode current under 12t/6t with internal program memory mode . figure 26 C 1 . supply current under 12t m ode , external clock (1) figure 26 C 2 . supply current under 12t m ode , external clock (2)
n78e366 a data sheet publication release date: march 11, 2011 - 124 - revision : v2.0 figure 26 C 3 . supply current under 6t m ode , external clock (1) figu re 26 C 4 . supply current under 6t m ode , external clock (2)
publication release date: march 11, 2011 - 125 - revision : v 2.0 figure 26 C 5 . idle mode c urrent under 12t mode , external clock (1) figure 26 C 6 . idle mode c urrent under 12t mode , external clock (2)
n78e366 a data sheet publication release date: march 11, 2011 - 126 - revision : v2.0 figure 26 C 7 . idle mode c urrent under 6t mode , external clock (1) figure 26 C 8 . idle mode c urrent under 6t mode , external clock (2)
publication release date: march 11, 2011 - 127 - revision : v 2.0 26.3 ac electrical characteristics table 26 C 2 . ac characteristics s y m bol p arameter 12t mode 6t mode u nit m in . m ax . m in . m ax . external clock 1/ t clcl ext ernal clock input frequency 0 40 0 33 mhz crystal/resonator frequency 4 40 4 33 t chcx high time 12 15 ns t clcx low time 12 15 ns t clch r ise time 8 5 ns t chcl f all time 8 5 ns program memory t lhll ale pulse width 2 t clcl - 15 t clcl - 15 ns t avll address valid to ale low t clcl - 15 0.5 t clcl - 15 ns t llax address hold after ale low t clcl - 15 0.5 t clcl - 15 ns t lliv ale low to valid instruction in 4 t clcl - 45 2 t clcl - 45 ns t llpl ale low to low t clcl - 15 0.5 t cl cl - 15 ns t plph pulse width 3 t clcl - 15 1.5 t clcl - 15 ns t pliv low to valid instru c tion in 3 t clcl - 50 1.5 t clcl - 50 ns t pxix input instruction hold after 0 0 ns t pxiz input instruction float after t clcl - 15 0.5 t clcl - 15 ns t aviv address to valid instruction in 5 t clcl - 60 2.5 t clcl - 60 ns t plaz low to address float 10 10 ns data memory t rlrh p ulse width 6 t clcl - 30 3 t clcl - 30 ns t wlwh pulse width 6 t clcl - 30 3 t clcl - 30 ns t rldv low to valid data in 5 t clcl - 50 2.5 t clcl - 50 ns t rhdx d ata hold after 0 0 ns t rhd z data float after 2 t clcl - 12 t clcl - 12 ns t lldv ale low to valid data in 8 t clcl - 50 4 t clcl - 50 ns t avdv a ddress to valid data in 9 t clcl - 75 4.5 t clcl - 75 ns t llwl ale low to or low 3 t clcl - 15 3 t clcl +15 1.5 t clcl - 15 1.5 t clcl +15 ns rd wr rd rd rd rd wr psen
n78e366 a data sheet publication release date: march 11, 2011 - 128 - revision : v2.0 s y m bol p arameter 12t mode 6t mode u nit m in . m ax . m in . m ax . t avwl a ddress valid to low or low 4 t clcl - 30 2 t clcl - 30 ns t qvwx d ata valid to transition t clcl - 20 0.5 t clcl - 20 ns t whqx d ata hold after t clcl - 15 0.5 t clcl - 15 ns t rlaz low to address float 0 0 ns t whlh or high to ale high t clcl - 15 t clcl +15 0.5 t clcl - 15 0. 5 t clcl +15 ns figure 26 C 9 . external clock input timing figure 26 C 10 . external program memory read cycle rd wr wr rd wr wr rd
publication release date: march 11, 2011 - 129 - revision : v 2.0 figure 26 C 11 . external data memory read cycle figure 26 C 12 . external data memory write cycle
n78e366 a data sheet publication release date: march 11, 2011 - 130 - revision : v2.0 table 26 C 3 . characteristics of on - chip rc oscillators s y m bol p ara meter condition fr e quency deviation m in . typ. m ax . u nit f ihrc system 22.1184mhz rc oscillator f reque n cy [1] [2] 25 1% 21.8972 22.1184 22.3396 mhz - 40 ~85 3% 21.4548 22.1184 22.7820 mhz f ilrc wdt and pdt 10k h z rc oscillator f r e quency 30% 7 10 13 khz [1] internal 11.0592mhz is not listed for the same frequency deviation due to directly divided by 2 from 22.1184m hz source . [ 2 ] a 0.1f capacitor is recommended to be add ed on xtal1 pin to gain the more precise frequency of the internal rc o s cillator frequency if it is selected as the system clock source. table 26 C 4 . ch aracteristics of brown - out detection s y m bol p arameter condition m in . typ. m ax . u nit t bod brown - out detect pulse width v dd < v bod 60 0 - - s t bodrd brown - out release delay period v dd > v bod 5.6 8 10.4 ms
publication release date: march 11, 2011 - 131 - revision : v 2.0 27. packages figur e 27 C 1 . dip - 40 package dimention 1.37 1.22 0.054 0.048 symbol min nom max max nom min dimension in inch dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.540 0.550 0.545 13.72 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 2.055 2.070 52.20 52.58 0 15 0.090 2.29 0.650 0.630 16.00 16.51 15 0 seating plane e a 2 a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1
n78e366 a data sheet publication release date: march 11, 2011 - 132 - revision : v2.0 figure 27 C 2 . plcc - 44 package dimention 44 40 39 29 28 18 17 7 6 1 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e symbol min nom max max nom min dimension in inch dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.51 3.68 0.66 0.41 0.20 16.46 14.99 17.27 2.29 3.81 0.71 0.46 0.25 16.59 15.49 17.53 2.54 1.27 4.70 3.94 0.81 0.56 0.36 16.71 16.00 17.78 2.79 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680
publication release date: march 11, 2011 - 133 - revision : v 2.0 figure 27 C 3 . pqfp - 44 package dimention 0.25 0.10 0.010 0.004 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.006 0.15 - - 0.002 0.075 0.01 0.081 0.014 0.087 0.018 1.90 0.25 0.05 2.05 0.35 2.20 0.45 0.390 0.510 0.025 0.063 0.004 0 10 0.394 0.520 0.031 0.398 0.530 0.037 9.9 0.80 12.95 0.65 1.60 10.00 13.20 0.8 10.1 13.45 0.95 0.398 0.394 0.390 0.530 0.520 0.510 13.45 13.20 12.95 10.1 10.00 9.9 10 0 0.10 .0315 0.01 0.02 0.25 0.5 seating plane 11 22 12 see detail f e b a y 1 a a 2 l l 1 c e e h 1 d 44 h d 34 33 detail f
n78e366 a data sheet publication release date: march 11, 2011 - 134 - revision : v2.0 figure 27 C 4 . lqfp - 48 package dimention
publication release date: march 11, 2011 - 135 - revision : v 2.0 28. document revision hi story version date page description v1.0 2010/8/13 initi al release. v1.1 2010/9/20 12 4 increase the maximum value of power down mode current. v1.2 2010/12/1 79 94 8 5 1. add restriction of disabling interrupts during ta protected writing. 2. add restriction of disabling interrupts during isp. 3. add more descriptions of software clearing interrupt flags. v2.0 2011/3/11 28 change xram default state enabled after all resets to fit general applications. technical supporting web 80c51 8 - bit mcu series http://www.nuvoton.com/80c51
n78e366 a data sheet publication release date: march 11, 2011 - 136 - revision : v2.0 more product details and update inform a tion , please visit our website : www.nuvoton. com headquarter - taiwan nuvoton technol o gy corp. no. 4, creation rd. ill, hsinchu science park, 300 taiwan tel: 886 - 3 - 5770066 worldwide sales offices taipei sales office 8f, no. 480, rueiguang rd., ne i hu chiu, taipei, 114 taiwan tel: 886 - 2 - 26588066 nuvoton el ectronics tech . (shenzhen) l i mited unit 1501, new world center, 6009 yitian road, futian, shenzhen, p.r.china 518026 tel: 86 - 755 - 83515350 nuvoton technology corp. ame r ica 2727 n. first street, san jose, ca 95134, u .s.a. tel: 1 - 408 - 544 - 1718 nuv oton electronics tech. ( h .k.) limited unit 9 - 11, 22f, millennium city 2, 378 kwun tong road, kowloon, hong kong tel: 852 - 27513100 important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfun c- tion or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed , insecure usage. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control in struments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, customer shall indemnify the damages and liabil i- ties thus incurred by nuvoton.

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