cystech electronics corp. spec. no. : c912f3 issued date : 2017.03.30 revised date : page no. : 1/9 mtb09n06f3 cystek product specification n-channel enhancement mode power mosfet mtb09n06f3 features ? low gate charge ? simple drive requirement ? fast switching characteristic ? rohs compliant package symbol outline ordering information device package shipping MTB09N06F3-0-T7-X to-263 (pb-free lead plating and rohs compliant package) 800 pcs / tape & reel to-263 mtb09n06f3 g gate d drain s source bv dss 60v i d @ v gs =10v, t c =25 c 87a i d @ v gs =10v, t a =25 c 11a 6.4m r dson(typ) @ v gs =10v, i d =30a 7.8m r dson(typ) @ v gs =4.5v, i d =20a g d s environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t7 : 800 pcs / tape & reel, 13? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c912f3 issued date : 2017.03.30 revised date : page no. : 2/9 mtb09n06f3 cystek product specification absolute maximum ratings (t c =25 c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds 60 gate-source voltage v gs 30 v continuous drain current @ t c =25 c, v gs =10v(silicon limit) 87 continuous drain current @ t c =100 c, v gs =10v(silicon limit) 61.5 continuous drain current @ t c =25 c, vgs=10v(package limit) (note 1) i d 60 pulsed drain current (note 3) i dm 240 continuous drain current @ t a =25 c (note 2) 11 continuous drain current @ t a =70 c (note 2) i dsm 8.8 avalanche current (note 3) i as 30 a avalanche energy @ l=1mh, i d =30a, r g =25 (note 2) e as 450 repetitive avalanche energy@ l=0.1mh (note 3) e ar 14 mj t c =25 c (note 1) 136 power dissipation t c =100 c (note 1) p d 68 w t a =25 c (note 2) 2 power dissipation t a =70 c (note 2) p dsm 1.3 w operating junction and storage temperature tj, tstg -55~+175 c thermal data parameter symbol value unit thermal resistance, junction-to-case, max r jc 1.1 thermal resistance, junction-to-ambient, max, t 10s (note 1) 15 thermal resistance, junction-to-ambient, max (note 1) r ja 62.5 c/w note : 1 . the power dissipation p d is based on t j(max) =175 c, using junction-to-case thermal resistance, and is more useful in setting the upper di ssipation limit for cases where additional heatsinking is used. 2 . the value of r ja is measured with the device mounted on 1 in 2 fr-4 board with 2 oz. copper, in a still air environment with t a =25 c. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c. the value in any given application depends on the user?s specific board design, and the maximum temperature of 175 c may be used if the pcb allows it. 3 . repetitive rating, pulse width limited by junction temperature t j(max) =175 c. ratings are based on low frequency and low duty cycles to keep initial t j =25 c. 4. the maximum current limited by package is 60a. 5. the static characteristics are obtained using <300 s pulses, duty cycle 0.5% maximum. 6. the r ja is the sum of thermal resistance from junction to case r jc and case to ambient.
cystech electronics corp. spec. no. : c912f3 issued date : 2017.03.30 revised date : page no. : 3/9 mtb09n06f3 cystek product specification characteristics (t c =25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 60 - - v gs =0v, i d =250 a v gs(th) 1 - 2.5 v v ds = v gs , i d =250 a g fs - 30 - s v ds =5v, i d =20a i gss - - 100 na v gs = 30v - - 1 v ds =48v, v gs =0v i dss - - 10 a v ds =48v, v gs =0v, tj=55 c - 6.4 8 v gs =10v, i d =30a *r ds(on) - 7.8 10.5 m v gs =4.5v, i d =20a dynamic *qg - 39.6 - *qgs - 5 - *qgd - 12.4 - nc i d =20a, v ds =30v, v gs =10v *t d(on) - 13.4 - *tr - 20.6 - *t d(off) - 49.4 - *t f - 15.4 - ns v dd =30v, i d =20a, v gs =10v, r g =3 ciss - 1678 - coss - 264 - crss - 142 - pf v gs =0v, v ds =30v, f=1mhz rg - 2.4 - f=1mhz source-drain diode *i s - - 60 a *v sd - 0.85 1.2 v i s =30a, v gs =0v *trr - 18.3 - ns *qrr - 13.6 - nc i f =30a, v gs =0v, di f /dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c912f3 issued date : 2017.03.30 revised date : page no. : 4/9 mtb09n06f3 cystek product specification typical characteristics typical output characteristics 0 30 60 90 120 150 180 012345 v ds , drain-source voltage(v) i d , drain current (a) 10v,9v,8v,7v,6v v gs =3v 4v 3.5v 4.5v 5v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 1 10 100 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =10v v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 024681 i dr , reverse drain current(a) v sd , source-drain voltage(v) 0 tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 20 40 60 80 100 024681 0 drain-source on-state resistance vs junction tempearture 0 0.4 0.8 1.2 1.6 2 2.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =20a r dson @tj=25c : 6.4m typ. v gs =4.5v, i d =20a r ds( on) @tj=25c : 7.8m typ. v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =20a
cystech electronics corp. spec. no. : c912f3 issued date : 2017.03.30 revised date : page no. : 5/9 mtb09n06f3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 100 1000 10000 0 5 10 15 20 25 30 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 i d , drain current(a) g fs , forward transfer admittance(s) ta=25c pulsed v ds =5v gate charge characteristics 0 2 4 6 8 10 0 102030405060 qg, total gate charge(nc) v gs , gate-source voltage(v) v ds =30v i d =20a maximum safe operating area 0.1 1 10 100 1000 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) t c =25c, tj=175c v gs =10v, r jc =1.1c/w single pulse dc 100ms r dson limited 10 s 100 s 1ms 10ms maximum drain current vs case temperature 0 10 20 30 40 50 60 70 80 90 100 25 50 75 100 125 150 175 200 t c , case temperature(c) i d , maximum drain current(a) v gs =10v, r jc =1.1c/w silicon limit package limit
cystech electronics corp. spec. no. : c912f3 issued date : 2017.03.30 revised date : page no. : 6/9 mtb09n06f3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 20 40 60 80 100 120 140 160 180 0246810 v gs , gate-source voltage(v) i d , drain current(a) v ds =10v single pulse power rating, junction to case 0 300 600 900 1200 1500 1800 2100 2400 2700 3000 0.0001 0.001 0.01 0.1 1 10 pulse width(s) power (w) t j(max) =175c t c =25c r jc =1.1c/w transient thermal response curves 0.001 0.01 0.1 1 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r jc (t) 4.r jc =1.1 c/w
cystech electronics corp. spec. no. : c912f3 issued date : 2017.03.30 revised date : page no. : 7/9 mtb09n06f3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c912f3 issued date : 2017.03.30 revised date : page no. : 8/9 mtb09n06f3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c912f3 issued date : 2017.03.30 revised date : page no. : 9/9 mtb09n06f3 cystek product specification to-263 dimension marking : b09 n06 device name millimeters inches millimeters inches dim min. max. min. max. dim min. max. min. max. a 4.40 4.70 0.173 0.185 e 10.06 10.26 0.396 0.404 a1 0.00 0.25 0.000 0.010 e1 7.80 8.20 0.307 0.323 a2 2.59 2.79 0.102 0.110 e 2.54 bsc 0.100 bsc b 0.77 0.90 0.030 0.035 h 14.70 15.50 0.579 0.610 b1 0.76 0.86 0.030 0.034 l 2.00 2.60 0.079 0.102 b2 1.23 1.36 0.048 0.054 l1 1.17 1.40 0.046 0.055 b3 1.22 1.32 0.048 0. 052 l2 - 1.75 - 0.069 c 0.34 0.47 0.013 0.019 l3 0.25 bsc 0.010 bsc c1 0.33 0.43 0.013 0.017 l4 2.00 ref 0.079 bsc c2 1.22 1.32 0.048 0.052 0 8 0 8 d 9.05 9.25 0.356 0.364 1 5 9 5 9 d1 6.60 - 0.260 - 2 1 5 1 5 notes : 1.controlling dimension : millimeters. 2.maximum lead thickness includes lead finish thickness, and mi nimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please contact your local cystek sales office. material : ? lead : pure tin plated. ? mold compound : epoxy resin family, flammability solid burning class:ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warra nted to be suitable for use in li fe-support applications, or systems. ? cystek assumes no liability for any conseque nce of customer product design, infringement of patents, or application assistance . style : pin 1.gate 2.drain 3.source 3-lead plastic surface mounted package cystek package code : f3 date code date code : (from left to right) first code : year code, the last dig it of christinr year. for example, 2014 4, 2015 , 2016 6, ?, etc. second code : month code, jan a, feb b, mar c, apr d, may e, jun f, jul g, a u g h, sep j, oct k, nov l, dec m third and fourth codes : production serial number, 01~99
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