cystech electronics corp. spec. no. : c430h8 issued date : 2018.07. 24 revised date : 2018.07.25 page no. : 1/ 10 mtb 010 a0 3 h8 preliminary cystek product specification ppreliminary dual n-channel enhancement mode power mosfet mtb 010 a0 3 h8 features ? low on resistance ? simple drive requirement ? low gate charge ? fast switching characteristic ? pb -free lead plating and halogen-free package equivalent circuit outline ordering information device package shipping mtb 010 a0 3 h8 -0- t6 -g dfn 5 6 ( pb -free lead plating and halogen-free package) 3000 pcs / tape & reel dfn5 6 mt b 010 a0 3 h8 bv dss 30v i d @v gs =10v, t c =25 c 36a i d @v gs =10v, t c =100 c 23a i d @v gs =10v, t a =25 c 8.8a i d @v gs =10v, t a =70 c 7.0a r ds(on) @v gs =10v, i d =12a 7.3m (typ) r ds(on) @v gs =4.5v, i d =7a 9.6m (typ) g gate d drain s source environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t6 : 3000 pcs / tape & reel,13 reel product rank, zero for no rank products product name pin 1 pin 1
cystech electronics corp. spec. no. : c430h8 issued date : 2018.07. 24 revised date : 2018.07.25 page no. : 2/ 10 mtb 010 a0 3 h8 preliminary cystek product specification ppreliminary absolute maximum ratings (t c =25 ? c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds 30 v gate-source voltage v gs 20 continuous drain current @t c =25 ? c, v gs =10v (note 1) i d 36 a continuous drain current @t c =100 ? c, v gs =10v (note 1) 23 continuous drain current @t a =25 ? c, v gs =10v (note 2) i dsm 8.8 continuous drain current @t a =70 ? c, v gs =10v (note 2) 7.0 pulsed drain current @ v gs =10v (note 3) i dm 144 avalanche current @l=0.1mh (note 3) i as 30 single pulse avalanche energy @ l=1mh, i d =1 2amps, v dd =15v (note 5) e as 72 mj repetitive avalanche energy (note 3) e ar 2.5 power dissipation t c =25 ? c (note 1) p d 25 w t c =100 ? c (note 1) 10 t a =25 ? c (note 2) p dsm 1.5 t a =70 ? c (note 2) 1.0 operating junction and storage temperature tj, tstg -55~+150 ? c *drain current limited by maximum junction temperature thermal data parameter symbol value unit thermal resistance, junction- to -case, max r jc 5 ? c /w thermal resistance, junction- to -ambient, max (note 4) r ja 85 note : 1 . the power dissipation p d is based on t j(max) =150 c, using junction- to -case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. 2 . the value of r ja is measured with the device mounted on 1 in2 fr -4 board with 2 oz. copper, in a still air environment with t a =25 c. the value in any given application depends on the user s specific board design. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c. 3 . ratings are based on low frequency and low duty cycles to keep initial t j =25 c. 4. when mounted on 1 in2 copper pad of fr -4 board ; 125 ? c/w when mounted on minimum copper pad. 5. 100% tested by conditions of l=0.1mh, i as =6a, v gs =10v, v dd =15v. characteristics (tj=25 ? c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 30 - - v v gs =0v, i d =250 a ? bv dss / ? tj - 0.03 - v/ ? c reference to 25 ? c, i d =250 a v gs(th) 1.0 - 2.5 v v ds = v gs , i d =250 a *g fs - 7.7 - s v ds =10v, i d =3a i gss - - 100 na v gs = 20v, v ds =0v i dss - - 1 a v ds =24v, v gs =0v - - 25 v ds =24v, v gs =0v, tj=85 ? c
cystech electronics corp. spec. no. : c430h8 issued date : 2018.07. 24 revised date : 2018.07.25 page no. : 3/ 10 mtb 010 a0 3 h8 preliminary cystek product specification ppreliminary *r ds ( on ) - 7.3 11 m v gs =10v, i d =12a - 9.6 15 v gs =4.5v, i d =7a dynamic *qg - 23.8 32 nc v ds =15v, i d =12a, v gs =10v *qgs - 3.9 - *qgd - 6.4 - *t d(on) - 11.4 23 ns v ds =15v, i d =1a, v gs =10v, r g =1 *tr - 18.2 28 *t d(off) - 41 53 *t f - 8.6 18 ciss - 1292 1680 pf v gs =0v, v ds =30v, f=1mhz co ss - 154 200 crss - 115 150 rg - 2.8 - f=1mhz source-drain diode *i s - - 36 a *i sm - - 144 *v sd - 0.72 1 v i s =1a, v gs =0v *trr - 11.7 - ns v gs =0v, i f =5a, di f /dt=100a/ s *qrr - 5.7 - nc *pulse test : pulse width ? 30 0s, duty cycle ? 2% recommended soldering footprint unit : mm
cystech electronics corp. spec. no. : c430h8 issued date : 2018.07. 24 revised date : 2018.07.25 page no. : 4/ 10 mtb 010 a0 3 h8 preliminary cystek product specification ppreliminary recommended stencil design note : 1. stencil thickness 5 mil (0.127mm) 2. may need to be adjusted to specific requirements.
cystech electronics corp. spec. no. : c430h8 issued date : 2018.07. 24 revised date : 2018.07.25 page no. : 5/ 10 mtb 010 a0 3 h8 preliminary cystek product specification ppreliminary typical characteristics typical output characteristics 0 30 60 90 120 150 0 1 2 3 4 5 v ds , drain-source voltage(v) i d , drain current(a) 10v 9v 8v 7v6v v gs =4v v gs =5v v gs =3.5v v gs =3v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature( c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain curre nt 1 10 100 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state eace v gs =4.5v v gs =10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 0 4 8 12 16 20 i dr , reverse drain current(a) v sd , source-drain voltage(v) tj=25 c tj=150 c static drain-source on-state resistance vs gate-sou rce voltage 0 10 20 30 40 50 0 2 4 6 8 10 v gs , gate-source voltage(v) r ds(on) , static drain-source on- ae eace i d =12a drain-source on-state resistance vs junction tempea rture 0 0.5 1 1.5 2 2.5 3 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature( c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =12a r ds(on) @=5c : 7.3 yp
cystech electronics corp. spec. no. : c430h8 issued date : 2018.07. 24 revised date : 2018.07.25 page no. : 6/ 10 mtb 010 a0 3 h8 preliminary cystek product specification ppreliminary typical characteristics (cont.) capacitance vs drain-to-source voltage 10 100 1000 10000 0 5 10 15 20 25 30 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss normalizedthreshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature( c) v g s(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 10 i d , drain current(a) g fs , forward transfer admittance(s) v ds =10v pulsed a=5c gate charge characteristics 0 2 4 6 8 10 0 4 8 12 16 20 24 28 32 total gate charge---qg(nc) v gs , gate-source voltage(v) v ds =15v i d =12a maximum safe operating area 0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current(a) dc 10ms 100ms 1ms 100 s r ds(on) limited t c =5c, =5, gs =10v r jc =85c, ge pe 1s maximum drain current vs junction temperature 0 1 2 3 4 5 6 7 8 9 10 25 50 75 100 125 150 175 tj , junction epeaec i d , maximum drain current(a) v gs =10v, r ja =85c
cystech electronics corp. spec. no. : c430h8 issued date : 2018.07. 24 revised date : 2018.07.25 page no. : 7/ 10 mtb 010 a0 3 h8 preliminary cystek product specification ppreliminary typical characteristics(cont.) typical transfer characteristics 0 30 60 90 120 150 0 1 2 3 4 5 v gs , gate-source voltage(v) i d , drain current (a) v ds =10v single pulse maximum power dissipation 0 20 40 60 80 100 120 140 160 0.0001 0.001 0.01 0.1 1 10 pulse width(s) power (w) t j(max) =5c t a =5c r jc =85c transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =85 c/w
cystech electronics corp. spec. no. : c430h8 issued date : 2018.07. 24 revised date : 2018.07.25 page no. : 8/ 10 mtb 010 a0 3 h8 preliminary cystek product specification ppreliminary reel dimension carrier tape dimension pin #1
cystech electronics corp. spec. no. : c430h8 issued date : 2018.07. 24 revised date : 2018.07.25 page no. : 9/ 10 mtb 010 a0 3 h8 preliminary cystek product specification ppreliminary recommended wave soldering condition product peak temperature soldering time pb -free devices 260 +0/- 5 ? c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn -pb eutectic assembly pb -free assembly average ramp-up rate (tsmax to tp) 3 ? c/second max. 3 ? c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 ? c 150 ? c 60 -120 seconds 150 ? c 200 ? c 60 -180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 ? c 60 -150 seconds 217 ? c 60 -150 seconds peak temperature(t p ) 240 +0/- 5 ? c 260 +0/- 5 ? c time within 5 ? c of actual peak temperature(tp) 10 -30 seconds 20 -40 seconds ramp down rate 6 ? c/second max. 6 ? c/second max. time 25 ? c to peak temperature 6 minutes max. 8 minutes max. note :1. all temperatures refer to topside of the package, measured on the package body surface. 2.for devices mounted on fr-4 pcb of 1.6mm or equivalent grade pcb. if other grade pcb is used, care should be taken to match the coefficients of thermal expansion between components and pcb. if they are not matched well, the solder joints may crack or the bodies of the parts may crack or shatter as the assembly cools.
cystech electronics corp. spec. no. : c430h8 issued date : 2018.07. 24 revised date : 2018.07.25 page no. : 10 / 10 mtb 010 a0 3 h8 preliminary cystek product specification ppreliminary dfn5 6 dimension dim millimeters inches d im millimeters inches min. max. min. max. min. max. min. max. a 0.900 1.000 0.035 0.039 e2 5.674 5.826 0.223 0.229 a3 0.254 ref 0.010 ref k 1.190 1.390 0.047 0.055 d 4.944 5.096 0.195 0.201 b 0.350 0.450 0.014 0.018 e 5.974 6.126 0.235 0.241 e 1.270 typ 0.050 typ d1 1.470 1.870 0.058 0.074 l 0.559 0.711 0.022 0.028 d2 0.470 0.870 0.019 0.034 l1 0.424 0.576 0.017 0.023 e1 3.375 3.575 0.133 0.141 h 0.574 0.726 0.023 0.029 d3 4.824 4.976 0.190 0.196 10 12 10 12 notes: 1. controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please contact your local cystek sa les office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v -0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. marking: 8-lead power pak plastic package cystek package code: h8 date code device name 8-lead dfn5 6 plastic package cys package code : h8 b0 10 a0 3
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