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1 datasheet dual, noninverting power mosfet radiation hardened drivers HS-4424DRH, hs4424deh the radiation hardened hs-4424 family are noninverting, dual, monolithic high-speed mosfet drivers designed to convert low voltage control input signals into higher voltage, high current outputs. the HS-4424DRH , hs-4424deh are fully tested across the 8v to 18v operating range. the inputs of these devices can be directly driven by the hs-1825arh pwm device or by our acs/acts and hcs/hcts type logic devices. the fast rise times and high current outputs allow very quick control of high gate capacitance power mosfets in high frequency applications. the high current outputs minimi ze power losses in mosfets by rapidly charging and discharging the gate capacitance. the output stage incorporates a lo w voltage lockout circuit that puts the outputs into a three-state mode when the supply voltage is below its undervolta ge lockout (uvlo) threshold voltage. constructed with intersil?s dielectrically isolated rad hard silicon gate (rsg) bicmos proc ess, these devices are immune to single event latch-up and have been specifically designed to provide highly reliable performance in harsh radiation environments. features ? electrically screened to dla smd# 5962-99560 ? qml qualified per mil-prf-38535 requirements ?latch-up immune ?radiation environment ? high dose rate (50-300rad(si)/s). . . . . . . . . . . . . 300krad(si) - low dose rate (0.01rad(si)/s) . . . . . . . . . . . . . 50krad(si)* *limit established by characterization ?i peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2a (minimum) ? matched rise and fall times (c l = 4300pf). . 75ns (maximum) ? low voltage lockout feature . . . . . . . . . . . . . . . . . . . . . . . . <8v ? wide supply voltage range . . . . . . . . . . . . . . . . . . . . 8v to 18v ? propagation delay . . . . . . . . . . . . . . . . . . . . 250ns (maximum) ? consistent delay times with v cc changes ?low power consumption - 40mw with inputs high - 20mw with inputs low ? low equivalent input capacitance . . . . . . . . . . 3.2pf (typical) ? esd protected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kv applications ? switching power supplies ?dc/dc converters ?motor controllers table 1. hs4424 product family specific uvlo vth part number uvlo (v) hs-4424rh hs-4424eh <10 hs4424brh hs4424beh <7.5 hs4424drh hs4424deh <8 figure 1. typical application figure 2. undervoltage lockout vs temperature controller pwm in b in a out a out b vcc +8v to +18v gnd hs-4424d hs-1825arh 7.2 7.3 7.4 7.5 7.6 7.7 -55 25 125 undervoltage lockout (v) temperature (c) uvlo_r uvlo_f october 15, 2015 fn8747.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
HS-4424DRH, hs4424deh 2 fn8747.2 october 15, 2015 submit document feedback pin configuration HS-4424DRH, hs-4424deh (16 ld flatpack) top view pin descriptions pin number pin name equivalent esd circuit description 1, 3, 6, 8, 9, 16 nc na no internal connection 2in a circuit 2driver a input 4gnd a naground reference a 5gnd b naground reference b 7in b circuit 2driver b input 10, 11 out b na driver b output 12, 13 vcc circuit 1 positive power supply 14, 15 out a na driver a output nc in a nc gnd a gnd b nc in b nc 2 3 4 5 6 7 8 116 15 14 13 12 11 10 9 nc out a out a vcc vcc out b out b nc figure 3. circuit 1 figure 4. circuit 2 vcc gnd in vcc 2k gnd
HS-4424DRH, hs4424deh 3 fn8747.2 october 15, 2015 submit document feedback functional block diagram ordering information smd number ordering ( note 2 ) part number ( note 1 ) temperature range (c) package (rohs compliant) pkg. dwg. # 5962f9956005v9a hs0-4424drh-q -55 to +125 die hs0-4424drh/sample hs0-4424drh/sample -55 to +125 die sample 5962f9956005vxc hs9-4424drh-q -55 to +125 16 ld flatpack k16.a hs9-4424drh/proto hs9-4424drh/proto -55 to +125 16 ld flatpack k16.a 5962f9956006v9a hs0-4424deh-q -55 to +125 die 5962f9956006vxc hs9-4424deh-q -55 to +125 16 ld flatpack k16.a notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and c ompatible with both snpb and pb-free soldering operations. 2. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbe rs listed in the ?ordering information? table must be used when ordering. control logic level shifter & uvlo & uvlo out a out b vcc in a gnd a vcc out a control logic level shifter 1k in b out b gnd b 1k out a out a out b out b vcc in a gnd a vcc in b gnd b level shifter level shifter control and logic uvlo control and logic uvlo 1k 1k figure 5. block diagram
HS-4424DRH, hs4424deh 4 fn8747.2 october 15, 2015 submit document feedback absolute maximum ratings thermal information maximum supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v min/max input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to v cc output short-circuit duration (1 output at a time). . . . . . . . . . . . indefinite esd rating human body model (tested per mil-prf-883 3015.7). . . . . . . . . . . 5kv machine model (tested per mil-prf-883 3015.7) . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c101d) . . . . . . . . . . . . 750v thermal resistance (typical) ? ja (c/w) ? jc (c/w) 16 ld flatpack package ( notes 3 , 4 ). . . . . 34 5 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c maximum operating junction temperature . . . . . . . . . . . . . . . . . .+175c maximum lead temperature (soldering 10 secs) . . . . . . . . . . . . . .+265c recommended operating conditions ambient operating temperature range . . . . . . . . . . . . . .-55c to +125c maximum operating junction temperature . . . . . . . . . . . . . . . . . .+150c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8v to 18v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. ? ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 4. for ? jc , the ?case temp? location is the center of the package underside. electrical specifications v cc = 8v, 12v, 18v, t a = +25c, unless otherwise noted. boldface limits apply across the operating temperature range, -55c to +125c; over radiation total ionizing dose. parameter description test conditions min ( note 5 )typ max ( note 5 )unit v supply supply voltage range 818 v i ccsb low 18v bias current v s = 18v, inputs = 0v 3.5 ma v s = 18v, inputs = 0v 4 ma v s = 18v, inputs = 0v, post radiation 4 ma i ccsb high 18v bias current v s , inputs = 18v 3.5 ma v s , inputs = 18v 4 ma v s , inputs = 18v, post radiation 4 ma i ccsb low 8v bias current v s = 8v, inputs = 0v 3.5 ma v s = 8v, inputs = 0v 4 ma v s = 8v, inputs = 0v, post radiation 4 ma i ccsb high 8v bias current v s , inputs = 8v 3.5 ma v s , inputs = 8v 4 ma v s , inputs = 8v, post radiation 4 ma i il_18 input current low v s = 18v, inputs = 0v -5 0.08 5 a v s = 18v, inputs = 0v -10 10 a v s = 18v, inputs = 0v, post radiation -10 10 a i ih_18 input current high v s , inputs = 18v -5 0.08 5 a v s , inputs = 18v -10 10 a v s , inputs = 18v, post radiation -10 10 a i il_8 input current low v s = 8v, inputs = 0v -5 0.08 5 a v s = 8v, inputs = 0v -10 10 a v s = 8v, inputs = 0v, post radiation -10 10 a i ih_8 input current high v s , inputs = 8v -5 0.08 5 a v s , inputs = 8v -10 10 a v s , inputs = 8v, post radiation -10 10 a v oh output voltage high v s = 8v, i out = 5ma v s - 0.75 v s - 0.45 v v s - 0.9 v
HS-4424DRH, hs4424deh 5 fn8747.2 october 15, 2015 submit document feedback v ol output voltage low v s = 8v, i out = 5ma 0.45 0.8 v 0.8 v v oh output voltage high v s = 8v, i out = 50ma v s - 0.95 v s - 0.75 v v s - 1.1 v v ol output voltage low v s = 8v, i out = 50ma 0.75 0.95 v 1.1 v v oh output voltage high v s = 12v, i out = 5ma v s - 0.75 v s - 0.45 v v s - 0.75 v v ol output voltage low v s = 12v, i out = 5ma 0.45 0.8 v 0.8 v v oh output voltage high v s = 12v, i out = 50ma v s - 0.95 v s - 0.75 v v s - 1.1 v v ol output voltage low v s = 12v, i out = 50ma 0.75 0.95 v 1.1 v v oh output voltage high v s = 18v, i out = 5ma v s - 0.75 v s - 0.45 v v s - 0.75 v v ol output voltage low v s = 18v, i out = 5ma 0.45 0.8 v 0.8 v v oh output voltage high v s = 18v, i out = 50ma v s - 0.95 v s - 0.75 v v s - 1.1 v v ol output voltage low v s = 18v, i out = 50ma 0.75 0.95 v 1.1 v v ih_18 input voltage high threshold v s = 18v 3 v 3.1 v v il_18 input voltage low threshold v s = 18v 0.8 v 0.8 v v ihys_18 input voltage threshold hysteresis v s = 18v 100 mv v ih_12 input voltage high threshold v s = 12v 3 v 3.1 v v il_12 input voltage low threshold v s = 12v 0.8 v 0.8 v v hys_12 input voltage threshold hysteresis v s = 12v 100 mv v ih_8 input voltage high threshold v s = 8v 3 v 3.1 v v il_8 input voltage low threshold v s = 8v 0.8 v 0.8 v v hys_8 input voltage threshold hysteresis v s = 8v 100 mv uvlo_r rising undervoltage lockout 7.2 7.5 7.8 v 6.9 7.95 v uvlo_f falling undervoltage lockout 7.1 7.45 7.75 v 6.8 7.9 v hys_uvlo undervoltage lockout hysteresis uvlo_r - uvlo_f 23 mv 24 mv min_pw minimum input pulse width 100 ns electrical specifications v cc = 8v, 12v, 18v, t a = +25c, unless otherwise noted. boldface limits apply across the operating temperature range, -55c to +125c; over radiation total ionizing dose. (continued) parameter description test conditions min ( note 5 )typ max ( note 5 )unit
HS-4424DRH, hs4424deh 6 fn8747.2 october 15, 2015 submit document feedback transient response t r , t f , rise time 10% to 90% of v out v s = 18v, c l = 4300pf 75 ns v s = 18v, c l = 4300pf 95 ns v s = 18v, c l = 4300pf, post radiation 95 ns fall time 90% to 10% of v out v s = 18v, c l = 4300pf 75 ns v s = 18v, c l = 4300pf 95 ns vs = 18v, c l = 4300pf, post radiation 95 ns rise time 10% to 90% of v out v s = 12v, c l = 4300pf 75 ns v s = 12v, c l = 4300pf 95 ns v s = 12v, c l = 4300pf, post radiation 95 ns fall time 90% to 10% of v out v s = 12v, c l = 4300pf 75 ns v s = 12v, c l = 4300pf 95 ns v s = 12v, c l = 4300pf, post radiation 95 ns rise time 10% to 90% of v out v s = 8v, c l = 4300pf 75 ns v s = 8v, c l = 4300pf 95 ns v s = 8v, c l = 4300pf, post radiation 95 ns fall time 90% to 10% of v out v s = 8v, c l = 4300pf 75 ns v s = 8v, c l = 4300pf 95 ns v s = 8v, c l = 4300pf, post radiation 95 ns t phl , t plh , 50% of rising input to 10% of rising output v s = 18v, c l = 4300pf 200 ns v s = 18v, c l = 4300pf 300 ns v s = 18v, c l = 4300pf, post radiation 300 ns 50% of falling input to 90% of falling output v s = 18v, c l = 4300pf 200 ns v s = 18v, c l = 4300pf 300 ns v s = 18v, c l = 4300pf, post radiation 300 ns 50% of rising input to 10% of rising output v s = 12v, c l = 4300pf 250 ns v s = 12v, c l = 4300pf 350 ns v s = 12v, c l = 4300pf, post radiation 350 ns 50% of falling input to 90% of falling output v s = 12v, c l = 4300pf 250 ns v s = 12v, c l = 4300pf 350 ns v s = 12v, c l = 4300pf, post radiation 350 ns 50% of rising input to 10% of rising output v s = 8v, c l = 4300pf 300 ns v s = 8v, c l = 4300pf 400 ns v s = 8v, c l = 4300pf, post radiation 400 ns 50% of falling input to 90% of falling output v s = 8v, c l = 4300pf 300 ns v s = 8v, c l = 4300pf 400 ns v s = 8v, c l = 4300pf, post radiation 400 ns note: 5. compliance to datasheet limits is assured by one or more methods; production test, characterization and/or design. electrical specifications v cc = 8v, 12v, 18v, t a = +25c, unless otherwise noted. boldface limits apply across the operating temperature range, -55c to +125c; over radiation total ionizing dose. (continued) parameter description test conditions min ( note 5 )typ max ( note 5 )unit
HS-4424DRH, hs4424deh 7 fn8747.2 october 15, 2015 submit document feedback typical performance curves unless otherwise specified, v s = 8v, 12v, 18v, c l = 4300pf, t a = +25c. figure 5. supply current vs temperature figure 6. supply current vs dual switching at frequency figure 7. output voltage vs temperature (5ma) f igure 8. output voltage vs temperature (50ma) figure 9. output voltage vs output current figure 10. input voltage threshold vs temperature and bias voltage 0 0.5 1.0 1.5 2.0 2.5 3.0 -55 25 125 supply current (ma) temperature (c) iccsbh_18 iccsbh_8 iccsbl_18 iccsbl_8 supply current (ma) frequency (hz) 0 50 100 150 200 1k 10k 100k 1m 18v_bias 8v_bias output voltage to supply temperature (c) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -55 25 125 voh_18_5 voh_8_5 vol_18_5 vol_8_5 or gnd (v) 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 -55 25 125 temperature (c) output voltage to supply voh_18_50 voh_8_50 vol_18_50 or gnd (v) vol_8_50 0 0.5 1.0 1.5 2.0 2.5 3.0 0 3 6 9 30 60 90 199 349 498 output voltage to 8v supply output current (ma) v oh -55 v ol -55 v oh +25 v ol +25 v oh +125 v ol +125 v oh +85 v ol +85 or gnd (v) 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 -55 25 125 input voltage threshold (v) temperature (c) 18v v ih 12v v ih 8v v ih 12v v il 8v v il 18v v il
HS-4424DRH, hs4424deh 8 fn8747.2 october 15, 2015 submit document feedback figure 11. input current vs temperature and bias voltage figure 12. propagation delay vs temperature figure 13. rise/fall time vs temperature figure 14. 1mhz at 8v bias figure 15. 1mhz at 18v bias figure 16. 8v rising/falling propagation time typical performance curves unless otherwise specified, v s = 8v, 12v, 18v, c l = 4300pf, t a = +25c. (continued) -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 -55 25 125 input current (a) temperature (c) iih_18 iih_8 iil_18 iil_8 0 50 100 150 200 250 300 -55 25 125 propagation delay (ns) temperature (c) tphl_8 tplh_8 tphl_12 tphl_18 tplh_12 tplh_18 35 40 45 50 55 60 65 70 -55 25 125 rise/fall (ns) temperature (c) tf_8 tr_8 tf_12 tf_18 tr_18 tr_12 ? input 5v/div output 2v/div 1s/div ? input 5v/div output 5v/div 1s/div ? input 5v/div output 2v/div 100ns/div
HS-4424DRH, hs4424deh 9 fn8747.2 october 15, 2015 submit document feedback figure 17. 12v rising/falling propagation time figure 18. 18v rising/f alling propagation time figure 19. rise time figure 20. fall time figure 21. uvlo output high z vs vcc figure 22. 18v, 1mhz operating ir temp typical performance curves unless otherwise specified, v s = 8v, 12v, 18v, c l = 4300pf, t a = +25c. (continued) ? input 5v/div output 2v/div 100ns/div ? input 5v/div output 5v/div 100ns/div ? 20ns/div 18v bias 12v bias 8v bias ? 18v bias 12v bias 8v bias 20ns/div 0.01 0.1 1 10 1000 100 01234567 vcc (v) output impedence (m) max temp = 100 c
HS-4424DRH, hs4424deh 10 fn8747.2 october 15, 2015 submit document feedback post high, low dose rate radiation characteristics unless otherwise specified, v s = 12v, t a = +25c. this data is typical mean test data post 300krad (si) ra diation exposure at a high dose exposure rate of 50 to 300rad (si)/s and post 50krad (si) radiation exposure at a high dose exposure rate of <10mrad(si)/s. this data is intended to show typical parame ter shifts due to high dose rate radiation. these are not limits nor are they guaranteed. figure 23. 18v supply current vs hdr radiation figure 24. 18v input current vs hdr radiation figure 25. output voltage vs hdr radiation figure 26. propagation delay vs hdr radiation figure 27. rise/fall time vs hdr radiation 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0 krad(si) supply current (ma) 300 i ccsb high i ccsb low -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 0 krad(si) input current (a) 300 i il a i il b i ih a i ih b 0.310 0.315 0.320 0.325 0.330 0.335 0.340 0.345 0.350 0.355 0.360 11.40 11.41 11.42 11.43 11.44 11.45 11.46 11.47 11.48 11.49 11.50 0 300 krad(si) v ol (v) v oh (v) v ol b v ol a v oh a v oh b 165 170 175 180 185 190 195 200 205 0 krad(si) propagation delay (ns) 300 t phl b t plh b t plh a t phl a 62.0 62.5 63.0 63.5 64.0 64.5 65.0 0 300 krad(si) rise/fall time (ns) t r a t r b t f b t f a
HS-4424DRH, hs4424deh 11 fn8747.2 october 15, 2015 submit document feedback figure 28. 18v supply current vs ldr radiation figure 29. 18v input current vs ldr radiation figure 30. output voltage vs ldr radiation figure 31. propagation delay vs ldr radiation figure 32. rise/fall time vs ldr radiation post high, low dose rate radiation characteristics unless otherwise specified, v s = 12v, t a = +25c. this data is typical mean test data post 300krad (si) ra diation exposure at a high dose exposure rate of 50 to 300rad (si)/s and post 50krad (si) radiation exposure at a high dose exposure rate of <10mrad(si)/s. this data is intended to show typical parame ter shifts due to high dose rate radiation. these are not limits nor are they guaranteed. (continued) krad(si) supply current (ma) 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 050 i ccsb high i ccsb low -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0 krad(si) input current (a) 50 i il a i il b i ih a i ih b v ol (v) v oh (v) 0.282 0.284 0.286 0.288 0.290 0.292 0.294 0.296 0.298 0.300 0.302 11.40 11.41 11.42 11.43 11.44 11.45 11.46 11.47 11.48 11.49 11.50 050 v ol a v oh a v ol b v oh b krad(si) 154 156 158 160 162 164 166 168 170 050 krad(si) propagation delay (ns) t phl b t plh b t plh a t phl a 40 42 44 46 48 50 52 54 56 58 050 krad(si) rise/fall time (ns) t r a t r b t f b t f a
HS-4424DRH, hs4424deh 12 fn8747.2 october 15, 2015 submit document feedback applications information functional description the hs-4424dxh mosfet drivers are designed for easy implementation with a pwm controller, such as the hs-1825arh, as the input control signal driver. the hs-4424dxh consist of two independent drivers sharing bias voltage and ground connections at the die level. undervoltage lockout and operating voltage range the hs-4424dxh have a guaranteed uvlo of <8v across the operating temperature range. all devices are recommended to operate up to and are characterize d and tested at a bias of 18v. the uvlo feature ensures that the internal mosfet drivers have sufficient gate drive to operate in their saturated mode. when in a uvlo condition the hs-4424dxh outputs are put into a high impedance tri-stated mode. characterization and testing occu rs (as appropriate) at 8v, 12v and 18v and across the -55c to +125c operating temperature range. input characteristics the hs-4424dxh inputs are designed to be used with low voltage level signals (<1v for a low input level and >3v for a high input level) and also be capable of accepting input voltages up to the vcc level. output buffer the hs-4424dxh output buffers are designed to drive >2a of peak output current into high capacitance loads and can be paralleled to increase the output current capability. the output buffer uses a final drive stage comprised of a pnp lower and npn upper complimentar y pair of transistors for the high output current drive. to enhance the pull-up and pull-down of this bipolar pair, they are each paralleled with mos devices to do so. power dissipation and junction temperature it is possible to exceed th e +150c maximum recommended junction temperature under ce rtain load and power supply conditions. calculate power dissipation using equation 1 ; where pd = power dissipation v = supply voltage i = operating supply current c = load capacitance f = operating frequency calculate junction temperature t j using equation 2 : where t j = junction temperature pd = power dissipation theta jc = junction-to-case thermal resistance t c = case temperature pcb layout guidelines use a ground plane in the pcb design, connect gnd a and gnd b pins directly to the ground plane in the same area, preferably close to the ic. reference all input circuitry including in a and in b to a common node and re ference all output circuitry including all out a and out b pins to a common node. bypass each vcc pin to the ground plane with a 0.047f ceramic chip capacitor in parallel with a 4.7f low esr solid tantalum capacitor. clamp both out pins to vcc, each with a single diode. the 1n5819 (1a, 40v) schottky diode is recommended. pd v i 2 c ? v 2 ? f ? + ? = (eq. 1) t j pd theta jc t c + ? = (eq. 2)
HS-4424DRH, hs4424deh 13 fn8747.2 october 15, 2015 submit document feedback die characteristics die dimensions 4890m x 3370m (193mils x 133mils) thickness: 483m 25.4m (19mils 1mil) interface materials glassivation type: psg (phosphorous silicon glass) thickness: 8.0k? 1.0k? top metallization type: alsicu thickness: 16.0k? 2k? backside finish silicon process radiation hardened silicon gate (di) assembly related information substrate potential floating (di) lid potential floating additional information worst case current density < 2 x 10 5 a/cm 2 transistor count 125 weight of packaged device 0. 591 grams (typical) lid characteristics finish: gold case isolation to any lead: 20 x10 9 (minimum) metallization mask layout gnd (5) in b (7) out b (10) out b (11) v cc (12) v cc (13) gnd (4) in a (2) out a (15) out a (14)
HS-4424DRH, hs4424deh 14 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8747.2 october 15, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change october 15, 2015 fn8747.2 added part number hs-4424deh throughout datasheet. july 1, 2015 fn8747.1 abs max ratings on page 4 - removed abs max input current and related text on page 13. esd ratings - changed machine model from: 1kv to: 200v and charged device model from: 4kv to: 750v changed over temp limits for uvlo rising from: mi n/max 7.0/7.9 to: 6.9/7.95 and falling min/max from: 6.9/7.85 to: 6.8/7.9. changed over temp 8v, 5ma voh limit min from v s - 0.75 to v s - 0.9. june 8, 2015 fn8747.0 initial release
HS-4424DRH, hs4424deh 15 fn8747.2 october 15, 2015 submit document feedback package outline drawing k16.a 16 lead ceramic metal seal flatpack package rev 2, 1/10 side view top view section a-a -d- -c- seating and base plane -h- base lead finish metal pin no. 1 id area 0.022 (0.56) 0.015 (0.38) 0.050 (1.27 bsc) 0.440 (11.18) 0.005 (0.13) min max 0.115 (2.92) 0.045 (1.14) 0.045 (1.14) 0.026 (0.66) 0.285 (7.24) 0.245 (6.22) 0.009 (0.23) 0.004 (0.10) 0.370 (9.40) 0.250 (6.35) 0.03 (0.76) min 0.13 (3.30) min 0.006 (0.15) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) max 0.022 (0.56) 0.015 (0.38) 0.015 (0.38) 0.008 (0.20) pin no. 1 id optional 1 2 4 6 3 lead finish 1. adjacent to pin one and shall be located within the shaded area shown. the manufacturers identification shall not be used as a pin on e identification mark. alternately, a tab may be used to identify pin one. 2. of the tab dimension do not apply. 3. the maximum limits of lead dimensions (section a-a) shall be measured at the centroid of the finished lead surfaces, when so lder dip or tin plate lead finish is applied. 4. 5. shall be molded to the bottom of the package to cover the leads . 6. meniscus) of the lead from the body. dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 7. 8. notes: dimensioning and tolerancing per ansi y14.5m - 1982. controlling di mension: inch. index area: a notch or a pin one i dentification mark shall be l ocated if a pin one identification mark is used in addition to a tab, the limits measure dimension at all four corners. for bottom-brazed lead packages, no organic or polymeric materi als dimension shall be measured at the point of exit (beyond the

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