features x hvcmos ? technology for high performance x very low quiescent power dissipation (-10a max.) x output on-resistance typically (22 typ.) x integrated bleed resistors on the outputs x low parasitic capacitances ? dc to 50mhz small signal frequency response x -60db typical output off isolation at 5.0mhz x cmos logic circuitry for low power x excellent noise immunity x on-chip shift register, latch and clear logic circuitry x flexible high volta ge supplies applicatio ns x medical ultraso und imaging x piezoelectric transdu cer drivers block diagram low charge injection, 8-channel, high voltage analog switches with bleed resistors general description the supertex hv230 is a low charge injection 8-channel, high-voltage, analog switch integrated circuit (ic) with bleed resistors. this device can be used in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. the bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. to reduce any possible clock feed-through noise, latch enable (le) should be left high until all bits are clocked in. using hvcmos ? technology, this switch combines high voltage bilateral dmos switches and low power cmos logic to provide effcient control of high voltage analog signals. this ic is suitable for various combinations of high voltage supplies, e.g., v pp /v nn : +50v/-150v, or +100v/-100v. le cl sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 vpp vnn vdd rgnd dout din clk 8-bit shift register latches level shifters output switches d le cl d le cl d le cl d le cl d le cl d le cl d le cl d le cl supertex inc. supertex inc. www .supertex.com doc.# dsfp-hv230 c071613 hv230
2 absolute maximum ratings parameter value v dd logic power supply voltage -0.5v to +15v v pp - v nn supply voltage 220v v pp positive high voltage supply -0.5v to v nn +200v v nn negative high voltage supply +0.5v to -200v logic input voltages -0.5v to v dd +0.3v analog signal range v nn to v pp peak analog signal current/channel 3.0a storage temperature -65 o c to +150 o c power dissipation: 26-lead llga 26-ball fpbga 1.0w 1.0w absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. pin configuration product marking 26-ball fpbga (top view) 26-ball fpbga yy = year sealed ww = week sealed l = lot number = ?green? packaging yyww hv230ga lllllll a b c d e f g h 1 2 3 4 5 6 7 8 9 26-lead llga yy = year sealed ww = week sealed l = lot number = ?green? packaging yyww hv230g1 llllllll 26-lead llga (top view) 1 26 2 18 10 package may or may not include the following marks: si or package may or may not include the following marks: si or ordering information part number package option packing hv230g1-g 26-lead llga 400/tray HV230GA-G 26-ball fpbga consult factory -g denotes a lead (pb)-free / rohs compliant package typical thermal resistance package ja 26-lead llga 41 o c/w 26-ball fpbga - operating conditions sym parameter value v dd logic power supply voltage 1,3 4.5v to 13.2v v pp positive high voltage supply 1,3 40v to v nn +200v v nn negative high voltage supply 1,3 -40v to -160v v ih high level input voltage v dd -1.5v to v dd v il low-level input voltage 0v to 1.5v v sig analog signal voltage peak-to-peak 2 v nn +10v to v pp -10v t a operating free air temperature 0 o c to 70 o c notes: 1. power up/down sequence is arbitrary except gnd must be powered-up first and powered-down last. 2. v sig must be v nn v sig v pp or floating during power up/down transition. 3. rise and fall times of power supplies v dd , v pp , and v nn should not be less than 1.0msec. supertex inc. www .supertex.com doc.# dsfp-hv230 c071613 hv230
3 sym parameter 0 o c +25 o c +70 o c unit conditions min max min typ max min max r ons small signal switch on-resistance - 30 - - 38 - 48 i sig = 5.0ma v pp = +40v v nn = -160v - 25 - - 27 - 32 i sig = 200ma - 25 - - 27 - 30 i sig = 5.0ma v pp = +100v v nn = -100v - 18 - - 24 - 27 i sig = 200ma - 23 - - 25 - 30 i sig = 5.0ma v pp = +160v v nn = -40v - 22 - - 25 - 27 i sig = 200ma r ons small signal switch on-resistance matching - 20 - - 20 - 20 % i sig = 5.0ma, v pp = +100v, v nn = -100v r onl large signal switch on-resistance - - - 15 - - - v sig = v pp -10v, i sig = 1.0a r int output switch shunt resistance - - 20 - 50 - - k output switch to r gnd i rint = 0.5ma i sol switch off leakage per switch - 5.0 - - 10 - 15 a v sig = v pp -10v v os dc offset switch off - 300 - - 300 - 300 mv no load dc offset switch on - 500 - - 500 - 500 mv no load i ppq quiescent v pp supply current - - - - 50 - - a all switches off i nnq quiescent v nn supply current - - - - -50 - - a all switches off i ppq quiescent v pp supply current - - - - 50 - - a all switches on, i sw = 5.0ma i nnq quiescent v nn supply current - - - - -50 - - a all switches on, i sw = 5.0ma i sw switch output peak current - 3.0 - 2.0 - 2.0 a v sig duty cycle -0.1% f sw output switching frequency - - - - 50 - - khz duty cycle = 50% i pp supply current - 6.5 - - 7.0 - 8.0 ma v pp = +40v v nn = -160v all output switches are turning on and off at 50khz with no load - 4.0 - - 5.0 - 5.5 v pp = +100v v nn = -100v - 4.0 - - 5.0 - 5.5 v pp = +160v v nn = -40v i nn supply current - 6.5 - - 7.0 - 8.0 ma v pp = +40v v nn = -160v all output switches are turning on and off at 50khz with no load - 4.0 - - 5.0 - 5.5 v pp = +100v v nn = -100v - 4.0 - - 5.0 - 5.5 v pp = +160v v nn = -40v i dd logic supply average current - 4.0 - - 4.0 - 4.0 ma f clk = 5.0mhz, v dd = 5.0v i ddq logic supply quiescent current - 10 - - 10 - 10 a --- i sor data out source current 0.45 - 0.45 - - 0.40 - ma v out = v dd -0.7v i sink data out sink current 0.45 - 0.45 - - 0.40 - ma v out = 0.7v c in logic input capacitance - 10 - - 10 - 10 pf --- dc electrical characteristics (over operating conditions unless otherwise specified ) supertex inc. www .supertex.com doc.# dsfp-hv230 c071613 hv230
4 sym parameter 0 o c +25 o c +70 o c unit conditions min max min typ max min max t sd set up time before le rises 150 - 150 - - 150 - ns --- t wle time width of le 150 - 150 - - 150 - ns --- t do clock delay time to data out 55 150 60 - 150 70 150 ns --- t wcl time width of cl 150 - 150 - - 150 - ns --- t su set up time data to clock 15 - 15 - - 20 - ns --- t h hold time data from clock 35 - 35 - - 35 - ns --- f clk clock frequency - 5.0 - - 5.0 - 5.0 mhz 50% duty cycle, f data = f clk /2 t r , t f clock rise and fall times - 1.0 - - 1.0 - 1.0 s --- t on turn on time - 5.0 - - 5.0 - 5.0 s v sig = v pp - 10v, r l = 10k t off turn off time - 5.0 - - 5.0 - 5.0 s v sig = v pp - 10v, r l = 10k dv/dt maximum v sig slew rate - 20 - - 20 - 20 v/ns v pp = +160v, v nn = -40v - 20 - - 20 - 20 v pp = +100v, v nn = -100v - 20 - - 20 - 20 v pp = +40v, v nn = -160v k o off isolation -30 - -30 - - -30 - db f = 5.0mhz, 1.0k/15pf load -58 - -58 - - -58 - f = 5.0mhz, 50 load k cr switch crosstalk -60 - -60 - - -60 - db f = 5.0mhz, 50 load i id output switch isolation diode current - 300 - - 300 - 300 ma 300ns pulse width, 2.0% duty cycle c sg(off) off capacitance sw to gnd 5.0 17 5.0 - 17 5.0 17 pf 0v, f = 1.0mhz c sg(on) on capacitance sw to gnd 25 50 25 - 50 25 50 pf 0v, f = 1.0mhz +v spk output voltage spike - - - - 150 - - mv v pp = +40v, v nn = -160v, r l = 50 -v spk - - - - 150 - - +v spk - - - - 150 - - v pp = +100v, v nn = -100v, r l = 50 -v spk - - - - 150 - - +v spk - - - - 150 - - v pp = +160v, v nn = -40v, r l = 50 -v spk - - - - 150 - - ac electrical characteristics (over recommended operating conditions, v dd = 5.0v, unless otherwise specified) supertex inc. www .supertex.com doc.# dsfp-hv230 c071613 hv230
5 data in le clock data out off on v out (typ) 50% 50% 50% 50% t wle t sd t su t h 50% 50% t off 50% t do t on t wcl clr d n+1 d n d n-1 50% 50% 90% 10% logic timing waveforms truth table d0 d1 d2 d3 d4 d5 d6 d7 le clk sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on x x x x x x x x h l hold previous state x x x x x x x x x h all switches off notes: 1. the eight switches operate independently. 2. serial data is clocked in on the l to h transition of the clk. 3. the switches go to a state retaining their present condition at the rising edge of le. when le is low the shift register data flow through the latch. 4. d out is high when data in the shift register 7 is high. 5. shift register clocking has no effect on the switch states if le is high. 6. the clr clear input overrides all other inputs. supertex inc. www .supertex.com doc.# dsfp-hv230 c071613 hv230
6 switch off leakage i sol v pp ?10v dc offset on/off v out t on /t off t est circuit 5.0v vpp vnn vdd gnd v pp ?10v r l 10k v out isolation diode current i id v nn v sig crosstalk k cr = 20log v out v in v in = 10 v p ? p @5mhz nc 50 50 charge injection v sig v out 1000pf q = 1000pf x dv out dv out output v oltage spike vout 1k rl 50 +v spk ?v spk off isolation k o = 20log v out v in v in = 10 v p ? p @5mhz r l v out open r gnd r gnd open r gnd r gnd r gnd r gnd rgnd r gnd 5.0v vpp vnn vdd gnd v pp 5.0v v nn vpp vnn vdd gnd 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd 5.0v vpp vnn vdd gnd v pp v nn v pp v nn v pp v nn v pp v nn v pp v nn v pp v nn v pp v nn test circuits supertex inc. www .supertex.com doc.# dsfp-hv230 c071613 hv230
7 pin function pin function 1 sw4 14 vdd 2 sw3 15 din 3 sw3 16 clk 4 sw2 17 le 5 sw2 18 cl 6 sw1 19 dout 7 sw1 20 sw7 8 sw0 21 sw7 9 sw0 22 sw6 10 vpp 23 sw6 11 vnn 24 sw5 12 rgnd 25 sw5 13 gnd 26 sw4 pin description (26-ball fpbga) ball location function ball location function a4 sw1 e1 sw4 c3 sw2 e3 sw4 c4 sw1 e4 sw5 c5 sw0 e5 sw7 c6 vpp e6 le c7 vnn e7 clk d1 sw3 e9 din d3 sw3 f3 sw5 d4 sw2 f4 sw6 d5 sw0 f5 sw7 d6 rgnd f6 dout d7 gnd f7 clr d9 vdd h4 sw6 pin description (26-lead llga) supertex inc. www .supertex.com doc.# dsfp-hv230 c071613 hv230
8 symbol a a1 b d d1 d2 d3 d4 e e l l1 dimension (mm) min 0.50 0.00 0.25 5.90 1.050 ref 0.400 ref 0.725 ref 0.925 ref 5.90 0.65 bsc 0.25 0.10 ref nom 0.55 - 0.35 6.00 6.00 0.35 max 0.60 0.05 0.45 6.10 6.10 0.45 drawings not to scale. supertex doc. #: dspd-26llgag1, version a090808. 26-lead llga package outline (g1) 6.00x6.00mm body, 0.60mm height (max), 0.65mm pitch bottom view pin 1 pin 2 a a1 seating plane d note 1 (index area d/2 x e/2) 1 26 top view side view ll b detail a detail b 0.10 x 45 o detail b e 7xe 7xe l1 detail a x25 2 l1 e d1 d2 d3 d4 e note 1 (index area d/2 x e/2) d3 d1 d2 d4 b note: 1. a pin 1 identifier must be located in the index area indicated. the pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. supertex inc. www .supertex.com doc.# dsfp-hv230 c071613 hv230
9 (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information go to http://www.supertex.com/packaging.html .) 26-ball fpbga package outline (ga) 6.00x5.35mm body, 1.20mm height (max), 0.65mm pitch symbol a a1 a2 b d d1 e e1 e sd se dimension (mm) min 0.844 0.18 0.664 0.25 5.90 5.20 bsc 5.25 4.55 bsc 0.65 bsc 0.65 bsc 0.325 bsc nom 0.994 0.23 0.764 0.30 6.00 5.35 max 1.200 0.28 0.864 0.35 6.10 5.45 drawings not to scale. supertex doc. #: dspd-26fpbgaga, version a092208. a b c d e f g h seating plane a2 d e e e1 d1 e sd se a a1 b 98765432 1 te rminal a1 corner index area (d/4 x e/4) note 1 note 2 vi ew b to p v iew side v iew bottom v iew vi ew b notes: 1. a ball a1 identifier must be located in the index area indicated. the ball a1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. corner a1 identifier (actual shape may vary). supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com doc.# dsfp-hv230 c071613 hv230
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