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general description features ics9250-09 integrated circuit systems, inc. block diagram frequency timing generator for pentium ii systems 9250-09 rev j 1/21/00 pin configuration 56-pin ssop
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ics9250-09 pin descriptions pin number pin name type description 1 gndref pwr gnd pin for ref clocks 2, 3 ref(0:1) out 14.318mhz reference clock outputs at 3.3v 4 vddref pwr power pin for ref clocks 5 x1 in xtal_in 14.318mhz crystal input 6 x2 out xtal_out crystal output 7, 13, 19 gndpci pwr gnd pin for pciclks 8 pciclk_f out free running pci clock at 3.3v. synchronous to cpu clocks. not affected by the pci_stop# input. 9, 11, 12, 14, 15, 17, 18 pciclk[1:7] out pci clock outputs at 3.3v. synchronous to cpu clocks. 10, 16 vddpci pwr 3.3volts power pin for pciclks 20, 24 gnd66 pwr gnd pin for 3v66 outputs 21, 22, 25, 26 3v66[0:3] out 66mhz outputs at 3.3v. these outputs are stopped when cpu_stop# is driven active.. 23, 27 vdd66 pwr power pin for the 3v66 clocks. 28 sel 133/100# in this selects the frequency for the cpu and cpu/2 outputs. high = 133mhz, low=100mhz 29 gnd48 pwr ground pin for the 48mhz output 30 48mhz out fixed 48mhz clock output. 3.3v 31 vdd48 pwr power pin for the 48mhz output. 32, 33 sel[0:1] in function select pins. see truth table for details. 34 spread# in enables spread spectrum when active(low). modulates all the cpu, pci, ioapic, 3v66 and cpu/2 clocks. does not affect the ref and 48mhz clocks. 0.5% down spread modulation. 35 pd# in this asynchronous input powers down the chip when drive active(low). the internal plls are disabled and all the output clocks are held at a low state. 36 cpu_stop# in this asychronous input halts the cpuclk[0:3] and the 3v66[0:3] clocks at l ogic "0" when driven active(low). does not affect the cpu/2 clocks. 37 pci_stop# in this asynchronous input halts the pciclk[1:7] at logic"0" when driven active(low). pciclk_f is not affected by this input. 38 gndcor pwr ground pin for the pll core 39 vddcor pwr power pin for the pll core. 3.3v 43, 47 vddlcpu pwr power pin for the cpuclks. 2.5v 40, 44 gndlcpu pwr ground pin for the cpuclks 41, 42, 45, 46 cpuclk[0:3] out host bus clock output at 2.5v. 133mhz or 100mhz depending on the state of the sel 133/100mhz. 48 gndlcpu/2 pwr ground pin for the cpu/2 clocks. 49, 50 cpu/2[0:1] out 2.5v clock outputs at 1/2 cpu frequency. 66mhz or50mhz depending on the state of the sel 133/100# input pin. 51 vddlcpu/2 pwr power pin for the cpu/2 clocks. 2.5v 52 gndlioapic pwr ground pin for the ioapic outputs. 53, 54, 55 ioapic[0:2] out ioapic clocks at 2.5v. synchronous with cpuclks but fixed at 16.67mhz. 56 vddlioapic pwr power pin for the ioapic outputs. 2.5v.
ics9250-09 frequency select:
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ics9250-09 power management requirements:
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7+*= group offset group offset measurement loads measure points cpu to 3v66 0.0-1.5ns cpu leads cpu @ 20pf, 3v66 @ 30pf cpu @1.25v, 3v66 @ 1.5v 3v66 to pci 1.5-4.0ns 3v66 leads 3v66 @ 30pf, pci @ 30pf 3v66 @ 1.5v, pci @ 1.5v cpu to ioapic 1.5-4.0ns cpu leads cpu @ 20pf, ioapic @ 20pf cpu @1.25v, ioapic @ 1.5v note: 1. all offsets are to be measured at rising edges. e lectrical characteristics - input/supply/common output parameters t a = 0 - 70o c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v i h 2v dd +0.3 v input low voltage v i l v s s -0.3 0.8 v input high current i i h v i n = v dd 0.1 5 a input low current i i l1 v i n = 0 v; inputs with no pull-up resistors -5 2.0 a input low current i i l2 v i n = 0 v; inputs with pull-up resistors -200 -100 a operating i dd3.3op100 select @ 100mhz; max discrete cap loads 68 180 supply current i dd3.3op133 select @ 133mhz; max discrete cap loads 80 power down supply current input frequency f i v dd = 3.3 v 12 14.318 16 mhz c i n logic inputs 5 pf c i nx x1 & x2 pins 27 36 45 pf transition time 1 t tran s to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 1 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3ms 1 guaranteed by design, not 100% tested in production. input capacitance 1 i dd3.3pd c l = 0 pf; pwrdwn# = 0 ua 200 62 ma electrical characteristics - input/supply/common output parameters t a = 0 - 70 o c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwis e s tated) parameter symbol conditions min typ max units operating i dd2.5op66 select @ 100mhz; max discrete cap loads 19 25 supply current i dd2.5op100 select @ 133mhz; max discrete cap loads 22 40 1 guaranteed by design, not 100% tested in production. ma
$ ics9250-09 electrical characteristics - cpuclk t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2 b i oh = -12.0 ma 2 2.2 v output low voltage v ol2 b i ol = 12 ma 0.3 0.4 v output high current i oh2 b v oh = 1.7 v -35 -19 ma output low current i ol2 b v ol = 0.7 v 19 27 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.2 1.6 ns fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v 0.4 1.25 1.6 ns duty cycle d t2b 1 v t = 1.25 v 454855% skew t sk2b 1 v t = 1.25 v 80 175 ps jitter, one sigma t j1 2b 1 v t = 1.25 v 20 150 ps jitter, absolute t jabs2b 1 v t = 1.25 v -250 61 +250 ps jitter, cycle-to-cycle t jcyc-cyc2b 1 v t = 1.25 v 150 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - cpu/2 t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2 b i oh = -12.0 ma 2 2.3 v output low voltage v ol2 b i ol = 12 ma 0.3 0.4 v output high current i oh2 b v oh = 1.7 v -35 -19 ma output low current i ol2 b v ol = 0.7 v 19 27 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.1 1.6 ns fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v 0.4 1 1.6 ns duty cycle d t2b 1 v t = 1.25 v 454855% jitter, one sigma t j1 2b 1 v t = 1.25 v 20 150 ps jitter, absolute t jabs2b 1 v t = 1.25 v -250 70 +250 ps jitter, cycle-to-cycle t jcyc-cyc2b 1 v t = 1.25 v 100 250 ps 1 guaranteed by design, not 100% tested in production.
ics9250-09 electrical characteristics - 3v66 t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l =30 pf parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.4 3.1 v output low voltage v ol1 i ol = 9.4 ma 0.25 0.4 v output high current i oh1 v oh = 2.0 v -60 -22 ma output low current i ol1 v ol = 0.8 v 25 44 ma ris e time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.6 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.3 2 ns duty cycle 1 d t1 v t = 1.5 v 45 48 55 % skew 1 t sk1 v t = 1.5 v 120 175 ps jitter, one sigma 1 t j1 1 v t = 1.5 v 43 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v -250 100 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 150 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - pciclk t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 60 pf for pci0 & pci1, cl = 30 pf for other pcis parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.4 3.1 v output low voltage v ol1 i ol = 9.4 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -60 -22 ma output low current i ol1 v ol = 0.8 v 25 45 ma ris e time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.7 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.6 2 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % skew 1 t sk1 v t = 1.5 v 360 500 ps jitter, one sigma 1 t j1 1 v t = 1.5 v 18 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v -250 80 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 155 500 ps 1 guaranteed by design, not 100% tested in production.
% ics9250-09 electrical characteristics - 48mhz, ref t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.6 2.9 v output low voltage v ol5 i ol = 9 ma 0.3 0.4 v output high current i oh5 v oh = 2.0 v -35 -22 ma output low current i ol5 v ol = 0.8 v 17 23 ma ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v, 48mhz 2 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v, 48mhz 2 4 ns duty cycle 1 d t5 v t = 1.5 v, 48mhz 45 50 55 % ris e time 1 t r5 vol = 0.4 v, voh = 2.4 v, ref 2.2 4 n s fall time 1 t f5 voh = 2.4 v, vol = 0.4 v, ref 1.9 4 n s duty cycle 1 d t5 vt = 1.5 v, ref 45 52 55 % jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v, 48mhz 200 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v, ref 800 1000 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ioapic t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh4b i oh = -12 ma 2 2.23 v output low voltage v ol4b i ol = 12 ma 0.3 0.4 v output high current i oh4b v oh = 1.7 v -36 -16 ma output low current i ol4b v ol = 0.7 v 19 26 ma ris e time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 0.4 1.3 1.6 ns fall time 1 t f4 b v oh = 2.0 v, v ol = 0.4 v 0.4 1.25 1.6 ns duty cycle 1 d t4b v t = 1.25 v 45 49 55 % jitter, one sigma 1 t j1 4b v t = 1.25 v 14 150 ps jitter, absolute 1 t jabs4b v t = 1.25 v -250 65 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc4b v t = 1.25 v 87 500 ps 1 guaranteed by design, not 100% tested in production.
%% ics9250-09 c3 1 clock load c1 c1 2 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 ferrite bead vdd c2 22f/20v tantalum ferrite bead vdd c2 22f/20v tantalum 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 = routed power = ground connection key (component side copper) = ground plane connection = power route connection = solder pads = clock load 3.3v power route 3.3v power route 2.5v power route &'(( ) *+ &+ '*+7 7*
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% ics9250-09 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. l o b m y ss n o i s n e m i d n o m m o cs n o i t a i r a vdn . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .2 0 1 .0 1 1 .d a0 2 7 .5 2 7 .0 3 7 .6 5 1 a8 0 0 .2 1 0 .6 1 0 . 2 a7 8 0 .0 9 0 .4 9 0 . b8 0 0 .- 5 3 1 0 . c5 0 0 .-0 1 0 . ds n o i t a i r a v e e s e1 9 2 .5 9 2 .9 9 2 . ec s b 5 2 0 . 0 h5 9 3 .-0 2 4 . h0 1 0 .3 1 0 .6 1 0 . l0 2 0 .-0 4 0 . ns n o i t a i r a v e e s 0- 8 56 pin 300 mil ssop package ?for current dimensional specifications, see jedec 95.? .093 dia. pin (optional) d/2 e/2 bottom view a 2 see detail ?a? -e- c end view h pin 1 top view index area parting line l detail ?a? a 1 -e- b a side view -c- -d- seating plane .004 c ordering information ics9250 y f-09-t

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