View IS66WVE1M16BLL_8933802.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com overview the is66/67wve1m16eall/bll/cll is an integrated memory device containing 16mbit pseudo static random access memory using a self - refresh dram array organized as 1m words by 16 bits. the device includes several power saving modes : partial array refresh mode where data is retained in a portion of the array and deep power down mode. both these modes reduce standby current drain. the die has separate power rails, vddq and vssq for the i/o to be run from a separate power supply from the device core. ? asynchronous and page mode interface ? dual voltage rails for optional performance ? all: vdd 1.7v~1.95v, vddq 1.7v~1.95v ? bll: vdd 2.7v~3.6v, vddq 2.7v~3.6v ? cll: vdd 1.7v~1.95v, vddq 2.7v~3.6v ? page mode read access ? interpage read access : 55ns, 70ns ? intrapage read access : 20ns ? low power consumption ? asynchronous operation < 30 ma ? intrapage read < 23ma ? standby < 150 a (max.) ? deep power - down (dpd ) ? all/cll: < 3a ( typ ) ? bll: < 10a ( typ ) ? low power feature ? temperature controlled refresh ? partial array refresh ? deep power - down (dpd) mode ? operating temperature range industrial: - 40 c~85 c automotive a1: - 40 c~85 c ? packages: 48 - ball tfbga, 48 - pin tsop - i 16mb async /page psram features copyright ? 2014 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specification and it s products at any time without notice. issi assumes no liability arising out of the application or use of any information, pr odu cts or services described herein. customers are advised to obtain the latest version of this device specification before relying on any publi she d information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fa ilu re or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives wri tte n assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances notes : 1. the 48 - pin tsop - i package option is not yet available. please contact sram marketing at sram@issi.com for additional information. preliminary information
2 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com general description psram products are high - speed, cmos pseudo - static random access memory developed for low - power, portable applications. the 16mb dram core device is organized as 1 meg x 16 bits. these devices include the industry - standard, asynchronous memory interface found on other low - power sram or pseudo - sram (psram) offerings. for seamless operation on an asynchronous memory bus, psram products incorporated a transparent self - refresh mechanism. the hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. a user - accessible configuration registers (cr) defines how the psram device performs on - chip refresh and whether page mode read accesses are permitted. this register is automatically loaded with a default setting during power - up and can be updated at any time during normal operation. special attention has been focused on current consumption during self - refresh. this product includes two system - accessible mechanisms to minimize refresh current. setting sleep enable (zz#) to low enables one of two low - power modes: partial - array refresh (par) or deep power - down (dpd). par limits refresh to only that part of the dram array that contains essential data. dpd halts refresh operation altogether and is used when no vital information is stored in the device. the system - configurable refresh mechanisms are accessed through the cr. [ functional block diagram] address decode logic configuration register (cr) 1m x 16 dram memory array input /output mux and buffers dq0~dq15 a0~a19 control logic ce# we# oe# lb# ub# zz#
3 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com 48ball tfbga ball assignment [top view] (ball down) 1 2 3 4 5 6 a b c d e f g h lb# oe# a0 dq8 ub# a3 dq9 dq10 a5 vssq dq11 a17 dq14 dq13 a14 dq15 a19 a12 a18 a8 a9 a1 a2 zz# a4 ce# dq0 a6 dq1 dq2 a7 dq3 vdd a15 dq5 dq6 a13 we# dq7 a10 a11 nc vddq dq12 nc a16 dq4 vss
4 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com 48 - pin tsop - i (top view) notes : 1. the 48 - pin tsop - i package option is not yet available. please contact sram marketing at sram@issi.com for additional information.
5 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com signal descriptions all signals for the device are listed below in table 1. symbol type description vss powe r supply all vss supply pins must be connected to ground vssq powe r supply all vssq supply pins must be connected to ground dq0~dq15 input / output data inputs/outputs (dq0~dq15) a0~a19 input address input (a0~a19) lb# inpu t lower byte select ub# inpu t upper byte select ce# inpu t chip enable/select oe# inpu t output enable we# inpu t write enable zz# input sleep enable : when zz# is low, the cr can be loaded, or the device can enter one of two low - power modes ( dpd or par). table 1. signal descriptions ? all: vdd 1.7v~1.95v , vddq 1.7v~1.95v ? bll: vdd 2.7v~3.6v, vddq 2.7v~3.6v ? cll: vdd 1.7v~1.95v, vddq 2.7v~3.6v
6 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com functional description all functions for the device are listed below in table 2. mode power ce# we# oe# ub#/lb# zz# dq [15:0] 4 note standby standby h x x x h high - z 2,5 read active l h l l h data - out 1,4 write active l l x l h data - in 1,3,4 no operation idle l x x x h x 4,5 par par h x x x l high - z 6 dpd dpd h x x x l high - z 6 load configuration register active l l x x l high - z table 2. functional descriptions notes 1. when ub# and lb# are in select mode (low), dq0~dq15 are affected as shown. when only lb# is in select mode, dq0~dq7 are affected as shown. when only ub# is in select mode, dq8~dq15 are affected as shown. 2. when the device is in standby mode, control inputs (we#, oe#), address inputs, and data inputs/outputs are internally isolated from any external influence. 3. when we# is active, the oe# input is internally disabled and has no effect on the i/os. 4. the device will consume active power in this mode whenever addresses are changed. 5. vin=vddq or 0v, all device pins be static ( unswitched ) in order to achieve standby current. 6. dpd is enabled when configuration register bit cr[4] is 0; otherwise, par is enabled.
7 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com functional description in general, this device is high - density alternatives to sram and pseudo sram products popular in low - power, portable applications. the 16mb device contains a 16mb dram core organized as 1,048,576 addresses by 16 bits. this device include the industry - standard, asynchronous memory interface found on other low - power sram or psram offerings page mode access is also supported as a bandwidth - enhancing extension to the asynchronous read protocol. power - up initialization psram products include an on - chip voltage sensor that is used to launch the power - up initialization process. initialization will load the cr with its default settings (see table 3). vdd and vddq must be applied simultaneously. when they reach a stable level above vdd, the device will require 150s to complete its self - initialization process ( see figure 1). during the initialization period, ce# should remain high. when initialization is complete, the device is ready for normal operation. figure 1: power - up initialization timing vdd device initialization tpu > 150us device ready for normal operation vdd vddq
8 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com bus operating modes psram products incorporates the industry - standard, asynchronous interface. this bus interface supports asynchronous read and write operations as well as page mode read operation for enhanced bandwidth. the supported interface is defined by the value loaded into the cr. asynchronous mode operation psram products power up in the asynchronous operating mode. this mode uses the industry - standard sram control interface (ce#, oe#, we#, and lb#/ub#). read operations are initiated by bringing ce#, oe#, and lb#/ub# low while keeping we# high (see figure 2). valid data will be driven out of the i/os after the specified access time has elapsed. write operations occur when ce#,we#, and lb#/ub# are driven low (see figure 3). during write operations, the level of oe# is a dont care; we# overrides oe#. the data to be written is latched on the rising edge of ce#, we#, or lb#/ub#, whichever occurs first. ce# or we # low time must be limited to tcem . address dq0 - dq15 ce# ub#/lb# oe# we# valid address valid data figure 2. asynchronous read operation t rc = read cycle time < t cem
9 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com figure 3. asynchronous write operation address dq0 - dq15 ce# ub#/lb# we# oe# valid address valid data t wc = write cycle time < t cem < t cem
10 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com page mode read operation page mode is a performance - enhancing extension to the legacy asynchronous read operation. in page - mode - capable products, an initial asynchronous read access is preformed, then adjacent addresses can be read quickly by simply changing the low - order address. addresses a[3:0] are used to determine the members of the 16 - address psram page. any change in addresses a[4] or higher will initiate a new taa access time. figure 4 shows the timing for a page mode access. page mode takes advantage of the fact that adjacent addresses can be read faster than random addresses. write operations do not include comparable page mode functionality. the ce# low time is limited by refresh considerations. ce# must not stay low longer than tcem . ub#/lb# operation the u b#/l b # enable signals accommodate byte - wide data transfers. during read operations, enabled bytes are driven onto the dq. the dq signals associated with a disabled byte are put into a high - z state during a read operation. during write operations, disabled bytes are not transferred to the memory array. and the internal value remains unchanged. during a write cycle the data to be written is latched on the rising edge of ce#, we#, lb# or ub#, whichever occurs first. when both the u b#/l b # are disabled (high) during an operation, the device prevents the data bus from receiving or transmitting data. although the device may appear to be deselected, it remains in active mode as long as ce# remains low. figure 4. page mode read operation address dq0 - dq15 ce# ub#/lb# oe# we# t aa add3 add2 add1 add0 d0 d1 d2 d3 t apa t apa t apa < t cem
11 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com low - power feature standby mode operation during standby, the device current consumption is reduced to the level necessary to perform the dram refresh operation. standby operation occurs when ce# and zz# are high. the device will enter a reduced power state upon completion of a read or write operations when the address and control inputs remain static for an extended period of time. this mode will continue until a change occurs to the address or control inputs. temperature compensated refresh temperature compensated refresh (tcr) is used to adjust the refresh rate depending on the device operating temperature. dram technology requires more frequent refresh operations to maintain data integrity as temperatures increase. more frequent refresh is required due to the increased leakage of the dram's capacitive storage elements as temperatures rise. a decreased refresh rate at lower temperatures will result in a savings in standby current. tcr allows for adequate refresh at four different temperature thresholds: +15 c, +45 c, +70 c, and +85 c. the setting selected must be for a temperature higher than the case temperature of the device. if the case temperature is +50 c, the system can minimize self refresh current consumption by selecting the +70 c setting. the +15 c and +45 c settings would result in inadequate refreshing and cause data corruption.
12 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com partial - array refresh partial - array refresh (par) restricts refresh operation to a portion of the total memory array. this feature enables the device to reduce standby current by refreshing only that part of the memory array that is absolutely necessary. the refresh options are full array, and none of the array. data stored in addresses not receiving refresh will become corrupted. read and write operations are ignored during par operation. the device only enters par mode if the sleep bit in the cr has been set high (cr[4] = 1). par can be initiated by taking the zz# ball to the low state for longer than 10us. returning zz# to high will cause an exit from par, and the entire array will be immediately available for read and write operations. alternatively, par can be initiated using the cr software - access sequence (see software access to the configuration register). using this method, par is enabled immediately upon setting cr[4] to 1 however, using software access to write to the cr alters the function of zz# so that zz# low no longer initiates par, even though zz# continues to enable writes to the cr. this functional change persists until the next time the device is powered up. deep power - down operation deep power - down (dpd) operation disables all refresh - related activity. this mode is used if the system does not require the storage provided by the psram device. any stored data will become corrupted upon entering dpd. when refresh activity has been re - enabled, the psram device will require 150s to perform an initialization procedure before normal operations can resume. read and write operations are ignored during dpd operation. the device can only enter dpd if the sleep bit in the cr has been set low (cr[4] =0). dpd is initiated by bringing zz# to the low state for longer than 10us. returning zz# to high will cause the device to exit dpd and begin a 150us initialization process. during this time, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. driving zz# low puts the device in par mode if the sleep bit in the cr has been set high (cr[4] = 1). the device should not be put into dpd using the cr software - access sequence.
13 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com configuration registers operation the configuration register (cr) defines how the psram device performs a transparent self refresh. altering the refresh parameters can dramatically reduce current consumption during standby mode. page mode controls is embedded in the cr. this register can be updated any time the device is operating in a standby state. the control bits used in the cr are shown in table 3. at power - up, the cr is set to 0070h . access using zz# the cr can be loaded using a write operation immediately after zz# makes a high - to - low transition (see figure 5). the values placed on addresses a[19:0 ] are latched into the cr on the rising edge of ce# or we#, whichever occurs first. lb#/ub# are dont care. access using zz# is write only. figure 5: load configuration register operation using zz# address ce# zz# we# valid address t < 500ns
14 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com software access sequence the contents of the cr can be read or modified using a software access sequence. the nature of this access mechanism can potentially eliminate the need for the zz# ball. if the software - access mechanism is used, zz# can simply be tied to vddq; the port line typically used for zz# control purposes will no longer be required. however, zz# should not be tied to vddq if the system will use dpd; dpd cannot be enabled or disabled using the software - access sequence. the cr is loaded using a four - step sequence consisting of two read operations followed by two write operations (see figure 6). the read sequence is virtually identical except that an asynchronous read is performed during the fourth operation (see figure 7). the address used during all read and write operations is the highest address of the psram device being accessed ( fffffh ); the content of this address is not changed by using the software - access sequence. the data bus is used to transfer data into or out of bit[15:0] of the cr. writing to the cr using the software - access sequence modifies the function of the zz# ball. after the software sequence loads the cr, the level of the zz# ball no longer enables par operation. par operation is updated whenever the software - access sequence loads a new value into the cr. this zz# functionality will remain active until the next time the device is powered up. the operation of the zz# ball is not affected if the software - access sequence is only used to read the contents of the cr. use of the software - access sequence does not affect the performance of standard (zz# - controlled) cr loading. figure 6 : configuration register write notes : 1. cr : 0000h max address output data max address output data max address max address cr value in *note1 oe# address dq0 - dq15 ce# ub#/lb# we# read read write write
15 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com notes : 1. cr : 0000h figure 7 : configuration register read max address output data max address output data max address max address cr value out *note1 read read write read oe# address dq0 - dq15 ce# ub#/lb# we#
16 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com bit number definition remark 19 C 8 reserved all must be set to 0 7 page 0 = page mode disabled (default) 1 = page mode enabled 6 C 5 tcr 1 1 = +85 c (default) 0 0 = +70 c 0 1 = +45 c 1 0 = +15 c 4 sleep 0 = dpd enabled 1 = par enabled (default) 3 reserved must be set to 0 2 C 0 par 1 000 = full array (default) 100 = none of array table 3. configuration register notes : 1. use of other setting will result in full - array refresh coverage.
17 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com partial - array refresh (cr[2:0]) default = full - array refresh the par bits restrict refresh operation to a portion of the total memory array. the refresh options are full array and none of the array. sleep mode (cr[4]) default = par enabled, dpd disabled the sleep mode bit defines the low - power mode to be entered when zz# is driven low. if cr[4] = 1, par operation is enabled. if cr[4] = 0, dpd operation is enabled. par can also be enabled directly by writing to the cr using the software - access sequence. note that this disables zz# initiation of par. dpd cannot properly be enabled or disabled using the software - access sequence; dpd should only be enabled or disabled using zz# to access the cr. dpd operation disables all refresh - related activity. this mode is used when the system does not require the storage provided by the psram device. when dpd is enabled, any stored data will become corrupted. when refresh activity has been re - enabled. the psram device will require 150us to perform an initialization procedure before normal operation can resume. dpd should not be enabled using cr software access. temperature compensated refresh (cr[6:5]) default = +85 o c operation temperature compensated refresh register bits can be programmed using the cr [5, 6] configuration registers and has four different temperature levels: +15 c, +45 c, +70 c, and +85 c. the temperature selected must be equal to or higher than the case temperature of the device. setting a lower temperature level would cause data to be corrupted due to insufficient refresh rate. page mode read operation (cr[7]) default = disabled the page mode operation bit determines whether page mode read operations are enabled in the power - up default state, page mode is disabled.
18 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com electrical characteristics (all) parameter rating voltage to any ball except vdd, vddq relative to vss - 0.5v to (4.0v or vddq + 0.3v, whichever is less) voltage on vdd supply relative to vss - 0.2v to + 2.45v voltage on vddq supply relative to vss - 0.2v to + 2.45v storage temperature (plastic) - 55 cto + 150 c operating temperature - 40 c to + 85 c soldering temperature and time 10s (solder ball only) + 260 c table 4. absolute maximum ratings notes: stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. description conditions symbol min max unit note supply voltage vdd 1.7 1.95 v i/o supply voltage vddq 1.7 1.95 v input high voltage vih vddq - 0.4 vddq+0.2 v 1 input low voltage vil - 0.2 0.4 v 2 output high voltage ioh = - 0.2ma voh 0.8 vddq v output low voltage iol = +0.2ma vol 0.2 vddq v input leakage current vin = 0 to vddq ili 1 ua output leakage current oe#=vih or chip disabled ilo 1 ua operating current conditions symbol typ max unit note asynchronous random read/write vin = vddq or 0v chip enabled, i out = 0 idd1 - 70 30 ma 3 asynchronous page read idd1p - 70 20 ma 3 standby current vin=vddq or 0v ce# = vddq isb 150 ua 4 table 5. electrical characteristics and operating conditions operating temperature ( C 40oc < tc < +85oc) notes: 1. input signals may overshoot to vddq + 1.0v for periods less than 2ns during transitions. 2. input signals may undershoot to vss C 1.0v for periods less than 2ns during transitions. 3. this parameter is specified with the outputs disabled to avoid external loading effects. user must add required current to drive output capacitance expected in the actual system. 4. isb (max) values measured with par set to full array at +85 c. in order to achieve low standby current, all inputs must be driven to either vddq or vss. isb might be set slightly higher for up to 500ms after power - up, or when entering standby mode.
19 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com electrical characteristics (bll) parameter rating voltage to any ball except vdd, vddq relative to vss - 0.5v to (4.0v or vddq + 0.3v, whichever is less) voltage on vdd supply relative to vss - 0.2v to + 4.0v voltage on vddq supply relative to vss - 0.2v to + 4.0v storage temperature (plastic) - 55 cto + 150 c operating temperature - 40 c to + 85 c soldering temperature and time 10s (solder ball only) + 260 c table 6. absolute maximum ratings notes: stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. description conditions symbol min max unit note supply voltage vdd 2.7 3.6 v i/o supply voltage vddq 2.7 3.6 v input high voltage vih vddq - 0.4 vddq+0.2 v 1 input low voltage vil - 0.2 0.4 v 2 output high voltage ioh = - 0.2ma voh 0.8 vddq v output low voltage iol = +0.2ma vol 0.2 vddq v input leakage current vin = 0 to vddq ili 1 ua output leakage current oe#=vih or chip disabled ilo 1 ua operating current conditions symbol typ max unit note asynchronous random read/write vin = vddq or 0v chip enabled, i out = 0 idd1 - 70 30 ma 3 asynchronous page read idd1p - 70 23 ma 3 standby current vin=vddq or 0v ce# = vddq isb 150 ua 4 table 7. electrical characteristics and operating conditions operating temperature ( C 40oc < tc < +85oc) notes: 1. input signals may overshoot to vddq + 1.0v for periods less than 2ns during transitions. 2. input signals may undershoot to vss C 1.0v for periods less than 2ns during transitions. 3. this parameter is specified with the outputs disabled to avoid external loading effects. user must add required current to drive output capacitance expected in the actual system. 4. isb (max) values measured with par set to full array at +85 c. in order to achieve low standby current, all inputs must be driven to either vddq or vss. isb might be set slightly higher for up to 500ms after power - up, or when entering standby mode.
20 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com electrical characteristics (cll) parameter rating voltage to any ball except vdd, vddq relative to vss - 0.5v to (4.0v or vddq + 0.3v, whichever is less) voltage on vdd supply relative to vss - 0.2v to + 2.45v voltage on vddq supply relative to vss - 0.2v to + 4.0v storage temperature (plastic) - 55 cto + 150 c operating temperature - 40 c to + 85 c soldering temperature and time 10s (solder ball only) + 260 c table 8. absolute maximum ratings notes: stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. description conditions symbol min max unit note supply voltage vdd 1.7 1.95 v i/o supply voltage vddq 2.7 3.6 v input high voltage vih vddq - 0.4 vddq+0.2 v 1 input low voltage vil - 0.2 0.4 v 2 output high voltage ioh = - 0.2ma voh 0.8 vddq v output low voltage iol = +0.2ma vol 0.2 vddq v input leakage current vin = 0 to vddq ili 1 ua output leakage current oe#=vih or chip disabled ilo 1 ua operating current conditions symbol typ max unit note asynchronous random read/write vin = vddq or 0v chip enabled, i out = 0 idd1 - 70 30 ma 3 asynchronous page read idd1p - 70 20 ma 3 standby current vin=vddq or 0v ce# = vddq isb 150 ua 4 table 9. electrical characteristics and operating conditions operating temperature ( C 40oc < tc < +85oc) notes: 1. input signals may overshoot to vddq + 1.0v for periods less than 2ns during transitions. 2. input signals may undershoot to vss C 1.0v for periods less than 2ns during transitions. 3. this parameter is specified with the outputs disabled to avoid external loading effects. user must add required current to drive output capacitance expected in the actual system. 4. isb (max) values measured with par set to full array at +85 c. in order to achieve low standby current, all inputs must be driven to either vddq or vss. isb might be set slightly higher for up to 500ms after power - up, or when entering standby mode.
21 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com description conditions symbol typ max unit deep power - down (all/cll) vin=vddq or 0v; +25 c zz# = 0v, cr[4] = 0 izz 3 10 ua deep power - down (bll ) vin=vddq or 0v; +25 c zz# = 0v, cr[4] = 0 izz 10 20 ua table 10. deep power - down specifications description conditions symbol min max unit note input capacitance t c =+25 c; f=1mhz; vin=0v c in 2.0 6.5 pf 1 input/output capacitance (dq) c io 3.5 6.5 pf 1 table 11. capacitance notes: 1. these parameters are verified in device characterization and are not 100% tested. vddq/2 3 output figure 8. ac input/output reference waveform test points ? ? vddq/2 2 input 1 vddq vss notes: 1. ac test inputs are driven at vddq for a logic 1 and vss for a logic 0. input rise and fall times (10% to 90%) < 1.6ns. 2. input timing begins at vddq/2. 3. output timing ends at vddq/2. dut 30pf 50 ? vddq/2 test point figure 9. output load circuit
22 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com table 12 . asynchronous read cycle timing requirements symbol parameter - 55 - 70 unit notes min max min max t aa address acess time 55 70 ns t apa page access time 20 20 ns t ba lb# /ub# access time 55 70 ns t bhz lb#/ub# disable to high - z output 8 8 ns 1 t blz lb#/ub# enable to low - z output 10 10 ns 2 t cem maximum ce# pulse width 8 8 us t co chip select access time 55 70 ns t hz chip disable to high - z output 8 8 ns 1 t lz chip enable to low - z output 10 10 ns 2 t oe output enable to valid output 20 20 ns t oh output hold from address change 5 5 ns t ohz output disable to high - z output 8 8 ns 1 t olz output enable to low - z output 3 3 ns 2 t pc page cycle time 20 20 ns t rc read cycle time 55 70 ns 3 t cph ce# high time read 5 5 ns ac characteristics notes: 1. low - z to high - z timings are tested with the circuit shown in figure 9. the high - z timings measure a 100mv transition from either voh or vol toward vddq/2. 2. high - z to low - z timings are tested with the circuit shown in figure 9. the low - z timings measure a 100mv transition away from the high - z (vddq/2) level toward either voh or vol . 3. address is valid prior to or coincident with ce# low transition and is valid prior to or coincident with ce # high transition.
23 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com table 13 . asynchronous write cycle timing requirements sym bol parameter - 55 - 70 unit notes min max min max t as address setup time 0 0 ns t aw address valid to end of write 55 70 ns t bw byte select to end of write 55 70 ns t cem maximum ce# pulse width 8 8 us t cph ce# high time during write 5 5 ns t cw chip enable to end of write 55 70 ns t dh data hold from write time 0 0 ns t dw data write setup time 23 23 ns t lz chip enable to low - z output 10 10 ns 1 t ow end write to low - z output 5 5 ns 1 t wc write cycle time 55 70 ns t whz write to high - z output 8 8 ns 2 t wp write pulse width 46 46 ns t wph write pulse width high 10 10 ns t wr write recovery time 0 0 ns 3 notes: 1. low - z to high - z timings are tested with the circuit shown in figure 9. the high - z timings measure a 100mv transition from either voh or vol toward vddq/2. 2. high - z to low - z timings are tested with the circuit shown in figure 9. the low - z timings measure a 100mv transition away from the high - z (vddq/2) level toward either voh or vol. 3. write a ddress is valid prior to or coincident with ce# low transition and is valid prior to or coincident with ce # high transition.
24 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com table14 . load configuration register timing requirements symbol parameter - 55 - 70 unit note min max min max t as address setup time 0 0 ns t aw address valid to end of write 55 70 ns t cdzz chip deselect to zz# low 5 5 ns t cem maximum ce# pulse width 8 8 us t cw chip enable to end of write 55 70 ns t wc write cycle time 55 70 ns t wp write pulse width 46 46 ns t wr write recovery time 0 0 ns 1 t zzwe zz# low to we# low 10 500 10 500 ns symbol parameter - 55 - 70 unit notes min max min max t cdzz chip deselect to zz# low 5 5 ns t r deep power - down recovery 150 150 us t zz (min) minimum zz# pulse width 10 10 us table15 . dpd timing requirements symbol parameter - 55 - 70 unit notes min max min max t pu initialization period (required before normal operations) 150 150 us table16 . initialization timing requirements notes: 1. write address is valid prior to or coincident with ce# low transition and is valid prior to or coincident with ce # high transition.
25 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com timing diagrams figure 10: power - up initialization timing vdd, vddq device initialization tpu > 150us device ready for normal operation vdd(min) zz# t zz (min) t r device ready for normal operation figure 12: dpd entry and exit timing ce# t cdzz figure 11: load configuration register address ce# opcode t cw t wr t wp t aw t zzwe t wc ub#/lb# t as t cdzz zz# we# oe#
26 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com figure 13: single read operation address dq0 - dq15 ce# ub#/lb# oe# we# valid address valid output t co t oe t hz t olz t ba t lz ( t blz ) t aa t bhz t ohz t rc figure 14: page mode read a4 - a19 dq0 - dq15 ce# ub#/lb# oe# we# valid address valid output t co t oe t hz t olz t ba t lz t aa t bhz t ohz t rc a0 - a3 valid address valid output valid output valid output valid address valid address valid address t pc t apa t oh
27 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com figure 15: ce# - controlled asynchronous write address dq0 - dq15 ce# ub#/lb# oe# we# valid address valid input t cw t cph t bw t aw t wc t wr t as t wp t dw t dh t lz t whz valid or invalid output t ow 1 note: 1. t dh shouldnt be longer than t ow when end of write changes operating mode into read.
28 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com figure 16: lb#/ub# - controlled asynchronous write address dq0 - dq15 ce# ub#/lb# oe# we# valid address valid input t cw t hz t bw t aw t wc t wr t as t wp t dw t dh t lz t whz valid or invalid output t ow 1 note: 1. t dh shouldnt be longer than t ow when end of write changes operating mode into read. t as
29 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com figure 17: we# - controlled asynchronous write address dq0 - dq15 ce# ub#/lb# oe# we# valid address valid input t cw t hz t bw t aw t wc t wr t as t wph t wp t dw t dh t lz t whz t as valid or invalid output note: 1. t dh shouldnt be longer than t ow when end of write changes operating mode into read. t ow 1
30 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com config . speed (ns) order part no. package 1mx16 55 is66wve1m16ebll - 55bli 48 - ball tfbga, lead - free 70 is66wve1m16ebll - 70bli 48 - ball tfbga, lead - free notes : 1. the 48 - pin tsop - i package option is not yet available. please contact sram marketing at sram@issi.com for additional information. industrial temperature range: ( - 40 o c to +85 o c) ordering information ? bll: vdd 2.7v~3.6v, vddq 2.7v~3.6v config . speed (ns) order part no. package 1mx16 70 is66wve1m16eall - 70bli 48 - ball tfbga, lead - free industrial temperature range: ( - 40 o c to +85 o c) ordering information ? all: vdd 1.7v~1.95v, vddq 1.7v~1.95v config . speed (ns) order part no. package 1mx16 70 is66wve1m16ecll - 70bli 48 - ball tfbga, lead - free industrial temperature range: ( - 40 o c to +85 o c) ordering information ? cll: vdd 1.7v~1.95v, vddq 2.7v~3.6v
31 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com config . speed (ns) order part no. package 1mx16 70 is67wve1m16ebll - 70bla1 48 - ball tfbga, lead - free notes : 1. the 48 - pin tsop - i package option is not yet available. please contact sram marketing at sram@issi.com for additional information. automotive (a1) temperature range: ( - 40 o c to +85 o c) ordering information ? bll: vdd 2.7v~3.6v, vddq 2.7v~3.6v config . speed (ns) order part no. package 1mx16 70 is67wve1m16eall - 70bla1 48 - ball tfbga, lead - free automotive (a1) temperature range: ( - 40 o c to +85 o c) ordering information ? all: vdd 1.7v~1.95v , vddq 1.7v~1.95v config . speed (ns) order part no. package 1mx16 70 is67wve1m16ecll - 70bla1 48 - ball tfbga, lead - free automotive (a1) temperature range: ( - 40 o c to +85 o c) ordering information ? cll: vdd 1.7v~1.95v, vddq 2.7v~3.6v
32 is66wve1m16eall/bll/cll is67wve1m16eall/bll/cll rev. 0d | november 2014 www.issi.com - sram@issi.com

▲Up To Search▲

Price & Availability of IS66WVE1M16BLL

	To Download IS66WVE1M16BLL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .