View IIS328DQ_8924399.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. april 2015 docid027250 rev 3 1/40 IIS328DQ high-performance ultra-low-power 3-axis accelerometer with digital output for industrial applications datasheet - production data features ? wide supply voltage range: 2.16 v to 3.6 v ? low voltage compatible ios: 1.8 v ? ultra-low power consumption: down to 10 a ?? 2 g /4 g / ? 8 g dynamically selectable full-scale ? spi / i 2 c digital output interface ? 16-bit data output ? 2 independent programmable interrupt generators ? system sleep/wakeup function ? extended temperature range: -40 c to 105 c ? embedded self-test ? high shock survivability: up to 10000 g ? ecopack ? , rohs and ?green? compliant applications ? anti-tampering devices ? impact recognition and logging ? vibration monitoring and compensation ? robotics ? platform/antenna stabilization ? tilt/inclination measurements ? motion-activated functions ? intelligent power saving description the IIS328DQ is an ultra-low-power high- performance 3-axis linear accelerometer with a digital serial interface, spi or i 2 c compatible. recommended for industrial applications requiring an extended temperature range and long lifespan, the device features ultra-low-power operational modes that allow advanced power saving and smart sleep-to-wakeup functions. the IIS328DQ has dynamic user-selectable full-scales of 2 g /4 g /8 g and is capable of measuring accelerations with output data rates from 0.5 hz to 1 khz. the self-test capability allows the user to check the functioning of the sensor in the final application. the device may be configured to generate an interrupt signal through inertial wakeup events, or by the position of the device itself. interrupt generators are programmable by the end user on-the-fly. available in a small, quad, flat pack no-lead package (qfpn) with a 4x4 mm footprint, the IIS328DQ corresponds to the trend towards application miniaturization, and is guaranteed to operate over a temperature range from -40 c to +105 c. qfn 24 (4 x 4 x 1.8 mm 3 ) table 1. device summary order codes temperature range [ ? c] package packaging IIS328DQ -40 to +105 qfpn 4x4x1.8 24l tray IIS328DQtr -40 to +105 qfpn 4x4x1.8 24l tape and reel www.st.com
contents IIS328DQ 2/40 docid027250 rev 3 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.2 i 2 c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.3 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.4 sleep-to-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 ic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
docid027250 rev 3 3/40 IIS328DQ contents 40 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 ctrl_reg3 [interrupt ctrl register] (22h) . . . . . . . . . . . . . . . . . . . . . . 26 7.5 ctrl_reg4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.6 ctrl_reg5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.7 hp_filter_reset (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.8 reference (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.9 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.10 out_x_l (28h), out_x_h (29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.11 out_y_l (2ah), out_y_h (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.12 out_z_l (2ch), out_z_h (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.13 int1_cfg (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.14 int1_src (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.15 int1_ths(32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.16 int1_duration (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.17 int2_cfg (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.18 int2_src (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.19 int2_ths (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.20 int2_duration (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1 general guidelines for soldering surface-mount accelerometers . . . . . . . 36 9.2 pcb design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2.1 pcb design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.3 stencil design and solder paste application . . . . . . . . . . . . . . . . . . . . . . . 38 9.4 process considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
list of tables IIS328DQ 4/40 docid027250 rev 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. i 2 c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. i 2 c terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 10. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 12. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 13. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 19 table 14. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 19 table 15. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 16. who_am_i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 17. ctrl_reg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 18. ctrl_reg1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 19. power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 25 table 20. normal-mode output data rate configurations and low-pass cutoff frequencies . . . . . . . . . 25 table 21. ctrl_reg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 22. ctrl_reg2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 23. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 24. high-pass filter cutoff frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 25. ctrl_reg3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 26. ctrl_reg3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 27. data signal on int 1 and int 2 pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 table 28. ctrl_reg4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 29. ctrl_reg4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 30. ctrl_reg5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 31. ctrl_reg5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 32. sleep-to-wake configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 33. reference register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 34. reference description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 35. status_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 36. status_reg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 37. int1_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 38. int1_cfg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 39. interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 40. int1_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 41. int1_src description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 42. int1_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 43. int1_ths description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 44. int1_duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 45. int2_duration description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 46. int2_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 47. int2_cfg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 48. interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
docid027250 rev 3 5/40 IIS328DQ list of tables 40 table 49. int2_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 50. int2_src description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 51. int2_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 52. int2_ths description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 53. int2_duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 54. int2_duration description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 55. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
list of figures IIS328DQ 6/40 docid027250 rev 3 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. detectable accelerations and pin indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. spi slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. i 2 c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. IIS328DQ electrical connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 6. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. multiple byte spi read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. multiple byte spi write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. qfpn 4x4x1.8mm 3 , 24l: mechanical data and package dimensions . . . . . . . . . . . . . . . . 35 figure 13. recommended land and solder mask design for qfpn packages . . . . . . . . . . . . . . . . . . 37
docid027250 rev 3 7/40 IIS328DQ block diagram and pin description 40 1 block diagram and pin description 1.1 block diagram figure 1. block diagram 1.2 pin description figure 2. detectable accelerations and pin indicator < = < = d ; ; ,& 63, &6 6&/63& 6'$6'26', 6'26$ &21752//2*,& ,17(55837*(1 ,17 &/2&. 75,00,1* &,5&8,76 5()(5(1&( 6(/)7(67 &21752/ /2*,& $'& ,17 08; &+$5*( $03/,),(5 $09 7239,(: ',5(&7,212)7+( '(7(&7$%/( $&&(/(5$7,216 %277209,(: < ; = 3lqlqglfdwru
block diagram and pin description IIS328DQ 8/40 docid027250 rev 3 table 2. pin description pin# name function 1,2 nc not connected 3 int_2 inertial interrupt 2 4 reserved connect to gnd 5 vdd power supply 6 gnd 0 v supply 7 int_1 inertial interrupt 1 8 gnd 0 v supply 9 gnd 0 v supply 10 gnd 0 v supply 11 spc scl spi serial port clock (spc) i2c serial clock (scl) internal active pull-up 12 cs spi enable i2c/spi mode selection (0: spi enabled; 1: i2c mode) internal active pull-up 13 reserved connect to vdd 14 vdd_io power supply for i/o pins 15 sdo sa0 spi serial data output (sdo) i2c less significant bit of the device address (sa0) internal active pull-up 16 sdi sdo sda spi serial data input (sdi) 3-wire interface serial data output (sdo) i2c serial data (sda) internal active pull-up 17-24 nc not internally connected
docid027250 rev 3 9/40 IIS328DQ mechanical and electrical specifications 40 2 mechanical and electrical specifications 2.1 mechanical characteristics @ vdd=3.3 v, t=25 c unless otherwise noted (a) . a. the product is factory calibrated at 3.3 v. operational power supply (vdd) over 3.6 v is not recommended. table 3. mechanical characteristics symbol parameter test conditions min. (1) typ. (2) max. (1) unit fs measurement range (3) fs bits set to 00 2.0 g fs bits set to 01 4.0 fs bits set to 11 8.0 so sensitivity fs bits set to 00 12-bit representation 0.9 0.98 1.1 m g /digit fs bits set to 01 12-bit representation 1.8 1.95 2.2 fs bits set to 11 12-bit representation 3.5 3.91 4.3 tcso sensitivity change vs temp. fs bits set to 00 0.01 %/c tyoff typical zero- g level offset accuracy (4),(5) fs bits set to 00 -30 20 +30 m g tcoff zero- g level change vs. temperature excursion from 25 c 0.8 m g /c off zero- g level offset accuracy (6) fs bits set to 00 -300 +300 m g an acceleration noise density fs bits set to 00 218 g / ? hz crax cross-axis (7) -5 +5 % vst self-test output change (8),(9),(10) fs bits set to 00 x-axis -500 -800 -1100 lsb fs bits set to 00 y-axis 500 800 1100 lsb fs bits set to 00 z-axis 400 600 800 lsb wh product weight 60 mgram top operating temperature range -40 +105 c 1. min/max values are based on characterization results, not tested in production 2. typical values are not guaranteed. 3. verified by wafer level test and measurement of initial offset and sensitivity. 4. offset can be eliminated by enabling the built-in high-pass filter. 5. typical zero- g level offset as per factory calibration @ t = 25 c . 6. min/max values for off parameter are across temperature (-40 c to 105 c) and after msl3 preconditioning. based on characterization data. not guaranteed and not tested in production.
mechanical and electrical specifications IIS328DQ 10/40 docid027250 rev 3 2.2 electrical characteristics @ vdd = 3.3 v, t = 25 c unless otherwise noted (b) . 7. guaranteed by design. 8. the sign of ?self-test output change? is defined by a sign bit, for all axes. values in table 3 are defined with the stsign bit in the ctrl_reg4 register equal to logic ?0? (positive self-test), at t = 25 c. 9. self-test output changes with the power supply. ?self-test output change? is defined as output[lsb] (ctrl_reg4 st bit=1) - output[lsb] (ctrl_reg4 st bit=0) . 1lsb=4 g /4096 at 12-bit representation, 2 g full- scale. 10. output data reaches 99% of final value after 3/odr when enabling self-test mode, due to device filtering. b. the product is factory calibrated at 3.3 v. operational power supply (vdd) over 3.6 v is not recommended. table 4. electrical characteristics symbol parameter test conditions min. typ (1) . max. unit vdd supply voltage 2.16 3.3 3.6 v vdd_io i/o pins supply voltage (2) 1.71 vdd+0.1 v idd current consumption in normal mode 2.4 v to 3.6 v 250 a iddlp current consumption in low-power mode odr=1 hz, bw=500 hz, t=25 c 10 a iddpdn current consumption in power-down mode 1 a vih digital high-level input voltage 0.8*vdd_io v vil digital low-level input voltage 0.2*vdd_io v voh high-level output voltage 0.9*vdd_io v vol low-level output voltage 0.1*vdd_io v odr output data rate in normal mode dr bits set to 00 50 hz dr bits set to 01 100 dr bits set to 10 400 dr bits set to 11 1000 odr lp output data rate in low-power mode pm bits set to 010 0.5 hz pm bits set to 011 1 pm bits set to 100 2 pm bits set to 101 5 pm bits set to 110 10 bw system bandwidth odr/2 hz ton turn-on time (3) odr = 100 hz 1/odr+1 ms s top operating temperature range -40 +105 c 1. typical values are not guaranteed.
docid027250 rev 3 11/40 IIS328DQ mechanical and electrical specifications 40 2.3 communication interface characteristics 2.3.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 3. spi slave timing diagram (2) 1. values are guaranteed at 10 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results, not tested in production. 2. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output ports. 3. when no communication is ongoing, data on cs, spc, sdi and sdo are driven by internal pull-up resistors. 2. it is possible to remove vdd maintaining vdd_io without blocking the communication busses; in this condition the measurement chain is powered off. 3. time to obtain valid data after exiting power-down mode. table 5. spi slave timing values symbol parameter value ( 1 ) unit min. max. t c(spc) spi clock cycle 100 ns f c(spc) spi clock frequency 10 mhz t su(cs) cs setup time 6 ns t h(cs) cs hold time 8 t su(si) sdi input setup time 5 t h(si) sdi input hold time 15 t v(so) sdo valid output time 50 t h(so) sdo output hold time 9 t dis(so) sdo output disable time 50 63& &6 6', 6' 2 w vx&6 w y62 w k62 w k6, w vx6, w k&6 w glv62 w f63 & 06% ,1 06% 287 /6%287 /6% ,1
mechanical and electrical specifications IIS328DQ 12/40 docid027250 rev 3 2.3.2 i 2 c - inter ic control interface subject to general operating conditions for vdd and top. figure 4. i 2 c slave timing diagram (c) table 6. i 2 c slave timing values symbol parameter i2c standard mode (1) i2c fast mode (1) unit min. max. min. max. f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0.01 3.45 0.01 0.9 s t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i2c protocol requirement, not tested in production. c. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports. 6'$ 6&/ w i6'$ w vx63 w z6&// w vx6'$ w u6'$ w vx65 w k67 w z6&/+ w k6'$ w u6&/ w i6&/ w z6365 67$57 5(3($7(' 67$57 6723 67$5 7
docid027250 rev 3 13/40 IIS328DQ mechanical and electrical specifications 40 2.4 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.0 v. 2.5 terminology 2.5.1 sensitivity sensitivity describes the gain of the sensor and can be determined, for example, by applying a 1 g acceleration to it. as the sensor can measure dc accelerations, this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. by doing so, a 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and also over time. the sensitivity tolerance describes the range of sensitivity of a large population of sensors. table 7. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4 v vdd_io i/o pin supply voltage -0.3 to 4 v vin input voltage on any control pin (cs, scl/spc, sda/sdi/sdo, sdo/sa0) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 2.5 v) (1) 3000 g for 0.5 ms 10000 g for 0.1 ms a unp acceleration (any axis, unpowered) (1) 1. design guarantee; characterization done at 1500 g /0.5 ms, 3000 g /0.3 ms, 10000 g /0.1 ms; tests under these conditions have passed successfully. 3000 g for 0.5 ms 10000 g for 0.1 ms t op operating temperature range -40 to +105 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 4 (hbm) kv 1.5 (cdm) kv 200 (mm) v this device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. this device is sensitive to electrostatic discharge (esd), improper handling can cause permanent damage to the part.
mechanical and electrical specifications IIS328DQ 14/40 docid027250 rev 3 2.5.2 zero- g level zero- g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady-state on a horizontal surface measures 0 g on the x-axis and 0 g on the y-axis, whereas the z-axis measures 1 g . the output is ideally in the center of the dynamic range of the sensor (the content of the out registers is 00h, data expressed as 2?s complement number). a deviation from the ideal value in this case is called zero- g offset. offset is, to some extent, a result of stress to the mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?zero- g level change vs. temperature? in table 3 . the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a population of sensors. 2.5.3 self-test self-test allows the sensor functionality to be tested without moving it. the self-test function is off when the self-test bit (st) of ctrl_reg4 (control register 4) is programmed to ?0?. when the self-test bit of ctrl_reg4 is programmed to ?1?, an actuation force is applied to the sensor, simulating a definite input acceleration. in this case, the sensor outputs exhibit a change in their dc levels which are related to the selected full scale through the device sensitivity. when the self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test force. if the output signals change within the amplitude specified in table 3 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 2.5.4 sleep-to-wakeup the ?sleep-to-wakeup? function, in conjunction with low-power mode, allows further reduction of system power consumption and development of new smart applications. the IIS328DQ may be set to a low-power operating mode, characterized by lower data rate refresh. in this way the device, even if sleeping, continues to sense acceleration and to generate interrupt requests. when the ?sleep-to-wakeup? function is activated, the IIS328DQ is able to automatically wake up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. with this feature, the system may be efficiently switched from low-power mode to full- performance depending on user-selectable positioning and acceleration events, therefore ensuring power saving and flexibility.
docid027250 rev 3 15/40 IIS328DQ functionality 40 3 functionality the IIS328DQ is a ?nano?, low-power, digital output 3-axis linear accelerometer packaged in a qfpn package. the device includes a sensing element and an ic interface capable of taking information from the sensing element and providing a signal to external applications through an i2c/spi serial interface. 3.1 sensing element a proprietary process is used to create a surface micromachined accelerometer. the technology makes it possible to construct suspended silicon structures which are attached to the substrate at several points called ?anchors?, and are free to move in the direction of the sensed acceleration. to be compatible with traditional packaging techniques, a cap is placed on top of the sensing element to prevent blocking of moving parts during the molding phase of the plastic encapsulation. when an acceleration is applied to the sensor, the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. this imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. at steady-state, the nominal value of the capacitors are a few pf, and when an acceleration is applied the maximum variation of the capacitive load is in the ff range. 3.2 ic interface the complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalancing of the mems sensor into an analog voltage that is made available to the user through an analog-to-digital converter. the acceleration data may be accessed through an i2c/spi interface, therefore making the device particularly suitable for direct interfacing with a microcontroller. the IIS328DQ features a data-ready signal (rdy) which indicates when a new set of measured acceleration data is available, therefore simplifying data synchronization in the digital system that uses the device. the IIS328DQ may also be configured to generate an inertial wakeup and free-fall interrupt signal based on a programmed acceleration event along the enabled axes. both free-fall and wakeup can be available simultaneously on two different pins. 3.3 factory calibration the ic interface is factory calibrated for sensitivity (so) and zero- g level (tyoff). the trimming values are stored inside the device in non-volatile memory. when the device is turned on, the trimming parameters are downloaded into the registers to be used during active operation. this allows the device to be used without further calibration.
application hints IIS328DQ 16/40 docid027250 rev 3 4 application hints figure 5. IIS328DQ electrical connections the device core is supplied through the vdd line while the i/o pads are supplied through the vdd_io line. power supply decoupling capacitors (100 nf ceramic, 10 f aluminum) should be placed as near as possible to pin 5 of the device (common design practice). all the voltage and ground supplies must be present at the same time to obtain proper behavior of the ic (refer to figure 5 ). it is possible to remove vdd while maintaining vdd_io without blocking the communication bus; in this condition the measurement chain is powered off. the functionality of the device and the measured acceleration data is selectable and accessible through the i2c or spi interfaces. when using the i2c, cs must be tied high. the functions, the threshold, and the timing of the two interrupt pins (int 1 and int 2) can be completely programmed by the user through the i2c/spi interface. &6 9gg *1' 9ggb,2 6'26$ 6'$6',6'2 ,17 6&/63& 7239,(: ,17 < ; = x) 'ljlwdovljqdoiurpw rvljqdofrqwuroohu6ljqdoohyhovduhghi lqhge\surshuvhohfwl rqri9ggb,2 q)
docid027250 rev 3 17/40 IIS328DQ digital interfaces 40 5 digital interfaces the registers embedded in the IIS328DQ may be accessed through both the i2c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped to the same pads. to select/exploit the i2c interface, the cs line must be tied high (i.e. connected to vdd_io). 5.1 i2c serial interface the IIS328DQ i2c is a bus slave. the i2c is employed to write data into registers, the content of which can also be read back. the relevant i2c terminology is provided in table 9 below. there are two signals associated with the i2c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving data to/from the interface. both lines are connected to vdd_io through a pull-up resistor embedded in the IIS328DQ. when the bus is free, both lines are high. the i2c interface is compliant with fast mode (400 khz) i2c standards as well as with the normal mode. table 8. serial interface pin description pin name pin description cs spi enable i2c/spi mode selection (1: i2c mode; 0: spi enabled) scl spc i2c serial clock (scl) spi serial port clock (spc) sda sdi sdo i2c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sa0 sdo i2c less significant bit of the device address (sa0) spi serial data output (sdo) table 9. i 2 c terminology term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
digital interfaces IIS328DQ 18/40 docid027250 rev 3 5.1.1 i2c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high-to-low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the IIS328DQ is 001100xb. the sdo / sa0 pad can be used to modify the less significant bit of the device address. if the sa0 pad is connected to voltage supply, lsb is ?1? (address 0011001b), otherwise if the sa0 pad is connected to ground, the lsb value is ?0? (address 0011000b). this solution permits the connection and addressing of two different accelerometers to the same i2c lines. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i2c embedded in the IIS328DQ behaves like a slave device, and the following protocol must be adhered to. after the start condition (st) a slave address is sent. once a slave acknowledge (sak) has been returned, an 8-bit sub-address (sub) is transmitted: the 7 lsb represent the actual register address while the msb enables address auto-increment. if the msb of the sub field is ?1?, the sub (register address) is automatically increased to allow multiple data read/write. the slave address is completed with a read/write bit. if the bit is ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write) the master transmits to the slave with direction unchanged. table 10 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 10. sad+read/write patterns command sad[6:1] sad[0] = sa0 r/w sad+r/w read 001100 0 1 00110001 (31h) write 001100 0 0 00110000 (30h) read 001100 1 1 00110011 (33h) write 001100 1 0 00110010 (32h) table 11. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak table 12. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak
docid027250 rev 3 19/40 IIS328DQ digital interfaces 40 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low-to-high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of the first register to be read. in the communication format presented, mak is master acknowledge and nmak is no master acknowledge. 5.2 spi bus interface the IIS328DQ spi is a bus slave. the spi allows writing to and reading from the registers of the device. the serial interface interacts with the outside world through 4 wires: cs , spc , sdi and sdo . figure 6. read and write protocol table 13. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 14. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data dat a dat a &6 63& 6', 6'2 5: $' $' $' $' $' $' ', ', ', ', ', ', ', ', '2 '2 '2 '2 '2 '2 '2 '2 06
digital interfaces IIS328DQ 20/40 docid027250 rev 3 cs is the serial port enable and is controlled by the spi master. it goes low at the start of the transmission and returns high at the end. spc is the serial port clock and is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are, respectively, the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in cases of multiple read/write bytes. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc , after the falling edge of cs, while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc, just before the rising edge of cs . bit 0 : r w bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in the latter case, the chip drives sdo at the start of bit 8. bit 1 : m s bit. when 0, the address remains unchanged in multiple read/write commands. when 1, the address is auto-incremented in multiple read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written to the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands further blocks of 8 clock periods are added. when the m s bit is ?0?, the address used to read/write data remains the same for every block. when the m s bit is ?1?, the address used to read/write data is increased at every block. the function and the behavior of sdi and sdo remain unchanged. 5.2.1 spi read figure 7. spi read protocol the spi read command is performed with 16 clock pulses. multiple byte read commands are performed by adding blocks of 8 clock pulses to the previous one. bit 0 : read bit. the value is 1. bit 1 : m s bit. when 0, does not increment the address; when 1, increments the address in multiple reads. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). bit 16-... : data do(...-8). further data in multiple byte reads. &6 63& 6', 6'2 5: '2 '2 '2 '2 '2 '2 '2 '2 $' $' $' $' $' $' 06
docid027250 rev 3 21/40 IIS328DQ digital interfaces 40 figure 8. multiple byte spi read protocol (2-byte example) 5.2.2 spi write figure 9. spi write protocol the spi write command is performed with 16 clock pulses. multiple byte write commands are performed by adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1 : m s bit. when 0, does not increment the address; when 1, increments the address in multiple writes. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written to the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writes. figure 10. multiple byte spi write protocol (2-byte example) &6 63& 6', 6'2 5: '2 '2 '2 '2 '2 '2 '2 '2 $' $' $' $' $' $' '2 '2 '2 '2 '2 '2 '2 '2 06 &6 63& 6', 5: ', ', ', ', ', ', ', ', $' $' $' $' $' $' 06 &6 63& 6', 5: $' $' $' $' $' $' ', ', ', ', ', ', ', ', ',',',',',',', ', 06
digital interfaces IIS328DQ 22/40 docid027250 rev 3 5.2.3 spi read in 3-wire mode 3-wire mode is entered by setting the sim bit to ?1? (spi serial interface mode selection) in ctrl_reg4. figure 11. spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : m s bit. when 0, does not increment the address; when 1, increments the address in multiple reads. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). a multiple read command is also available in 3-wire mode. note: if the IIS328DQ is used in a multi-spi slave environment (several devices sharing the same spi bus), the accelerometer can be forced by software to remain in spi mode. this objective can be achieved by sending at the beginning of the spi communication the following sequence to the device: a = read(0x17) write(0x17, (0x80 or a)) in this way, ctrl_reg4 is programmed to enhance the robustness of the spi. &6 63& 6',2 5: '2 '2 '2 '2 '2 '2 '2 '2 $' $' $' $' $' $' 06
docid027250 rev 3 23/40 IIS328DQ register mapping 40 6 register mapping table 15 below provides a list of the 8-bit registers embedded in the device, and the corresponding addresses. registers marked as reserved must not be changed. writing to those registers may change calibration data and therefore lead to device malfunction. the content of the registers that are loaded at boot should not be changed. they contain the factory calibrated values. their content is automatically restored when the device is powered up. table 15. register address map name type register address default comment hex binary reserved (do not modify) 00 - 0e reserved who_am_i r 0f 000 1111 00110010 dummy register reserved (do not modify) 10 - 1f reserved ctrl_reg1 rw 20 010 0000 00000111 ctrl_reg2 rw 21 010 0001 00000000 ctrl_reg3 rw 22 010 0010 00000000 ctrl_reg4 rw 23 010 0011 00000000 ctrl_reg5 rw 24 010 0100 00000000 hp_filter_reset r 25 010 0101 dummy register reference rw 26 010 0110 00000000 status_reg r 27 010 0111 00000000 out_x_l r 28 010 1000 output out_x_h r 29 010 1001 output out_y_l r 2a 010 1010 output out_y_h r 2b 010 1011 output out_z_l r 2c 010 1100 output out_z_h r 2d 010 1101 output reserved (do not modify) 2e - 2f reserved int1_cfg rw 30 011 0000 00000000 int1_src r 31 011 0001 00000000 int1_ths rw 32 011 0010 00000000 int1_duration rw 33 011 0011 00000000 int2_cfg rw 34 011 0100 00000000 int2_src r 35 011 0101 00000000 int2_ths rw 36 011 0110 00000000 int2_duration rw 37 011 0111 00000000 reserved (do not modify) 38 - 3f reserved
register description IIS328DQ 24/40 docid027250 rev 3 7 register description the device contains a set of registers which are used to control its behavior and to retrieve acceleration data. the register addresses, composed of 7 bits, are used to identify the device and to write the data through the serial interface. 7.1 who_am_i (0fh) this is the device identification register. this register contains the device identifier, which for the IIS328DQ is set to 32h. 7.2 ctrl_reg1 (20h) the pm bits allow selection between power-down and two active operating modes. the device is in power-down mode when the pd bits are set to ?000? (default value after boot). table 19 shows all the possible power mode configurations and respective output data rates. output data in the low-power modes are computed with the low-pass filter cutoff frequency defined by the dr1 and dr0 bits. the dr bits, in normal-mode operation, select the data rate at which acceleration samples are produced. in low-power mode they define the output data resolution. table 20 shows all the possible configurations for the dr1 and dr0 bits. table 16. who_am_i register 00110010 table 17. ctrl_reg1 register pm2 pm1 pm0 dr1 dr0 zen yen xen table 18. ctrl_reg1 description pm2 - pm0 power mode selection. default value: 000 (000: power-down; others: refer to table 19 ) dr1, dr0 data rate selection. default value: 00 (00: 50 hz; others: refer to table 20 ) zen z-axis enable. default value: 1 (0: z-axis disabled; 1: z-axis enabled) yen y-axis enable. default value: 1 (0: y-axis disabled; 1: y-axis enabled) xen x-axis enable. default value: 1 (0: x-axis disabled; 1: x-axis enabled)
docid027250 rev 3 25/40 IIS328DQ register description 40 7.3 ctrl_reg2 (21h) table 19. power mode and low-power output data rate configurations pm2 pm1 pm0 power mode selection output data rate [hz] odr lp 0 0 0 power-down -- 0 0 1 normal mode odr 0 1 0 low-power 0.5 0 1 1 low-power 1 1 0 0 low-power 2 1 0 1 low-power 5 1 1 0 low-power 10 table 20. normal-mode output data rate configurations and low-pass cutoff frequencies dr1 dr0 output data rate [hz] odr low-pass filter cutoff frequency [hz] 0 0 50 37 0 1 100 74 1 0 400 292 1 1 1000 780 table 21. ctrl_reg2 register boot hpm1 hpm0 fds hpen2 hpen1 hpcf1 hpcf0 table 22. ctrl_reg2 description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) hpm1, hpm0 high-pass filter mode selection. default value: 00 (00: normal mode; others: refer to table 23 ) fds filtered data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register) hpen2 high-pass filter enable for interrupt 2 source. default value: 0 (0: filter bypassed; 1: filter enabled) hpen1 high-pass filter enable for interrupt 1 source. default value: 0 (0: filter bypassed; 1: filter enabled) hpcf1, hpcf0 high-pass filter cutoff frequency configuration. default value: 00 (00: hpc=8; 01: hpc=16; 10: hpc=32; 11: hpc=64)
register description IIS328DQ 26/40 docid027250 rev 3 the boot bit is used to refresh the content of internal registers stored in the flash memory block. at device power-up, the content of the flash memory block is transferred to the internal registers related to the trimming functions, to permit correct behavior of the device. if for any reason the content of the trimming register is changed, this bit can be used to restore the correct values. when the boot bit is set to ?1? the content of the internal flash is copied to the corresponding internal registers and is used to calibrate the device. these values are factory-trimmed and they are different for every accelerometer. they permit correct behavior of the device and normally do not need to be modified. at the end of the boot process, the boot bit is again set to ?0?. hpcf[1:0] . these bits are used to configure the high-pass filter cutoff frequency f t which is given by: the equation can be simplified to the following approximated equation: 7.4 ctrl_reg3 [interrupt ctrl register] (22h) table 23. high-pass filter mode configuration hpm1 hpm0 high-pass filter mode 0 0 normal mode (reset by reading hp_reset_filter) 0 1 reference signal for filtering 1 0 normal mode (reset by reading hp_reset_filter) table 24. high-pass filter cutoff frequency configuration hpcoeff2,1 f t [hz] data rate = 50 hz f t [hz] data rate = 100 hz f t [hz] data rate = 400 hz f t [hz] data rate = 1000 hz 00 1 2 8 20 01 0.5 1 4 10 10 0.25 0.5 2 5 11 0.125 0.25 1 2.5 f t 1 1 hpc ----------- - ? ?? ?? f s 2 ? ------ ? ln = f t f s 6hpc ? ------------------- = table 25. ctrl_reg3 register ihl pp_od lir2 i2_cfg1 i2_cfg0 lir1 i1_cfg1 i1_cfg0
docid027250 rev 3 27/40 IIS328DQ register description 40 7.5 ctrl_reg4 (23h) table 26. ctrl_reg3 description ihl interrupt active-high/low. default value: 0 (0: active high; 1: active low) pp_od push-pull/open-drain selection on interrupt pad. default value 0 (0: push-pull; 1: open drain) lir2 latch interrupt request on the int2_src register, with the int2_src register cleared by reading int2_src itself. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) i2_cfg1, i2_cfg0 data signal on int 2 pad control bits. default value: 00 (see table 27 ) lir1 latch interrupt request on the int1_src register, with the int1_src register cleared by reading the int1_src register. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) i1_cfg1, i1_cfg0 data signal on int 1 pad control bits. default value: 00 (see table 27 ) table 27. data signal on int 1 and int 2 pad i1(2)_cfg1 i1(2)_cfg0 int 1(2) pad 0 0 interrupt 1 (2) source 0 1 interrupt 1 source or interrupt 2 source 1 0 data ready 1 1 boot running table 28. ctrl_reg4 register bdu ble fs1 fs0 stsign 0 st sim table 29. ctrl_reg4 description bdu block data update. default value: 0 (0: continuous update; 1: output registers not updated between reading msb and lsb) ble big/little endian data selection. default value 0 (0: data lsb @ lower address; 1: data msb @ lower address) fs1, fs0 full-scale selection. default value: 00 (00: 2 g ; 01: 4 g ; 11: 8 g ) stsign self-test sign. default value: 00 (0: self-test plus; 1 self-test minus) st self-test enable. default value: 0 (0: self-test disabled; 1: self-test enabled) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface)
register description IIS328DQ 28/40 docid027250 rev 3 the bdu bit is used to inhibit the output register update until both upper and lower register parts are read. in default mode (bdu = ?0?), the lower and upper register parts are updated continuously. when the bdu is activated (bdu = 1), the content of the output registers is not updated until both msb and lsb are read which avoids reading values related to different sample times. 7.6 ctrl_reg5 (24h) the turnon bits are used for turning on the sleep-to-wake function. by setting turnon[1:0] bits to 11, the ?sleep-to-wake? function is enabled. when an interrupt event occurs, the device is switched to normal mode, increasing the odr to the value defined in ctrl_reg1. although the device is in normal mode, the ctrl_reg1 content is not automatically changed to ?normal mode? configuration. 7.7 hp_filter_reset (25h) dummy register. reading at this address instantaneously zeroes the content of the internal high-pass filter. if the high-pass filter is enabled, all three axes are instantaneously set to 0 g. this makes it possible to nullify the settling time of the high-pass filter. 7.8 reference (26h) this register sets the acceleration value taken as a reference for the high-pass filter output. table 30. ctrl_reg5 register 0 0 0 0 0 0 turnon1 turnon0 table 31. ctrl_reg5 description turnon1, turnon0 turn-on mode selection for sleep-to-wake function. default value: 00 table 32. sleep-to-wake configuration turnon1 turnon0 sleep-to-wake status 0 0 sleep-to-wake function is disabled 1 1 turned on: the device is in low-power mode (odr is defined in ctrl_reg1) table 33. reference register ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 table 34. reference description ref7 - ref0 reference value for high-pass filter. default value: 00h
docid027250 rev 3 29/40 IIS328DQ register description 40 when the filter is turned on (at least one fds, hpen2, or hpen1 bit is equal to ?1?) and hpm bits are set to ?01?, filter output is generated, taking this value as a reference. 7.9 status_reg (27h) 7.10 out_x_l (28h), out_x_h (29) x-axis acceleration data. the value is expressed as 2?s complement. 7.11 out_y_l (2ah), out_y_h (2bh) y-axis acceleration data. the value is expressed as 2?s complement. table 35. status_reg register zyxor zor yor xor zyxda zda yda xda table 36. status_reg description zyxor x-, y- and z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new set of data has overwritten the previous set before it was read) zor z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the z-axis has overwritten the previous data) yor y-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the y-axis has overwritten the previous data) xor x-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the x-axis has overwritten the previous data) zyxda x-, y- and z-axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z-axis new data available. default value: 0 (0: new data for the z-axis is not yet available; 1: new data for the z-axis is available) yda y-axis new data available. default value: 0 (0: new data for the y-axis is not yet available; 1: new data for the y-axis is available) xda x-axis new data available. default value: 0 (0: new data for the x-axis is not yet available; 1: new data for the x-axis is available)
register description IIS328DQ 30/40 docid027250 rev 3 7.12 out_z_l (2ch), out_z_h (2dh) z-axis acceleration data. the value is expressed as 2?s complement. 7.13 int1_cfg (30h) configuration register for interrupt 1 source. table 37. int1_cfg register aoi 6d zhie zlie yhie ylie xhie xlie table 38. int1_cfg description aoi and/or combination of interrupt events. default value: 0 (see table 39 ) 6d 6-direction detection function enable. default value: 0 (see table 39 ) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 39. interrupt 1 source configurations aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6-direction movement recognition 1 0 and combination of interrupt events 1 1 6-direction position recognition
docid027250 rev 3 31/40 IIS328DQ register description 40 7.14 int1_src (31h) interrupt 1 source register. read-only register. reading at this address clears the int1_src ia bit (and the interrupt signal on the int 1 pin) and allows the refresh of data in the int1_src register if the latched option was chosen. 7.15 int1_ths(32h) 7.16 int1_duration (33h) the d6 - d0 bits set the minimum duration of the interrupt 2 event to be recognized. duration steps and maximum values depend on the odr chosen. table 40. int1_src register 0 ia zhzlyhylxhxl table 41. int1_src description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 42. int1_ths register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 43. int1_ths description ths6 - ths0 interrupt 1 threshold. default value: 000 0000 table 44. int1_duration register 0 d6d5d4d3d2d1d0 table 45. int2_duration description d6 - d0 duration value. default value: 000 0000
register description IIS328DQ 32/40 docid027250 rev 3 7.17 int2_cfg (34h) configuration register for interrupt 2 source. 7.18 int2_src (35h) table 46. int2_cfg register aoi 6d zhie zlie yhie ylie xhie xlie table 47. int2_cfg description aoi and/or combination of interrupt events. default value: 0 (see table 48 ) 6d 6-direction detection function enable. default value: 0 (see table 48 ) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 48. interrupt mode configuration aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6-direction movement recognition 1 0 and combination of interrupt events 1 1 6-direction position recognition table 49. int2_src register 0 ia zhzlyhylxhxl
docid027250 rev 3 33/40 IIS328DQ register description 40 interrupt 2 source register. read-only register. reading at this address clears the int2_src ia bit (and the interrupt signal on the int 2 pin) and allows the refresh of data in the int2_src register if the latched option was chosen. 7.19 int2_ths (36h) 7.20 int2_duration (37h) the d6 - d0 bits set the minimum duration of the interrupt 2 event to be recognized. duration time steps and maximum values depend on the odr chosen. table 50. int2_src description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 51. int2_ths register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 52. int2_ths description ths6 - ths0 interrupt 1 threshold. default value: 000 0000 table 53. int2_duration register 0 d6d5d4d3d2d1d0 table 54. int2_duration description d6 - d0 duration value. default value: 000 0000
package information IIS328DQ 34/40 docid027250 rev 3 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
docid027250 rev 3 35/40 IIS328DQ package information 40 figure 12. qfpn 4x4x1.8mm 3 , 24l: mechanical data and package dimensions 'lp pp 0lq 7\s 0d[ $ $ $ uhi e ' evf ' ( evf ( h evf / ddd hhh 4)31[[pp 4xdg)odw 3dfndjh1rohdg b&
soldering information IIS328DQ 36/40 docid027250 rev 3 9 soldering information the qfpn-24 package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resistance according to jedec j-std-020c, in msl3 condi- tions. for complete land pattern and soldering recommendations, please refer to the technical note tn0019 available on www .st.com . 9.1 general guidelines for soldering surface-mount accelerometers the following three elements must be considered in order to adhere to common pcb design and good industrial practices when soldering mems sensors: 1. pcb with its own conductive layers (i.e. copper) and other organic materials used for board protection and dielectric isolation. 2. accelerometer to be mounted on the board. the accelerometer senses acceleration, but it senses also the mechanical stress coming from the board. this stress is minimized with simple pcb design rules. 3. solder paste like snagcu. this solder paste can be dispensed on the board with a screen printing method through a stencil. the pattern of the solder paste on the pcb is given by the stencil mask itself. 9.2 pcb design guidelines pcb land and solder mask general recommendations are shown in figure 13 . refer to figure 12 for specific device size, land count and pitch. ? it is recommended to open the solder mask external to the pcb land. ? it is mandatory, for correct device functionality, to ensure that some clearance is present between the accelerometer thermal pad and pcb. in order to obtain this clearance it is recommended to open the pcb thermal pad solder mask. ? the area below the sensor (on the same side of the board) must be defined as a keepout area. it is strongly recommended not to place any structure in the top metal layer underneath the sensor. ? traces connected to pads should be as symmetrical as possible. symmetry and balance for pad connection helps component self-alignment and leads to better control of solder paste reduction after reflow. ? for better performance over temperature it is strongly recommended not to place large insertion components like buttons or shielding boxes at distances less than 2 mm from the sensor. ? central die pad and ?pin 1 indicator? are physically connected to gnd. leave ?pin 1 indicator? unconnected during soldering.
docid027250 rev 3 37/40 IIS328DQ soldering information 40 9.2.1 pcb design rules figure 13. recommended land and solder mask design for qfpn packages a = clearance from pcb land edge to solder mask opening ? 0.1 mm to ensure that some solder mask remains between pcb pads b = pcb land length = qfpn solder pad length + 0.1 mm c = pcb land width = qfpn solder pad width + 0.1 mm d = pcb thermal pad solder mask opening = qfpn thermal pad side + 0.2 mm 3$&.$*()22735,17 3&% /$1' 62/'(50$6.23(1,1* 3&%7+(50$/3$'12772 %('(6,*1('213&% 3&%7+(50$/3$'62/'(5 0$6.23(1,1* 5(&200(1'('72,1&5($6( '(9,&(7+(50$/3$'wr3&% &/($5$1&( $ % & ' $09
soldering information IIS328DQ 38/40 docid027250 rev 3 9.3 stencil design and solder paste application the thickness and the pattern of the solder paste are important in order to correctly mount the accelerometer on the board. ? stainless steel stencils are recommended for solder paste application. ? a stencil thickness of 125 - 150 m (5 - 6 mils) is recommended for screen printing ? the final thickness of the solder paste should allow proper cleaning of flux residuals and clearance between the sensor package and pcb. ? stencil aperture should have a rectangular shape with a dimension up to 25 m (1 mil) smaller than pcb land. ? the openings of the stencil for the signal pads should be between 50% and 80% of the pcb pad area. ? optionally, for better solder paste release, the aperture walls should be trapezoidal and the corners rounded. ? the fine pitch of the ic leads requires accurate alignment of the stencil to the printed circuit board. the stencil and printed circuit assembly should be aligned to within 25 m (1 mil) prior to application of the solder paste. 9.4 process considerations ? if self-cleaning solder paste is not used, it is mandatory to properly wash the board after soldering to eliminate any possible source of leakage between adjacent pads due to flux residues. ? the pcb soldering profile depends on the number, size and placement of components on the application board. for this reason it is not possible to define a unique soldering profile for the sensor only.the user should use a time and temperature reflow profile that is derived from pcb design and manufacturing expertise.
docid027250 rev 3 39/40 IIS328DQ revision history 40 10 revision history table 55. document revision history date revision changes 17-dec-2014 1 initial release 05-mar-2014 2 added off parameter as well as min and max values for tyoff and tcoff in table 3: mechanical characteristics 21-apr-2015 3 first public release
IIS328DQ 40/40 docid027250 rev 3 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

▲Up To Search▲

Price & Availability of IIS328DQ

	To Download IIS328DQ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .