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four - adc, two - dac, low power codec with audio processor data sheet adau1777 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or paten t rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2016 analog devices, inc. all rights reserved. technical support www.analog.com features programmable audio processing engine fast (up to 768 khz) and slow processing paths biquad filters, limiters, volume controls, and mixing low latency, 24- bit adcs and dacs 102 db snr (through pga and adc with a weighted filter) 108 db combi ned snr (through dac and headphone with a w eighted filter ) serial port sampling rate from 8 khz to 192 khz 5 s analog - to - analog latency 4 single - ended analog inputs, configurable as microp hone or line input s dual stereo digital microphone inputs stereo analog audio output , single - ended or differential, configurable as either line output or headphone driver pll supporting any input clock rate from 8 mhz to 27 mhz full duplex , asynchronous sample rate converters (asrcs) power supplies analog and digital input/output of 1.8 v to 3.3 v digital signal processing (dsp) core of 1.1 v to 1.8 v low power i 2 c and spi control interfaces, self boot from i 2 c eeprom 7 m ultipurpose (mp x ) pins for digital controls and outputs applications noise cance ling handsets, headsets, and headphones bluetooth ? active noise canceling (anc) handsets, headsets, and headphones personal navigation devices digital still and video cameras general descriptio n the adau1777 is a codec with four inputs and two outputs that incorporates a digital processing engine to perform filtering, level control, signal level monitoring, and mixing. the path from the analog input to the dsp core to the analog output is optimized for low latency and is ideal for noise canceling headsets. with the addition of just a few passive components, a crystal, and an eeprom for booting, the adau1777 provides a complete headset solution. note that throughout this data sheet, multifunction pins, such as scl/sclk, are referred to either by the entire pin name or by a single function of the pin, for example, sclk, whe n only that function is relevant. functional block dia gram microphone bias generators micbias0 micbias1 cm dmic0_1/mp4 dmic2_3/mp5 digital microphone inputs input/output signal routing dsp core: biquad filters, limiters, volume controls, mixing i 2 c/spi control interface and self boot bidirectional asrcs serial input/ output port ldo regulator reg_out avdd avdd avdd iovdd dvdd power management pd pll clock oscillator selfboot dgnd agnd agnd agnd addr0/ss addr1/mosi scl/sclk sda/miso dac_sdata/mp0 adc_sdata1/clkout/mp6 xtali/mclkin xtalo adc_sdata0/pdmout/mp1 bclk/mp2 lrclk/mp3 dac hpoutlp/loutlp dac adc adc stereo pdm modulator adau1777 adc pga ain2 pga ain0 pga ain1 ain3 pga adc hpoutln/loutln hpoutrp/loutrp hpoutrn/loutrn 14796-001 figure 1.
adau1777 data sheet rev. 0 | page 2 of 108 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 analog performance specifications ........................................... 4 crystal amplifier specifications ................................................. 8 digital input/output specifications ........................................... 8 power supply specifications ........................................................ 8 typical power management settings ......................................... 9 digital filters specifications ....................................................... 9 digital timing specifications ................................................... 10 absolute maximum ratings .......................................................... 14 thermal resistance .................................................................... 14 esd cau tion ................................................................................ 14 pin configuration and function descriptions ........................... 15 typical performance characteristics ........................................... 17 theory of operation ...................................................................... 24 system clocking and power - up ................................................... 25 clock initialization ..................................................................... 25 pll ................................................................................................ 25 clock output ............................................................................... 26 power sequencing ...................................................................... 26 signal routing ................................................................................. 27 input signal paths ........................................................................... 28 analog inputs .............................................................................. 28 digital microphone input ......................................................... 29 analog - to - digital converters (adcs) .................................... 29 output signal paths ........................................................................ 30 analog outputs ........................................................................... 30 digital - to - analog converters (dacs) .................................... 30 pdm output ............................................................................... 30 asynchronous sample rate converters .................................. 31 signal levels ................................................................................ 31 signal processing ............................................................................ 32 instructions ................................................................................. 32 data memory .............................................................................. 32 parameters ................................................................................... 32 control port ..................................................................................... 35 burst mode communication .................................................... 35 i 2 c port ........................................................................................ 35 spi port ........................................................................................ 38 self boot ....................................................................................... 39 multipurpose pins .......................................................................... 40 push - button volume controls ................................................. 40 limiter compression enable .................................................... 40 parameter bank switching ........................................................ 40 mute ............................................................................................. 40 dsp bypass mode ...................................................................... 41 serial data input/output ports .................................................... 42 tristating unused channels ..................................................... 42 applications information .............................................................. 45 power supply bypass capacitors .............................................. 45 layout .......................................................................................... 45 grounding ................................................................................... 4 5 pcb stackup ................................................................................ 45 low latency register settings ...................................................... 46 register summary .......................................................................... 49 register details ............................................................................... 52 clock control register .............................................................. 52 pll denominator msb register .............................................. 53 pll denominator lsb register ............................................... 53 pll numerator msb register .................................................. 53 pll numerator lsb register .................................................... 54 pll integer setting register ..................................................... 54 pll lock flag register .............................................................. 55 clkout setting selection register ........................................ 55 regulator control register ....................................................... 56 core control register ................................................................ 56 sleep on program address count register ............................. 57 filter engine and limiter control register ............................ 59 db value register 0 read .......................................................... 59 db value register 1 read .......................................................... 60 db value register 2 read .......................................................... 60 core channel 0/core channel 1 input select register ......... 61 core channel 2/core channel 3 input select register ......... 62 dac input select register ........................................................ 63 pdm modulator input select register .................................... 64
data sheet adau1777 rev. 0 | page 3 of 108 serial data output 0/serial data output 1 input select register ......................................................................................... 65 ? serial data output 2/serial data output 3 input select register ......................................................................................... 66 ? serial data output 4/serial data output 5 input select register ......................................................................................... 67 ? serial data output 6/serial data output 7 input select register ......................................................................................... 68 ? adc_sdata0/adc_sdata1 channel select register ...... 69 ? output asrc0/output asrc1 source register ..................... 69 ? output asrc2/output asrc3 source register ..................... 70 ? input asrc channel select register ........................................ 71 ? adc0/adc1 control 0 register .............................................. 72 ? adc2/adc3 control 0 register .............................................. 73 ? adc0/adc1 control 1 register .............................................. 74 ? adc2/adc3 control 1 register .............................................. 75 ? adc0 volume control register ............................................... 75 ? adc1 volume control register ............................................... 76 ? adc2 volume control register ............................................... 76 ? adc3 volume control register ............................................... 77 ? pga control 0 register .............................................................. 77 ? pga control 1 register .............................................................. 78 ? pga control 2 register .............................................................. 78 ? pga control 3 register .............................................................. 79 ? pga slew control register ........................................................ 80 ? pga 10 db gain boost register ................................................ 80 ? input and output capacitor charging register ..................... 81 ? dsp bypass path register .......................................................... 82 ? dsp bypass gain for pga0 register ........................................ 82 ? dsp bypass gain for pga1 register ........................................ 82 ? micbias0_1 control register .................................................. 83 ? dac control register ................................................................ 83 ? dac0 volume control register ................................................ 84 ? dac1 volume control register ................................................ 84 ? headphone output mutes register .......................................... 85 ? serial port control 0 register .................................................... 85 ? serial port control 1 register .................................................... 86 ? tdm output channel disable register .................................. 87 ? pdm enable register ................................................................. 88 ? pdm pattern setting register ................................................... 89 ? mp0 function setting register ................................................. 89 ? mp1 function setting register ................................................. 90 ? mp2 function setting register ................................................. 91 ? mp3 function setting register ................................................. 91 ? mp4 function setting register ................................................. 92 ? mp5 function setting register ................................................. 93 ? mp6 function setting register ................................................. 94 ? push-button volume settings register .................................... 94 ? push-button volume control assignment register .............. 95 ? debounce modes register ......................................................... 96 ? headphone line output select register .................................. 97 ? decimator power control register .......................................... 97 ? asrc interpolator and dac modulator power control register ......................................................................................... 99 ? analog bias control 0 register ................................................. 99 ? analog bias control 1 register ............................................... 100 ? digital pin pull-up control 0 register .................................. 101 ? digital pin pull-up control 1 register .................................. 102 ? digital pin pull-down control 0 register ............................ 103 ? digital pin pull-down control 1 register ............................ 103 ? digital pin drive strength control 0 register ...................... 104 ? digital pin drive strength control 1 register ...................... 105 ? fast rate control register ....................................................... 105 ? dac interpolation control register ...................................... 106 ? volume control bypass register ............................................ 107 ? outline dimensions ...................................................................... 108 ? ordering guide ......................................................................... 108 ? revision history 12/2016revision 0: initial version
adau1777 data sheet rev. 0 | page 4 of 108 specifications master clock = 12.288 mhz, serial input sa mple rate = 48 khz, measurement bandwidth = 20 hz to 20 khz, word width = 24 bits, t a = 25c, outputs line loaded with 10 k?. analog performance s pecifications avdd = iovdd = 1.8 v, dvdd = 1.1 v, unless otherwise noted. phase - locked loop ( pll ) disabled, direct master clock. table 1 . parameter test conditions/comments min t yp max unit analog - to - digital converters (adcs) adc resolution all adcs 24 bits digital attenuation step 0.375 db digital attenuation range 95 db input resistance gain settings do not include 10 db gain from pga_x_boost settings; this additional gain does not affect input impedance; pga_pop_disx = 1 single - ended line input 0 db gain 14.3 k? programmable gain amplifier ( pga ) inputs ? 12 db gain 32.0 k? 0 db gain 20 k? + 35.25 db gain 0.68 k? line input pga_enx = 0, pga_x_boost = 0, pga_pop_disx = 1 full - scale input voltage scales linearly with avdd avdd/ 3.3 v rms avdd = 1.8 v 0. 55 v rms avdd = 1.8 v 1. 54 v p - p avdd = 3.3 v 1.00 v rms avdd = 3.3 v 2. 83 v p - p dynamic range 1 20 hz to 20 khz, ?60 db input with a - weighted filter (rms) avdd = 1.8 v 95 97 db avdd = 3.3 v 99 102 db with flat 20 hz to 20 khz filter avdd = 1.8 v 92 94 db avdd = 3.3 v 96 99 db signal - to - noise ratio (snr) 2 with a - weighted filter (rms) avdd = 1.8 v 96 98 db avdd = 3.3 v 100 103 db with flat 20 hz to 20 khz filter avdd = 1.8 v 92 96 db avdd = 3.3 v 96 100 db interchannel gain mismatch 0 40 200 mdb total harmonic distortion + noise (thd + n) 20 hz to 20 khz, ?1 db from f ull - s cale i nput avdd = 1.8 v ? 90 ? 83 db avdd = 3.3 v ? 94 ? 87 db offset error ? 0.11 +0.12 mv gain error ? 0.4 +0.2 db interchannel isolation cm capacitor = 2 2 f 95 db power supply rejection ratio (psrr) cm capacitor = 2 2 f, 100 mv p - p at 1 khz 55 db pga input pga_enx = 1, pga_x_boost = 0 full - scale input voltage scales linearly with avdd avdd/3.3 v rms avdd = 1.8 v 0.5 5 v rms avdd = 1.8 v 1.54 v p - p avdd = 3.3 v 1 .00 v rms avdd = 3.3 v 2.83 v p - p dynamic range 1 20 hz to 20 khz, ?60 db input with a - weighted filter (rms) avdd = 1.8 v 9 4 db avdd = 3.3 v 102 db with flat 20 hz to 20 khz filter avdd = 1.8 v 92 db avdd = 3.3 v 9 8 db
data sheet adau1777 rev. 0 | page 5 of 108 parameter test conditions/comments min t yp max unit thd + n 20 hz to 20 khz, ?1 d b from full - scale input avdd = 1.8 v ? 88 db avdd = 3.3 v ? 90 db snr 2 with a - weighted filter (rms) avdd = 1.8 v 9 4 db avdd = 3.3 v 102 db with flat 20 hz to 20 khz filter avdd = 1.8 v 93 db avdd = 3.3 v 98 db pga gain variation standard deviation with ?12 db setting 0.05 db with +35.25 db setting 0.15 db pga boost pga_x_boost 10 db pga mute attenuation pga_mutex ? 6 3 db interchannel gain mismatch 0.0 4 db offset error ? 0.12 +0.12 mv gain error ? 0.05 db interchannel isolation 100 db psrr cm capacitor = 20 f , 100 mv p - p at 1 khz 63 db microphone bias mic_enx = 1 bias voltage 0.65 avdd avdd = 1.8 v, mic_gainx = 1 1.14 1.16 1.17 v avdd = 3.3 v, mic_gainx = 1 2.10 2.12 2.14 v 0.90 avdd avdd = 1.8 v, mic_gainx = 0 1.61 1.63 1.65 v avdd = 3.3 v, mic_gainx = 0 2.95 2.97 2.99 v bias current source 3 ma output impedance 1 ? micbiasx isolation mic_gainx = 0 95 db mic_gainx = 1 99 db noise in the signal bandwidth 20 hz to 20 khz , 4.7 f decoupling capacitor , 5.0 k? load on the micbiasx pins avdd = 1.8 v mic_gainx = 0 27 nv/hz mic_gainx = 1 16 nv/hz avdd = 3.3 v mic_gainx = 0 35 nv/hz mic_gainx = 1 19 nv/hz digital - to - analog converters (dacs) resolution all dacs 24 bits digital attenuation step 0.375 db digital attenuation range 95 db dac single - ended output single - ended operation , hpoutlp/loutlp and hpoutrp/loutrp pins full - scale output voltage scales linearly with avdd avdd/3.4 v rms avdd = 1.8 v 0.53 v rms avdd = 1.8 v 1.5 v p - p avdd = 3.3 v 0.97 v rms avdd = 3.3 v 2.74 v p - p mute attenuation ? 72 db line o utput m ode dynamic range 1 20 hz to 20 khz, 60 db input with a - weighted filter (rms) avdd 1.8 v 97 100 db avdd 3.3 v 102 104 db with flat 20 hz to 20 khz filter avdd 1.8 v 95 97 db avdd 3.3 v 99 101 db
adau1777 data sheet rev. 0 | page 6 of 108 parameter test conditions/comments min t yp max unit snr 2 20 hz to 20 khz with a - weighted filter (rms) avdd = 1.8 v 98 100 db avdd = 3.3 v 102 104 db with flat 20 hz to 20 khz filter avdd = 1.8 v 96 98 db avdd = 3.3 v 99 102 db interchannel gain mismatch 0 50 200 mdb thd + n 20 hz to 20 khz, ?1 dbfs input db avdd = 1.8 v ? 93 ? 89 db avdd = 3.3 v ? 94 ? 90 db gain error ? 0.13 + 0.13 db headphone m ode dynamic range 1 20 hz to 20 khz, ?60 db input with a - weighted filter (rms) avdd = 1.8 v 97 100 db avdd = 3.3 v 102 104 db with flat 20 hz to 20 khz filter avdd = 1.8 v 95 97 db avdd = 3.3 v 99 101 db snr 2 20 hz to 20 khz with a - weighted filter (rms) avdd = 1.8 v 98 100 db avdd = 3.3 v 102 104 db with flat 20 hz to 20 khz filter avdd = 1.8 v 96 98 db avdd = 3.3 v 100 102 db interchannel gain mismatch 0 50 230 mdb thd + n 20 hz to 20 khz, ?1 dbfs input 32 ? l oad avdd = 1.8 v, o utput p ower = 6. 3 mw ? 7 9 ? 67 db avdd = 3.3 v, o utput p ower = 20 . 5 mw ? 8 4 ? 67 db 24 ? l oad avdd = 1.8 v, o utput p ower = 8.4 mw ? 79 ? 65 db avdd = 3.3 v, o utput p ower = 27 m w ? 80 ? 64 db 16 ? l oad avdd = 1.8 v, o utput p ower = 13 mw ? 74 ? 61 db avdd = 3.3 v, o utput p ower = 30 mw ? 77 ? 67 db gain error ? 0.13 +0.13 db headphone output power 32 ? load avdd = 1.8 v, <0.1% thd + n 8.0 mw avdd = 3.3 v, <0.1% thd + n 28.1 mw 24 ? load avdd = 1.8 v, <0.1% thd + n 11. 1 mw avdd = 3.3 v, <0.1% thd + n 30.5 mw 16 ? load avdd = 1.8 v, <0.1% thd + n 16. 5 mw avdd = 3.3 v, <0.1% thd + n 32.7 mw offset error ? 0.11 +0.09 mv interchannel isolation 1 khz, 0 dbfs input signal 100 db psrr cm capacitor = 22 f , 100 mv p - p at 1 khz 70 db dac differential output differential operation full - scale output voltage scales linearly with avdd avdd/1.7 v rms avdd = 1.8 v 1.0 6 v rms avdd = 1.8 v 3.00 v p - p avdd = 3.3 v 1.94 v rms avdd = 3.3 v 5.49 v p - p mute attenuation ? 72 db line output mode dynamic range 1 20 hz to 20 khz, ?60 db input with a - weighted filter (rms) avdd = 1.8 v 102 105 db avdd = 3.3 v 105 107 db with flat 20 hz to 20 khz filter avdd = 1.8 v 100 102 db avdd = 3.3 v 102 105 db
data sheet adau1777 rev. 0 | page 7 of 108 parameter test conditions/comments min t yp max unit snr 2 20 hz to 20 khz with a - weighted filter (rms) avdd = 1.8 v 103 105 db avdd = 3.3 v 106 108 db with flat 20 hz to 20 khz filter avdd = 1.8 v 100 102 db avdd = 3.3 v 103 105 db interchannel gain mismatch 0 50 200 mdb thd + n 20 hz to 20 khz, ?1 dbfs input db avdd = 1.8 v ? 96 ? 90 db avdd = 3.3 v ? 96 ? 90 db gain error ? 0.1 +0.16 db headphone mode dynamic range 1 20 hz to 20 khz, ?60 db input with a - weighted filter (rms) avdd = 1.8 v 102 105 db avdd = 3.3 v 105 107 db with flat 20 hz to 20 khz filter avdd = 1.8 v 100 102 db avdd = 3.3 v 102 104 db snr 2 20 hz to 20 khz with a - weighted filter (rms) avdd = 1.8 v 103 106 db avdd = 3.3 v 106 108 db with flat 20 hz to 20 khz filter avdd = 1.8 v 101 103 db avdd = 3.3 v 104 106 db interchannel gain mismatch 0 75 370 mdb thd + n 32 ? load ? 1 dbfs, avdd = 1.8 v, o utput p ower = 2 6 mw ? 75 ? 64 db ? 1 dbfs, avdd = 3.3 v, o utput p ower = 87 mw ? 83 ? 75 db 24 ? load ? 2 dbfs, avdd = 1.8 v, o utput p ower = 27 mw ? 75 ? 64 db ? 1 dbfs, avdd = 3.3 v, o utput p ower = 11 5 mw ? 82 ? 75 db 16 ? load ? 3 dbfs, avdd = 1.8 v, o utput p ower = 32 mw ? 75 ? 65 db ? 1 dbfs, avdd = 3.3 v, o utput p ower = 168 mw ? 77 ? 68 db gain error headphone mode ? 0.25 +0.25 db headphone output power 32 ? load avdd = 1.8 v, <0.1% thd + n 29.1 mw avdd = 3.3 v, <0.1% thd + n 111.8 mw 24 ? load avdd = 1.8 v, <0.1% thd + n 31.8 mw avdd = 3.3 v, <0.1% thd + n 148.3 mw 16 ? load avdd = 1.8 v, <0.1% thd + n 32.3 mw avdd = 3.3 v, <0.1% thd + n 193.0 mw offset error ? 0.12 0 +0.08 mv interchannel isolation 1 khz, 0 dbfs input signal 100 db psrr cm capacitor = 22 f , 100 mv p - p at 1 khz 73 db analog - to - analog latency f s = 768 khz 5 s f s = 192 khz 38 s cm reference cm pin common - mode reference output avdd/2 v common - mode source impedance 5 k? regulator line regulation 1 mv/v load regulation 6 mv/ma 1 dynamic range is the ratio of the sum of the noise and harmonic power in the band of interest with a ? 60 dbfs signal present vs. the full - scale power level in decibels . 2 snr is the ratio of the sum of all noise power in the band of interest with no signal present vs. the full - scale power level in decibels.
adau1777 data sheet rev. 0 | page 8 of 108 crystal amplifier sp ecifications avdd = iovdd = 1.8 v, dvdd = 1.1 v, unless otherwise noted. table 2 . parameter min typ max unit crystal amplifier jitter 270 500 p s rms frequency range 8 27 mhz load capacitance 20 pf digital input/output specifications ?40c < t a < +85c, iovdd = 3. 3 v 10% and 1.8 v ? 5% to 1.8 v + 10% , unless otherwise noted . table 3 . parameter test conditions/comments min typ max unit input/output input voltage high (v ih ) iovdd = 3.3 v 2.0 v iovdd = 1.8 v 1.1 v low (v il ) iovdd = 3.3 v 0.8 v iovdd = 1.8 v 0.45 v input leakage iovdd = 3.3 v, i ih 1 at v ih = 2.0 v 10 a i il 1 at v il = 0.8 v 10 a iovdd = 1.8 v, i ih 1 at v ih = 1.1 v 10 a i il 1 at v il = 0.45 v 10 a output voltage high (v oh ) low drive strength i oh 1 = 1 ma iovdd ? 0.6 v high drive strength i oh 1 = 3 ma iovdd ? 0.6 v output voltage low (v ol ) low drive strength i ol 1 = 1 ma 0.4 v high drive strength i ol 1 = 3 ma 0.4 v input capacitance 5 pf 1 i ih is the c urrent when the i nput is h igh ; i i l is the current when the input is low; i oh is the current when the output is high; and i o l is the current when the output is low. power supply specifi cations avdd = iovdd = 1.8 v, dvdd = 1.1 v, unless otherwise noted. table 4 . parameter test conditions/comments min typ max unit supplies avdd voltage 1.71 1.8 3.63 v dvdd voltage 1.045 1.1 1.98 v iovdd voltage 1.71 1.8 3.63 v analog current (i avdd ) normal operation see table 5 power - down 1.6 a digital i nput /o utput current (i iovdd ) normal operation see table 5 power - down 1.3 a power consumption all supplies see table 5 power - down, all supplies 1 w
data sheet adau1777 rev. 0 | page 9 of 108 typical power manage ment settings typical anc settings , m aster clock = 12.288 mhz , pll disabled, crystal oscillator enabled , core f s = dac = adc = 768 khz. o n - board regulator enabled. two adcs with pga enabled and two adcs configured for line input , no input signal. two dacs are configured for differential headphone (hp) operation; dac outputs are unloaded. both micbias0 and micbias1 enabled at 0.9 av d d . asrcs and pulse density modu lation (pdm) modulator disabled. core running 26 out of 32 possible instructions. serial port set to slave. see r egister 0x46 and register 0x47 for settings. table 5 . operating voltage power management setting typical avdd current consumption (ma) typical iovdd current consumption (ma) typical adc thd + n (db) typical hp output thd + n (db) total power consumption (mw) avdd = iovdd = 3.3 v normal 9.71 2.58 ? 91 ? 97 40.56 extreme p ower s aving 7.55 2.57 ? 86 ? 96 33.40 power s aving 7.99 2.57 ? 87 ? 96 34.85 enhanced p erformance 10.97 2.58 ? 91 ? 98 44.72 avdd = iovdd = 1.8 v normal 7.29 0.37 ? 87 ? 95 13.79 extreme p ower s aving 5.38 0.37 ? 81 ? 89 10.35 power s aving 5.73 0.37 ? 81 ? 90 10.98 enhanced performance 8.62 0.37 ? 87 ? 95 16.18 digital filters specifications table 6 . parameter test conditions/comments min typ max unit adc input to dac output path pass - band ripple dc to 20 khz, f s 768 khz 0.03 +0.01 db dc to 20 khz, f s 192 khz 0.02 db sample rate converter
adau1777 data sheet rev. 0 | page 10 of 108 digital timing speci fications ?40c < t a < +85c, iovdd = 1.71 v to 3.63 v, dvdd = 1.045 v to 1.98 v. table 7 . digital timing limit parameter t min t max unit description master clock (mclk) t mp 37 125 ns mclkin period; 8 mhz to 27 mhz input clock using pll t mclk 77 82 ns internal mclk period; direct mclk and pll output divided by 2 serial port t bl 40 ns bclk low pulse width (master and slave modes) t bh 40 ns bclk high pulse width (master and slave modes) t ls 10 ns lrclk setup; time to bclk rising (slave mode) t lh 10 ns lrclk hold; time from bclk rising (slave mode) t ss 5 ns dac_sdata setup; time to bclk rising (master and slave modes) t sh 5 ns dac_sdata hold; time from bclk rising (master and slave modes) t ts 10 ns bclk falling to lrclk timing skew (master mode) t sod 0 34 ns adc_sdatax delay; time from bclk falling (master and slave modes) t sotd 30 ns bclk falling to adc_sdatax driven in time - division multiplexing (tdm ) tristate mode t sotx 30 ns bclk falling to adc_sdatax tristate in tdm tristate mode seriral peripheral interface ( spi ) port f sclk 6.25 mhz sclk frequency t ccpl 80 ns sclk pulse width low t ccph 80 ns sclk pulse width high t cls 5 ns ss setup; time to sclk rising t clh 100 ns ss hold; time from sclk rising t clph 80 ns ss pulse width high t cds 10 ns mosi setup; time to sclk rising t cdh 10 ns mosi hold; time from sclk rising t cod 101 ns miso delay; time from sclk falling i 2 c port f scl 400 khz scl frequency t sclh 0.6 s scl high t scll 1.3 s scl low t scs 0.6 s scl rise setup time (to sda falling), relevant for repeated start condition t scr 250 ns scl and sda rise time, c load = 400 pf t sch 0.6 s scl fall hold time (from sda falling), relevant for start condition t ds 100 ns sda setup time (to scl rising) t scf 250 ns scl and sda fall time; c load = 400 pf t bft 0.6 s scl rise setup time (to sda rising), relevant for stop condition i 2 c eeprom self boot t sche 26 t mp ? 70 ns scl fall hold time (from sda falling), relevant for start condition; t mp is the input clock on the mclkin pin t scse 38 t mp ? 70 ns scl rise setup time (to sda falling), relevant for repeated start condition t bfte 70 t mp ? 70 ns scl rise setup time (to sda rising), relevant for stop condition t dse 6 t mp ? 70 ns delay from scl falling to sda changing t bhte 32 t mp ns sda rising in self boot stop condition to sda falling edge for external master start condition
data sheet adau1777 rev. 0 | page 11 of 108 limit parameter t min t max unit description multipurpose and power- down pins t gil 1.5 1/f s s mpx input latency; time until high or low value is read by core t rlpw 20 ns pd low pulse width digital microphone t cf 20 ns digital microphone clock fall time t cr 20 ns digital microphone clock rise time t ds 40 digital microphone valid data start time t de 0 ns digital microphone valid data end time pdm output t dcf 20 ns pdm clock fall time t dcr 20 ns pdm clock rise time t ddv 0 30 ns pdm delay time for valid data digital timing diagrams bclk lrclk dac_sdata left justified mode lsb dac_sdata i 2 s mode dac_sdata right justified mode t bh msb msb ? 1 msb msb 8-bit clocks (24-bit data) 12-bit clocks (20-bit data) 14-bit clocks (18-bit data) 16-bit clocks (16-bit data) t ls t ss t sh t sh t ss t ss t sh t ss t sh t lh t bl 14796-002 figure 2. serial input port timing
adau1777 data sheet rev. 0 | page 12 of 108 lrclk lsb adc_sdatax i 2 s mode adc_sdatax right justified mode msb adc_sdatax left justified mode msb msb ? 1 adc_sdatax with tristate msb lsb msb 8-bit clocks (24-bit data) 12-bit clocks (20-bit data) 14-bit clocks (18-bit data) 16-bit clocks (16-bit data) t ls t sod t sod t sotd t sod t sotx t lh t ts t bl bclk t bh high-z high-z 14796-003 figure 3. serial output port timing ss s clk mosi miso t cls t cds t cdh t cod t ccph t ccpl t clh t clph 14796-004 figure 4. spi port timing t sch t sclh t scr t scll t scf t ds s d a scl t sch t bft t scs 14796-005 figure 5. i 2 c port timing
data sheet adau1777 rev. 0 | page 13 of 108 t sche t dse t scse t bfte t bhte s d a scl 14796-006 figure 6. i 2 c eeprom self boot timing dmic0_1/dmic2_3 valid left sample valid left sample valid right sample clkout t cr t cf t ds t de t ds t de 14796-007 figure 7. digital microphone timing t dcf pdmout clkout right left right left t dcr t ddv t ddv 14796-008 figure 8. pdm output timing
adau1777 data sheet rev. 0 | page 14 of 108 absolute maximum rat ings table 8 . parameter rating power suppl ies (avdd, iovdd) ?0.3 v to +3.63 v digital supply (dvdd) ?0.3 v to +1.98 v input current (except supply pins) 20 ma analog input voltage (signal pins) ? 0.3 v to avdd + 0.3 v digital input voltage (signal pins) ? 0.3 to iovdd + 0.3 v operating temperature range (case ) ?40c to +85c storage temperature range ?65c to +150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specif ication is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance thermal performance is directly linked to printed circuit board (pcb) design and operating environment. caref ul attention to pcb thermal design is required. ja is the natural convection junction - to - ambient thermal resistance measured in a one cubic foot sealed enclosure for more information, see the a n - 617 application note , wafer level chip scale package . table 9 . thermal resistance package type ja unit cb -36-4 1 36 c/w 1 thermal impedance simulated values are based on a 4 - layer pcb with two signal layers and two power planes using natural convection cooling. see jedec jesd51 - 9 . esd caution
data sheet adau1777 rev. 0 | page 15 of 108 pin configuration an d function descripti ons ball a1 indicator adau1777 top view (ball side down) scl/sclk xtali/mclkin dmic2_3/mp5 micbias0 selfboot micbias1 sda/miso dmic0_1/mp4 iovdd adc_sdata1/ clkout/mp6 xtalo adc_sdata0/ pdmout/mp1 dac_sdata/ mp0 addr0/ss 1 2 3 4 a b c d e avdd ain0 pd ain3 addr1/mosi agnd ain1 agnd ain2 cm reg_out hpoutrn/ loutrn bclk/mp2 lrclk/mp3 hpoutlp/ loutlp avdd hpoutrp/ loutrp avdd dgnd dvdd agnd hpoutln/ loutln 5 6 f 7 14796-009 figure 9 . pin configuration table 10 . pin function descriptions pin no. mnemonic type 1 description a1 dgnd pwr digital ground. t ie t he agnd and dgnd pins directly together in a common ground plane. a2 bclk/mp2 d_io serial data port bit clock (bclk). multipurpose p in (mp2) . a3 adc_sdata0/pdmout/mp1 d_io adc serial data output 0 (adc_sdata0). stereo pdm output to drive a high efficiency class - d amplifier (pdmout). multipurpose p in (mp1). a4 adc_sdata1/clkout/mp6 d_io serial data output 1 (adc_sdata1). master clock output/clock for the digital microphone input and pdm output (clkout). multipurpose p in (mp6). a5 xtalo a_out crystal clock output. this pin is the output of the crystal amplifier ; do not use t his pin to provid e a clock to other ics in the system. if a master clock output is needed, use clkout (pin a4 ). a6 xtali/mclkin d_in crystal clock input (xtali). master clock input (mclkin). a7 iovdd pwr supply for digital input and output pins. the digital output pi ns are supplied from iovdd ; thus, the iovdd voltage level is the highest input voltage that can be present on the digital input pins. the current draw of this pin is variable because it is dependent on the loads of the digital outputs. decouple iovdd to dgnd with a 0.1 f capacitor. b1 dvdd pwr digital core supply. the digital supply can be generated from an on - board regulator or supplied directly from an external supply. in each case, decouple dvdd to dgnd with a 0.1 f capacitor. b2 lrclk/mp3 d_io serial data port frame clock (lrclk). multipurpose pin ( mp3). b3 dac_sdata/mp0 d_io dac serial input data (dac_sdata). multipurpose pin ( mp0). b4 dmic2_3/mp5 d_in digital microphone stereo input 2 and digital microphone stereo input 3 (dmic2_3). multipurpose pin ( mp5).
adau1777 data sheet rev. 0 | page 16 of 108 pin no. mnemonic type 1 description b5 dmic0_1/mp4 d_in digital microphone stereo input 0 and digital microphone stereo input 1 (dmic0_1). multipurpose pin ( mp4). b6 sda/miso d_io i 2 c data (sda) . this pin is a bidirectional open - collector. the line connected to this pin must have a 2.0 k? pull - up resistor. spi data output (miso). this spi data output read s back registers and memory locations. it is tristated when an spi read is not active. b7 scl/sclk d_in i 2 c clock (scl) . this pin is always an open - collector input when the device is in i 2 c control mode. when the device is in self boot mode, this pin is an open - collector output (i 2 c master) . the line connected to this pin must have a 2.0 k? pull - up resistor. spi clock (sclk). this pin either can run continuously or be gated off between spi transactions. c1 hpoutrp/loutrp a_out right headphone output noninverted (hpoutrp). line output noninverted, single - ended line output (loutrp). c2 reg_out a_out regulator output voltage. connect t his pin to dvdd if the internal voltage regulator is being used to generate the dvdd voltage. c6 addr0/ ss d_in i 2 c address 0 ( addr0) . spi latch signal ( ss ) . this pin must go low at the beginning of an spi transaction and high at the end of a transaction. each spi transaction can take a different number of sclk cycles to complete, depending on the address and read/write bit that are sent at the beginning of the spi transaction. c7 micbias0 a_out bias voltage for electret microphone. decouple this pin with a 1 f capacitor. d1 avdd pwr headphone amplifier power, 1.8 v to 3.3 v analog supply. decouple t his pin to agnd with a 0.1 f capacitor. the pcb trace to this pin must have the capacity to supply the higher current necessary for driving the headphone outputs. d2 hpoutrn/loutrn a_out right headphone output inverted (hpoutrn). line output inverted (loutrn). d6 addr1/mosi d_in i 2 c address 1 ( addr1) . spi data input (mosi). d7 micbias1 a_out bias voltage for electret microphone. decouple this pin with a 1 f capacitor. e1 agnd pwr headphone amplifier ground. e2 hpoutlp/loutlp a_out left headphone output noninverted (hpoutlp). line output noninverted, single - ended line output (loutlp). e3 pd d_in active low power - down. all digital and analog circuits are powered down. a n internal pull - down resistor is on this pi n; therefore, the adau1777 is held in power - down mode if its input signal is floating while power is applied to the supply pins. e4 ain3 a_in adc3 input. e5 ain0 a_in adc0 input. e6 selfboot d_in self boot enable . pull this pin up to iovdd at power - up to enable the self boot mode. e7 avdd pwr 1.8 v to 3.3 v analog supply. decouple t his pin to agnd with a 0.1 f capacitor. f1 hpoutln/loutln a_out left headphone output inverted (hpoutln). line output inverted (loutln). f2 avdd pwr 1.8 v to 3.3 v analog supply. decouple t his pin to agnd with a 0.1 f capacitor. f3 agnd pwr analog ground. f4 ain2 a_in adc2 input. f5 ain1 a_in adc1 input. f6 cm a_out a vdd/2 v common - mode reference. connect a 10 f to 47 f decoupling capacitor between t his pin and ground to reduce crosstalk between the adcs and dacs. the material of the capacitors is not critical. this pin can bias external analog circuits, as long as t hey are not drawing current from cm (for example, the noninverting input of an op amp). f7 agnd pwr analog ground. the agnd and dgnd pins can be tied directly together in a common ground plane. decouple agnd to avdd with a 0.1 f capacitor. 1 pwr is power; d_io is digital input/output ; a_out is analog output; d_in is digital input ; and a_in is analog input.
data sheet adau1777 rev. 0 | page 17 of 108 typical performance characteristics 0.4 ?3.0 ?2.8 ?2.6 ?2.4 ?2.2 ?2.0 ?1.8 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 10k 100 1k relative level (db) frequency (hz) 14796- 1 12 figure 10 . relative level vs. frequency, f s = 96 khz, signal path = ain0 to dsp (without processing) to loutlx ?100 ?150 ?200 ?250 ?300 ?350 ?400 ?450 ?500 ?550 ?600 ?650 ?700 ?750 ?800 ?850 ?900 ?950 ?1000 ?1050 ?1100 0 4 8 12 16 20 24 28 32 36 40 phase (degrees) frequency (khz) 14796- 1 16 figure 11 . phase vs. frequency, 40 khz bandwidth, f s = 96 khz, signal path = ain0 to dsp (without processing) to loutlx 1 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 10k 1k 100 relative level (db) frequency (hz) 14796- 1 17 figure 12 . relative level vs. frequency, f s = 192 khz, signal path = ain0 to dsp (without processing) to loutlx 120 110 100 90 80 70 60 50 40 30 20 10 0 0 4 8 12 16 20 24 28 32 36 40 group delay (s) frequency (khz) 14796- 1 15 figure 13 . group delay vs. frequency, f s = 96 khz, signal path = ain0 to dsp (without processing) to loutlx ?155 ?160 ?165 ?170 ?175 ?180 ?185 ?190 ?195 ?200 ?205 ?210 ?215 ?220 ?225 0.1 0.3 0.5 0.9 0.9 1.1 1.3 1.5 1.7 1.9 phase (degrees) frequency (khz) 14796- 1 19 figure 14 . phase vs. frequency, 2 khz bandwidth, f s = 96 khz, signal path = ain0 to dsp (without processing) to loutlx 120 0 10 20 30 40 50 60 70 80 90 100 110 0 10 20 30 40 50 60 70 80 group delay (s) frequency (khz) 14796-120 figure 15 . group delay vs. frequency, f s = 192 khz, signal path = ain0 to dsp (without processing) to loutlx
adau1777 data sheet rev. 0 | page 18 of 108 0 ?1400 ?1300 ?1200 ?1100 ?1000 ?900 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 0 10 20 30 40 50 60 70 80 phase (degrees) frequency (khz) 14796- 1 18 figure 16 . phase vs. frequency, 80 khz bandwidth, f s = 192 khz, signal path = ain0 to dsp (without processing) to loutlx 0.50 ?0.50 ?0.45 ?0.40 ?0.35 ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 10k 1k 100 relative level (db) frequency (hz) 14796-222 figure 17 . relative level vs. frequency , f s =768 khz, signal path = ain0 to dsp (witho ut processing) to loutlx ?140 ?160 ?180 ?200 ?220 ?240 ?260 ?280 ?300 ?320 ?340 ?360 ?380 ?400 ?420 0 10 20 30 40 50 60 70 80 phase (degrees) frequency (khz) 14796-223 figure 18 . phase vs. frequency, 8 0 khz bandwidth , f s =768 khz, signal path = ain0 to dsp (without processing) to loutlx ?155 ?160 ?165 ?170 ?175 ?180 ?185 ?190 ?195 ?200 ?205 ?210 ?215 ?220 ?225 0.1 0.3 0.5 0.9 0.9 1.1 1.3 1.5 1.7 1.9 phase (degrees) frequency (khz) 14796-121 figure 19 . phase vs. frequency, 2 khz bandwidth, f s = 192 khz, signal path = ain0 to dsp (without processing) to loutlx 120 0 10 20 30 40 50 60 70 80 90 100 110 0 10 20 30 40 50 60 70 80 group delay (s) frequency (khz) 14796-225 figure 20 . group delay vs. frequency , f s =768 khz, signal path = ain0 to dsp (without processing) to loutlx ?160 ?162 ?164 ?166 ?168 ?170 ?172 ?174 ?176 ?178 ?180 ?182 ?184 ?186 0.1 0.3 0.5 0.9 0.9 1.1 1.3 1.5 1.7 1.9 phase (degrees) frequency (khz) 14796-226 figure 21 . phase vs. frequency, 2 khz bandwidth , f s =768 khz, signal path = ain0 to dsp (without processing) to loutlx
data sheet adau1777 rev. 0 | page 19 of 108 1.0 ?8.0 ?7.5 ?7.0 ?6.5 ?6.0 ?5.5 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 100 1k 10k relative level (db) frequency (hz) 14796-124 figure 22 . relative level vs. frequency, f s = 96 khz, signal path = ain0 to asrc to adc_sdata0 200 ?1500 ?1400 ?1300 ?1200 ?1100 ?1000 ?900 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 0 100 0 4 8 12 16 20 24 28 32 36 40 phase (degrees) frequency (khz) 14796-128 figure 23 . phase vs. frequency, 40 khz bandwidth, f s = 96 khz, signal path = ain0 to asrc to adc_sdata0 2 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 10k 100 1k relative level (db) frequency (hz) 14796-129 figure 24 . relative level vs. frequency, f s = 192 khz, signal path = ain0 to asrc to adc_sdata0 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 4 8 12 16 20 24 28 32 36 40 group delay (s) frequency (khz) 14796-127 figure 25 . group delay vs. frequency, f s = 96 khz, signal path = ain0 to asrc to adc_sdata0 10 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 phase (degrees) frequency (khz) 14796-131 figure 26 . phase vs. frequency, 2 khz bandwidth, f s = 96 khz, signal path = ain0 to asrc to adc_sdata0 300 0 20 40 60 80 100 120 140 160 180 220 260 280 200 240 0 10 20 30 40 50 60 70 80 group delay (s) frequency (khz) 14796-132 figure 27 . group delay vs. frequency, f s = 192 khz, signal path = ain0 to asrc to adc_sdata0
adau1777 data sheet rev. 0 | page 20 of 108 200 ?1800 ?1600 ?1400 ?1200 ?1000 ?800 ?600 ?400 ?200 0 80 0 10 20 30 40 50 60 70 phase (degrees) frequency (khz) 14796-130 figure 28 . phase vs. frequency, 80 khz bandwidth, f s = 192 khz, signal path = ain0 to asrc to adc_sdata0 2 ?16 ?15 ?14 ?13 ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 10k 1k 100 relative level (db) frequency (hz) 14796-227 figure 29 . relative level vs. frequency, f s = 786 khz, signal path = ain0 to asrc to adc_sdata0 100 ?1300 ?1200 ?1100 ?1000 ?900 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 0 0 10 20 30 40 50 60 70 80 phase (degrees) frequency (khz) 14796-228 figure 30 . phase vs. frequency, 8 0 khz bandwidth , f s = 786 khz, signal path = ain0 to asrc to adc_sdata0 10 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 phase (degrees) frequency (khz) 14796-133 figure 31 . phase vs. frequency, 2 khz bandwidth, f s = 192 khz, signal path = ain0 to asrc to adc_sdata0 300 260 280 240 220 200 180 160 140 120 100 80 60 40 20 0 0 10 20 30 40 50 60 70 80 group delay (s) frequency (khz) 14796-229 figure 32 . group delay vs. frequency, f s = 786 khz, signal path = ain0 to asrc to adc_sdata0 25 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 phase (degrees) frequency (khz) 14796-230 figure 33 . phase vs. frequency, 2 khz bandwidth , f s = 786 khz, signal path = ain0 to asrc to adc_sdata0
data sheet adau1777 rev. 0 | page 21 of 108 0.5 ?6.0 ?5.5 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 100 1k 10k relative level (db) frequency (hz) 14796-136 figure 34 . relative level vs. frequency, f s = 96 khz, signal path = dac_sdata to asrc to loutlx 200 ?1700 ?1600 ?1500 ?1400 ?1300 ?1200 ?1100 ?1000 ?900 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 0 100 phase (degrees) frequency (khz) 0 4 8 12 16 20 24 28 32 36 40 14796-140 figure 35 . phase vs. frequency, 40 khz bandwidth, f s = 96 khz, signal path = dac_sdata to asrc to loutlx 1.0 ?8.0 ?7.5 ?7.0 ?6.5 ?6.0 ?5.5 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 relative level (db) frequency (hz) 100 1k 10k 14796-141 figure 36 . relative level vs. frequency, f s = 192 khz, signal path = dac_sdata to asrc to loutlx 300 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 group delay (s) frequency (khz) 0 4 8 12 16 20 24 28 32 36 40 14796-139 figure 37 . group delay vs. frequency, f s = 96 khz, signal path = dac_sdata to asrc to loutlx ?150 ?250 ?245 ?240 ?235 ?230 ?225 ?220 ?215 ?210 ?205 ?200 ?195 ?190 ?185 ?180 ?175 ?170 ?165 ?160 ?155 phase (degrees) frequency (khz) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 14796-143 figure 38 . phase vs. frequency, 2 khz bandwidth, f s = 96 khz, signal path = dac_sdata to asrc to loutlx 300 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 80 0 10 20 30 40 50 60 70 group delay (s) frequency (khz) 14796-144 figure 39 . group delay vs. frequency, f s = 192 khz, signal path = dac_sdata to asrc to loutlx
adau1777 data sheet rev. 0 | page 22 of 108 0 ?1800 ?1700 ?1600 ?1500 ?1400 ?1300 ?1200 ?1100 ?1000 ?900 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 0 1020304050607080 phase (degrees) frequency (khz) 14796-142 figure 40. phase vs. frequency, 80 khz bandwidth, f s = 192 khz, signal path = dac_sdata to asrc to loutlx 0.4 ?3.4 ?3.2 ?3.0 ?2.8 ?2.6 ?2.4 ?2.2 ?2.0 ?1.8 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 relative level (db) frequency (hz) 100 1k 10k 14796-231 figure 41. relative level vs. frequency, f s = 786 khz, signal path = dac_sdata to asrc to loutlx ? 100 ?1100 ?1000 ?900 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?150 ?1050 ?950 ?850 ?750 ?650 ?550 ?450 ?350 ?250 phase (degrees) frequency (khz) 0 4 8 1216202428323640 14796-232 figure 42. phase vs. frequency, 20 khz bandwidth, f s = 786 khz, signal path = dac_sdata to asrc to loutlx ? 160 ?215 ?210 ?205 ?200 ?195 ?190 ?185 ?180 ?175 ?170 ?165 phase (degrees) frequency (khz) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 14796-145 figure 43. phase vs. frequency, 2 khz bandwidth, f s = 192 khz, signal path = dac_sdata to asrc to loutlx 300 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 80 0 10203040506070 group delay (s) frequency (khz) 14796-233 figure 44. group delay vs. frequency, f s = 786 khz, signal path = dac_sdata to asrc to loutlx ? 160 ?165 ?164 ?166 ?168 ?170 ?172 ?174 ?176 ?178 ?180 ?182 ?184 ?186 ?188 ?190 ?192 ?194 ?196 ?198 ?200 phase (degrees) frequency (khz) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 14796-234 figure 45. phase vs. frequency, 2 khz bandwidth f s = 786 khz, signal path = dac_sdata to asrc to loutlx
data sheet adau1777 rev. 0 | page 23 of 108 35 30 25 20 15 10 5 0 input impedance (k ? ) pga gain setting (db) ?12?6 0 6 1218243036 14796-051 figure 46. input impedance vs. pga gain setting (see the input impedance section) 2 ?10 ?8 ?6 ?4 ?2 0 020 15 10 5 magnitude (dbfs) frequency (khz) 14796-055 figure 47. decimation pass band response, f s = 768 khz ?120 ?100 ?80 ?60 ?40 ?20 0 0 10090 80 70605040302010 magnitude (dbfs) frequency (khz) 14796-056 figure 48. total decimation response, f s = 768 khz 2 ?10 ?8 ?6 ?4 ?2 0 020 15 10 5 magnitude (dbfs) frequency (khz) 14796-057 figure 49. interpolation pass band response, f s = 768 khz ?120 ?100 ?80 ?60 ?40 ?20 0 magnitude (dbfs) frequency (khz) 0 10090 80 70605040302010 14796-058 figure 50. total interpolation response, f s = 768 khz
adau1777 data sheet rev. 0 | page 24 of 108 theory of operation the adau1777 is a low power audio codec with a streamlined audio processing core, making it ideal for noise canceling applications that require high quality audio, low power, small size, and low latency. the operating voltage range is 1.71 v to 3.63 v, with an on - boar d regulator optionally generating the internal digital supply voltage. by enabling low latency settings, the adau1777 can reach latencies as low as 5 s. the adcs and dacs are high quality, 24 - bit , - converters that operate at a selectable 768 khz, 192 khz, or 96 khz sampling rate. the adcs have an optional high - pass filter with a cutoff frequency of 1 hz, 4 hz, or 8 hz. the adcs and dacs also include fine step digital volume controls. the st ereo dac output can differentially drive a headphone earpiece speaker with 16 ? or higher impedance. one side of the differential output can be powered down if single - ended operation is required. there is also the option to change to line output mode when the output has a low load. the input signal path is flexible and can accept single - ended analog microphone inputs, serial audio inputs, and digital microphone inputs. two microphone bias pins provide seamless interfacing to electret microphones. each analo g input has an independent pga that can be used for volume adjustment. the serial data port is compatible with i 2 s, left justified, right justified, and tdm modes, with tristating for interfacing to digital audio data streams. the core has a reduced instru ction set that is optimized for active noise cancellation. the program and parameter rams can be loaded with custom audio processing signal flows built using the sigmastudio? graphical programming software from analog devices, inc. the values stored in the parameter ram control individual signal processing blocks. the adau1777 also has a self boot function that can load the program ram, parameter ram, and register settings on power - up using an external eeprom. the sigmastudio software programs and controls the core through the i 2 c or spi control port. along with aiding in the design and tuning of a signal flow, sigmastudio can configure all of the adau1777 registers. the sigmastudio graphical interface allows anyone with digital or analog audio processing knowledge to easily design the dsp signal flow and port it to a target application. the interface also provides enough flexibility and programmability for an experienced dsp programmer to have in - depth control of the design. in sigmastudio, the user can connect graphical blocks (such as biquad filters, volume controls, and arithmetic operations), compile the design, and load the prog ram and parameter files into the adau1777 memory through the control port. sigmastudio also allows the user to download the design to an external eeprom for self boot operation. signal process ing blocks available in the provided libraries include the following: ? single - precision biquad filters ? second - order filters ? absolute value and two - input adder ? volume controls ? limiter the adau1777 can generate its internal clocks from a wide range of input clocks by using the on - board fractional pll. the pll accepts inputs from 8 mhz to 27 mhz. for standalone operation, the clock can be generated using the on - board crystal oscillator.
data sheet adau1777 rev. 0 | page 25 of 108 system clocking and power-up clock initialization the adau1777 can generate its clocks either from an externally provided clock or from a crystal oscillator. in both cases, the on-board pll can be used or the clock can be fed directly to the core. when a crystal oscillator is used, it is desirable to use a 12.288 mhz crystal, and the crystal oscillator function must be enabled in the coren bit (address 0x00, bit 0). if the pll is used, it must always be set to output 24.576 mhz. the pll can be bypassed if a clock of 12.288 mhz or 24.576 mhz is available in the system. bypassing the pll saves system power. the cc_mdiv and cc_cdiv bits must not be changed after setup, but the clksrc bit can be switched while the core is running. set the cc_mdiv and cc_cdiv bits so that the core and internal master clock are always 12.288 mhz; for example, when using a 24.576 mhz external source clock or if using the pll, it is necessary to use the internal divide by 2 (see table 11). table 11. clock configuration settings cc_mdiv cc_cdiv description 1 1 divide the pll/external clock by 1. use these settings for a 12.288 mhz direct input clock source. 0 0 divide the pll/external clock by 2. use these settings for a 24.576 mhz direct input clock source or if using the pll. pll bypass setup on power-up, the adau1777 exits an internal reset after 15 ms. the rate of the internal master clock must be set properly using the cc_mdiv bit in the clock control register (address 0x00). when bypassing the pll, the clock associated with mclkin must be either 12.288 mhz or 24.576 mhz. the internal master clock of the adau1777 is disabled until the coren bit is asserted. pll enabled setup the core clock of the adau1777 is disabled by the default setting of the coren bit and must remain disabled during the pll lock acquisition period. the user can poll the lock bit to determine when the pll has locked. after lock is acquired, the adau1777 can be started by asserting the coren bit. this bit enables the core clock for all the internal blocks of the adau1777 . to program the pll during initialization or reconfiguration of the codec, use the following procedure: 1. ensure that pll_en (bit 7, address 0x00) is set low. 2. set or reset the pll control registers (address 0x01 to address 0x05). 3. enable the pll using the pll_en bit. 4. poll the pll lock bit in register 0x06. 5. set the coren bit in register 0x00 after the pll lock is acquired. control port access during initialization during the lock acquisition period, only register 0x00 to register 0x06 are accessible through the control port. a read or write to any other register is prohibited until the core clock enable bit and the lock bit are both asserted. after the core_run bit (address 0x09) is set high, the following register bits must not be changed: ? adc_0_1_sinc and adc_2_3_sinc ? dac_source0 and dac_source1 if these bits must be changed after the adau1777 is running, the core_run bit first must be disabled. pll the pll uses the mclkin signal as a reference to generate the core clock. the pll settings are set in register 0x00 to register 0x05. depending on the mclk frequency, the pll must be set for either integer or fractional mode. the pll can accept input frequencies in the range of 8 mhz to 27 mhz. mclk x (r + n/m) to pll clock divider 14796-059 figure 51. pll block diagram input clock divider before reaching the pll, the input clock signal goes through an integer clock divider to ensure that the clock frequency is within a suitable range for the pll. the x bits in the pll_ctrl4 register (address 0x05, bits[2:1]) set the pll input clock divide ratio. integer mode use integer mode when the clock input is an integer multiple of the pll output. for example, if mclkin = 12.288 mhz, (x + 1) = 1, and f s = 48 khz, pll required output = 24.576 mhz r /2 = 24.576 mhz/12.288 mhz = 2 where r /2 = 2 or r = 4. in integer mode, the values set for n and m are ignored. table 12 lists common integer pll parameter settings for 48 khz sampling rates. fractional mode use fractional mode when the clock input is a fractional multiple of the pll output. for example, if mclkin = 13 mhz, (x + 1) = 1, and f s = 48 khz, pll required output = 24.576 mhz (1/2) ( r + ( n / m )) = 24.576 mhz/13 mhz = (1/2) (3 + (1269/1625)) where: r = 3. n = 1269. m = 1625.
adau1777 data sheet rev. 0 | page 26 of 108 table 13 lists common fractional pll parameter settings for 48 khz sampling rates. when the pll is used in fractio nal mode, the n/m fraction must be kept in the range of 0.1 to 0.9 to ensure correct operation of the pll. the pll output clock must be kept in the range of 20.5 mhz to 27 mhz , which must be taken into account when calculating pll values and mclk frequenc ies. clock output use t he clkout pin as a master clock output to clock other ics in the system or as the clock for the digital microphone inputs and pdm output. this clock can be generated from the 12.288 mhz master clock of the adau1777 by factors of 2, 1, ?, ?, and ?. if pdm mode is enabled, only the ?, ?, and ? settings produce a clock signal on clkout. the factor of 2 multiplier works properly only if the input clock was previously divided by 2 using the cc_mdiv bit. power sequencing avdd and iovdd can each be set to any voltage between 1.8 v and 3.3 v, and dvdd can be set between 1.1 v and 1.8 v or between 1.1 v and 1.2 v if using the on - board regulator. on power - up, avdd must be powered up before or at the same time as iovdd. do not power up iovdd when power is not applied to avdd. enabling the pd pi n powers down all analog and digital circuits. before enabling pd (that is, setting it low), be sure to mute the outputs to avoid any pops when the ic is powered down. tie pd directly to iovdd for normal operation. power - down considerations when powering down the adau1777 , mute the outputs before avdd power is removed; otherwise, pops or clicks may be heard. the easiest way to achieve this is to use a regulat or that has a power - good (pgood) signal to power the adau1777 or to generate a power - good signal using additional circuitry external to the regulator itself. typically, on such regulators , the power - good signal changes state when the regulated voltage drops below ~90% of its target value. connect t his power - good signal to one of the adau1777 multipurpose pins and mute the dac outputs by setting the multipurpose pin functionality to mute both dacs in register 0x 38 to register 0x 3e. taking these precautions ensure s that the outputs are muted before power is completely removed. table 12 . integer pll parameter settings for pll output = 24.576 mhz mclk input (mhz) input divider (x + 1) integer (r) denominator (m) numerator (n) pll_ctrl4 settings (address 0x 05) 12.288 1 4 dont care dont care 0x20 24.576 1 2 dont care dont care 0x10 table 13 . fractional pll parameter settings for pll output = 24.576 mhz mclk input (mhz) input divider (x + 1) pll parameter register settings (address 0x 05 to address 0x 01) integer (r) denominator (m) numerator (n) pll_ctrl 4 ( addr. 0x 05) pll_ctrl 3 ( addr. 0x 04) pll_ctrl 2 ( addr. 0x 03) pll_ctrl 1 ( addr. 0x 02) pll_ctrl 0 ( addr. 0x 01) 8 1 6 125 18 0x31 0x12 0x00 0x7d 0x00 13 1 3 1625 1269 0x19 0xf5 0x04 0x59 0x06 14.4 2 6 75 62 0x33 0x3e 0x00 0x4b 0x00 19.2 2 5 25 3 0x2b 0x03 0x00 0x19 0x00 26 2 3 1625 1269 0x1b 0xf5 0x04 0x59 0x06 27 2 3 1125 721 0x1b 0xd1 0x02 0x65 0x04
data sheet adau1777 rev. 0 | page 27 of 108 signal routing the adau1777 features flexible signal routing. the signal routing is specified by register 0x0f through register 0x1a. adc modulator adc decimator ain0 pga adc modulator adc decimator ain1 pga adc modulator ain2 pga adc modulator ain3 pga adc decimator adc decimator stereo input asrc dmic0_1/mp4 dmic2_3/mp5 digital microphone inputs hpoutln/loutln hpoutlp/loutlp dac hpoutrn/loutrn pdmout 1 adc_sdata0 1 adc_sdata1 hpoutrp/loutrp dac stereo pdm modulator core input selection audio processing core dac and pdm output selection serial input port serial output port 1 the adc_sdata0 and pdmout functions share a physical pin; therefore only one of these functions can be used at a time. dual stereo output asrcs dac_sdata 14796-060 figure 52. input and output signal routing
adau1777 data sheet rev. 0 | page 28 of 108 input signal paths four input paths, from either an adc or a digital microphone, can be routed to the core. the input sources (adc or digital microphone) must be configured in pairs (for example, 0 and 1, or 2 and 3), but each channel can be routed individually. the core inputs can also be sourced from a stereo input asrc. analog inputs the adau1777 can accept both line level and microphone inputs. each of the four analog input channels can be configured in single-ended mode or a single-ended with pga mode. there are also inputs for up to four digital microphones. the analog inputs are biased at avdd/2 v. connect unused input pins to the cm pin or ac-couple them to ground. signal polarity signals routed through the pgas are inverted. as a result, signals input through the pga are output from the adcs with a polarity that is opposite that of the input. single-ended inputs are not inverted. the adcs are noninverting. input impedance the input impedance of the analog inputs varies with the gain of the pga. this impedance ranges from 0.68 k at the +35.25 db gain setting to 32.0 k at the ?12 db setting. the resistors inside the adau1777 are precisely matched to each other, resulting in very little gain error. however, the exact value of the resistors depends on various conditions in the silicon manufacturing process and can vary by as much as 20%. the input impedance (r in ) on each pin can be calculated as follows: k 1 10 40 )20/( ? ? gain in r where gain is set by pga_gainx. the optional 10 db pga boost, set in the pga_x_boost bits, does not affect the input impedance. this setting is an alternative way of increasing gain without decreasing input impedance; however, it causes some degradation in performance. analog microphone inputs for microphone signals, the adau1777 analog inputs can be configured as single-ended with pga mode. the pga settings are controlled in register 0x23 to register 0x26. the pga is enabled by setting the pga_enx bits. connect the microphone signal to the inverting inputs of the pgas (ainx), as shown in figure 53. microphone pga ?12db to +35.25db adau1777 ainx micbiasx 2k? 14796-061 figure 53. single-ended microphone configuration analog line inputs line level signals can be input on the ainx pins of the analog inputs. figure 54 shows a single-ended line input using the ainx pins. adau1777 line input 0 ain0 line input 1 ain1 line input 2 ain2 line input 3 ain3 14796-062 figure 54. single-ended line inputs precharging input capacitors precharge amplifiers are enabled by default to charge large series capacitors quickly on the inputs and outputs. precharging these capacitors prevents pops in the audio signal. the precharge circuits are powered up by default on startup and can be disabled in the pop_suppress register. the precharge amplifiers are automati- cally disabled when the pga or headphone amplifiers are enabled. for unused pgas and headphone outputs, disable these precharge amplifiers using the pop_suppress register. the precharging time is dependent on the input/output series capacitors. the impedance looking into the ainx pin is 500 in this mode. however, at startup, the impedance looking into the pin is dominated by the time constant of the cm pin because the precharge amplifiers reference the cm voltage. microphone bias the adau1777 includes two microphone bias outputs: micbias0 and micbias1. these pins provide a voltage reference for electret analog microphones. the micbiasx pins also cleanly supply voltage to digital or analog microelectromechanical systems (mems) microphones with separate power supply pins. the micbiasx voltage is set in the microphone bias control register (address 0x2d). using this register, the micbias0 or micbias1 output can be enabled or disabled. the gain options provide two possible voltages: 0.65 avdd or 0.90 avdd. many applications require enabling only one of the two bias outputs. the two bias outputs must both be enabled when many microphones are used in the system or when the positioning of the microphones on the pcb does not allow one pin to bias all microphones.
data sheet adau1777 rev. 0 | page 29 of 108 digital microphone input when using a digital microphone connected to the dmic0_1/mp4 and dmic2_3/mp5 pins, the dcm_0_1 and dcm_2_3 bits in register 0x1d and register 0x1e must be set to enable the digital microphone signal paths. set the pin functions to digital microphone input in the corresponding pin mode registers (address 0x3c and address 0x3d). the dmic0/dmic2 and dmic1/dmic3 channels can be swapped (left/right swap) by writing to the dmic_sw0 and dmic_sw1 bits in the adc_ control2 and adc_control3 registers (address 0x1d and address 0x1e, respectively). in addition, the microphone polarity can be reversed by setting the dmic_polx bits, which reverses the phase of the incoming audio by 180. the digital microphone inputs are clocked from the clkout pin. the digital microphone data stream must be clocked by this pin and not by a clock from another source, such as another audio ic, even if the other clock is of the same frequency as clkout. the digital microphone signal bypasses the analog input path and the adcs and is routed directly into the decimation filters. the digital microphone and the adcs share digital filters and, therefore, both cannot be used simultaneously. the digital micro- phone inputs are enabled in pairs. the adau1777 inputs can be set for either four analog inputs, four digital microphone inputs, or two analog inputs and two digital microphone inputs. figure 55 shows the digital microphone interface and signal routing. adau1777 clkout dmic0_1 digital microphone clk v dd data l/r select gnd 0.1f digital microphone clk v dd data l/r select gnd 0.1f 1.8v to 3.3v 14796-063 figure 55. digital microphone interface block diagram figure 55 shows two digital microphones connected to the dmic0_1/mp4 pin. these microphones can also be connected to dmic2_3/mp5 if that signal path is to be used for digital microphones. if more than two digital microphones are to be used in a system, then up to two microphones are connected to both dmic0_1/mp4 and dmic2_3/mp5 and the clkout signal is fanned out to the clock input of all of the microphones. analog-to-digital converters (adcs) the adau1777 includes four 24-bit, - adcs, each with a selectable sample rate of 768 khz, 192 khz, or 96 khz. adc full-scale level the full-scale input to the adcs (0 dbfs) scales linearly with avdd. at avdd = 3.3 v, the full-scale input level is 1 v rms. signal levels greater than the full-scale value cause the adcs to clip. digital adc volume control the volume setting of each adc can be digitally attenuated in the adcx_volume registers (address 0x1f to address 0x22). the volume can be set between 0 db and ?95.625 db in 0.375 db steps. the adc volume can also be digitally muted in the adc_ controlx registers (address 0x1b to address 0x1e). high-pass filter a high-pass filter is available on the adc path to remove dc offsets; this filter can be enabled or disabled using the hp_x_y_en bits. at f s = 192 khz, the corner frequency of this high-pass filter can be set to 1 hz, 4 hz, or 8 hz.
adau1777 data sheet rev. 0 | page 30 of 108 output signal paths data from the serial input port can be routed to the core , to the output selection multiplexer , or directly to the serial output ports . data from the core can be r outed to the serial output port, the stereo da c, and the stereo pdm modulator (s ee figure 52) . the analog outputs of the adau1777 can be configured as differential or single - ended o utputs. the analog output pins can driv e headphone or earpiece speakers. the line outputs can drive a load of at least 10 k or can be set into headphone mode to drive headphon es or earpiece speakers. the analog output pins are biased at avdd/2. analog outputs headphone output the output pins can be driven by either a line output driver or a headphone driver by setting the hp_en_l and hp_en_r bits in the headphone line output s elect register ( address 0x 43). the headphone outputs can drive a load of at least 16 . headphone output power - up sequencing to prevent pops when turning on the headphone outputs, wait at least 6 ms to unmute these outputs after enabling the headphone output using the hp_en_x bits. waiting 6 ms allows an internal capacitor to charge before these outputs are used. figure 56 illustrates the headphone output pow er - up sequencing . hp_en_r and hp_en_l 1 = headphone hp_mute_r and hp_mute_l 00 = unmute internal precharge 6ms user defined 14796-064 figure 56 . headphone output power - up sequencing ground centered headphone configuration the headphone outputs can also be configured as ground centered outputs by connecting coupling cap acitors in series with the output pins. ground centered headphones must use the agnd pin as the ground reference. when the headphone outputs are configured as ground centered , the capacitors create a high - pass filter on the outputs. the corner frequency of this filter (f 3 db ) , which has an attenuation of 3 db, is calculated by the following formula: f 3 db = 1/(2 r c ) where : r is the impedance of the headphones. c is the capacitor value. for a typical headphone impedance of 32 with a 220 f capacitor, the corner frequency is 23 hz. pop and click suppression on power - up, the precharge circuitry is enabled on all four analog output pins to suppress pops and clicks. after power - up, the precharge circuitry can be set to a low power mod e using the hp_pop_disx bits in the pop_suprress register (address 0x 29). the precharge time depends on the value of the capacitor connected to the cm pin and the rc time constant of the load on the output pin. for a typical line output load, the precharg e time is between 2 ms and 3 ms. after this precharge time, the hp_pop_disx bit s can be set to low power mode. to avoid clicks and pops, mute all analog outputs that are in use while changing any register settings that may affect the signal path. these out puts can then be unmuted after the changes are made. line outputs the analog output pins (hpoutlp/loutlp, hpoutln/ loutln, hpoutrp/loutrp, and hpoutrn/loutrn) can be used to drive both differential and single - ended loads. in their default settings, these pins can drive typical line loads of 10 k or greater. when the line output pins are used in single - ended mode, use the hpoutlp/loutlp and hpoutrp/loutrp pins to output the signals, and power down the hpoutln/loutln and hpoutrn/loutrn pins. digital - to - an alog converters (dac s ) the adau1777 includes two 24 - bit , - dacs . dac full - scale level the full - scale output from the dacs (0 dbfs) scales linearly with av dd. at av dd = 3.3 v, the full - scale output level is 1.94 v rms for a differential output or 0.97 v rms for a single - ended output. digital dac volume control the volume of each dac can be digitally attenuated using the dacx_volume registers (address 0x 2f and address 0x 30). the volume can be set to be between 0 db and ?95.625 db in 0.375 db steps. pdm output the adau1777 includes a 2 - channel pdm modulator. the pdmout pin can be used to drive a pdm input amplifi er, such as the ssm2517 mono 2.4 w amplifier. two ssm2517 devices can be connected to the pdmout data stream to enable a stereo output. the pdm output signal is clocked by the clkout pin output. t he pdm output stream must be clocked by this pin and not by a clock from another source, such as a nother audio ic, even if the other clock is of the same frequency as clkout . the pdm output data is clipped at the ?6 db level to prevent overdriving a connected amplifier like the ssm2517 .
data sheet adau1777 rev. 0 | page 31 of 108 the adau1777 has the ability to output pdm control patterns to configure devices such as the ssm2517 . each pattern is a byte long and is written with a user defined pattern in the pdm_pattern register (address 0x37). the control pattern is enabled and the output channel selection is configured in the pdm_out register (address 0x36). the pdm pattern must not be changed while the adau1777 is outputting the control pattern to the external device. after the external device is configured, the control pattern can be disabled. for the ssm2517 , the control pattern must be repeated a minimum of 128 times to configure the device. table 14 describes typical control patterns for the ssm2517 . table 14. ssm2517 pdm control pattern descriptions pattern control description 0xac power-down. all blocks off except for the pdm interface. normal start-up time. 0xd8 gain optimized for pvdd = 5 v operation. overrides gain_fs pin setting. 0xd4 gain optimized for pvdd = 3.6 v operation. overrides gain_fs pin setting. 0xd2 gain optimized for pvdd = 2.5 v operation. overrides gain_fs pin setting. 0xd1 f s set to opposite value determined by gain_fs pin. 0xe1 ultralow electromagneti c interference (emi) mode. 0xe2 half clock cycle pulse mode for power savings. 0xe4 special 32 khz,128 f s operation mode. asynchronous sample rate converters the adau1777 includes asrcs to enable synchronous, full duplex operation of the serial ports. two stereo asrcs are available for the digital outputs, and one stereo asrc is available for the digital input signals. the asrcs can convert serial output data from the core rates to the serial port rates of 192 khz down to less than 8 khz. all intermediate frequencies and ratios are also supported. signal levels the adcs, dacs, and asrcs have fixed gain settings that must be considered when configuring the system. these settings are chosen to maximize performance of the converters and to ensure that there is 0 db gain for any signal path from the input of the adau1777 to its output. therefore, the full-scale level of a signal in the processing core is slightly different from a full-scale level external to the ic. input paths, such as through the adcs and input asrcs, are scaled by 0.75, or about ?2.5 db. output paths, such as through the dacs or output asrcs, are scaled by 1.33, or about 2.5 db. this scaling is shown in figure 57. a dc input asrcs ?2.5db dac +2.5db ?2.5db output asrcs +2.5db core 14796-065 figure 57. signal level diagram because of this input and output scaling, output signals from the core must be limited to ?2.5 db full scale to prevent the dacs and asrcs from clipping.
adau1777 data sheet rev. 0 | page 32 of 108 signal processing the adau1777 processing core is optimized for anc processing. the processing capabilities of the core include biquad filters, limiters, volume controls, and mixing. the core has four inputs and four outputs. the core is controlled with a 10 - bit program word, with a ma ximum of 32 instructions per frame. instructions a complete list of instructions/processing blocks along with documentation can be found in the sigmastudio software for the adau1777 . the proce ssing blocks available are ? single precision biquad/second - order filters ? absolute value ? two - input addition ? t connection in sigmastudio ? limiter with/without external detector loop ? linear gain ? volume slider ? mute ? dbreg level detection data memory the adau1777 data path is 26 bits (5.21 format). the data memory is 32 words of 2 26 bits. the double length memory enables the core to double precision arithmetic with double length data and single length coefficients. parameters parameters, such as filter coeffici ents, limiter settings, and volume control settings, are saved in parameter registers. each parameter is a 32 - bit number. the format of this number depends on whether it is controlling a filter or a limiter. the number formats of different parameters are s hown in table 15 . when the parameter formats use less than the full 32 - bit memory space, as with the limiter parameters, the data is lsb aligned. tab le 15 . parameter number formats parameter type format filter coefficient (b0, b1, b2) 5.27 filter coefficient (a1) 2.27 (sign extended) filter coefficient (a2) 1.27 (sign extended) maximum gain 2.23 minimum gain 2.23 attack time 24.0 decay time 24.0 threshold 2.23 t wo parameter banks are available. each bank can hold a full set of 160 parameters (32 filters 5 coe fficients). users can switch between bank a and bank b, allowing t wo sets of parame - ters t o be saved in memory and switched on - the - fly while the codec is running. bank switching can be achieved by writing to the core_control register (address 0x 09) or by using the multipurpose push - button switches, but not by using a combi - nation of the two. parameters in th e active bank must not be updated while the core is running; doing so may result in noises on the outputs. parameters are assigned to instructions in the order in which the instructions are instantiated in the code. the instruction types that use paramete rs are the biquad filters and limiters. table 17 shows the addresses of each parameter in bank a that are associated with each of the 32 instructions, and table 18 shows the addresses of each parameter in bank b. table 16 shows the addresses of the lsb aligned, 10 - bit program words. table 16 . program addresses instruction instruction address 0 0x0080 1 0x0081 2 0x0082 3 0x0083 4 0x0084 5 0x0085 6 0x0086 7 0x0087 8 0x0088 9 0x0089 10 0x008a 11 0x008b 12 0x008c 13 0x008d 14 0x008e 15 0x008f 16 0x0090 17 0x0091 18 0x0092 19 0x0093 20 0x0094 21 0x0095 22 0x0096 23 0x0097 24 0x0098 25 0x0099 26 0x009a 27 0x009b 28 0x009c 29 0x009d 30 0x009e 31 0x009f
data sheet adau1777 rev. 0 | page 33 of 108 table 17 . parameter addresses, bank a assignment order b0/max imum gain b1/min imum gain b2/attack a1/decay a2/threshold 0 0x00e0 0x0100 0x0120 0x0140 0x0160 1 0x00e1 0x0101 0x0121 0x0141 0x0161 2 0x00e2 0x0102 0x0122 0x0142 0x0162 3 0x00e3 0x0103 0x0123 0x0143 0x0163 4 0x00e4 0x0104 0x0124 0x0144 0x0164 5 0x00e5 0x0105 0x0125 0x0145 0x0165 6 0x00e6 0x0106 0x0126 0x0146 0x0166 7 0x00e7 0x0107 0x0127 0x0147 0x0167 8 0x00e8 0x0108 0x0128 0x0148 0x0168 9 0x00e9 0x0109 0x0129 0x0149 0x0169 10 0x00ea 0x010a 0x012a 0x014a 0x016a 11 0x00eb 0x010b 0x012b 0x014b 0x016b 12 0x00ec 0x010c 0x012c 0x014c 0x016c 13 0x00ed 0x010d 0x012d 0x014d 0x016d 14 0x00ee 0x010e 0x012e 0x014e 0x016e 15 0x00ef 0x010f 0x012f 0x014f 0x016f 16 0x00f0 0x0110 0x0130 0x0150 0x0170 17 0x00f1 0x0111 0x0131 0x0151 0x0171 18 0x00f2 0x0112 0x0132 0x0152 0x0172 19 0x00f3 0x0113 0x0133 0x0153 0x0173 20 0x00f4 0x0114 0x0134 0x0154 0x0174 21 0x00f5 0x0115 0x0135 0x0155 0x0175 22 0x00f6 0x0116 0x0136 0x0156 0x0176 23 0x00f7 0x0117 0x0137 0x0157 0x0177 24 0x00f8 0x0118 0x0138 0x0158 0x0178 25 0x00f9 0x0119 0x0139 0x0159 0x0179 26 0x00fa 0x011a 0x013a 0x015a 0x017a 27 0x00fb 0x011b 0x013b 0x015b 0x017b 28 0x00fc 0x011c 0x013c 0x015c 0x017c 29 0x00fd 0x011d 0x013d 0x015d 0x017d 30 0x00fe 0x011e 0x013e 0x015e 0x017e 31 0x00ff 0x011f 0x013f 0x015f 0x017f table 18 . parameter addresses, bank b assignment order b0/max imum gain b1/min imum gain b2/attack a1/decay a2/threshold 0 0x0180 0x01a0 0x01c0 0x01e0 0x0200 1 0x0181 0x01a1 0x01c1 0x01e1 0x0201 2 0x0182 0x01a2 0x01c2 0x01e2 0x0202 3 0x0183 0x01a3 0x01c3 0x01e3 0x0203 4 0x0184 0x01a4 0x01c4 0x01e4 0x0204 5 0x0185 0x01a5 0x01c5 0x01e5 0x0205 6 0x0186 0x01a6 0x01c6 0x01e6 0x0206 7 0x0187 0x01a7 0x01c7 0x01e7 0x0207 8 0x0188 0x01a8 0x01c8 0x01e8 0x0208 9 0x0189 0x01a9 0x01c9 0x01e9 0x0209 10 0x018a 0x01aa 0x01ca 0x01ea 0x020a 11 0x018b 0x01ab 0x01cb 0x01eb 0x020b 12 0x018c 0x01ac 0x01cc 0x01ec 0x020c 13 0x018d 0x01ad 0x01cd 0x01ed 0x020d 14 0x018e 0x01ae 0x01ce 0x01ee 0x020e 15 0x018f 0x01af 0x01cf 0x01ef 0x020f
adau1777 data sheet rev. 0 | page 34 of 108 assignment order b0/max imum gain b1/min imum gain b2/attack a1/decay a2/threshold 16 0x0190 0x01b0 0x01d0 0x01f0 0x0210 17 0x0191 0x01b1 0x01d1 0x01f1 0x0211 18 0x0192 0x01b2 0x01d2 0x01f2 0x0212 19 0x0193 0x01b3 0x01d3 0x01f3 0x0213 20 0x0194 0x01b4 0x01d4 0x01f4 0x0214 21 0x0195 0x01b5 0x01d5 0x01f5 0x0215 22 0x0196 0x01b6 0x01d6 0x01f6 0x0216 23 0x0197 0x01b7 0x01d7 0x01f7 0x0217 24 0x0198 0x01b8 0x01d8 0x01f8 0x0218 25 0x0199 0x01b9 0x01d9 0x01f9 0x0219 26 0x019a 0x01ba 0x01da 0x01fa 0x021a 27 0x019b 0x01bb 0x01db 0x01fb 0x021b 28 0x019c 0x01bc 0x01dc 0x01fc 0x021c 29 0x019d 0x01bd 0x01dd 0x01fd 0x021d 30 0x019e 0x01be 0x01de 0x01fe 0x021e 31 0x019f 0x01bf 0x01df 0x01ff 0x021f
data sheet adau1777 rev. 0 | page 35 of 108 control port the adau1777 has both a 4 - wi re spi control port and a 2 - wire i 2 c bus control port. each port ca n be used to set the memories and registers. the ic defaults to i 2 c mode but can be put into spi control mode by pulling the ss pin low three times. the control port is capable of full read/write operation for all addressable memories and registers. most signal processing parameters are controlled by writing new values to the param - eter memories using the control port. other functions, such as mute and input/output mode control, are programmed thro ugh the registers. all addresses can be accessed in either single address mode or burst mode. the first byte (byte 0) of a control port write contains the 7 - bit ic address plus the r/ w bit. the next two bytes (byte 1 and byte 2) are the 16 - bit subaddress of the memory or register location within the adau1777 . all subsequent bytes (starting with byte 3) contain the data, such as register data, program data, or parameter data. the number of bytes per word depends on the type of data that is being written. table 19 shows the word length of the different da ta types of the adau1777 . the exact formats for specific types of writes are shown in figure 60 and figure 61 . table 19 . data - word sizes data type word size ( b ytes) registers 1 program 2 parameters 4 if large blocks of data must be downloaded to the adau1777 , halt the output of the core (using the core_run bit in the core control register (addres s 0x 09)), load new data , and then restart the core. halting the core is typically done during the booting sequence at start up or when loading a new program into memory. registers and bits shown as reserved in the register map read back 0s. when writing to these registers and bits, such as during a burst write across a reserved register, or when wr iting to reserved bits in a register with other used bits, write 0s. the control port pins are multifunctional, depending on the mode in which the device is operating. table 20 details these multiple functions. table 20 . control port pin functions pin i 2 c mode spi mode scl/sclk scl , input sclk , input sda/miso sda , open - collector output miso , output addr1/mosi i 2 c address bit 1 , input mosi , input addr0/ ss i 2 c address bit 0 , input ss , input burst mode communica tion use b urst mode addressing, in which the subaddresses are automati cally incremented at word boundaries, for writing large amounts of data to contiguous memory locations. this incremen t occurs automatically after a single - word write unless the control port communication is stopped ; that is, a stop condition is issued for i 2 c mode , or ss is brought high for spi mode . the registers and rams in the adau1777 range i n width from one to four bytes; therefore, the auto - increment feature knows the mapping between subaddresses and th e word length of the destination register (or memory location). i 2 c port the adau1777 supports a 2 - wire serial (i 2 c - compatible) micro - p rocessor bus driving multiple peripherals. i 2 c mode uses two pins serial data (sda) and serial clock (scl) to carry data between the adau1777 and the system i 2 c master controller. in i 2 c mode, the adau1777 is always a slave on the bus, except when the ic is self booting. see the self boot section for details about using the adau1777 in self boot mode. each slave device is recognized by a unique 7 - bit address. the adau1777 i 2 c address format is shown in table 21 . the lsb of this first byte sent fr om the i 2 c master sets either a read or write operation. logic level 1 corresponds to a read operation, and logic level 0 corresponds to a write operation. the addr0 and addr1 pins set the lsbs of the i 2 c address ( see table 22 ); therefore, each adau1777 can be set to one of four unique addresses. this feature allows multiple ics to exist on the same i 2 c bus without address contention. the 7 - bit i 2 c addresses are shown in table 22. an i 2 c data transfer is always terminated by a stop condit ion. both sda and scl must have 2.0 k? pull - up resistors on the lines connected to them. the voltage on these signal lines must not be higher than iovdd. table 21. i 2 c address format bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 1 1 1 addr1 addr0 table 22. i 2 c addresses addr1 addr0 slave address 0 0 0x3c 0 1 0x3d 1 0 0x3e 1 1 0x3f
adau1777 data sheet rev. 0 | page 36 of 108 addressing initially, each device on the i 2 c bus is in an idle state and monitor- ing the sda and scl lines for a start condition and the proper address. the i 2 c master initiates a data transfer by establishing a start condition, defined by a high to low transition on sda while scl remains high. this condition indicates that an address/data stream follows. all devices on the bus respond to the start condi- tion and shift the next eight bits (the 7-bit address plus the r/ w bit) msb first. the device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this ninth bit is an acknowledge bit. all other devices withdraw from the bus at this point and return to the idle condi- tion. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the first byte indicates that the master is writing information to the peripheral, whereas a logic 1 indicates that the master is reading information from the peripheral after writing the subaddress and repeating the start address. a data transfer occurs until a stop condition is encountered. a stop condition occurs when sda transitions from low to high while scl is held high. figure 58 shows the timing of an i 2 c write, and figure 59 shows the timing of an i 2 c read. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, the adau1777 immediately jumps to the idle condition. during a given scl high period, the user must issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. if the user issues an invalid subaddress, the adau1777 does not issue an acknowledge and returns to the idle condition. if the user exceeds the highest subaddress while in auto-increment mode, one of two actions is taken. in read mode, the adau1777 outputs the highest subaddress register contents until the master device issues a no acknowledge, indicating the end of a read. a no acknowledge condition is where the sda line is not pulled low on the ninth clock pulse on scl. if the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the adau1777 , and the device returns to the idle condition. r/w 0 scl sda sda (continued) scl (continued) 111 addr0 addr1 1 start by master frame 1 chip address byte frame 2 subaddress byte 1 frame 3 subaddress byte 2 frame 4 data byte 1 acknowledge by adau1777 acknowledge by adau1777 acknowledge by adau1777 acknowledge by adau1777 stop by master 14796-066 figure 58. i 2 c write to adau1777 clocking r/w scl sda sda (continued) scl (continued) sda (continued) scl (continued) start by master frame 2 subaddress byte 1 frame 3 subaddr ess byte 2 frame 4 chip address byte frame 1 chip address byte frame 5 read data byte 1 frame 6 read data byte 2 acknowledge by adau1777 acknowledge by adau1777 acknowledge by adau1777 acknowledge by adau1777 acknowledge by adau1777 stop by master acknowledge by adau1777 repeated start by master r/w addr0 addr0 addr1 addr1 0111 1 0111 1 14796-067 figure 59. i 2 c read from adau1777 clocking
data sheet adau1777 rev. 0 | page 37 of 108 i 2 c read and write operations figure 60 shows the format of a single-word write operation. every ninth clock pulse, the adau1777 issues an acknowledge by pulling sda low. figure 61 shows the format of a burst mode write sequence. this figure shows an example where the target destination words are two bytes, such as the program memory. the adau1777 knows to increment its subaddress register every two bytes because the requested subaddress corresponds to a register or memory area with a 2-byte word length. the format of a single-word read operation is shown in figure 62. note that the first r/ w bit is 0, indicating a write operation because the subaddress still must be written to set up the internal address. after the adau1777 acknowledges the receipt of the subaddress, the master must issue a repeated start command followed by the chip address byte with the r/ w set to 1 (read). this command causes the sda pin to reverse and begin driving data back to the master. the master then responds every ninth pulse with an acknowledge pulse to the adau1777 . figure 63 shows the format of a burst mode read sequence. this figure shows an example where the target read words are two bytes. the adau1777 increments its subaddress every two bytes because the requested subaddress corresponds to a register or memory area with word lengths of two bytes. other address ranges may have a variety of word lengths, ranging from one to four bytes. the adau1777 always decodes the subaddress and sets the auto-increment circuit so that the address increments after the appropriate number of bytes. figure 60 to figure 63 use the following abbreviations: ? s = start bit ? p = stop bit ? am = acknowledge by master ? as = acknowledge by slave s i 2 c address, r/w = 0 as subaddress high as subaddress low as data byte 1 as data byte 2 as ... data byte n p 14796-068 figure 60. single-word i 2 c write format ... s i 2 c address, r/w = 0 as subaddress high as subaddress low as data-word 1, byte 1 data-word 1, byte 2 as as data-word 2, byte 1 data-word 2, byte 2 p as as 14796-069 figure 61. burst mode i 2 c write format data byte 1 am data byte 2 am... data byte n p s i 2 c address, r/w = 0 as subaddress high as subaddress low as i 2 c address, r/w = 1 as s 14796-070 figure 62. single-word i 2 c read format ... data-word 1, byte 1 data-word 1, byte 2 am am p s i 2 c address, r/w = 0 as subaddress high as subaddress low as i 2 c address, r/w = 1 as s 14796-071 figure 63. burst mode i 2 c read format
adau1777 data sheet rev. 0 | page 38 of 108 spi port by default, the adau1777 is in i 2 c mode, but it can be put into spi control mode by pulling ss low three times. the device can be configured for spi mode by issuing three spi writes, which are in turn ignored by the adau1777 . the next (fourth) spi write is then latched into the spi port. the spi port uses a 4-wire interfaceconsisting of the ss , sclk, mosi, and miso signalsand is always a slave port. the ss signal goes low at the beginning of a transaction and high at the end of a transaction. the sclk signal latches mosi on a low to high transition. miso data is shifted out of the adau1777 on the falling edge of sclk and must be clocked into a receiving device, such as a microcontroller, on the sclk rising edge. the mosi signal carries the serial input data, and the miso signal is the serial output data. the miso signal remains tristated until a read operation is requested. tristating allows other spi-compatible peripherals to share the same readback line. all spi transactions have the same basic format shown in table 23. timing diagrams are shown in figure 64 and figure 65. all data is written msb first. the adau1777 can be taken out of spi mode only by pulling the pd pin low or by powering down the ic. read/write the first byte of an spi transaction indicates whether the com- munication is a read or a write with the r/ w bit. the lsb of this first byte determines whether the spi transaction is a read (logic level 1) or a write (logic level 0). subaddress the 16-bit subaddress word is decoded into a location of one of the memories or registers. this subaddress is the location of the appropriate memory location or register. data bytes the number of data bytes varies according to the register or memory being accessed. during a burst mode write, an initial subaddress is written followed by a continuous sequence of data for consecutive memory/register locations. a sample clocking diagram for a single write spi operation to the parameter ram is shown in figure 64. a sample clocking diagram of a single read spi operation is shown in figure 65. the miso pin goes from tristate to being driven at the beginning of byte 3. in this example, byte 0 to byte 2 contain the addresses and the r/ w bit and the subsequent bytes carry the data. table 23. generic spi word format byte 0 byte 1 byte 2 byte 3 byte 4 1 0000000, r/w register/memory address[15:8] register/memory address[7:0] data data 1 continues to the end of data transmission for the burst mode write. ss s clk mosi 14796-072 figure 64. spi write to adau1777 clocking (single write mode) ss sclk mosi miso byte 0 byte 1 byte 2 data data high-z high-z 14796-073 figure 65. spi read from adau1777 clocking (single read mode)
data sheet adau1777 rev. 0 | page 39 of 108 self boot the adau1777 boots up from an eeprom over the i 2 c bus when the selfboot pin is set high at power-up and the pd pin is set high. the state of the selfboot pin is checked only when the adau1777 exits a reset via the pd pin, and when the eeprom is not used after a self boot is complete. during booting, ensure that a stable dvdd voltage is in the system. the pd pin remains high during the self boot operation. the master scl clock output from the adau1777 is derived from the input clock on xtali/ mclkin. a divide by 64 circuit ensures that the scl output frequency during the self boot operation is never greater than 400 khz for most input clock frequencies. with the external master clock to the adau1777 between 12 mhz and 27 mhz, the scl frequency ranges from 176 khz to 422 khz. if the self boot eeprom is not rated for operation above 400 khz, use a master clock that is no faster than 25.6 mhz. table 25 shows the list of instructions that are possible during an adau1777 self boot. the 0x01 and 0x05 instruction bytes load the register, program, and parameter settings. eeprom size the self boot circuit is compatible with an eeprom that has a 2-byte address. for most eeprom families, a 2-byte address is used on devices that are 32 kb or larger. the eeprom must be set to address 0x50. examples of two compatible eeproms include the atmel? at24c32d and stmicroelectronics m24c32-f. table 24 lists the maximum necessary eeprom size, assuming that there is 100% utilization of the program and parameters (both banks). there is inherently some overhead for instructions to control the self boot procedure. table 24. maximum eeprom size adau1777 memory blocks word size (bytes per word) words total eeprom space require- ment (bytes) program 2 32 64 bank a parameters 4 160 (32 5) 640 bank b parameters 4 160 640 registers 1 65 65 total bytes 2049 cyclic redundancy check (crc) an 8-bit crc validates the content of the eeprom. this crc is strong enough to detect single error bursts of up to eight bits in size. the terminate self boot instruction (0x instruction byte) must be followed by a crc byte. the crc is generated using all of the eeprom bytes from address 0x00 to the last 0x00 instruction byte. the polynomial for the crc is x 8 + x 2 + x + 1 if the crc is incorrect or if an unrecognized instruction byte is read during self boot, the boot process is immediately stopped and restarted after a 250 ms delay (for a 12.288 mhz input clock). when sigmastudio is used, the crc byte is generated auto- matically when a configuration is downloaded to the eeprom. delay the delay instruction (0x02 instruction byte) delays by the 16-bit setting 2048 clock cycles. boot time the time to self boot the adau1777 from an eeprom can be calculated using the following equation: boot time = 64/ mclk frequency total bytes + wait time the self boot operation starts after 16,568 clock cycles are seen on the xtali/mclkin pin after pd is set high. with a 12.288 mhz clock, this number of cycles corresponds to approximately a 1.35 ms wait time from power-up. this delay ensures that the crystal used for generating the master clock has ramped up to a stable oscillation. table 25. eeprom self boot instructions instruction byte id instruction byte description following bytes 0x00 end self boot crc 0x01 write multibyte length minus two bytes, starting at target address length (high byte), length (low byte), address (high byte), address (low byte), data (0), data (1), ? , data (length ? 3) 0x02 delays by the 16-bit setting 2048 clock cycles delay (high byte), delay (low byte) 0x03 no operation none 0x04 wait for pll lock none 0x05 write single byte to target address address (high byte), address (low byte), data 0x1a 0x2b 0x3c 0x04 0x03 0x00 data (0) data (1) data (length ? 3) pll lock no op end program ram data 0x02 0x00 0x04 0x01 0x00 0x05 0x00 0x80 delay delay (high byte) delay (low byte) write length (high byte) length (low byte) address (high byte) address (low byte) delay length length program ram address 14796-074 figure 66. example self boot eeprom instructions
adau1777 data sheet rev. 0 | page 40 of 108 multipurpose pins the adau1777 has seven multipurpose (mp x ) pins that can be used for ser ial data input/output , clock outputs, and control in a system without a microcontroller. each pin can be individually set to either its default or mp x setting. the functions include push - button volume controls, enabling the compressors, parameter bank switching, dsp bypass mode, and muting the outputs. the function of each of these pins is set in register 0x 38 to register 0x 3e. by default, each pin is configured as an input. table 26 . multipurpose pin functions pin no. default pin function secondary pin functions a2 bclk multipurpose control inputs a3 mp1 act s as push - button volume up adc_sdata0, pdm output, multipurpose control inputs a4 mp6 act s as push - button volume down adc_sdata1, clkout, multipurpose control inputs b2 lrclk multipurpose control inputs b 3 dac_sdata multipurpose control inputs b4 dmic2_3 multipurpose control inputs b5 dmic0_1 multipurpose control inputs push - button volume controls the adc and dac volume controls can be controlled with two push - buttons: one to increase vol ume and one to decrease volume . the volume setting can either be changed with a click of the button or can be ramped by holding either button but not both at the same time . the volume settings change when the signal on the pin from the button goes from low to high. when in push - button mode, the initial volume level is set with the pb_vol_init_val bits . by default, mp1 acts as the push - button v olume up control and mp6 acts as the push - button volume down control ; however, any of the mpx pins can be set to act as the push - button up and push - button down volume controls. when the adc and/or dac volumes are controlled with the push - buttons, the corr esponding volume control registers no longer allow control of the volume from the control port. therefore, writing to these volume control registers has no effect on the codec volume level. limiter compression enable th e limiter compression enable functio n allows a user to enable limiter compression regardless of the signal level. setting an mpx pin low when this function is enabled causes the limiter to compress the incoming signal by the minimum gain setting. when the mpx pin is released, the limiter res umes normal behavior. parameter bank switc hing an mpx pin can be used to switch the active parameter bank between bank a and bank b . when one of these setting s is selected, bank a is active when the mpx pin is high and bank b is active when the mpx pin is low. s et the bank_sl bits in the core_control register (address 0x 09) to the default value of 0x00 before enabling mpx pin control over bank switching. simultaneous control of bank switching by both register setting and mpx pin selection is not possible. t he zero_state bit selects whether the data memory of the codec is set to 0 during a bank switch. if the data is not set to 0 when a new set of filter coefficients is enabled via a bank switch, there may be a pop in the audio as the old data is circulated i n the new filters. mute the mpx pins can be put into a mode to mute the adcs or dacs. when in this mode, mute is enabled when an mpx pin is set low. the full combination of possible mutes for the adcs and dacs using the mpx pins are set in register 0x 38 t o register 0x 3e.
data sheet adau1777 rev. 0 | page 41 of 108 dsp bypass mode when dsp bypass mode is enabled, a direct path from the adc outputs to the dacs is set up to enable bypassing the core pro- cessing to listen to environmental sounds. this mode is useful for listening to someone speaking without having to remove the noise canceling headphones. the dsp bypass path is enabled by setting an mpx pin low. figure 67 shows the dsp bypass path disabled, and figure 68 shows the dsp bypass path enabled by pressing the push-button switch. the dsp bypass feature works for both analog and digital microphone inputs. dsp bypass is enabled when a switch connected to an mpx pin that is set to dsp bypass mode is closed and the mpx pin signal is pulled low. pressing and holding the switch closed enables the dsp bypass signal path as defined in the talkthru register (address 0x2a). the dac volume control setting is switched from the default gain setting to the new talkthru_gainx register setting (address 0x2b and address 0x2c). dsp bypass is enabled only on adc0 and adc1. the dsp bypass signal path is from the output of adcx to the input of the dac(s). when dsp bypass is enabled, the current dac volume setting is ramped down to ?95.625 db and the dsp bypass volume setting is ramped up to avoid pops when switching paths. adau1777 pga and adc dac and hp amplifier normal setting hpoutxp hpoutxn core processing 10k? mpx ainx 14796-075 figure 67. dsp bypass path disabled adau1777 pga and adc dac and hp amplifier talkthru setting hpoutxp hpoutxn core processing 10k? mpx ainx 14796-076 figure 68. dsp bypass path enabled
adau1777 data sheet rev. 0 | page 42 of 108 serial data input/output ports the serial data input and output ports of the adau1777 can be set to accept or transmit data in a 2-channel format or in a 4-channel or 8-channel tdm stream mode to interface to external adcs, dacs, dsps, and systems on chip (socs). data is processed in twos complement, msb first format. the left channel data field always precedes the right channel data field in the 2-channel streams. in 8-channel tdm mode, the data channels are output sequentially, starting with the channel set by the adc_sdata0_st and adc_sdata1_st bits. the serial modes and the position of the data in the frame are set in the serial data port (sai_0, sai_1) and serial output control registers (sout_source_x_y, address 0x13 to address 0x16). the serial data clocks do not need to be synchronous with the adau1777 master clock input, but the lrclk and bclk pins must be synchronous to each other. the lrclk and bclk pins both clock the serial input and output ports. the adau1777 can be set to be either the master or the slave in a system. because there is only one set of serial data clocks, the input and output ports must always both be either master or slave. the serial data control registers allow control of the clock polarity and the data input modes. the valid data formats are i 2 s, left justified, right justified (24- or 16-bit), pcm, and tdm. in all modes except for the right justified modes, the serial port inputs an arbitrary number of bits up to a limit of 24. extra bits do not cause an error, but they are truncated internally. the serial port can operate with an arbitrary number of bclk transitions in each lrclk frame. the lrclk in tdm mode can be input to the adau1777 either as a 50% duty cycle clock or as a 1-bit wide pulse. table 27 lists the modes in which the serial input/output port can function. when using low iovdd (1.8 v) with a high bclk rate (12.288 mhz), a sample rate of 192 khz, or a 8-channel tdm mode operating at a sample rate of 48 khz, it is recommended to use the high drive settings on the serial port pins. the high drive strength effectively speeds up the transition times of the waveforms, thereby improving the signal integrity of the clock and data lines. these can be set in the pad_control4 register (address 0x4c). table 27. serial input/output port master/slave mode capabilities serial data sample rate 2-channel modes (i 2 s, left justified, right justified) 4-channel tdm 8-channel tdm 48 khz yes yes yes 96 khz yes yes no 192 khz yes no no table 28 describes the proper serial port settings for standard audio data formats. more information about the settings in table 28 is in the serial port control 0 register and the serial port control 1 register (address 0x32 and address 0x33) descriptions in table 87 and table 88, respectively. tristating unused channels unused outputs can be tristated so that multiple ics can drive a single tdm line. this function is available only when the serial ports of the adau1777 are operating in tdm mode. set inactive channels in the sout_control0 register (address 0x34). the tristating of inactive channels is set in the sai_1 register (address 0x33), which offers the option of tristating or driving the inactive channel. in a 32-bit tdm frame with 24-bit data, the eight unused bits are tristated. inactive channels are also tristated for the full frame. table 28. serial port data format settings format lrclk polarity (lr_pol) lrclk type (lr_mode) bclk polarity (bclkedge) 1 msb position (sdata_fmt) i 2 s (see figure 69) 0 0 0 00 left justified (see figure 70) 1 0 0 01 right justified (see figure 71 and figure 72) 1 0 0 10 or 11 tdm (see figure 73 and figure 74) 1 0 or 1 0 00 pcm/dsp short frame sync (see figure 75) 1 1 x 00 pcm/dsp long frame sync (see figure 76) 1 0 x 01 1 x means dont care. msb lsb left channel msb lsb right channel lrclk bclk (64 f s ) i 2 s (24-bit) 1 2 3 4 24 25 26 32 33 34 35 36 56 57 58 64 14796-077 figure 69. i 2 s mode, 16 bits to 24 bits per channel
data sheet adau1777 rev. 0 | page 43 of 108 msb lsb left channel msb lsb right channel lrclk bclk (64 f s ) lj (24-bit) 1 2 3 2324253233343555565764 14796-078 figure 70. left justified (lj) mode, 16 bits to 24 bits per channel lrclk bclk (64 f s ) rj (24-bit) left channel msb lsb right channel msb lsb 1 2 9 10111231323334 414243446364 14796-079 figure 71. right justified (r j) mode, 24 bits per channel bclk (64 f s ) rj (24-bit) left channel msb lsb right channel msb lsb lrclk 1 2 17 18 19 20 31 32 33 34 49 50 51 52 63 64 14796-080 figure 72. right justified (r j) mode, 16 bits per channel 256 bclks 32 bclks lrcl k bclk data lrclk bclk data msb ? 2 msb ? 1 msb slot 1 slot 2 slot 3 slot 4 slot 5 slot 6 slot 7 slot 8 14796-081 figure 73. 8-channel tdm mode l rcl k bclk data ch 0 ch 8 msb tdm msb tdm 32 bclks slot 0 slot 1 slot 2 slot 3 slot 4 slot 5 slot 6 slot 7 14796-082 figure 74. 8-channel tdm mode, pulse lrclk
adau1777 data sheet rev. 0 | page 44 of 108 left channel msb msb lsb lsb right channel lrclk bclk (64 f s ) pcm (24-bit) 1 2 3 4 16 17 18 19 20 32 33 34 14796-083 figure 75 . pcm/dsp mode, 16 bits per channel, short frame sync lrclk bclk (64 f s ) pcm (24-bit) left channel msb msb lsb lsb right channel 1 2 3 4 16 17 18 19 20 32 33 34 14796-084 figure 76 . pcm/dsp mode, 16 bits per channel, long frame sync
data sheet adau1777 rev. 0 | page 45 of 108 applications information power supply bypass capacitors bypass each analog and digital power supply pin to its nearest appropriate ground pin with a single 0.1 f capacitor. the connections to each side of the capacitor must be as short as possible, and the trace must be routed on a single layer with no vias. for maximum effectiveness, locate the capacitor equidistant from the power and ground pins or slightly closer to the power pin if equidistant placement is not possible. make thermal connections to the ground planes on the far side of the capacitor. bypass each supply signal on the board with a single bulk capacitor (10 f to 47 f). 14796-240 avdd pin from avdd capacitor agnd pin to gnd figure 77. recommended example power supply bypass capacitor layout layout pin d1 and pin f2 are the avdd supplies for the headphone amplifiers. if the headphone amplifiers are enabled, the pcb trace to these pins must be wider than traces to other pins to increase the current carrying capacity. a wider trace must also be used for the headphone output lines where possible. grounding a ground plane must be used in the application layout. place components in an analog signal path away from digital signals wherever possible. pcb stackup the example pcb stackup in figure 78 is a 4-layer design. four is the minimum layer count. the two inner layers are used as power and ground planes. the outer layers are used as signal layers and are flooded with the ground plane. it is recommended to use several 0.1 f bypass capacitors to decouple the power and ground plane for emi concerns. place these capacitors around the edges of the ground plane. 0.062 0.005 inch 4-layer construction detai l scale: none silkscreen solder mask layer 1 top side, 1.5 oz. cu finished laminate = 0.010 inch thick layer 2 ground plane, 1.0 oz. cu core prepreg = 0.040 inch thick layer 3 power plane, 1.0 oz. cu layer 4 bottom side, 1.5 oz. cu finished solder mask silkscreen laminate = 0.010 inch thick 14796-086 figure 78. example pcb stackup details
adau1777 data sheet rev. 0 | page 46 of 108 low l atency r egister s ettings the adau1777 utilizes the adau1772 architecture and incorporates additional register setti ngs for reductions in latency, as shown in table 29 to table 35. table 29. c ore c ontrol r egister ( register 0x0009) bits bit name settings description [4:3] fast_slow_rate these bits select the speed of the slow rate relative to the fast rate. this setting must not be changed while the core is running. the core_run bit must be set to 0 for this setting to be updated. 00 s low rate = fast rate . 01 s low rate = fast rate/4 . 10 s low rate = fast rate/8 . [2:1] core_fs these bits select the core sample rate. note that the adau1777 supports an additional 768 khz sample rate for reduced latency. this setting must not be changed while the core is running. the core_run bit must be set to 0 for this setting to be updated. 00 reserved . 01 96 khz . 10 192 khz . 11 768 khz . table 30 . sleep on program address count r egister ( register 0x000 a ) bits bit name settings description [4:0] sleep the s leep on p rogram a ddress c ount r egister controls which registers are executed. subtract 2 from the sleep bit setting to indicate the number of addresses that are affected. for example, if sleep = 7, only instructions at address 0x0000 to address 0x0005 are executed. this setting must not be changed while the core is running. the core_run bit must be set to 0 for this setting to be updated. 00000 no sleep, all instructions are executed . 00001 reserved . 00010 sleep on 0 . 00011 sleep on 1 . 11111 sleep on 29 . table 31 . adc0/adc1 control 0 r egister ( register 0x00 1b ) bits bit name settings description 5 adc_0_1_sinc this bit selects either a third - order or fourth - order sinc filter. this setting must not be changed while the core is running. the core_run bit must be set to 0 for this setting to be updated. 0 fourth - order sinc . 1 third - order sinc . [1:0] adc_0_1_fs these bits set the adc sample rate. the adau1777 supports the option of 768 khz as well. note that the frequency selected must match the core_fs selected via bits[2:1] of register 0x0009. 00 96 khz . 01 192 khz . 10 768 khz . 11 reserved .
data sheet adau1777 rev. 0 | page 47 of 108 table 32 . adc 2 /adc 3 1 control 0 r egister ( register 0x00 1c ) bits bit name settings description 5 adc_ 2 _ 3 _sinc this bit selects either a third - order or fourth - order sinc filter. this setting must not be changed while the core is running. the core_run bit must be set to 0 for this setting to be updated. 0 fourth - order sinc . 1 third - order sinc . [1:0] adc_ 2 _ 3 _fs these bits set the adc sample rate. the adau1777 supports the option of 768 khz as well. 00 96 khz . 01 192 khz . 10 768 khz . 11 reserved . table 33. fast rate c ontrol r egister ( register 0x00 4e ) bits bit name settings description [2:0] rate_div bits[2:0] set the fast rate division factor. this factor is used to divide the internal master clock (6.144 mhz) when core_fs = 11. this setting must not be changed while the core is running. core_run must be set to 0 for this setting to be updated. the settings for rate_div follow : 000 divide by 8 (768 khz) . 001 divide by 9 (683 khz) . 010 divide by 10 (614 khz) . 011 divide by 12 (512 khz) . 100 divide by 14 (439 khz) . 101 divide by 16 (384 khz) . table 34. dac interpolation c ontrol r egister ( register 0x00 4f ) bits bit name settings description [7:6] dac_rate these bits set the dac_rate value, which sets the sample rate for the dac only. 00 core f s . 01 core f s /4 . 10 core f s /8 . 11 r e served . [5:3] dac_intp these bits set the dac_intp value, which sets the interpolation mode for the dac. 000 both dac0 and dac1 set to compensated interpolation . 001 dac0 set to zero - order hold ( zoh ) , dac1 set to compensated interpolation . 010 dac0 set to compensated interpolation, dac1 set to zoh . 011 both dac0 and dac1 set to zoh . 100 dac0 set to linear interpolation, dac1 set to compensated interpolation . 101 dac0 set to compensated interpolation, dac1 set to linear interpolation . 110 both dac0 and dac1 set to linear interpolation .
adau1777 data sheet rev. 0 | page 48 of 108 table 35. volume c ontrol bypass r egister ( register 0x00 54 ) bits bit name settings description 5 dac1vol_by dac1 volume control bypass. 0 volume control enabled. 1 bypassed. 4 dac0vol_by dac0 volume control bypass. 0 volume control enabled. 1 bypassed. 3 adc3vol_by adc3 volume control bypass. 0 volume control enabled. 1 bypassed. 2 adc2vol_by adc2 volume control bypass. 0 volume control enabled. 1 bypassed. 1 adc1vol_by adc1 volume control bypass. 0 volume control enabled. 1 bypassed. 0 adc0vol_by adc0 volume control bypass. 0 volume control enabled. 1 bypassed.
data sheet adau1777 rev. 0 | page 49 of 108 register summary table 36 . register summary reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 clk_control [7:0] pll_en reserved spk_flt_dis xtal_dis clksrc cc_cdiv cc_mdiv coren 0x00 r/w 0x01 pll_ctrl0 [7:0] m_msb 0x00 r/w 0x02 pll_ctrl1 [7:0] m_lsb 0x00 r/w 0x03 pll_ctrl2 [7:0] n_msb 0x00 r/w 0x04 pll_ctrl3 [7:0] n_lsb 0x00 r/w 0x05 pll_ctrl4 [7:0] reserved r x pll_type 0x00 r/w 0x06 pll_ctrl5 [7:0] reserved lock 0x00 r/w 0x07 clkout_sel [7:0] reserved clkout_freq 0x00 r/w 0x08 regulator [7:0] reserved reg_pd regv 0x00 r/w 0x09 core_control [7:0] zero_ state bank_sl fast_slow_rate core_fs core_run 0x04 r/w 0x0a sleep_inst [7:0] reserved sleep 0x00 r/w 0x0b core_enable [7:0] reserved lim_en dsp_clk_ en 0x03 r/w 0x0c dbreg0 [7:0] dbval0 0x00 r 0x0d dbreg1 [7:0] dbval1 0x00 r 0x0e dbreg2 [7:0] dbval2 0x00 r 0x0f core_in_mux_ 0_1 [7:0] core_in_mux_sel_1 core_in_mux_sel_0 0x10 r/w 0x10 core_in_mux_ 2_3 [7:0] core_in_mux_sel_3 core_in_mux_sel_2 0x32 r/w 0x11 dac_source_ 0_1 [7:0] dac_source1 dac_source0 0x10 r/w 0x12 pdm_source_ 0_1 [7:0] pdm_source1 pdm_source0 0x32 r/w 0x13 sout_source_ 0_1 [7:0] sout_source1 sout_source0 0x54 r/w 0x14 sout_source_ 2_3 [7:0] sout_source3 sout_source2 0x76 r/w 0x15 sout_source_ 4_5 [7:0] sout_source5 sout_source4 0x54 r/w 0x16 sout_source_ 6_7 [7:0] sout_source7 sout_source6 0x76 r/w 0x17 adc_sdata_ ch [7:0] reserved adc_sdata1_st adc_sdata0_st 0x04 r/w 0x18 asrco_ source_ 0_1 [7:0] asrc_out_source1 asrc_out_source0 0x10 r/w 0x19 asrco_ source_2_3 [7:0] asrc_out_source3 asrc_out_source2 0x32 r/w 0x1a asrc_mode [7:0] reserved asrc_in_ch asrc_out_en asrc_in_ en 0x00 r/w 0x1b adc_ control0 [7:0] reserved adc_0_1_ sinc adc1_mute adc0_mute reserved adc_0_1_fs 0x19 r/w 0x1c adc_ control1 [7:0] reserved adc_2_3_ sinc adc3_mute adc2_mute reserved adc_2_3_fs 0x19 r/w 0x1d adc_ control2 [7:0] reserved hp_0_1_en dmic_pol0 dmic_sw0 dcm_0_1 adc_1_en adc_0_en 0x00 r/w 0x1e adc_ control3 [7:0] reserved hp_2_3_en dmic_pol1 dmic_sw1 dcm_2_3 adc_3_en adc_2_en 0x00 r/w 0x1f adc0_volume [7:0] adc_0_vol 0x00 r/w 0x20 adc1_volume [7:0] adc_1_vol 0x00 r/w 0x21 adc2_volume [7:0] adc_2_vol 0x00 r/w 0x22 adc3_volume [7:0] adc_3_vol 0x00 r/w
adau1777 data sheet rev. 0 | page 50 of 108 reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x23 pga_control_ 0 [7:0] pga_en0 pga_ mute0 pga_gain0 0x40 r/w 0x24 pga_control_ 1 [7:0] pga_en1 pga_ mute1 pga_gain1 0x40 r/w 0x25 pga_control_ 2 [7:0] pga_en2 pga_ mute2 pga_gain2 0x40 r/w 0x26 pga_control_ 3 [7:0] pga_en3 pga_ mute3 pga_gain3 0x40 r/w 0x27 pga_step_ control [7:0] reserved slew_rate slew_pd3 slew_pd2 slew_pd1 slew_pd0 0x00 r/w 0x28 pga_10db_ boost [7:0] reserved pga_3_ boost pga_2_boost pga_1_boost pga_0_ boost 0x00 r/w 0x29 pop_suppress [7:0] reserved hp_pop_ dis1 hp_pop_ dis0 pga_pop_ dis3 pga_pop_dis2 pga_pop_dis1 pga_pop_ dis0 0x3f r/w 0x2a talkthru [7:0] reserved talkthru_path 0x00 r/w 0x2b talkthru_ gain0 [7:0] talkthru_gain0_val 0x00 r/w 0x2c talkthru_ gain1 [7:0] talkthru_gain1_val 0x00 r/w 0x2d mic_bias [7:0] reserved mic_en1 mic_en0 reserved reserved mic_gain1 mic_ gain0 0x00 r/w 0x2e dac_ control1 [7:0] reserved dac_pol dac1_mute dac0_mute reserved dac1_en dac0_en 0x18 r/w 0x2f dac0_volume [7:0] dac_0_vol 0x00 r/w 0x30 dac1_volume [7:0] dac_1_vol 0x00 r/w 0x31 op_stage_ mutes [7:0] reserved hp_mute_r hp_mute_l 0x0f r/w 0x32 sai_0 [7:0] sdata_fmt sai ser_port_fs 0x00 r/w 0x33 sai_1 [7:0] tdm_ts bclk_ tdmc lr_mode lr_pol sai_msb bclkrate bclkedge sai_ms 0x00 r/w 0x34 sout_ control0 [7:0] tdm7_dis tdm6_dis tdm5_dis tdm4_dis tdm3_dis tdm2_dis tdm1_dis tdm0_dis 0x00 r/w 0x36 pdm_out [7:0] reserved pdm_ctrl pdm_ch pdm_en 0x00 r/w 0x37 pdm_pattern [7:0] pattern 0x00 r/w 0x38 mode_mp0 [7:0] reserved mode_mp0_val 0x00 r/w 0x39 mode_mp1 [7:0] reserved mode_mp1_val 0x10 r/w 0x3a mode_mp2 [7:0] reserved mode_mp2_val 0x00 r/w 0x3b mode_mp3 [7:0] reserved mode_mp3_val 0x00 r/w 0x3c mode_mp4 [7:0] reserved mode_mp4_val 0x00 r/w 0x3d mode_mp5 [7:0] reserved mode_mp5_val 0x00 r/w 0x3e mode_mp6 [7:0] reserved mode_mp6_val 0x11 r/w 0x3f pb_vol_set [7:0] pb_vol_init_val hold 0x00 r/w 0x40 pb_vol_conv [7:0] gainstep rampspeed pb_vol_conv_val 0x87 r/w 0x41 debounce_ mode [7:0] reserved debounce 0x05 r/w 0x43 op_stage_ ctrl [7:0] reserved hp_en_r hp_en_l hp_pdn_r hp_pdn_l 0x0f r/w 0x44 decim_pwr_ modes [7:0] dec_3_en dec_2_en dec_1_en dec_0_en sinc_3_en sinc_2_en sinc_1_en sinc_0_en 0x00 r/w 0x45 interp_pwr_ modes [7:0] reserved mod_1_en mod_0_en int_1_en int_0_en 0x00 r/w 0x46 bias_ control0 [7:0] hp_ibias afe_ibias01 adc_ibias23 adc_ibias01 0x00 r/w 0x47 bias_ control1 [7:0] reserved cbias_dis afe_ibias23 mic_ibias dac_ibias 0x00 r/w 0x48 pad_ control0 [7:0] reserved dmic2_3_ pu dmic0_1_pu lrclk_pu bclk_pu adc_sdata1_ pu adc_sdata0_ pu dac_ sdata_pu 0x7f r/w 0x49 pad_ control1 [7:0] reserved selfboot_ pu scl_pu sda_pu addr1_pu addr0_pu 0x1f r/w
data sheet adau1777 rev. 0 | page 51 of 108 reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x4a pad_ control2 [7:0] reserved dmic2_3_ pd dmic0_1_pd lrclk_pd bclk_pd adc_sdata1_ pd adc_sdata0_ pd dac_ sdata_pd 0x00 r/w 0x4b pad_ control3 [7:0] reserved selfboot_ pd scl_pd sda_pd addr1_pd addr0_ pd 0x00 r/w 0x4c pad_ control4 [7:0] reserved reserved reserved lrclk_drv bclk_drv adc_sdata1_ drv adc_sdata0_ drv reserved 0x00 r/w 0x4d pad_ control5 [7:0] reserved reserved scl_drv sda_drv reserved reserved 0x00 r/w 0x4e fast_rate [7:0] reserved rate_div 0x00 r/w 0x4f dac_ control0 [7:0] dac_rate dac_intp reserved 0x00 r/w 0x54 vol_bypass [7:0] reserved dac1vol_by dac0vol_ by adc3vol_by adc2vol_by adc1vol_by adc0vol_ by 0x00 r/w
adau1777 data sheet rev. 0 | page 52 of 108 register details clock control register address: 0x00, reset: 0x00, name: clk_control this registe r enable s the internal clocks. table 37 . bit d escriptions for clk_control bits bit name settings description reset access 7 pll_en enable pll. when this bit is set to 0, the pll is powered down and the pll output clock is disabled. do not enable t he pll until after all the pll control settings (register pll_ctrl0 to register pll_ctrl5) are set. the pll clock output is active when both pll_en = 1 and coren = 1. 0x0 r/w 0 pll disabled. 1 pll enabled. 6 reserved reserved. 0x0 r/w 5 spk_flt_dis disable i 2 c spike filter. by default, the sda and scl inputs have a 50 ns spike suppression filter. when the control interface is in spi mode, this filter is disabled regardless of this setting. 0x0 r/w 0 i 2 c spike filter enabled. 1 i 2 c spike filter disabled. 4 xtal_dis disable crystal oscillator . 0x0 r/w 0 crystal oscillator enabled. 1 crystal oscillator disabled. 3 clksrc main clock source . 0x0 r/w 0 external pin drives main clock. 1 pll drives main clock. this bit must only be set after lock in register pll_ctrl5 has gone high. 2 cc_cdiv sclk divider control. the core clock (sclk) is used only by the core. it must run at 12.288 mhz. 0x0 r/w 0 div 2: divide pll/external clock by 2. 1 div 1: divide pll/external clock by 1.
data sheet adau1777 rev. 0 | page 53 of 108 bits bit name settings description reset access 1 cc_mdiv mclk divider control. the internal master clock (mclk) of the ic is used by all digital logic except the core. it must run at 12.288 mhz. 0x0 r/w 0 div 2: divide pll/external clock by 2. 1 div 1: divide pll/external clock by 1. 0 coren main clock enable. when coren = 0, it is only possible to write to this register and the pll control registers (pll_ctrl0 to pll_ctrl5). this control also enables the pll clock. if using the pll, do not set coren = 1 until lock in register pll_ctrl5 is 1. note that , after coren is enabled, writing to the param eters is disabled until setting dsp_clk_en in the core_enable register. 0x0 r/w 0 main clock disabled. 1 main clock enabled. pll denominator msb register address: 0x01, reset: 0x00, name: pll_ctrl0 only write to t his register when pll_en = 0 in register clk_control. table 38. bit descriptions for pll_ctrl0 bits bit name settings description reset access [7:0] m_msb pll denominator msb . 0x0 r/w pll denominator lsb register address: 0x02, reset: 0x00, name: pll_ctrl1 only write to this register when pll_en = 0 in register clk_control. table 39. bit descriptions for pll_ctrl1 bits bit name settings description reset access [7:0] m_lsb pll denominator lsb . 0x0 r/w pll numerator msb register address: 0x03, reset: 0x00, name: pll_ctrl2 only write to this register when pll_en = 0 in register clk_control. table 40. bit descriptions for pll_ctrl2 bits bit name settings description reset access [7:0] n_msb pll numerator msb . 0x0 r/w
adau1777 data sheet rev. 0 | page 54 of 108 pll numerator lsb register address: 0x04, reset: 0x00, name: pll_ctrl3 only write to this register when pll_en = 0 in register clk_control. table 41. bit descriptions for pll_ctrl3 bits bit name settings description reset access [7:0] n_lsb pll numerator lsb . 0x0 r/w pll integer setting register address: 0x05, reset: 0x00, name: pll_ctrl4 only write to this register when pll_en = 0 in register clk_control. table 42. bit descriptions for pll_ctrl4 bits bit name settings description reset access 7 reserved reserved. 0x0 r/w [6:3] r pll integer setting . 0x0 r/w 0000 reserved. 0001 reserved. 0010 2. 0011 3. 0100 4. 0101 5. 0110 6. 0111 7. 1000 8. [2:1] x pll input clock divide ratio . 0x0 r/w 00 pin clock input/1. 01 pin clock input/2. 10 pin clock input/3. 11 pin clock input/4. 0 pll_type pll type . 0x0 r/w 0 integer. 1 fractional.
data sheet adau1777 rev. 0 | page 55 of 108 pll lock flag register address: 0x06, reset: 0x00, name: pll_ctrl5 table 43. bit descriptions for pll_ctrl5 bits bit name settings description reset access [7:1] reserved reserved. 0x0 r/w 0 lock flag to indicate if the pll is locked. this bit is read only. 0x0 r 0 pll unlocked. 1 pll locked. clkout setting selec tion register address: 0x07, reset: 0x00, name: clkout_sel when the adc_sdata1/clkout/mp6 p i n is set to clock output mode, the frequency of the output clock is set in this register . clkout can be used to provide a master clock to another ic, the clock for digital microphones, or as the clock for the pdm output stream. the 12 mhz/24 mhz setting is used when clocking another ic, 3 mhz/6 mhz is used for pdmout, and 1.5 mhz/3 mh z is used when clocking digital microphones. the clkout frequency is derived from the master clock frequency, which is assumed to (and always must ) be 12.288 mhz. the 12.288 mhz and 24.576 mhz output modes are not functional if pdm is enabled (register pdm _out, bits[1:0]). table 44. bit descriptions for clkout_sel bits bit name settings description reset access [7:3] reserved reserved. 0x0 r/w [2:0] clkout_freq clkout pin frequency . 0x0 r/w 000 master clock 2 (24.576 mhz) . 001 master clock (12.288 mhz) . 010 master clock/2 (6.144 mhz) . 011 master clock/4 (3.072 mhz) . 100 master clock/8 (1.536 mhz) . 111 clock output off = 0.
adau1777 data sheet rev. 0 | page 56 of 108 regulator control register address: 0x08, reset: 0x00, name: regulator table 45. bit descriptions for regulator bits bit name settings description reset access [7:3] reserved reserved. 0x0 r/w 2 reg_pd powers down ldo regulator . 0x0 r/w 0 regulator active. 1 regulator powered down. [1:0] regv set regulator output voltage . 0x0 r/w 00 1.2 v. 01 1.1 v. 10 reserved. 11 reserved. core control register address: 0x09, reset: 0x04, name: core_control zeroes the state of the data memory during bank switching 1: zero state during back switch. 0: do not zero state during bank switch. run bit for the core 1: core on. 0: core off. selects active filter bank 11: reserved. 10: reserved. 01: bank b active. 00: bank a active. this bit sets the core sample rate 11: 768 khz. 10: 192 khz. 01: 96 khz. 00: reserved. selects the speed of the slow rate relative to the fast rate 10: slow rate = fast rate/8. 01: slow rate = fast rate/4. 00: slow rate = fast rate. 0 0 1 0 2 1 3 0 4 0 5 0 6 0 7 0 [7] zero_state (r/w ) [0] core_run (r/w ) [6:5] bank_sl (r/w ) [2:1] core_fs (r/w ) [4:3] fast_slow _rate (r/w ) table 46. bit descriptions for core_control bits bit name settings description reset access 7 zero_state zeroes the state of the data memory during bank switching. when switching active parameter banks between two settings, zeroing the state of the bank prevents the new filter settings from being active on old data that is recirculatin g in the filters. zeroing the state may prevent filter instability or unwanted noises upon bank switching. 0x0 r/w 0 do not zero state during bank switch. 1 zero state during back switch.
data sheet adau1777 rev. 0 | page 57 of 108 bits bit name settings description reset access [6:5] bank_sl selects active filter bank . 0x0 r/w 00 bank a active. 01 bank b active. 10 reserved. 11 reserved. [4:3] fast_slow_rate selects the speed of the slow rate relative to the fast rate. do not change t his setting while the core is running. core_run must be set to 0 for this setting to be updated. 0x0 r/w 00 slow rate = fast rate. 01 slow rate = fast rate/4. 10 slow rate = fast rate/8. [2:1] core_fs this bit sets the core sample rate. do not change t his setting while the core is running. core_run must be set to 0 for this setting to be updated. 0x2 r/w 00 reserved. 01 96 khz. 10 192 khz. 11 768 khz . when this mode is set, the fast rate of the core is set in bits rate_div in the fast rate control register. 0 core_run run bit for the core. enable t his bit only when the program and parameters are loaded and the sample rate settings are set. core_run starts and stops the core at the beginning of the program. 0x0 r/w 0 core off. 1 core on. sleep on program add ress count register address: 0x0a, reset: 0x00, name: sleep_inst the sleep bits control which registers are sleeping. for example, if sleep = 7, only instructions at address 0x0 0 to address 0x0 5 are executed. sleep = 0 disables sleeping.
adau1777 data sheet rev. 0 | page 58 of 108 table 47. bit descriptions for sleep_inst bits bit name settings description reset access [7:5] reserved reserved. 0x0 r/w [4:0] sleep sleep at a ddress sleep ? 2. these bits control which registers are sleeping. subtracting 2 from the sleep setting indicates the number of addresses that are affected. for example, if sleep = 7, only instructions at address 0x0 0 to address 0x0 5 are executed. do not change t his set ting while the core is running. core_run must be set to 0 for this setting to be updated. 0x0 r/w 00000 no sleep, all instructions are executed. 00001 reserved. 00010 sleep on 0 ( 0x00 ) . 00011 sleep on 1 ( 0x01 ) . 00100 sleep on 2 ( 0x02 ) . 00101 sleep on 3 ( 0x03 ) . 00110 sleep on 4 ( 0x04 ) . 00111 sleep on 5 ( 0x05 ) . 01000 sleep on 6 ( 0x06 ) . 01001 sleep on 7 ( 0x07 ) . 01010 sleep on 8 ( 0x08 ) . 01011 sleep on 9 ( 0x09 ) . 01100 sleep on 10 ( 0x0a ) . 01101 sleep on 11 ( 0x0b ) . 01110 sleep on 12 ( 0x0c ) . 01111 sleep on 13 ( 0x0d ) . 10000 sleep on 14 ( 0x0e ) . 10001 sleep on 15 ( 0x0f ) . 10010 sleep on 16 ( 0x10 ) . 10011 sleep on 17 ( 0x11 ) . 10100 sleep on 18 ( 0x12 ) . 10101 sleep on 19 ( 0x13 ) . 10110 sleep on 20 ( 0x14 ) . 10111 sleep on 21 ( 0x15 ) . 11000 sleep on 22 ( 0x16 ) . 11001 sleep on 23 ( 0x17 ) . 11010 sleep on 24 ( 0x18 ) . 11011 sleep on 25 ( 0x19 ) . 11100 sleep on 26 ( 0x1a ) . 11101 sleep on 27 ( 0x1b ) . 11110 sleep on 28 ( 0x1c ) . 11111 sleep on 29 ( 0x1d ) .
data sheet adau1777 rev. 0 | page 59 of 108 filter engine and li miter control register address: 0x0b, reset: 0x03, name: core_enable disabling the limiter only disables the attack operation. the d ecay operation is always active; therefore, a limiter can be safely disabled while the decay operation performs gain adjustments. table 48. bit descriptions for core_enable bits bit name settings description reset access [7:2] reserved reserved. 0x0 r/w 1 lim_en limiter enable. when the limiter function is disabled, a fixed max imum gain setting is applied to instructions using the limiters. 0x1 r/w 0 disabled. 1 enabled. 0 dsp_clk_en enable the clock to the core. this bit d irectly controls the clock to the core. s et this bit to 0 when the chip is used in a codec only configuration, in which the core is not used. writing to any of the biquad coefficient registers (parameter memory address 0x0e0 to parameter memory address 0x2 bf) is blocked until this bit is 1. do not use t his bit to start or stop the core while it is running, because it immediately start s or stop s the core clock and does not allow the program to finish. instead, use core_run in the core_control r egister to sta rt or stop the core. 0x1 r/w 0 core clock disabled. 1 core clock enabled. db value register 0 read address: 0x0c, reset: 0x00, name: dbreg0 the core can write data to this register, and the data is automatically converted to a level in db. the most common us e for this register is to determin e t he rms value of a signal by taking the absolute value, and then performing low - pass filtering and moving the result to the dbreg0 register. table 49. bit descriptions for dbreg0 bits bit name settings description reset access [7:0] dbval0 db value register 0 read . 0x0 r 00000000 ?96 db. 00010000 ?90 db. 00100000 ?84 db. 00110000 ?78 db. 11100000 ?12 db. 11110000 ?6 db. 11111111 ?0.375 db.
adau1777 data sheet rev. 0 | page 60 of 108 db value register 1 rea d address: 0x0d, reset: 0x00, name: dbreg1 the core can write data to this register, and the data is automatically converted to a l evel in db. the most common us e for this register is to deter - mine the rms value of a signal by taking th e absolute value, and then performing low - pass filtering and moving the result to the dbreg1 register. table 50. bit descriptions for dbreg1 bits bit name settings description reset access [7:0] dbval1 db value register 1 read . 0x0 r 00000000 ?96 db. 00010000 ?90 db. 00100000 ?84 db. 00110000 ?78 db. 11100000 ?12 db. 11110000 ?6 db. 11111111 ?0.375 db. db value register 2 read address: 0x0e, reset: 0x00, name: dbreg2 the core can write data to this register, and the data is automatically converted to a l evel in db. the most common us e for this register is to deter - mine the rms value of a signal by taking the absolute value, and then performing low - pass filtering and moving the result to the dbr eg2 register. table 51. bit descriptions for dbreg2 bits bit name settings description reset access [7:0] dbval2 db value register 2 read . 0x0 r 00000000 ?96 db. 00010000 ?90 db. 00100000 ?84 db. 00110000 ?78 db. 11100000 ?12 db. 11110000 ?6 db. 11111111 ?0.375 db.
data sheet adau1777 rev. 0 | page 61 of 108 core channel 0/core channel 1 input sele ct register address: 0x0f, reset: 0x10, name: core_in_mux_0_1 table 52. bit descriptions for core_in_mux_0_1 bits bit name settings description reset access [7:4] core_in_mux_sel_1 core input channel 1 source . 0x1 r/w 0000 ain0/dmic0. 0001 ain1/dmic1. 0010 ain2/dmic2. 0011 ain3/dmic3. 0100 reserved. 0101 reserved. 0110 reserved. 0111 reserved. 1000 reserved. 1001 reserved. 1010 reserved. 1011 reserved. 1100 input asrc channel 0. 1101 input asrc channel 1. [3:0] core_in_mux_sel_0 core input channel 0 source . 0x0 r/w 0000 ain0/dmic0. 0001 ain1/dmic1. 0010 ain2/dmic2. 0011 ain3/dmic3. 0100 reserved. 0101 reserved. 0110 reserved. 0111 reserved. 1000 reserved. 1001 reserved. 1010 reserved. 1011 reserved. 1100 input asrc channel 0. 1101 input asrc channel 1.
adau1777 data sheet rev. 0 | page 62 of 108 core channel 2/core channel 3 input sele ct register address: 0x10, reset: 0x32, name: core_in_mux_2_3 table 53. bit descriptions for core_in_mux_2_3 bits bit name settings description reset access [7:4] core_in_mux_sel_3 core input channel 3 source . 0x3 r/w 0000 ain0/dmic0. 0001 ain1/dmic1. 0010 ain2/dmic2. 0011 ain3/dmic3. 0100 reserved. 0101 reserved. 0110 reserved. 0111 reserved. 1000 reserved. 1001 reserved. 1010 reserved. 1011 reserved. 1100 input asrc channel 0. 1101 input asrc channel 1. [3:0] core_in_mux_sel_2 core input channel 2 source . 0x2 r/w 0000 ain0/dmic0. 0001 ain1/dmic1. 0010 ain2/dmic2. 0011 ain3/dmic3. 0100 reserved. 0101 reserved. 0110 reserved. 0111 reserved. 1000 reserved. 1001 reserved. 1010 reserved. 1011 reserved. 1100 input asrc channel 0. 1101 input asrc channel 1.
data sheet adau1777 rev. 0 | page 63 of 108 dac input select register address: 0x11, reset: 0x10, name: dac_source_0_1 table 54. bit descriptions for dac_source_0_1 bits bit name settings description reset access [7:4] dac_source1 dac1 input source. do not change t his setting while the core is running. core_run must be set to 0 for this setting to be updated. 0x1 r/w 0000 core output 0. 0001 core output 1. 0010 core output 2. 0011 core output 3. 0100 reserved. 0101 reserved. 0110 reserved. 0111 reserved. 1000 reserved. 1001 reserved. 1010 reserved. 1011 reserved. 1100 input asrc channel 0. 1101 input asrc channel 1. [3:0] dac_source0 dac0 input source. do not change t his setting while the core is running. core_run must be set to 0 for this setting to be updated. 0x0 r/w 0000 core output 0. 0001 core output 1. 0010 core output 2. 0011 core output 3. 0100 reserved. 0101 reserved. 0110 reserved. 0111 reserved. 1000 reserved. 1001 reserved. 1010 reserved. 1011 reserved. 1100 input asrc channel 0. 1101 input asrc channel 1.
adau1777 data sheet rev. 0 | page 64 of 108 pdm modulator input select register address: 0x12, reset: 0x32, name: pdm_source_0_1 table 55. bit descriptions for pdm_source_0_1 bits bit name settings description reset access [7:4] pdm_source1 pdm modulator channel 1 input source . 0x3 r/w 0000 core output 0. 0001 core output 1. 0010 core output 2. 0011 core output 3. 0100 reserved. 0101 reserved. 0110 reserved. 0111 reserved. 1000 reserved. 1001 reserved. 1010 reserved. 1011 reserved. 1100 input asrc channel 0. 1101 input asrc channel 1. [3:0] pdm_source0 pdm modulator channel 0 input source . 0x2 r/w 0000 core output 0. 0001 core output 1. 0010 core output 2. 0011 core output 3. 0100 reserved. 0101 reserved. 0110 reserved. 0111 reserved. 1000 reserved. 1001 reserved. 1010 reserved. 1011 reserved. 1100 input asrc channel 0. 1101 input asrc channel 1.
data sheet adau1777 rev. 0 | page 65 of 108 serial data output 0 /serial data output 1 input select register address: 0x13, reset: 0x54, name: sout_source_0_1 table 56. bit descriptions for sout_source_0_1 bits bit name settings description reset access [7:4] sout_source1 serial data output channel 1 source select . 0x5 r/w 0000 reserved. 0001 reserved. 0010 reserved. 0011 reserved. 0100 output asrc channel 0. 0101 output asrc channel 1. 0110 output asrc channel 2. 0111 output asrc channel 3. 1000 serial input 0. 1001 serial input 1. 1010 serial input 2. 1011 serial input 3. 1100 serial input 4. 1101 serial input 5. 1110 serial input 6. 1111 serial input 7. [3:0] sout_source0 serial data output channel 0 source select . 0x4 r/w 0000 reserved. 0001 reserved. 0010 reserved. 0011 reserved. 0100 output asrc channel 0. 0101 output asrc channel 1. 0110 output asrc channel 2. 0111 output asrc channel 3. 1000 serial input 0. 1001 serial input 1. 1010 serial input 2. 1011 serial input 3. 1100 serial input 4. 1101 serial input 5. 1110 serial input 6. 1111 serial input 7.
adau1777 data sheet rev. 0 | page 66 of 108 serial data output 2 /serial data output 3 input select register address: 0x14, reset: 0x76, name: sout_source_2_3 table 57. bit descriptions for sout_source_2_3 bits bit name settings description reset access [7:4] sout_source3 serial data output channel 3 source select . 0x7 r/w 0000 reserved. 0001 reserved. 0010 reserved. 0011 reserved. 0100 output asrc channel 0. 0101 output asrc channel 1. 0110 output asrc channel 2. 0111 output asrc channel 3. 1000 serial input 0. 1001 serial input 1. 1010 serial input 2. 1011 serial input 3. 1100 serial input 4. 1101 serial input 5. 1110 serial input 6. 1111 serial input 7. [3:0] sout_source2 serial data output channel 2 source select . 0x6 r/w 0000 reserved. 0001 reserved. 0010 reserved. 0011 reserved. 0100 output asrc channel 0. 0101 output asrc channel 1. 0110 output asrc channel 2. 0111 output asrc channel 3. 1000 serial input 0. 1001 serial input 1. 1010 serial input 2. 1011 serial input 3. 1100 serial input 4. 1101 serial input 5. 1110 serial input 6. 1111 serial input 7.
data sheet adau1777 rev. 0 | page 67 of 108 serial data output 4 /serial data output 5 input select register address: 0x15, reset: 0x54, name: sout_source_4_5 table 58. bit descriptions for sout_source_4_5 bits bit name settings description reset access [7:4] sout_source5 serial data output channel 5 source select . 0x5 r/w 0000 reserved. 0001 reserved. 0010 reserved. 0011 reserved. 0100 output asrc channel 0. 0101 output asrc channel 1. 0110 output asrc channel 2. 0111 output asrc channel 3. 1000 serial input 0. 1001 serial input 1. 1010 serial input 2. 1011 serial input 3. 1100 serial input 4. 1101 serial input 5. 1110 serial input 6. 1111 serial input 7. [3:0] sout_source4 serial data output channel 4 source select . 0x4 r/w 0000 reserved. 0001 reserved. 0010 reserved. 0011 reserved. 0100 output asrc channel 0. 0101 output asrc channel 1. 0110 output asrc channel 2. 0111 output asrc channel 3. 1000 serial input 0. 1001 serial input 1. 1010 serial input 2. 1011 serial input 3. 1100 serial input 4. 1101 serial input 5. 1110 serial input 6. 1111 serial input 7.
adau1777 data sheet rev. 0 | page 68 of 108 serial data output 6 /serial data output 7 input select register address: 0x16, reset: 0x76, name: sout_source_6_7 table 59. bit descriptions for sout_source_6_7 bits bit name settings description reset access [7:4] sout_source7 serial data output channel 7 source select . 0x7 r/w 0000 reserved. 0001 reserved. 0010 reserved. 0011 reserved. 0100 output asrc channel 0. 0101 output asrc channel 1. 0110 output asrc channel 2. 0111 output asrc channel 3. 1000 serial input 0. 1001 serial input 1. 1010 serial input 2. 1011 serial input 3. 1100 serial input 4. 1101 serial input 5. 1110 serial input 6. 1111 serial input 7. [3:0] sout_source6 serial data output channel 6 source select . 0x6 r/w 0000 reserved. 0001 reserved. 0010 reserved. 0011 reserved. 0100 output asrc channel 0. 0101 output asrc channel 1. 0110 output asrc channel 2. 0111 output asrc channel 3. 1000 serial input 0. 1001 serial input 1. 1010 serial input 2. 1011 serial input 3. 1100 serial input 4. 1101 serial input 5. 1110 serial input 6. 1111 serial input 7.
data sheet adau1777 rev. 0 | page 69 of 108 adc_sdata0/adc_sdata 1 channel select register address: 0x17, reset: 0x04, name: adc_sdata_ch table 60. bit descriptions for adc_sdata_ch bits bit name settings description reset access [7:4] reserved reserved. 0x0 r/w [3:2] adc_sdata1_st sdata1 output channel output select. these bits s elect the output channel at which adc_sdata1 starts to output data. the output port sequentially outputs data following this start channel according to the setting of bit sai. 0x1 r/w 00 channel 0. 01 channel 2. 10 channel 4. 11 channel 6. [1:0] adc_sdata0_st sdata0 output channel output select. these bits s elect the output channel at which adc_sdata0 starts to output data. the output port sequentially outputs data following this start channel according to the setting of bit sai. 0x0 r/w 00 channel 0. 01 channel 2. 10 channel 4. 11 channel 6. output asrc0/output asrc1 source register address: 0x18, reset: 0x10, name: asrco_source_0_1 table 61. bit descriptions for asrco_source_0_1 bits bit name settings description reset access [7:4] asrc_out_source1 output asrc channel 1 source select . 0x1 r/w 0000 core output 0. 0001 core output 1. 0010 core output 2. 0011 core output 3. 0100 adc0. 0101 adc1. 0110 adc2. 0111 adc3.
adau1777 data sheet rev. 0 | page 70 of 108 bits bit name settings description reset access 1000 serial input 0. 1001 serial input 1. 1010 serial input 2. 1011 serial input 3. 1100 serial input 4. 1101 serial input 5. 1110 serial input 6. 1111 serial input 7. [3:0] asrc_out_source0 output asrc channel 0 source select . 0x0 r/w 0000 core output 0. 0001 core output 1. 0010 core output 2. 0011 core output 3. 0100 adc0. 0101 adc1. 0110 adc2. 0111 adc3. 1000 serial input 0. 1001 serial input 1. 1010 serial input 2. 1011 serial input 3. 1100 serial input 4. 1101 serial input 5. 1110 serial input 6. 1111 serial input 7. output asrc2/output asrc3 source register address: 0x19, reset: 0x32, name: asrco_source_2_3 table 62. bit descriptions for asrco_source_2_3 bits bit name settings description reset access [7:4] asrc_out_source3 output asrc channel 3 source select . 0x3 r/w 0000 core output 0. 0001 core output 1. 0010 core output 2. 0011 core output 3. 0100 adc0.
data sheet adau1777 rev. 0 | page 71 of 108 bits bit name settings description reset access 0101 adc1. 0110 adc2. 0111 adc3. 1000 serial input 0. 1001 serial input 1. 1010 serial input 2. 1011 serial input 3. 1100 serial input 4. 1101 serial input 5. 1110 serial input 6. 1111 serial input 7. [3:0] asrc_out_source2 output asrc channel 2 source select . 0x2 r/w 0000 core output 0. 0001 core output 1. 0010 core output 2. 0011 core output 3. 0100 adc0. 0101 adc1. 0110 adc2. 0111 adc3. 1000 serial input 0. 1001 serial input 1. 1010 serial input 2. 1011 serial input 3. 1100 serial input 4. 1101 serial input 5. 1110 serial input 6. 1111 serial input 7. input asrc channel s elect register address: 0x1a, reset: 0x00, name: asrc_mode
adau1777 data sheet rev. 0 | page 72 of 108 table 63. bit descriptions for asrc_mode bits bit name settings description reset access [7:4] reserved reserved. 0x0 r/w [3:2] asrc_in_ch input asrc channel select . 0x0 r/w 00 serial input port channel 0/serial input port channel 1. 01 serial input port channel 2/serial input port channel 3. 10 serial input port channel 4/serial input port channel 5. 11 serial input port channel 6/serial input port channel 7. 1 asrc_out_en output asrc enable . 0x0 r/w 0 disabled. 1 enabled. 0 asrc_in_en input asrc enable . 0x0 r/w 0 disabled. 1 enabled. adc0/adc1 control 0 register address: 0x1b, reset: 0x19, name: adc_control0 table 64. bit descriptions for adc_control0 bits bit name settings description reset access [7:6] reserved reserved. 0x0 r/w 5 adc_0_1_sinc selects third - or fourth - order sinc. do not change t his setting while the core is running. core_run must be set to 0 for this setting to be updated. 0x0 r/w 0 fourth - order sinc. 1 third - order sinc. 4 adc1_mute mute adc1. muting is accomplished by setting the volume control to maximum attenuation. this bit has no effect if volume control is bypassed. 0x1 r/w 0 unmuted. 1 muted. 3 adc0_mute mute adc0. muting is accomplished by setting the volume control to maximum attenuation. this bit has no effect if volume control is bypassed. 0x1 r/w 0 unmuted. 1 muted. 2 reserved reserved. 0x0 r/w
data sheet adau1777 rev. 0 | page 73 of 108 bits bit name settings description reset access [1:0] adc_0_1_fs sets adc sample rate. the settings of these bits must be consistent with the settings of the fast_ slow_rate bits, and core_run must be set to 0 for this setting to be updated. 0x1 r/w 00 96 khz. 01 192 khz. 10 768 khz. 11 reserved. adc2/adc3 control 0 register address: 0x1c, reset: 0x19, name: adc_control1 table 65. bit descriptions for adc_control1 bits bit name settings description reset access [7:6] reserved reserved. 0x0 r/w 5 adc_2_3_sinc selects third - or fourth - order sinc. do not change t his setting while the core is running. core_run must be set to 0 for this setting to be updated. 0x0 r/w 0 fourth - order sinc. 1 third - order sinc. 4 adc3_mute mute adc3 . 0x1 r/w 0 unmuted. 1 muted. 3 adc2_mute mute adc2. muting is accomplished by setting the volume control to maximum attenuation. this bit has no effect if volume control is bypassed. 0x1 r/w 0 unmuted. 1 muted. 2 reserved reserved. 0x0 r/w [1:0] adc_2_3_fs sets adc sample rate. the settings of these bits must be consistent with the settings of the fast_ slow_rate bits, and core_run must be set to 0 for this setting to be updated. 0x1 r/w 00 96 khz. 01 192 khz. 10 768 khz. 11 reserved.
adau1777 data sheet rev. 0 | page 74 of 108 adc0/adc1 control 1 register address: 0x1d, reset: 0x00, name: adc_control2 table 66. bit descriptions for adc_control2 bits bit name settings description reset access 7 reserved reserved. 0x0 r/w [6:5] hp_0_1_en high - pass filter settings . 0x0 r/w 00 off. 01 1 hz. 10 4 hz. 11 8 hz. 4 dmic_pol0 selects microphone polarity . 0x0 r/w 0 0 positive, 1 negative. 1 1 positive, 0 negative. 3 dmic_sw0 digital microphone swap . 0x0 r/w 0 channel swap off (left channel on rising edge, right channel on falling edge) . 1 swap left and right. 2 dcm_0_1 sets the input source to adcs or digital microphones . 0x0 r/w 0 decimator source set to adc. 1 decimator source set to digital microphones. 1 adc_1_en enable adc1. this bit must be set in conjunction with the sinc_1_en bit in the decim_pwr_modes register to fully enable or disable the adc . 0x0 r/w 0 disable. 1 enable. 0 adc_0_en enable adc0. this bit must be set in conjunction with the sinc_0_en bit in the decim_pwr_modes register to fully enable or disable the adc . 0x0 r/w 0 disable. 1 enable.
data sheet adau1777 rev. 0 | page 75 of 108 adc2/adc3 control 1 register address: 0x1e, reset: 0x00, name: adc_control3 table 67. bit descriptions for adc_control3 bits bit name settings description reset access 7 reserved reserved. 0x0 r/w [6:5] hp_2_3_en high - pass filter settings . 0x0 r/w 00 off. 01 1 hz. 10 4 hz. 11 8 hz. 4 dmic_pol1 microphone polarity . 0x0 r/w 0 0 positive, 1 negative. 1 1 positive, 0 negative. 3 dmic_sw1 digital microphone swap . 0x0 r/w 0 channel swap off (left channel on rising edge, right channel on falling edge) . 1 swap left and right. 2 dcm_2_3 sets the input source to adcs or digital microphones . 0x0 r/w 0 decimator source set to adc. 1 decimator source set to digital microphone. 1 adc_3_en enable adc3. this bit must be set in conjunction with the sinc_3_en bit in the decim_pwr_modes register to fully enable or disable the adc. 0x0 r/w 0 disable. 1 enable. 0 adc_2_en enable adc2. this bit must be set in conjunction with the sinc_2_en bit in the decim_pwr_modes register to fully enable or disable the adc. 0x0 r/w 0 disable. 1 enable. adc0 volume control register address: 0x1f, reset: 0x00, name: adc0_volume when sinc_0_en is set, the volume starts to ramp from ?95.625 db to the value in this register. the volume ramp time is (numb er of steps) 16/f s , where there are 256 steps between 0 db and ?95.625 db. for example, with f s = 192 khz, the volume ramps from ?95.625 db to 0 db in 21 ms.
adau1777 data sheet rev. 0 | page 76 of 108 table 68. bit descriptions for adc0_volume bits bit name settings description reset access [7:0] adc_0_vol adc0 volume setting . 0x0 r/w 00000000 0 db. 00000001 ?0.375 db. 11111111 ?95.625 db. adc1 volume control register address: 0x20, reset: 0x00, name: adc1_volume when sinc_1_en is set, the volume starts to ramp from ?95.625 db to the value in this register. the volume ramp time is (numb er of st eps) 16/f s , where there are 256 steps between 0 db and ?95.625 db. for example, with f s = 192 khz, the volume ramps from ?95.625 db to 0 db in 21 ms. table 69. bit descriptions for adc1_volume bits bit name settings description reset a ccess [7:0] adc_1_vol adc1 volume setting . 0x0 r/w 00000000 0 db. 00000001 ?0.375 db. 11111111 ?95.625 db. adc2 volume control register address: 0x21, reset: 0x00, name: adc2_volume when sinc_2_en is set, the volume starts to ramp from ?95.625 db to the value in this register. the volume ramp time is (number of steps) 16/f s , where there are 256 steps between 0 db and ?95.625 db. for example, with f s = 192 khz, the volume ramps from ?95.625 db to 0 db in 21 ms. table 70. bit descriptions for adc2_volume bits bit name settings description reset access [7:0] adc_2_vol adc2 volume setting . 0x0 r/w 00000000 0 db. 00000001 ?0.375 db. 11111111 ?95.625 db.
data sheet adau1777 rev. 0 | page 77 of 108 adc3 volume control register address: 0x22, reset: 0x00, name: adc3_volume when sinc_3_en is set, the volume starts to ramp from ?95.625 db to the value in this register. the volume ramp time is (numb er of steps) 16/f s , where there are 256 steps between 0 db and ?95.625 db. for example, with f s = 192 khz, the volume ramps from ?95.625 db to 0 db in 21 ms. table 71. bit descriptions for adc3_volume bits bit name settings description reset access [7:0] adc_3_vol adc3 volume setting . 0x0 r/w 00000000 0 db. 00000001 ?0.375 db. 11111111 ?95.625 db. pga control 0 register address: 0x23, reset: 0x40, name: pga_control_0 this register controls the pga connected to ain0. table 72. bit descriptions for pga_control_0 bits bit name settings description reset access 7 pga_en0 select line or microphone input. note that the pga inverts the signal going through it. 0x0 r/w 0 ain0 used as a single - ended line input. pga powered down. 1 ain0 used as a single - ended microphone input. pga powered up with slewing. 6 pga_mute0 enable pga mute. when pga is muted, pga_gain0 is ignored. 0x1 r/w 0 unmuted. 1 muted. [5:0] pga_gain0 set the gain of pga0 . 0x0 r/w 000000 ?12 db. 000001 ?11.25 db. 010000 0 db. 111110 +34.5 db. 111111 +35.25 db.
adau1777 data sheet rev. 0 | page 78 of 108 pga control 1 register address: 0x24, reset: 0x40, name: pga_control_1 this register controls the pga connected to ain1. table 73. bit descriptions for pga_control_1 bits bit name settings description reset access 7 pga_en1 select line or microphone input. note that the pga inverts the signal going through it. 0x0 r/w 0 ain1 used as a single - ended line input. pga powered down. 1 ain1 used as a single - ended microphone input. pga powered up with slewing. 6 pga_mute1 enable pga1 mute. when pga is muted, pga_gain1 is ignored. 0x1 r/w 0 unmuted. 1 muted. [5:0] pga_gain1 set the gain of pga1 . 0x0 r/w 000000 ?12 db. 000001 ?11.25 db. 010000 0 db. 111110 +34.5 db. 111111 +35.25 db. pga control 2 register address: 0x25, reset: 0x40, name: pga_control_2 this register controls the pga connected to ain2. table 74. bit descriptions for pga_control_2 bits bit name settings description reset access 7 pga_en2 select line or microphone input. note that the pga inverts the signal going through it. 0x0 r/w 0 ain2 used as a single - ended line input. pga powered down. 1 ain2 used as a single - ended microphone input. pga powered up with slewing.
data sheet adau1777 rev. 0 | page 79 of 1 08 bits bit name settings description reset access 6 pga_mute2 enable pga2 mute. when pga is muted, pga_gain2 is ignored. 0x1 r/w 0 unmuted. 1 muted. [5:0] pga_gain2 set the gain of pga2 . 0x0 r/w 000000 ?12 db. 000001 ?11.25 db. 010000 0 db. 111110 +34.5 db. 111111 +35.25 db. pga control 3 register address: 0x26, reset: 0x40, name: pga_control_3 this register controls the pga connected to ain3. table 75. bit descriptions for pga_control_3 bits bit name settings description reset access 7 pga_en3 select line or microphone input. note that the pga inverts the signal going through it. 0x0 r/w 0 ain3 used as a single - ended line input. pga powered down. 1 ain3 used as a single - ended microphone input. pga powered up with slewing. 6 pga_mute3 enable pga3 mute. when pga is muted, pga_gain3 is ignored. 0x1 r/w 0 unmuted. 1 muted. [5:0] pga_gain3 set the gain of pga3 . 0x0 r/w 000000 ?12 db. 000001 ?11.25 db. 010000 0 db. 111110 +34.5 db. 111111 +35.25 db.
adau1777 data sheet rev. 0 | page 80 of 108 pga slew control register address: 0x27, reset: 0x00, name: pga_step_control if pga slew is disabled with the slew_pdx controls, the slew_rate parameter is ignored for that pga block. table 76. bit descriptions for pga_step_control bits bit name settings description reset access [7:6] reserved reserved. 0x0 r/w [5:4] slew_rate controls how fast the pga is slewed when changing gain . 0x0 r/w 00 21.5 ms. 01 42.5 ms. 10 85 ms. 3 slew_pd3 pga3 slew disable . 0x0 r/w 0 pga slew enabled. 1 pga slew disabled. 2 slew_pd2 pga2 slew disable . 0x0 r/w 0 pga slew enabled. 1 pga slew disabled. 1 slew_pd1 pga1 slew disable . 0x0 r/w 0 pga slew enabled. 1 pga slew disabled. 0 slew_pd0 pga0 slew disable . 0x0 r/w 0 pga slew enabled. 1 pga slew disabled. pga 10 db gain boost register address: 0x28, reset: 0x00, name: pga_10db_boost each pga can have an additional +10 db gain added, making the pga gain range ?2 db to +46 db.
data sheet adau1777 rev. 0 | page 81 of 108 table 77. bit descriptions for pga_10db_boost bits bit name settings description reset access [7:4] reserved reserved. 0x0 r/w 3 pga_3_boost boost control for pga3 . 0x0 r/w 0 default pga gain set in register pga_control_3. 1 additional 10 db gain above setting in register pga_control_3. 2 pga_2_boost boost control for pga2 . 0x0 r/w 0 default pga gain set in register pga_control_2. 1 additional 10 db gain above setting in register pga_control_2. 1 pga_1_boost boost control for pga1 . 0x0 r/w 0 default pga gain set in register pga_control_1. 1 additional 10 db gain above setting in register pga_control_1. 0 pga_0_boost boost control for pga0 . 0x0 r/w 0 default pga gain set in register pga_control_0. 1 additional 10 db gain above setting in register pga_control_0. input and output cap acitor charging register address: 0x29, reset: 0x3f, name: pop_suppress table 78. bit descriptions for pop_suppress bits bit name settings description reset access [7:6] reserved reserved. 0x0 r/w 5 hp_pop_dis1 disable pop suppression on headphone output 1 . 0x1 r/w 0 enabled. 1 disabled. 4 hp_pop_dis0 disable pop suppression on headphone output 0 . 0x1 r/w 0 enabled. 1 disabled. 3 pga_pop_dis3 disable pop suppression on pga3 input . 0x1 r/w 0 enabled. 1 disabled. 2 pga_pop_dis2 disable pop suppression on pga2 input . 0x1 r/w 0 enabled. 1 disabled.
adau1777 data sheet rev. 0 | page 82 of 108 bits bit name settings description reset access 1 pga_pop_dis1 disable pop suppression on pga1 input . 0x1 r/w 0 enabled. 1 disabled. 0 pga_pop_dis0 disable pop suppression on pga0 input . 0x1 r/w 0 enabled. 1 disabled. dsp bypass path register address: 0x2a, reset: 0x00, name: talkthru table 79. bit descriptions for talkthru bits bit name settings description reset access [7:2] reserved reserved. 0x0 r/w [1:0] talk thru_path signal path when dsp bypass is enabled . 0x0 r/w 00 no dsp bypass. 01 adc0 to dac0. 10 adc1 to dac1. 11 adc0 and adc1 to dac0 and dac1. dsp bypass gain for pga0 register address: 0x2b, reset: 0x00, name: talkthru_gain0 table 80. bit descriptions for talkthru_gain0 bits bit name settings description reset access [7:0] talkthru_gain0_val sets the dac0 volume when dsp bypass mode is enabled. 0x0 r/w dsp bypass gain for pga1 register address: 0x2c, reset: 0x00, name: talkthru_gain1 table 81. bit descriptions for talkthru_gain1 bits bit name settings description reset access [7:0] talkthru_gain1_val sets the dac1 volume when dsp bypass mode is enabled . 0x0 r/w
data sheet adau1777 rev. 0 | page 83 of 108 micbias0_1 control register address: 0x2d, reset: 0x00, name: mic_bias table 82. bit descriptions for mic_bias bits bit name settings description reset access [7:6] reserved reserved. 0x0 r/w 5 mic_en1 micbias1 output enable . 0x0 r/w 0 disabled. 1 enabled. 4 mic_en0 micbias0 output enable . 0x0 r/w 0 disabled. 1 enabled. 3 reserved reserved. 0x0 r/w 2 reserved reserved. 0x0 r/w 1 mic_gain1 level of the micbias1 output . 0x0 r/w 0 0.9 avdd. 1 0.65 avdd. 0 mic_gain0 level of the micbias0 output . 0x0 r/w 0 0.9 avdd. 1 0.65 avdd. dac control register address: 0x2e, reset: 0x18, name: dac_control1 table 83. bit descriptions for dac_control1 bits bit name settings description reset access [7:6] reserved reserved. 0x0 r/w
adau1777 data sheet rev. 0 | page 84 of 108 bits bit name settings description reset access 5 dac_pol invert input polarity . 0x0 r/w 0 normal. 1 inverted. 4 dac1_mute mute dac1 . 0x1 r/w 0 unmuted. 1 muted. 3 dac0_mute mute dac0 . 0x1 r/w 0 unmuted. 1 muted. 2 reserved reserved. 0x0 r/w 1 dac1_en enable dac1 . 0x0 r/w 0 disable dac1. 1 enable dac1. 0 dac0_en enable dac0 . 0x0 r/w 0 disable dac0. 1 enable dac0. dac0 volume control register address: 0x2f, reset: 0x00, name: dac0_volume table 84. bit descriptions for dac0_volume bits bit name settings description reset access [7:0] dac_0_vol dac0 volume setting . 0x0 r/w 00000000 0 db. 00000001 ?0.375 db. 11111111 ?95.625 db. dac1 volume control register address: 0x30, reset: 0x00, name: dac1_volume
data sheet adau1777 rev. 0 | page 85 of 108 table 85. bit descriptions for dac1_volume bits bit name settings description reset access [7:0] dac_1_vol dac1 volume setting . 0x0 r/w 00000000 0 db. 00000001 ?0.375 db. 11111111 ?95.625 db. headphone output mut es register address: 0x31, reset: 0x0f, name: op_stage_mutes table 86. bit descriptions for op_stage_mutes bits bit name settings description reset access [7:4] reserved reserved. 0x0 r/w [3:2] hp_mute_r mute the right output pins. when a pin is muted, it can be used as a common - mode output. 0x3 r/w 00 outputs unmuted. 01 hpoutrp/loutrp muted, hpoutrn/loutrn unmuted. 10 hpoutrp/loutrp unmuted, hpoutrn/loutrn muted. 11 both output pins muted. [1:0] hp_mute_l mute the left output pins. when a pin is muted, it can be used as a common - mode output. 0x3 r/w 00 outputs unmuted. 01 hpoutlp/loutlp muted, hpoutln/loutln unmuted. 10 hpoutlp/loutlp unmuted, hpoutln/loutln muted. 11 both output pins muted. serial port control 0 register address: 0x32, reset: 0x00, name: sai_0 using 16 - bit serial input/output limits device performance.
adau1777 data sheet rev. 0 | page 86 of 108 table 87. bit descriptions for sai_0 bits bit name settings description reset access [7:6] sdata_fmt serial data format . 0x0 r/w 00 tdm, i 2 s data delayed from edge of lrclk by 1 bclk cycle. 01 tdm, left justified data synchronized to edge of lrclk. 10 right justified, 24 - bit data. 11 right justified, 16 - bit data. [5:4] sai serial port mode . 0x0 r/w 00 stereo ( i 2 s , left justified, right justified) . 01 tdm2. 10 tdm4. 11 tdm8. [3:0] ser_port_fs sampling rate on the serial ports . 0x0 r/w 0000 48 khz. 0001 8 khz. 0010 12 khz. 0011 16 khz. 0100 24 khz. 0101 32 khz. 0110 96 khz. 0111 192 khz. serial port control 1 register address: 0x33, reset: 0x00, name: sai_1 using 16 - bit serial input/output limits device performance. table 88. bit descriptions for sai_1 bits bit name settings description reset access 7 tdm_ts select whether to tristate unused tdm channels or to actively drive these data slots . 0x0 r/w 0 unused outputs driven. 1 unused outputs tristated.
data sheet adau1777 rev. 0 | page 87 of 108 bits bit name settings description reset access 6 bclk_tdmc bit width in tdm mode . 0x0 r/w 0 24- bit data in each tdm channel. 1 16- bit data in each tdm channel. 5 lr_mode sets lrclk mode . 0x0 r/w 0 50% duty cycle clock. 1 pulse lrclk is a single bclk cycle wide pulse. 4 lr_pol sets lrclk polarity . 0x0 r/w 0 50%: when lrclk goes low and then high, pulse mode is short positive pulse. 1 50%: when lrclk goes high and then low, pulse mode is short negative pulse. 3 sai_msb sets data to be input/output either msb or lsb first . 0x0 r/w 0 msb first data. 1 lsb first data. 2 bclkrate sets the number of bit clock cycles per data channel . 0x0 r/w 0 32 bclk cycles/channel. 1 16 bclk cycles/channel. 1 bclkedge sets the bit clock edge on which data changes . 0x0 r/w 0 data changes on falling edge. 1 data changes on rising edge. 0 sai_ms sets the serial port into master or slave mode . 0x0 r/w 0 lrclk/bclk slave. 1 lrclk/bclk master. tdm output channel d isable register address: 0x34, reset: 0x00, name: sout_control0 this register is for use only in tdm mode. table 89. bit descriptions for sout_control0 bits bit name settings description reset access 7 tdm7_dis disable data in tdm output slot 7 . 0x0 r/w 0 output channel enabled. 1 output channel disabled.
adau1777 data sheet rev. 0 | page 88 of 108 bits bit name settings description reset access 6 tdm6_dis disable data in tdm output slot 6 . 0x0 r/w 0 output channel enabled. 1 output channel disabled. 5 tdm5_dis disable data in tdm output slot 5 . 0x0 r/w 0 output channel enabled. 1 output channel disabled. 4 tdm4_dis disable data in tdm output slot 4 . 0x0 r/w 0 output channel enabled. 1 output channel disabled. 3 tdm3_dis disable data in tdm output slot 3 . 0x0 r/w 0 output channel enabled. 1 output channel disabled. 2 tdm2_dis disable data in tdm output slot 2 . 0x0 r/w 0 output channel enabled. 1 output channel disabled. 1 tdm1_dis disable data in tdm output slot 1 . 0x0 r/w 0 output channel enabled. 1 output channel disabled. 0 tdm0_dis disable data in tdm output slot 0 . 0x0 r/w 0 output channel enabled. 1 output channel disabled. pdm enable register address: 0x36, reset: 0x00, name: pdm_out table 90. bit descriptions for pdm_out bits bit name settings description reset access [7:5] reserved reserved. 0x0 r/w 4 pdm_ctrl enable the control pattern in the pdm data stream . 0x0 r/w 0 disabled. 1 enabled.
data sheet adau1777 rev. 0 | page 89 of 108 bits bit name settings description reset access [3:2] pdm_ch selects the channel on which the control patterns are written. do not change these control bits while the pdm channel is operating and transmitting audio. 0x0 r/w 00 both channels. 01 left channel. 10 right channel. 11 reserved. [1:0] pdm_en enable pdm output on pin pdmout. 0x0 r/w 00 pdm disabled. 01 pdm left signal in both pdm channels. 10 pdm right signal in both pdm channels. 11 pdm stereo. pdm pattern setting register address: 0x37, reset: 0x00, name: pdm_pattern table 91. bit descriptions for pdm_pattern bits bit name settings description reset access [7:0] pattern pdm pattern byte. the pdm pattern byte mu st not be changed while the pdm channel is operating and transmitting the pattern. 0x0 r/w mp0 function setting register address: 0x38, reset: 0x00, name: mode_mp0 table 92. bit descriptions for mode_mp0 bits bit name settings description reset access [7:5] reserved reserved. 0x0 r/w [4:0] mode_mp0_val sets the function of pin dac_sdata/mp0. 0x0 r/w 00000 serial input 0. 00001 mute adc0. 00010 mute adc1. 00011 mute adc2. 00100 mute adc3. 00101 mute adc0 and adc1. 00110 mute adc2 and adc3. 00111 mute all adcs.
adau1777 data sheet rev. 0 | page 90 of 108 bits bit name settings description reset access 01000 mute dac0. 01001 mute dac1. 01010 mute both dacs. 01011 a/b bank switch. 01110 enable compression. 01111 dsp bypass enable. 10000 push - button volume up. 10001 push - button volume down. mp1 function setting register address: 0x39, reset: 0x10, name: mode_mp1 table 93. bit descriptions for mode_mp1 bits bit name settings description reset access [7:5] reserved reserved. 0x0 r/w [4:0] mode_mp1_val sets the function of pin adc_sdata0/pdmout/mp1 . 0x10 r/w 00000 serial output 0. 00001 mute adc0. 00010 mute adc1. 00011 mute adc2. 00100 mute adc3. 00101 mute adc0 and adc1. 00110 mute adc2 and adc3. 00111 mute all adcs. 01000 mute dac0. 01001 mute dac1. 01010 mute both dacs. 01011 a/b bank switch. 01110 enable compression. 01111 dsp bypass enable. 10000 push - button volume up. 10001 push - button volume down. 10010 pdm modulator output.
data sheet adau1777 rev. 0 | page 91 of 108 mp2 function setting register address: 0x3a, reset: 0x00, name: mode_mp2 sets the function of pin bclk/mp2 10001: push-button volume down. 10000: push-button volume up. 01111: dsp bypass enable. ... 00010: mute adc1. 00001: mute adc0. 00000: bit clock. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :5 ] reserved [4:0] mode_mp2_val (r/w) table 94 . bit d escriptions for mode_mp2 bits bit name settings description reset access [7:5] reserved reserved. 0x0 r/w [4:0] mode_mp2_val sets the function of pin bclk/mp2 0x0 r/w 00000 bit clock. 00001 mute adc0. 00010 mute adc1. 00011 mute adc2. 00100 mute adc3. 00101 mute adc0 and adc1. 00110 mute adc2 and adc3. 00111 mute all adcs. 01000 mute dac0. 01001 mute dac1. 01010 mute both dacs. 01011 a/b bank switch. 01100 reserved. 01101 reserved. 01110 enable compression. 01111 dsp bypass enable. 10000 push - button volume up. 10001 push - button volume down. mp3 function setting register address: 0x3b, reset: 0x00, name: mode_mp3 sets the function of pin lrclk/mp3 10001: push-button volume down. 10000: push-button volume up. 01111: dsp bypass enable. ... 00010: mute adc1. 00001: mute adc0. 00000: left/right clock. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :5 ] reserved [4:0] mode_mp3_val (r/w) table 95 . bit d escriptions for mode_mp3 bits bit name settings description reset access [7:5] reserved reserved. 0x0 r/w
adau1777 data sheet rev. 0 | page 92 of 108 bits bit name settings description reset access [4:0] mode_mp3_val sets the function of pin lrclk/mp3 0x0 r/w 00000 left/right clock. 00001 mute adc0. 00010 mute adc1. 00011 mute adc2. 00100 mute adc3. 00101 mute adc0 and adc1. 00110 mute adc2 and adc3. 00111 mute all adcs. 01000 mute dac0. 01001 mute dac1. 01010 mute both dacs. 01011 a/b bank switch. 01100 reserved. 01101 reserved. 01110 enable compression. 01111 dsp bypass enable. 10000 push - button volume up. 10001 push - button volume down. mp4 function setting register address: 0x3c, reset: 0x00, name: mode_mp4 sets the function of pin dmic0_1/mp4 10001: push-button volume down. 10000: push-button volume up. 01111: dsp bypass enable. ... 00010: mute adc1. 00001: mute adc0. 00000: 0/digital microphone input channel 1. digital microphone input channel 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7 :5 ] reserved [4:0] mode_mp4_val (r/w) table 96 . bit d escriptions for mode_mp4 bits bit name settings description reset access [7:5] reserved reserved. 0x0 r/w [4:0] mode_mp4_val sets the function of pin dmic0_1/mp4 0x0 r/w 00000 digital microphone input channel 0/digital microphone input channel 1. 00001 mute adc0. 00010 mute adc1. 00011 mute adc2. 00100 mute adc3. 00101 mute adc0 and adc1. 00110 mute adc2 and adc3. 00111 mute all adcs. 01000 mute dac0.
data sheet adau1777 rev. 0 | page 93 of 108 bits bit name settings description reset access 01001 mute dac1. 01010 mute both dacs. 01011 a/b bank switch. 01100 reserved. 01101 reserved. 01110 enable compression. 01111 dsp bypass enable. 10000 push - button volume up. 10001 push - button volume down. mp5 function setting register address: 0x3d, reset: 0x00, name: mode_mp5 table 97. bit descriptions for mode_mp5 bits bit name settings description reset access [7:5] reserved reserved. 0x0 r/w [4:0] mode_mp5_val sets the function of pin dmic2_3/mp5 . 0x0 r/w 00000 digital microphone input channel 2/digital microphone input channel 3. 00001 mute adc0. 00010 mute adc1. 00011 mute adc2. 00100 mute adc3. 00101 mute adc0 and adc1. 00110 mute adc2 and adc3. 00111 mute all adcs. 01000 mute dac0. 01001 mute dac1. 01010 mute both dacs. 01011 a/b bank switch. 01100 reserved. 01101 reserved. 01110 enable compression. 01111 dsp bypass enable. 10000 push - button volume up. 10001 push - button volume down.
adau1777 data sheet rev. 0 | page 94 of 108 mp6 function setting register address: 0x3e, reset: 0x11, name: mode_mp6 table 98. bit descriptions for mode_mp6 bits bit name settings description reset access [7:5] reserved reserved. 0x0 r/w [4:0] mode_mp6_val sets the function of pin adc_sdata1/clkout/mp6 . 0x11 r/w 00000 serial output 1. 00001 mute adc0. 00010 mute adc1. 00011 mute adc2. 00100 mute adc3. 00101 mute adc0 and adc1. 00110 mute adc2 and adc3. 00111 mute all adcs. 01000 mute dac0. 01001 mute dac1. 01010 mute both dacs. 01011 a/b bank switch. 01100 reserved. 01101 reserved. 01110 enable compression. 01111 dsp bypass enable. 10000 push - button volume up. 10001 push - button volume down. 10010 clock output. push - button volume settin gs register address: 0x3f, reset: 0x00, name: pb_vol_set this register must be written before bits pb_vol_conv_val are set to something other than the default value. otherwise, the p ush - button volume control is initialized to ?96 db.
data sheet adau1777 rev. 0 | page 95 of 108 table 99. bit descriptions for pb_vol_set bits bit name settings description reset access [7:3] pb_vol_init_val sets the initial volume of the push - button volume control. each increment of this register attenuates the level by 1.5 db, from 0 db to ?46.5 db. 0x0 r/w 00000 0.0 db. 00001 ?1.5 db. 11111 ?46.5 db. [2:0] hold sets the length of time that the button is held before the volume ramp begins. 0x0 r/w 000 150 ms. 001 300 ms. 010 450 ms. 011 600 ms. 100 900 ms. 101 1200 ms. push - button volume contro l assignment register address: 0x40, reset: 0x87, name: pb_vol_conv table 100 . bit descriptions for pb_vol_conv bits bit name settings description reset access [7:6] gainstep sets the gain step for each press of the volume control button . 0x2 r/w 00 0.375 db/press. 01 1.5 db/press. 10 3.0 db/press. 11 4.5 db/press. [5:3] rampspeed sets the speed in db/sec at which the volume control ramps when a button is held . 0x0 r/w 000 60 db/sec. 001 48 db/sec. 010 36 db/sec. 011 30 db/sec. 100 24 db/sec. 101 18 db/sec. 110 12 db/sec. 111 6 db/sec.
adau1777 data sheet rev. 0 | page 96 of 108 bits bit name settings description reset access [2:0] pb_vol_conv_val converters controlled by push - button volume. the push - button volume control is enabled when these bits are set to something other than the default setting (111). when set to 111, the push - button volume is disabled and the converter volumes are set by the adcx_volume and dacx_volume registers. 0x7 r/w 000 adc0 and adc1. 001 adc2 and adc3. 010 all adcs. 011 dac0 and dac1. 100 dac0. 101 dac1. 110 reserved. 111 none (default) . debounce modes register address: 0x41, reset: 0x05, name: debounce_mode table 101 . bit descriptions for debounce_mode bits bit name settings description reset access [7:3] reserved reserved. 0x0 r/w [2:0] debounce the debounce time setting for the mpx inputs . 0x5 r/w 000 debounce 300 s. 001 debounce 600 s. 010 debounce 900 s. 011 debounce 5 ms. 100 debounce 10 ms. 101 debounce 20 ms. 110 debounce 40 ms. 111 no debounce.
data sheet adau1777 rev. 0 | page 97 of 108 headphone line outpu t select register address: 0x43, reset: 0x0f, name: op_stage_ctrl table 102 . bit descriptions for op_stage_ctrl bits bit name settings description reset access [7:6] reserved reserved. 0x0 r/w 5 hp_en_r sets the right channel in line output or headphone mode . 0x0 r/w 0 right output in line output mode. 1 right output in headphone mode. 4 hp_en_l sets the left channel in line output or headphone mode 0x0 r/w 0 left output in line output mode. 1 left output in headphone output mode. [3:2] hp_pdn_r output stage power control. these bits p ower down the right output stage, regardless of whether the device is in line output or headphone mode. after enabling the headphone output, wait at least 6 ms before unmuting the headphone output by setting hp_mute_r in the op_stage_mutes register to 00. 0x3 r/w 00 hpoutrn/loutrn and hpoutrp/loutrp outputs enabled. 01 hpoutrn/loutrn enabled, hpoutrp/loutrp disabled. 10 hpoutrn/loutrn disabled, hpoutrp/loutrp enabled. 11 right output stages powered down. [1:0] hp_pdn_l output stage power control. these bits p ower down the left output stage, regardless of whether the device is in line output or headphone mode. after enabling the headphone output, wait at least 6 ms before unmuting the headphone output by setting hp_mute_l in the op_stage_mutes regis ter to 00. 0x3 r/w 00 hpoutln/loutln and hpoutlp/loutlp outputs enabled. 01 hpoutln/loutln enabled, hpoutlp/loutlp disabled. 10 hpoutln/loutln disabled, hpoutlp/loutlp enabled. 11 left output stages powered down. decimator power cont rol register address: 0x44, reset: 0x00, name: decim_pwr_modes the bits in this register enable clocks to the digital filters and the asrc decimator filters of the adcs. these bits must be enabled for all channels used in the design. to use the adcs, these sinc_x_en bits must be enabled along with the appropriate adc_x_en bits in the adc_control2 and adc_control3 registers. if the digital microphone inputs are used, the sinc_x_en bits can be set without setting adc_x_en.
adau1777 data sheet rev. 0 | page 98 of 108 table 103 . bit descriptions for decim_pwr_modes bits bit name settings description reset access 7 dec_3_en control power to the asrc3 decimator . 0x0 r/w 0 powered down. 1 powered up. 6 dec_2_en control power to the asrc2 decimator . 0x0 r/w 0 powered down. 1 powered up. 5 dec_1_en control power to the asrc1 decimator . 0x0 r/w 0 powered down. 1 powered up. 4 dec_0_en control power to the asrc0 decimator . 0x0 r/w 0 powered down. 1 powered up. 3 sinc_3_en adc3 filter power control . 0x0 r/w 0 powered down. 1 powered up. 2 sinc_2_en adc2 filter power control . 0x0 r/w 0 powered down. 1 powered up. 1 sinc_1_en adc1 filter power control . 0x0 r/w 0 powered down. 1 powered up. 0 sinc_0_en adc0 filter power control . 0x0 r/w 0 powered down. 1 powered up.
data sheet adau1777 rev. 0 | page 99 of 108 asrc interpolator an d dac modulator powe r control register address: 0x45, reset: 0x00, name: interp_pwr_modes table 104 . bit descriptions for interp_pwr_modes bits bit name settings description reset access [7:4] reserved reserved. 0x0 r/w 3 mod_1_en dac modulator 1 enable . 0x0 r/w 0 powered down. 1 powered up. 2 mod_0_en dac modulator 0 enable . 0x0 r/w 0 powered down. 1 powered up. 1 int_1_en asrc interpolator 1 enable . 0x0 r/w 0 powered down. 1 powered up. 0 int_0_en asrc interpolator 0 enable . 0x0 r/w 0 powered down. 1 powered up. analog bias control 0 register address: 0x46, reset: 0x00, name: bias_control0 table 105 . bit descriptions for bias_control0 bits bit name settings description reset access [7:6] hp_ibias headphone output bias current setting. higher bias currents result in higher performance. 0x0 r/w 00 normal operation (default) . 01 extreme power saving. 10 enhanced performance. 11 power saving.
adau1777 data sheet rev. 0 | page 100 of 108 bits bit name settings description reset access [5:4] afe_ibias01 analog front - end 0 and analog front - end 1 bias current setting. higher bias currents result in higher performance. 0x0 r/w 00 normal operation (default) . 01 extreme power saving. 10 enhanced performance. 11 power saving. [3:2] adc_ibias23 adc2 and adc3 bias current setting. higher bias currents result in higher performance. 0x0 r/w 00 normal operation (default) . 01 reserved. 10 enhanced performance. 11 power saving. [1:0] adc_ibias01 adc0 and adc1 bias current setting. higher bias currents result in higher performance. 0x0 r/w 00 normal operation (default) . 01 reserved. 10 enhanced performance. 11 power saving. analog bias control 1 register address: 0x47, reset: 0x00, name: bias_control1 table 106 . bit descriptions for bias_control1 bits bit name settings description reset access 7 reserved reserved. 0x0 r/w 6 cbias_dis central analog bias circuitry. higher bias currents result in higher performance. 0x0 r/w 0 powered up. 1 powered down. [5:4] afe_ibias23 analog front - end 2 and analog front - end 3 bias current setting. higher bias currents result in higher performance. 0x0 r/w 00 normal operation (default) . 01 extreme power saving. 10 enhanced performance. 11 power saving.
data sheet adau1777 rev. 0 | page 101 of 108 bits bit name settings description reset access [3:2] mic_ibias microphone input bias current setting. higher bias currents result in higher performance. 0x0 r/w 00 normal operation (default) . 01 extreme power saving. 10 enhanced performance. 11 power saving. [1:0] dac_ibias dac bias current setting. higher bias currents result in higher performance. 0x0 r/w 00 normal operation (default) . 01 power saving. 10 superior performance. 11 enhanced performance. digital pin pull - up control 0 register address: 0x48, reset: 0x7f, name: pad_control0 enable pull - up resistors for each digital pin. table 107 . bit descriptions for pad_control0 bits bit name settings description reset access 7 reserved reserved. 0x0 r/w 6 dmic2_3_pu pull - up disable . 0x1 r/w 0 pull - up enabled. 1 pull - up disabled. 5 dmic0_1_pu pull - up disable . 0x1 r/w 0 pull - up enabled. 1 pull - up disabled. 4 lrclk_pu pull - up disable . 0x1 r/w 0 pull - up enabled. 1 pull - up disabled. 3 bclk_pu pull - up disable . 0x1 r/w 0 pull - up enabled. 1 pull - up disabled.
adau1777 data sheet rev. 0 | page 102 of 108 bits bit name settings description reset access 2 adc_sdata1_pu pull - up disable . 0x1 r/w 0 pull - up enabled. 1 pull - up disabled. 1 adc_sdata0_pu pull - up disable . 0x1 r/w 0 pull - up enabled. 1 pull - up disabled. 0 dac_sdata_pu pull - up disable . 0x1 r/w 0 pull - up enabled. 1 pull - up disabled. digital pin pull - up control 1 register address: 0x49, reset: 0x1f, name: pad_control1 enable pull - up resistors for each digital pin. table 108 . bit descriptions for pad_control1 bits bit name settings description reset access [7:5] reserved reserved. 0x0 r/w 4 selfboot_pu pull - up disable . 0x1 r/w 0 pull - up enabled. 1 pull - up disabled. 3 scl_pu pull - up disable . 0x1 r/w 0 pull - up enabled. 1 pull - up disabled. 2 sda_pu pull - up disable . 0x1 r/w 0 pull - up enabled. 1 pull - up disabled. 1 addr1_pu pull - up disable . 0x1 r/w 0 pull - up enabled. 1 pull - up disabled. 0 addr0_pu pull - up disable . 0x1 r/w 0 pull - up enabled. 1 pull - up disabled.
data sheet adau1777 rev. 0 | page 103 of 108 digital pin pull - down control 0 register address: 0x4a, reset: 0x00, name: pad_control2 enable pull - down resistors for each digital pin. table 109 . bit descriptions for pad_control2 bits bit name settings description reset access 7 reserved reserved. 0x0 r/w 6 dmic2_3_pd pull - down enable . 0x0 r/w 0 pull - down disabled. 1 pull - down enabled. 5 dmic0_1_pd pull - down enable . 0x0 r/w 0 pull - down disabled. 1 pull - down enabled. 4 lrclk_pd pull - down enable . 0x0 r/w 0 pull - down disabled. 1 pull - down enabled. 3 bclk_pd pull - down enable . 0x0 r/w 0 pull - down disabled. 1 pull - down enabled. 2 adc_sdata1_pd pull - down enable . 0x0 r/w 0 pull - down disabled. 1 pull - down enabled. 1 adc_sdata0_pd pull - down enable . 0x0 r/w 0 pull - down disabled. 1 pull - down enabled. 0 dac_sdata_pd pull - down enable . 0x0 r/w 0 pull - down disabled. 1 pull - down enabled. digital pin pull - down control 1 register address: 0x4b, reset: 0x00, name: pad_control3 enable pull - down resistors for each digital pin.
adau1777 data sheet rev. 0 | page 104 of 108 table 110 . bit descriptions for pad_control3 bits bit name settings description reset access [7:5] reserved reserved. 0x0 r/w 4 selfboot_pd pull - down enable . 0x0 r/w 0 pull - down disabled. 1 pull - down enabled. 3 scl_pd pull - down enable . 0x0 r/w 0 pull - down disabled. 1 pull - down enabled. 2 sda_pd pull - down enable . 0x0 r/w 0 pull - down disabled. 1 pull - down enabled. 1 addr1_pd pull - down enable . 0x0 r/w 0 pull - down disabled. 1 pull - down enabled. 0 addr0_pd pull - down enable . 0x0 r/w 0 pull - down disabled. 1 pull - down enabled. digital pin drive st rength control 0 register address: 0x4c, reset: 0x00, name: pad_control4 table 111 . bit descriptions for pad_control4 bits bit name settings description reset access 7 reserved reserved. 0x0 r/w 6 reserved reserved. 0x0 r/w 5 reserved reserved. 0x0 r/w
data sheet adau1777 rev. 0 | page 105 of 108 bits bit name settings description reset access 4 lrclk_drv drive strength control . 0x0 r/w 0 low drive strength. 1 high drive strength. 3 bclk_drv drive strength control . 0x0 r/w 0 low drive strength. 1 high drive strength. 2 adc_sdata1_drv drive strength control . 0x0 r/w 0 low drive strength. 1 high drive strength. 1 adc_sdata0_drv drive strength control . 0x0 r/w 0 low drive strength. 1 high drive strength. 0 reserved reserved. 0x0 r/w digital pin drive st rength control 1 register address: 0x4d, reset: 0x00, name: pad_control5 table 112 . bit descriptions for pad_control5 bits bit name settings description reset access [7:5] reserved reserved. 0x0 r/w 4 reserved reserved. 0x0 r/w 3 scl_drv drive strength control . 0x0 r/w 0 low drive strength. 1 high drive strength. 2 sda_drv drive strength control . 0x0 r/w 0 low drive strength. 1 high drive strength. 1 reserved reserved. 0x0 r/w 0 reserved reserved. 0x0 r/w fast rate control register address: 0x4e, reset: 0x00, name: fast_rate
adau1777 data sheet rev. 0 | page 106 of 108 table 113 . bit descriptions for fast_rate bits bit name settings description reset access [7:3] reserved reserved. 0x0 r/w [2:0] rate_div set fast rate division factor. this factor is used to divide the internal master clock (6.144 mhz) when core_fs = 11. do not change t his setting while the core is running. core_run must be set to 0 for this setting to be updated. 0x0 r/w 000 divide by 8 (768 khz) . 001 divide by 9 (683 khz) . 010 divide by 10 (614 khz) . 011 divide by 12 (512 khz) . 100 divide by 14 (439 khz) . 101 divide by 16 (384 khz) . dac interpolation co ntrol register address: 0x4f, reset: 0x00, name: dac_control0 the lowest interpolator latency is achieved with a zero - order hold (zoh) selection. zoh can be used for both 768 khz and 192 khz data. for 96 khz data, use the linear interpolation to attain the lowest latency. table 114 . bit descriptions for dac_control0 bits bit name settings description reset access [7:6] dac_rate sample rate for dac. 0x0 r/w 00 core f s . 01 core f s /4. 10 core f s /8. 11 reserved. [5:3] dac_intp interpolation mode for the dac . 0x0 r/w 000 both dac0 and dac1 set to compensated interpolation. 001 dac0 set to zoh, dac1 set to compensated interpolation. 010 dac0 set to compensated interpolation, dac1 set to zoh. 011 both dac0 and dac1 set to zoh. 100 dac0 set to linear interpolation, dac1 set to compensated interpolation. 101 dac0 set to compensated interpolation, dac1 set to linear interpolation. 110 both dac0 and dac1 set to linear interpolation.
data sheet adau1777 rev. 0 | page 107 of 108 bits bit name settings description reset access [2:0] reserved reserved. 0x0 r/w volume control bypas s register address: 0x54, reset: 0x00, name: vol_bypass table 115 . bit descriptions for vol_bypass bits bit name settings description reset access [7:6] reserved reserved. 0x0 r/w 5 dac1vol_by dac1 volume control bypass . 0x0 r/w 0 volume control enabled. 1 bypassed. 4 dac0vol_by dac0 volume control bypass . 0x0 r/w 0 volume control enabled. 1 bypassed. 3 adc3vol_by adc3 volume control bypass . 0x0 r/w 0 volume control enabled. 1 bypassed. 2 adc2vol_by adc2 volume control bypass . 0x0 r/w 0 volume control enabled. 1 bypassed. 1 adc1vol_by adc1 volume control bypass . 0x0 r/w 0 volume control enabled. 1 bypassed. 0 adc0vol_by adc0 volume control bypass . 0x0 r/w 0 volume control enabled. 1 bypassed.
adau1777 data sheet rev. 0 | page 108 of 108 outline dimensions a b c d e f 3.805 3.765 3.725 3.235 3.195 3.155 1 2 3 45 6 7 bottom view (ball side up) top view (ball side down) ball a1 identifier 0.660 0.600 0.540 0.390 0.360 0.330 side view 0.270 0.240 0.210 0.360 0.320 0.280 coplanarity 0.05 seating plane 08-07-2014-a pkg-004601 2.50 ref 3.00 ref 0.50 bsc figure 79. 36-ball wafer level chip scale package [wlcsp] (cb-36-4) dimension shown in millimeters ordering guide model 1 temperature range package description package option adau1777bcbzrl ?40c to +85c 36-ball wafer level chip scale package [wlcsp], 13 tape and reel cb-36-4 EVAL-ADAU1777Z evaluation board 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d14796-0-12/16(0)

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EVAL-ADAU1777Z 50AK1145	Analog Devices Inc	Eval Board, Audio Codec W/Processor; Silicon Manufacturer:Analog Devices; Silicon Core Number:Adau1777; Kit Application Type:Audio; Application Sub Type:Audio Codec; Product Range:- Rohs Compliant: Yes \|Analog Devices EVAL-ADAU1777Z	1: USD281.49	0

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EVAL-ADAU1777Z 584-EVAL-ADAU1777Z	Analog Devices Inc	Audio IC Development Tools Eval Board for ADAU1772	1: USD270.97	18

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EVAL-ADAU1777Z	Analog Devices Inc	Eval Board for ADAU1772	1: USD281.68	115

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EVAL-ADAU1777Z EVAL-ADAU1777Z	Analog Devices Inc	SEMICONDUCTOR DESIGNER KIT	1: USD270.41	0

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