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this is information on a product in full production. february 2016 docid027226 rev 1 1/218 stm32l471xx ultra-low-power arm ? cortex ? -m4 32-bit mcu+fpu, 100dmips, up to 1mb flash, 12 8 kb sram, analog, audio datasheet - production data features ? ultra-low-power with flexpowercontrol ? 1.71 v to 3.6 v power supply ? -40 c to 85/105/125 c temperature range ? 300 na in v bat mode: supply for rtc and 32x32-bit backup registers ? 30 na shutdown mode (5 wakeup pins) ? 120 na standby mode (5 wakeup pins) ? 420 na standby mode with rtc ? 1.1 a stop 2 mode, 1.4 a stop 2 with rtc ? 100 a/mhz run mode ? batch acquisition mode (bam) ? 4 s wakeup from stop mode ? brown out reset (bor) in all modes except shutdown ? interconnect matrix ? core: arm ? 32-bit cortex ? -m4 cpu with fpu, adaptive real-time accelerator (art accelerator?) allowing 0- wait-state execution from flash memory, frequency up to 80 mhz, mpu, 100dmips/1.25dmips/mhz (dhrystone 2.1), and dsp instructions ? clock sources ? 4 to 48 mhz crystal oscillator ? 32 khz crystal oscillator for rtc (lse) ? internal 16 mhz factory-trimmed rc (1%) ? internal low-power 32 khz rc (5%) ? internal multispeed 100 khz to 48 mhz oscillator, auto-trimmed by lse (better than 0.25 % accuracy) ? 3 plls for system clock, audio, adc ? rtc with hw calendar, alarms and calibration ? up to 24 capacitive sensing channels: support touchkey, linear and ro tary touch sensors ? 16x timers: 2 x 16-bit advanced motor-control, 2 x 32-bit and 5 x 16-bit general purpose, 2x 16-bit basic, 2x low-power 16-bit timers (available in stop mode), 2x watchdogs, systick timer ? up to 114 fast i/os, most 5 v-tolerant, up to 14 i/os with independent supply down to 1.08 v ? memories ? up to 1 mb flash, 2 banks read-while- write, proprietary code readout protection ? up to 128 kb of sram including 32 kb with hardware parity check ? external memory interface for static memories supporting sram, psram, nor and nand memories ? quad spi memory interface ? 4x digital filters for sigma delta modulator ? rich analog peripherals (independent supply) ? 3 12-bit adc 5 msps, up to 16-bit with hardware oversampling, 200 a/msps ? 2x 12-bit dac, low-power sample and hold ? 2x operational amplifiers with built-in pga ? 2x ultra-low-power comparators ? 17x communication interfaces ? 2x sais (serial audio interface) ?3x i2c fm+(1 mbi t/s), smbus/pmbus ? 6x usarts (iso 7816, lin, irda, modem) ? 3x spis (4x spis with the quad spi) ? can (2.0b active) and sdmmc interface ? swpmi single wire pr otocol master i/f ? 14-channel dma controller ? true random number generator ? crc calculation unit, 96-bit unique id ? development support: serial wire debug (swd), jtag, embedded trace macrocell? table 1. device summary reference part number stm32l471xx stm32l471rg, stm32l471vg, STM32L471QG, stm32l471zg, stm32l471re, stm32l471ve, stm32l471qe, stm32l471ze (7 7) lqfp144 (20 20) lqfp100 (14 x 14) lqfp64 (10 x 10) ufbga132 www.st.com
contents stm32l471xx 2/218 docid027226 rev 1 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 arm ? cortex ? -m4 core with fpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . . 16 3.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 19 3.9 power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9.5 reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.9.6 vbat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.10 interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.11 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.12 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.13 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.14 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.14.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 36 3.14.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . 36 3.15 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.15.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.15.2 internal voltage reference (vrefint) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.15.3 vbat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.16 digital to analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 docid027226 rev 1 3/218 stm32l471xx contents 5 3.17 voltage reference buffer (vrefbuf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.18 comparators (comp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.19 operational amplifier (opamp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.20 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.21 digital filter for sigma-delta modulators (dfsdm) . . . . . . . . . . . . . . . . . . 41 3.22 random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.23 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.23.1 advanced-control timer (tim1, tim8) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.23.2 general-purpose timers (tim2, tim3, tim4, tim5, tim15, tim16, tim17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.23.3 basic timers (tim6 and tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.23.4 low-power timer (lptim1 and lptim2) . . . . . . . . . . . . . . . . . . . . . . . . 44 3.23.5 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.23.6 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.23.7 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.24 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 46 3.25 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.26 universal synchronous/asynchronous re ceiver transmitter (usart) . . . 48 3.27 low-power universal asynchronous rece iver transmitter (lpuart) . . . . 49 3.28 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.29 serial audio interfaces (sai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.30 single wire protocol master interface (swpmi) . . . . . . . . . . . . . . . . . . . . 51 3.31 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.32 secure digital input/output and multimediacards interface (sdmmc) . . . 52 3.33 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . . 52 3.34 quad spi memory interface (quadspi) . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.35 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.35.1 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.35.2 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 contents stm32l471xx 4/218 docid027226 rev 1 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 96 6.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . . 96 6.3.4 embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.6 wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.3.8 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.10 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.3.16 analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.3.17 analog-to-digital converter characteristi cs . . . . . . . . . . . . . . . . . . . . . 145 6.3.18 digital-to-analog converter characteristi cs . . . . . . . . . . . . . . . . . . . . . 158 6.3.19 voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 162 6.3.20 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.3.21 operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 165 6.3.22 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.3.23 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.3.24 dfsdm characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.3.25 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.3.26 communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 172 docid027226 rev 1 5/218 stm32l471xx contents 5 6.3.27 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 7.1 lqfp144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 7.2 ufbga132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 7.3 lqfp100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 7.4 lqfp64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 7.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 7.5.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 7.5.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 213 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 list of tables stm32l471xx 6/218 docid027226 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32l471xx family device features and periphera l counts . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 17 table 4. stm32l471 modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 table 5. functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 6. stm32l471xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 7. dma implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 8. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 9. internal voltage reference calibrati on values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 10. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 11. i2c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 12. stm32l4x1 usart/uart/lpuart features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 13. sai implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 14. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 15. stm32l471xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) . . . . . . . . . . . . . . . . . . . . . 71 table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) . . . . . . . . . . . . . . . . . . . . . 78 table 18. stm32l471xx memory map and peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 19. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 20. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 21. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 22. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 23. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 24. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 25. embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 table 26. current consumption in run and lo w-power run modes, code with data processing running from flash, art enable (cache on prefetch off) . . . . . . . . . . . . . . . . . . . . . . 101 table 27. current consumption in run and low-power run modes, code with data processing running from flash, art disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 28. current consumption in run and lo w-power run modes, code with data processing running from sram1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 29. typical current consumption in run a nd low-power run modes, with different codes running from flash, art enable (cache on prefetch off) . . . . . . . . . . . . . . . . . . . . . . 104 table 30. typical current consumption in run a nd low-power run modes, with different codes running from flash, art disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 31. typical current consumption in run a nd low-power run modes, with different codes running from sram1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 32. current consumption in sleep and low-power sleep modes, flash on . . . . . . . . . . . . . 106 table 33. current consumption in low-power sleep modes, flash in power-down . . . . . . . . . . . . . 107 table 34. current consumption in stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 35. current consumption in stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 36. current consumption in stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 37. current consumption in standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 38. current consumption in shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 39. current consumption in vbat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 40. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 41. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 docid027226 rev 1 7/218 stm32l471xx list of tables 8 table 42. regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 43. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 44. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 45. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 46. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 47. hsi16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 48. msi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 table 49. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 50. pll, pllsai1, pllsai2 characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 51. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 52. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 53. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 54. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 55. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 table 56. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 57. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 58. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 59. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 60. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 61. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 62. analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 63. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 64. maximum adc rain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 65. adc accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 66. adc accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 67. adc accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 68. adc accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 69. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 70. dac accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 71. vrefbuf characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 72. comp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 73. opamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 74. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 75. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 76. v bat charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 77. dfsdm characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 78. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 79. iwdg min/max timeout period at 32 khz (lsi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 80. wwdg min/max timeout value at 80 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 81. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 82. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 83. quad spi characteristics in sdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 84. quadspi characteristics in ddr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 85. sai characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 86. sd / mmc dynamic characteristics, vdd=2.7 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 87. emmc dynamic characteristics, vdd = 1.71 v to 1.9 v . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 88. asynchronous non-multiplexed sram/psram/nor read timings . . . . . . . . . . . . . . . . . 185 table 89. asynchronous non-multiplexed sram/psram /nor read-nwait timings . . . . . . . . . . . 185 table 90. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . 186 table 91. asynchronous non-multiplexed sram/psram /nor write-nwait timings. . . . . . . . . . . 187 table 92. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 93. asynchronous multiplexed psram/nor read-nwai t timings . . . . . . . . . . . . . . . . . . . . 188 list of tables stm32l471xx 8/218 docid027226 rev 1 table 94. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 95. asynchronous multiplexed psram/nor write-nwai t timings . . . . . . . . . . . . . . . . . . . . 190 table 96. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 97. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 98. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 195 table 99. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 100. switching characteristics for nand flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 101. switching characteristics for nand flash write cycl es. . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 102. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 103. ufbga132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 104. ufbga132 recommended pcb design rules (0.5 mm pitch bga) . . . . . . . . . . . . . . . . . 205 table 105. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 106. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 107. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 108. stm32l471xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 109. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 docid027226 rev 1 9/218 stm32l471xx list of figures 10 list of figures figure 1. stm32l471xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 2. power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 3. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 4. voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 5. stm32l471zx lqfp144 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 6. stm32l471qx ufbga132 ballout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 7. stm32l471vx lqfp100 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 8. stm32l471rx lqfp64 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 9. stm32l471 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 10. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 11. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 12. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 13. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 14. vrefint versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 15. high-speed external clock source ac timing diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 16. low-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 17. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 figure 18. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 19. hsi16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 20. typical current consumption versus msi frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 21. i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 22. i/o ac characteristics definition (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 23. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 24. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 25. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 26. 12-bit buffered / non-buffered dac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 27. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 28. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 29. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 75 figure 30. quad spi timing diagram - sdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 31. quad spi timing diagram - ddr mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 32. sai master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 figure 33. sai slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 34. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 35. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 figure 36. asynchronous non-multip lexed sram/psram/nor read waveforms . . . . . . . . . . . . . . 184 figure 37. asynchronous non-multip lexed sram/psram/nor write wavefo rms . . . . . . . . . . . . . . 186 figure 38. asynchronous multiplexed psram/nor read wavefo rms. . . . . . . . . . . . . . . . . . . . . . . . 187 figure 39. asynchronous multiplexed psram/nor write wave forms . . . . . . . . . . . . . . . . . . . . . . . 189 figure 40. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 figure 41. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 figure 42. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 43. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 44. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 figure 45. nand controller waveforms for wr ite access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 figure 46. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 198 figure 47. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 199 figure 48. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 200 list of figures stm32l471xx 10/218 docid027226 rev 1 figure 49. lqfp144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 50. lqfp144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 51. ufbga132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 52. ufbga132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 53. ufbga132 marking (package top vi ew) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 54. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 207 figure 55. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 56. lqfp100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 figure 57. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 210 figure 58. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 59. lqfp64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 60. lqfp64 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 docid027226 rev 1 11/218 stm32l471xx introduction 55 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the stm32l471xx microcontrollers. this document should be read in conjun ction with the stm32l4x1 reference manual (rm0392). the reference manual is available from the stmicroelectronics website www.st.com . for information on the arm ? cortex ? -m4 core, please refer to the cortex ? -m4 technical reference manual, available from the www.arm.com website. description stm32l471xx 12/218 docid027226 rev 1 2 description the stm32l471xx devices are the ultra-low- power microcontrollers based on the high- performance arm ? cortex ? -m4 32-bit risc core operating at a frequency of up to 80 mhz. the cortex-m4 core features a floating point un it (fpu) single precision which supports all arm single-precision data-processing instructions and data types. it also implements a full set of dsp instructions and a memory protec tion unit (mpu) which enhances application security. the stm32l471xx devices embed high-speed memories (flash memory up to 1 mbyte, up to 128 kbyte of sram), a flexible external memory controller (fsmc) for static memories (for devices with packages of 100 pins and more), a quad spi flash memories interface (available on all packages) and an extens ive range of enhanced i/os and peripherals connected to two apb buses, two ahb bus es and a 32-bit multi-ahb bus matrix. the stm32l471xx devices embed several pr otection mechanisms for embedded flash memory and sram: readout protection, writ e protection, proprietary code readout protection and firewall. the devices offer up to three fast 12-bit adcs (5 msps), two comparators, two operational amplifiers, two dac channels, an internal vo ltage reference buffer, a low-power rtc, two general-purpose 32-bit timer, two 16-bit pw m timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. the devices support four digital filters for external sigma delta modulators (dfsdm). in addition, up to 24 capacitive sensing channels are available. they also feature standard and advanced communication interfaces. ? three i2cs ? three spis ? three usarts, two uarts and one low-power uart. ? two sais (serial audio interfaces) ? one sdmmc ? one can ? one swpmi (single wire protocol master interface) the stm32l471xx operates in the -40 to +85 c (+105 c junction), -40 to +105 c (+125 c junction) and -40 to +125 c (+130 c junction) temperature ranges from a 1.71 to 3.6 v power supply. a comprehensive set of power-saving modes allows the design of low- power applications. some independent power supplies are supported: analog independent supply input for adc, dac, opamps and comparators, and up to 14 i/os can be supplied independently down to 1.08v . a vbat input allows to backup the rtc and backup registers. the stm32l471xx family offers four packages from 64-pin to 144-pin packages. docid027226 rev 1 13/218 stm32l471xx description 55 table 2. stm32l471xx family device features and peripheral counts peripheral stm32l471zx stm32l471qx stm32l471vx stm32l471rx flash memory 512kb 1mb 512kb 1mb 512kb 1mb 512kb 1mb sram 128kb external memory controller for static memories yes yes yes (1) no quad spi yes timers advanced control 2 (16-bit) general purpose 5 (16-bit) 2 (32-bit) basic 2 (16-bit) low -power 2 (16-bit) systick timer 1 watchdog timers (independent, window) 2 comm. interfaces spi 3 i 2 c3 usart uart lpuart 3 2 1 sai 2 can 1 sdmmc yes swpmi yes digital filters for sigma-delta modulators yes (4 filters) number of channels 8 rtc yes tamper pins 3 2 random generator yes gpios wakeup pins nb of i/os down to 1.08 v 114 5 14 109 5 14 82 5 0 51 4 0 capacitive sensing number of channels 24 24 21 12 12-bit adcs number of channels 3 24 3 19 3 16 3 16 12-bit dac channels 2 internal voltage reference buffer yes no analog comparator 2 operational amplifiers 2 max. cpu frequency 80 mhz operating voltage 1.71 to 3.6 v description stm32l471xx 14/218 docid027226 rev 1 operating temperature ambient operating temperature: -40 to 85 c / -40 to 105 c / -40 to 125 c junction temperature: -40 to 105 c / -40 to 125 c / -40 to 130 c packages lqfp144 ufbga132 lqfp100 lqfp64 1. for the lqfp100 package, only fmc bank1 is avai lable. bank1 can only support a multiplexed nor/psram memory using the ne1 chip select. table 2. stm32l471xx family device features and peripheral counts (continued) peripheral stm32l471zx stm32l471qx stm32l471vx stm32l471rx docid027226 rev 1 15/218 stm32l471xx description 55 figure 1. stm32l471xx block diagram note: af: alternate function on i/o pins. 0 6 y 9 ) o d v k x s w r 0 % ) o h [ l e o h v w d w l f p h p r u \ f r q w u r o o h u ) 6 0 & |