cystech electronics corp. spec. no. : c138f3 issued date : 2015.08.31 revised date : page no. : 1/9 MTE30N20F3 cystek product specification n -channel enhancement mode power mosfet MTE30N20F3 bv dss 200v i d @v gs =10v, t c =25 c 50a 28.6m r dson(typ) v gs =10v, i d =17a features ? low gate charge ? simple drive requirement ? pb-free lead plating package symbol outline to-263 MTE30N20F3 g d s g gate d drain s source ordering information device package shipping MTE30N20F3-0-t7-s to-263 (pb-free lead plating and rohs compliant package) 800 pcs / tape & reel environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t7 : 800 pcs / tape & reel, 13? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c138f3 issued date : 2015.08.31 revised date : page no. : 2/9 MTE30N20F3 cystek product specification absolute maximum ratings (t c =25c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds 200 gate-source voltage v gs 20 v continuous drain current @ t c =25 c, v gs =10v 50 continuous drain current @ t c =100 c, v gs =10v i d 35 continuous drain current @ t a =25 c, v gs =10v (note 2) 4.8 continuous drain current @ t a =70 c, v gs =10v (note 2) i dsm 3.8 pulsed drain current (note 3) i dm 200 avalanche current (note 3) i as 16 a avalanche energy @ l=2mh, i d =16a, v dd =50v (note 2) e as 256 repetitive avalanche energy@ l=0.1mh (note 3) e ar 25 mj power dissipation @t c =25 (note 1) 250 power dissipation @t c =100 (note 1) p d 125 power dissipation @t a =25 (note 2) 2 power dissipation @t a =70 (note 2) p dsm 1.3 w operating junction and storage temperature range tj, tstg -55~+175 c *100% uis tested at condition of l=2mh, i as =8a, vdd=50v. thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 0.6 thermal resistance, junction-to-ambient, max (note 2) r th,j-a 62 c/w note : 1 . the power dissipation p d is based on t j(max) =175 c, using junction-to-case thermal resistance, and is more useful in setting the upper di ssipation limit for cases where additional heatsinking is used. 2 . the value of r ja is measured with the device mounted on 1 in 2 fr-4 board with 2 oz. copper, in a still air environment with t a =25 c. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c. the value in any given application depends on the user?s specific board design, and the maximum temperature of 175 c may be used if the pcb allows it. 3 . repetitive rating, pulse width limited by junction temperature t j(max) =175 c. ratings are based on low frequency and low duty cycles to keep initial t j =25 c. 4. the static characteristics are obtained using <300 s pulses, duty cycle 0.5% maximum. 5 . the r ja is the sum of thermal resistance from junction to case r jc and case to ambient.
cystech electronics corp. spec. no. : c138f3 issued date : 2015.08.31 revised date : page no. : 3/9 MTE30N20F3 cystek product specification characteristics (tc=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 200 - - v v gs =0v, i d =250 a bv dss / tj - 0.18 - v/ c reference to i d =250 a v gs(th) 2 - 4 v v ds =v gs , i d =250 a i gss - - 100 na v gs = 20v, v ds =0v - - 1 v ds =200v, v gs =0v i dss - - 25 a v ds =160v, v gs =0v, t j =125 c r ds(on) *1 - 28.6 36 m v gs =10v, i d =17a g fs *1 - 24.5 - s v ds =15v, i d =10a dynamic qg *1, 2 - 71.1 - qgs *1, 2 - 12.4 - qgd *1, 2 - 31.2 - nc v ds =160v, i d =39a, v gs =10v t d(on) *1, 2 - 28.4 - tr *1, 2 - 60 - t d(off) *1, 2 - 74 - t f *1, 2 - 100 - ns v ds =100v, i d =37a, v gs =10v, r g =5.6 ciss - 3197 - coss - 335 - crss - 116 - pf v gs =0v, v ds =25v, f=1mhz rg - 1.8 - f=1mhz source-drain diode i s *1 - - 50 i sm *3 - - 200 a v sd *1 - 0.8 1.2 v i f =25a, v gs =0v trr - 78 - ns qrr - 300 - nc i f =20a, di f /dt=100a/ s note : *1.pulse test : pulse width 300 s, duty cycle 2% *2.independent of operating temperature *3.pulse width limited by maximum junction temperature.
cystech electronics corp. spec. no. : c138f3 issued date : 2015.08.31 revised date : page no. : 4/9 MTE30N20F3 cystek product specification typical characteristics typical output characteristics 0 20 40 60 80 100 0246810 v ds , drain-source voltage(v) i d , drain current(a) 10v,9v,8v,7v v gs =4.5v 5.5v 6v 5v brekdown voltage vs junction temperature 0.4 0.6 0.8 1.0 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 10 100 1000 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =10v v gs =4.5v v gs =7v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 04812162 i dr , reverse drain current(a) v sd , source-drain voltage(v) 0 tj=25c tj=150c static drain-source on-state resistance vs gate-source voltage 0 20 40 60 80 100 120 140 160 180 200 024681 0 drain-source on-state resistance vs junction tempearture 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =17a r ds( on) @tj=25c : 28.6m typ. v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =17a
cystech electronics corp. spec. no. : c138f3 issued date : 2015.08.31 revised date : page no. : 5/9 MTE30N20F3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 10000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 i d , drain current(a) g fs , forward transfer admittance(s) pulsed ta=25c v ds =10v v ds =15v gate charge characteristics 0 2 4 6 8 10 0 1020304050607080 total gate charge---qg(nc) v gs , gate-source voltage(v) v ds =160v i d =39a v ds =40v maximum safe operating area 0.1 1 10 100 1000 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) dc 10ms 1m 100 s 10 s r ds( on) limit t c =25c, tj=175c, v gs =10v,r jc =0.6c/w, single pulse maximum drain current vs case temperature 0 10 20 30 40 50 60 25 50 75 100 125 150 175 200 t c , case temperature(c) i d , maximum drain current(a) v gs =10v, r jc =0.6c/w
cystech electronics corp. spec. no. : c138f3 issued date : 2015.08.31 revised date : page no. : 6/9 MTE30N20F3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 10 20 30 40 50 60 70 80 90 100 0246810 v gs , gate-source voltage(v) i d , drain current (a) v ds =10v single pulse maximum power dissipation 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0.0001 0.001 0.01 0.1 1 10 pulse width(s) peak transient power (w) t j(max) =175c t c =25c r jc =0.6c/w transient thermal response curves 0.01 0.1 1 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r jc (t) 4.r jc =0.6 c/w
cystech electronics corp. spec. no. : c138f3 issued date : 2015.08.31 revised date : page no. : 7/9 MTE30N20F3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c138f3 issued date : 2015.08.31 revised date : page no. : 8/9 MTE30N20F3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak 10-30 seconds 20-40 seconds temperature(tp) ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c138f3 issued date : 2015.08.31 revised date : page no. : 9/9 MTE30N20F3 cystek product specification to-263 dimension *:typical style : pin 1.gate 2.drain 3.source 3-lead plastic surface mounted package cystek package code : f3 marking : e30 n20 device name date code millimeters inches millimeters inches dim min. max. min. max. dim min. max. min. max. a 4.470 4.670 0.176 0.184 e 8.500 8.900 0.335 0.350 a1 0.000 0.150 0.000 0.006 e *2.540 *0.100 b 1.170 1.370 0.046 0.054 e1 4.980 5.180 0.196 0.204 b 0.710 0.910 0.028 0.036 l 15.050 15.450 0.593 0.608 b1 1.170 1.370 0.046 0.054 l1 5.080 5.480 0.200 0.216 c 0.310 0.530 0.012 0.021 l2 2.340 2.740 0.092 0.108 c1 1.170 1.370 0.046 0.054 l3 1.300 1.700 0.051 0.067 d 10.010 10.310 0.394 0.406 v 5.600 ref 0.220 ref notes : 1.controlling dimension : millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material : ? lead : pure tin plated. ? mold compound : epoxy resin family, flammability solid burning class:ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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