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| ? semiconductor components industries, llc, 2014 august, 2014 ? rev. 5 1 publication order number: MC74LVXT8051/d MC74LVXT8051 analog multiplexer/ demultiplexer high?performance silicon?gate cmos the MC74LVXT8051 utilizes silicon?gate cmos technology to achieve fast propagation delays, low on resistances, and low off leakage currents. this analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from v cc to gnd). the lvxt8051 is similar in pinout to the high?speed hc4051a and the metal?gate mc14051b. the channel?select inputs determine which one of the analog inputs/outputs is to be connected by means of an analog switch to the common output/input. when the enable pin is high, all analog switches are turned off. the channel?select and enable inputs are compatible with ttl?type input thresholds. the input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic?level translator from 3.0 v cmos logic to 5.0v cmos logic or from 1.8v cmos logic to 3.0 v cmos logic while operating at the higher?voltage power supply. the MC74LVXT8051 input structure provides protection when voltages up to 7.0 v are applied, regardless of the supply voltage. this allows the MC74LVXT8051 to be used to interface 5.0 v circuits to 3.0 v circuits. this device has been designed so that the on resistance (r on ) is more linear over input voltage than r on of metal?gate cmos analog switches. features ? fast switching and propagation speeds ? low crosstalk between switches ? diode protection on all inputs/outputs ? analog power supply range (v cc ? gnd) = 2.0 to 6.0 v ? digital (control) power supply range (v cc ? gnd) = 2.0 to 6.0 v ? improved linearity and lower on resistance than metal?gate counterparts ? low noise ? in compliance with the requirements of jedec standard no. 7a ? these devices are pb?free and are rohs compliant http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information marking diagrams tssop?16 dt suffix case 948f soic?16 d suffix case 751b lvxt8051g awlyww 1 16 1 16 lvxt8051 = specific device code a = assembly location wl, l = wafer lot y = year ww, w = work week g or = pb?free package (note: microdot may be in either location) lvxt 8051 alyw tssop?16 soic?16 pin assignment 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 x2 x1 x0 x3 a b c x4 x6 x x7 x5 enable nc gnd
MC74LVXT8051 http://onsemi.com 2 figure 1. logic diagram single?pole, 8?position plus common off x0 13 x1 14 x2 15 x3 12 x4 1 x5 5 x6 2 x7 4 a 11 b 10 c 9 enable 6 multiplexer/ demultiplexer x 3 analog inputs/ channel inputs pin 16 = v cc pin 8 = gnd common output/ input outputs select l l l l h h h h x l l h h l l h h x l h l h l h l h x function table ? MC74LVXT8051 control inputs on channels enable select cba x0 x1 x2 x3 x4 x5 x6 x7 none l l l l l l l l h x = don?t care maximum ratings symbol parameter value unit v cc positive dc supply voltage (referenced to gnd) ?0.5 to + 7.0 v v is analog input voltage ?0.5 to v cc + 0.5 v v in digital input voltage (referenced to gnd) ?0.5 to v cc + 0.5 v i dc current, into or out of any pin ?20 ma p d power dissipation in still air, soic package? tssop package? 500 450 mw t stg storage temperature range ?65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ?derating: soic package: ?7 mw/ c from 65 to 125 c tssop package: ?6.1 mw/ c from 65 to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open. MC74LVXT8051 http://onsemi.com 3 recommended operating conditions symbol parameter min max unit v cc positive dc supply voltage (referenced to gnd) 2.0 6.0 v v is analog input voltage 0.0 v cc v v in digital input voltage (referenced to gnd) gnd v cc v v io * static or dynamic voltage across switch 1.2 v t a operating temperature range, all package types ?55 +85 c t r , t f input rise/fall time (channel select or enable inputs) v cc = 3.3 v 0.3 v v cc = 5.0 v 0.5 v 0 0 100 20 ns/v functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. *for voltage drops across switch greater than 1.2 v (switch on), excessive v cc current may be drawn; i.e., the current out of the switch may contain both v cc and switch input components. the reliability of the device will be unaffected unless the maximum ratings are exceeded. dc characteristics ? digital section (voltages referenced to gnd) symbo l parameter condition v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c v ih minimum high?level input voltage, channel?select or enable inputs r on = per spec 3.0 4.5 5.5 1.2 2.0 2.0 1.2 2.0 2.0 1.2 2.0 2.0 v v il maximum low?level input voltage, channel?select or enable inputs r on = per spec 3.0 4.5 5.5 0.53 0.8 0.8 0.53 0.8 0.8 0.53 0.8 0.8 v i in maximum input leakage current, channel?select or enable inputs v in = v cc or gnd 5.5 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) channel select, enable and v is = v cc or gnd; v io = 0 v 5.5 4 40 160 a dc electrical characteristics analog section symbo l parameter test conditions v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c r on maximum ?on? resistance v in = v il or v ih v is = v cc to gnd |i s | 10.0 ma (figures 1, 2) 3.0 4.5 5.5 40 30 25 45 32 28 50 37 30 v in = v il or v ih v is = v cc or gnd (endpoints) |i s | 10.0 ma (figures 1, 2) 3.0 4.5 5.5 30 25 20 35 28 25 40 35 30 r on maximum difference in ?on? resistance between any two channels in the same package v in = v il or v ih v is = 1/2 (v cc ? gnd) |i s | 10.0 ma 3.0 4.5 5.5 15 8.0 8.0 20 12 12 25 15 15 i off maximum off?channel leakage current, any one channel v in = v il or v ih ; v io = v cc or gnd; switch off (figure 3) 5.5 0.1 0.5 1.0 a maximum off?channel leakage current, common channel v in = v il or v ih ; v io = v cc or gnd; switch off (figure 4) 5.5 0.2 2.0 4.0 i on maximum on?channel leakage current, channel?to?channel v in = v il or v ih ; switch?to?switch = v cc or gnd; (figure 5) 5.5 0.2 2.0 4.0 a MC74LVXT8051 http://onsemi.com 4 ac characteristics (c l = 50 pf, input t r = t f = 3 ns) symbo l parameter v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c t plh , t phl maximum propagation delay, channel?select to analog output (figure 9) 2.0 3.0 4.5 5.5 30 20 15 15 35 25 18 18 40 30 22 20 ns t plh , t phl maximum propagation delay, analog input to analog output (figure 10) 2.0 3.0 4.5 5.5 4.0 3.0 1.0 1.0 6.0 5.0 2.0 2.0 8.0 6.0 2.0 2.0 ns t plz , t phz maximum propagation delay, enable to analog output (figure 11) 2.0 3.0 4.5 5.5 30 20 15 15 35 25 18 18 40 30 22 20 ns t pzl , t pzh maximum propagation delay, enable to analog output (figure 11) 2.0 3.0 4.5 5.5 20 12 8.0 8.0 25 14 10 10 30 15 12 12 ns c in maximum input capacitance, channel?select or enable inputs 10 10 10 pf c i/o maximum capacitance analog i/o 35 35 35 pf (all switches off) common o/i 130 130 130 feedthrough 1.0 1.0 1.0 c pd power dissipation capacitance (figure 13)* typical @ 25 c, v cc = 5.0 v pf 45 * used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . additional application characteristics (gnd = 0 v) symbo l parameter condition v cc v limit* unit 25 c bw maximum on?channel bandwidth or minimum frequency response (figure 6) f in = 1mhz sine wave; adjust f in voltage to obtain 0dbm at v os ; increase f in frequency until db meter reads ?3db; r l = 50 , c l = 10pf 3.0 4.5 5.5 mhz 80 80 80 ? off?channel feedthrough isolation (figure 7) f in = sine wave; adjust f in voltage to obtain 0dbm at v is f in = 10khz, r l = 600 , c l = 50pf 3.0 4.5 5.5 ?50 ?50 ?50 db f in = 1.0mhz, r l = 50 , c l = 10pf 3.0 4.5 5.5 ?37 ?37 ?37 ? feedthrough noise. channel?select input to common i/o (figure 8) v in 1mhz square wave (t r = t f = 3ns); adjust r l at setup so that i s = 0a; enable = gnd r l = 600 , c l = 50pf 3.0 4.5 5.5 25 105 135 mv pp r l = 10k , c l = 10pf 3.0 4.5 5.5 35 145 190 ? crosstalk between any two switches (figure 12) f in = sine wave; adjust f in voltage to obtain 0dbm at v is f in = 10khz, r l = 600 , c l = 50pf 3.0 4.5 5.5 ?50 ?50 ?50 db f in = 1.0mhz, r l = 50 , c l = 10pf 3.0 4.5 5.5 ?60 ?60 ?60 thd total harmonic distortion (figure 14) f in = 1khz, r l = 10k , c l = 50pf thd = thd measured ? thd source v is = 2.0v pp sine wave v is = 4.0v pp sine wave v is = 5.0v pp sine wave 3.0 4.5 5.5 0.10 0.08 0.05 % *limits not tested. determined by design and verified by qualification. MC74LVXT8051 http://onsemi.com 5 figure 1a. typical on resistance, v cc = 3.0 v 25 20 15 10 5 0 1.0 2.0 3.0 4.0 v in , input voltage (volts) r on , on resistance (ohms) 85 c -55 c 125 c 0 25 c 40 35 30 figure 1b. typical on resistance, v cc = 4.5 v figure 1c. typical on resistance, v cc = 5.5 v 25 20 5 0 1.0 2.0 4.0 3.0 5.0 v in , input voltage (volts) r on , on resistance (ohms) 85 c -55 c 125 c 0 25 c 5 0 1.0 2.0 3.0 4.0 5.0 6.0 v in , input voltage (volts) r on , on resistance (ohms) 85 c -55 c 125 c 0 25 c 10 15 30 10 15 20 25 figure 2. on resistance test set?up plotter mini computer programmable power supply dc analyzer v cc device under test + - gnd analog in common out gnd MC74LVXT8051 http://onsemi.com 6 figure 3. maximum off channel leakage current, any one channel, test set?up figure 4. maximum off channel leakage current, common channel, test set?up figure 5. maximum on channel leakage current, channel to channel, test set?up figure 6. maximum on channel bandwidth, test set?up figure 7. off channel feedthrough isolation, test set?up figure 8. feedthrough noise, channel select to common out, test set?up off off 6 8 16 common o/i v cc v ih nc a v cc gnd v cc off off 6 8 16 common o/i v cc v ih analog i/o v cc gnd v cc on off 6 8 16 common o/i v cc v il v cc gnd v cc n/c a analog i/o on 6 8 16 v cc 0.1 f c l * f in r l db meter *includes all probe and jig capacitance off 6 8 16 v cc 0.1 f c l * f in r l db meter *includes all probe and jig capacitance v os v os r l v is v il or v ih channel select on/off 6 8 16 v cc c l * r l *includes all probe and jig capacitance channel select test point common o/i 11 v cc off/on analog i/o r l r l v ih v il v in 1 mhz t r = t f = 3 ns MC74LVXT8051 http://onsemi.com 7 figure 9a. propagation delays, channel select to analog out figure 9b. propagation delay, test set?up channel select to analog out figure 10a. propagation delays, analog in to analog out figure 10b. propagation delay, test set?up analog in to analog out figure 11a. propagation delays, enable to analog out figure 11b. propagation delay, test set?up enable to analog out v cc gnd channel select analog out 50% t plh t phl 50% on/off 6 8 16 v cc c l * *includes all probe and jig capacitance channel select test point common o/i off/on analog i/o v cc v cc gnd analog in analog out 50% t plh t phl 50% on 6 8 16 v cc c l * *includes all probe and jig capacitance test point common o/i analog i/o on/off 6 8 enable v cc enable 90% 50% 10% t f t r v cc gnd analog out t pzl analog out t pzh high impedance v ol v oh high impedance 10% 90% t plz t phz 50% 50% analog i/o c l * test point 16 v cc 1k 1 2 1 2 position 1 when testing t phz and t pzh position 2 when testing t plz and t pzl v ih v il MC74LVXT8051 http://onsemi.com 8 r l figure 12. crosstalk between any two switches, test set?up figure 13. power dissipation capacitance, test set?up figure 14a. total harmonic distortion, test set?up figure 14b. plot, harmonic distortion 0 -10 -20 -30 -40 -50 - 100 1.0 2.0 3.125 frequency (khz) db -60 -70 -80 -90 fundamental frequency device source on 6 8 16 c l * *includes all probe and jig capacitance off r l r l v is r l c l * v os f in 0.1 f on/off 6 8 16 v cc channel select nc common o/i off/on analog i/o v cc a 11 v cc on 6 8 16 v cc 0.1 f c l * f in r l to distortion meter *includes all probe and jig capacitance v os v is applications information the channel select and enable control pins should be at v cc or gnd logic levels. v cc being recognized as a logic high and gnd being recognized as a logic low. in this example: v cc = +5v = logic high gnd = 0v = logic low the maximum analog voltage swing is determined by the supply voltage v cc . the positive peak analog voltage should not exceed v cc . similarly, the negative peak analog voltage should not go below gnd. in this example, the difference between v cc and gnd is five volts. therefore, using the configuration of figure 15, a maximum analog signal of five volts peak?to?peak can be controlled. unused analog inputs/outputs may be left floating (i.e., not connected). however, tying unused analog inputs and outputs to v cc or gnd through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. although used here, balanced supplies are not a requirement. the only constraints on the power supplies are that: v cc ? gnd = 2 to 6 volts when voltage transients above v cc and/or below gnd are anticipated on the analog channels, external germanium or schottky diodes (d x ) are recommended as shown in figure 16. these diodes should be able to absorb the maximum anticipated current surges during clipping. MC74LVXT8051 http://onsemi.com 9 analog signal figure 15. application example figure 16. external germanium or schottky clipping diodes a. low voltage logic level shifting control b. 2?stage logic level shifting control figure 17. interfacing to low voltage cmos outputs on 6 8 16 +5v analog signal +5v 0v +5v 0v 11 10 9 to external lsttl compatible circuitry 0 to v ih digital signals on/off 8 16 v cc gnd d x v cc d x gnd d x v cc d x analog signal on/off 6 8 16 +3v analog signal +3v gnd +3v gnd 11 10 9 1.8v - 2.5v circuitry analog signal on/off 6 8 16 +5v analog signal +5v gnd +5v gnd 11 10 9 1.8v - 2.5v circuitry +5v mc74vhct1gt50 buffers v cc = 3.0v figure 18. function diagram, lvxt8051 13 x0 14 x1 15 x2 12 x3 1 x4 5 x5 2 x6 4 x7 3 x level shifter level shifter level shifter level shifter 11 a 10 b 9 c 6 enable MC74LVXT8051 http://onsemi.com 10 ordering information device package shipping ? MC74LVXT8051dg soic?16 (pb?free) 48 units / rail MC74LVXT8051dr2g soic?16 (pb?free) 2500 tape & reel MC74LVXT8051dtr2g tssop?16 (pb?free) 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. MC74LVXT8051 http://onsemi.com 11 package dimensions tssop?16 case 948f issue b ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. MC74LVXT8051 http://onsemi.com 12 package dimensions soic?16 case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemni fy and hold scillc and its officers, em ployees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 MC74LVXT8051/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative |
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