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n79e 71 5 datasheet jan. 6 , 201 6 page 1 of 189 revision 1.0 1 nuvoton 8051 - based microcontroller N79E715 data s heet
n79e 71 5 datasheet jan. 6 , 201 6 page 2 of 189 revision 1.0 1 table of c ontents 1 general description ................................ ................................ ................................ ................................ 5 2 features ................................ ................................ ................................ ................................ .......................... 6 3 parts information li st ................................ ................................ ................................ ............................ 8 4 block diagram ................................ ................................ ................................ ................................ .............. 9 5 pin configuration ................................ ................................ ................................ ................................ ...... 10 6 memory organization ................................ ................................ ................................ ............................. 15 6.1 aprom flash memory ................................ ................................ ................................ ........................ 16 6.2 ldrom flash memory ................................ ................................ ................................ ........................ 16 6.3 config - bits ................................ ................................ ................................ ................................ .......... 16 6.4 on - chip non - volatile data flash ................................ ................................ ................................ ......... 16 6.5 on - chip xram ................................ ................................ ................................ ................................ ....... 18 6.6 on - chip scratch - pad ram and sfr ................................ ................................ ................................ ... 18 6.7 working registers ................................ ................................ ................................ ................................ . 19 6.8 bit - addressable locations ................................ ................................ ................................ ................... 20 6.9 stack ................................ ................................ ................................ ................................ ....................... 20 7 special function reg ister (sfr) ................................ ................................ ................................ ....... 21 8 general 80c51 system control ................................ ................................ ................................ ......... 25 9 i/o port structure a nd operation ................................ ................................ ................................ .. 29 9.1 quasi - bidirectional output c onfiguration ................................ ................................ .......................... 29 9.1.1 read - modify - write ................................ ................................ ................................ .................. 30 9.2 open drain output configuration ................................ ................................ ................................ ....... 31 9.3 push - pull output configuration ................................ ................................ ................................ .......... 31 9.4 input only configuration ................................ ................................ ................................ ...................... 32 10 timers/counters ................................ ................................ ................................ ................................ ........ 36 10.1 timers/counters 0 and 1 ................................ ................................ ................................ ..................... 36 10.1.1 mode 0 (13 - bit timer) ................................ ................................ ................................ ........... 40 10.1.2 mode 1 (16 - bit time r) ................................ ................................ ................................ ........... 41 10.1.3 mode 2 (8 - bit auto - reload timer) ................................ ................................ ...................... 41 10.1.4 mode 3 (two separate 8 - bit timers) ................................ ................................ ................. 42 10.2 timer/counter 2 ................................ ................................ ................................ ................................ .... 43 10.2.1 input capture mode ................................ ................................ ................................ .............. 45 10.2.2 auto - reload mode ................................ ................................ ................................ .................. 49 10.2.3 compare mode ................................ ................................ ................................ ...................... 50 11 watchdog timer (wdt) ................................ ................................ ................................ ............................. 51 11.1 functional description ................................ ................................ ................................ .......................... 51 11.2 applications of watchdog timer reset ................................ ................................ .............................. 54 11.3 applications of watchdog timer interrupt ................................ ................................ ......................... 55 12 serial port (uart) ................................ ................................ ................................ ................................ ...... 57 12.1 mode 0 ................................ ................................ ................................ ................................ .................... 59 12.2 mode 1 ................................ ................................ ................................ ................................ .................... 61 12.3 mode 2 ................................ ................................ ................................ ................................ .................... 63 12.4 mode 3 ................................ ................................ ................................ ................................ .................... 65 12.5 baud rates ................................ ................................ ................................ ................................ ............ 67 12.6 framing error detection ................................ ................................ ................................ ....................... 68 12.7 multiprocessor communication ................................ ................................ ................................ ........... 68 12.8 automatic address recognition ................................ ................................ ................................ .......... 69 13 serial peripheral in terface (spi) ................................ ................................ ................................ .... 72
n79e 71 5 datasheet jan. 6 , 201 6 page 3 of 189 revision 1.0 1 13.1 features ................................ ................................ ................................ ................................ ................. 72 13.2 functional description ................................ ................................ ................................ .......................... 72 13.3 spi control registers ................................ ................................ ................................ ........................... 75 13.4 operating modes ................................ ................................ ................................ ................................ ... 78 13.4.1 master mode ................................ ................................ ................................ .......................... 78 13.4.2 slave mode ................................ ................................ ................................ ............................ 78 13.5 clock formats and data transfer ................................ ................................ ................................ ...... 79 13.6 slave select pin configuration ................................ ................................ ................................ ........... 81 13.7 mode fault detection ................................ ................................ ................................ ........................... 82 13.8 write collision error ................................ ................................ ................................ .............................. 82 13.9 overrun error ................................ ................................ ................................ ................................ ......... 82 13.10 spi interrupts ................................ ................................ ................................ ................................ ........ 83 14 keyboard interrupt ( kbi) ................................ ................................ ................................ ....................... 85 15 analog - to - digital converter (a dc) ................................ ................................ ................................ 89 16 inter - integrated circuit ( i 2 c) ................................ ................................ ................................ ............. 95 16.1 features ................................ ................................ ................................ ................................ ................. 95 16.2 functional description ................................ ................................ ................................ .......................... 95 16.2.1 start and stop conditions ................................ ................................ ............................. 96 16.2.2 7 - bit address with data format ................................ ................................ ........................... 97 16.2.3 acknowledge ................................ ................................ ................................ .......................... 98 16.2.4 arbitration ................................ ................................ ................................ ............................... 99 16.3 control registers of i 2 c ................................ ................................ ................................ ..................... 100 16.4 operation modes ................................ ................................ ................................ ................................ . 103 16.4.1 master transmitter mode ................................ ................................ ................................ ... 103 16.4.2 master receiver mode ................................ ................................ ................................ ....... 105 16.4.3 slave receiver mode ................................ ................................ ................................ .......... 106 16.4.4 slave transmitter mode ................................ ................................ ................................ ..... 10 7 16.4.5 general call ................................ ................................ ................................ ......................... 108 16.4.6 miscellaneous states ................................ ................................ ................................ .......... 108 16.5 typical structure of i 2 c interrupt service routine ................................ ................................ ......... 109 16.6 i 2 c time - out ................................ ................................ ................................ ................................ ......... 113 16.7 i 2 c interrupts ................................ ................................ ................................ ................................ ........ 113 17 pulse width modulate d (pwm) ................................ ................................ ................................ .......... 115 17.1 features ................................ ................................ ................................ ................................ ............... 115 17.2 functional description ................................ ................................ ................................ ........................ 115 18 timed access protect ion (ta) ................................ ................................ ................................ ........... 125 19 interrupt system ................................ ................................ ................................ ................................ .... 127 19.1 interrupt sources ................................ ................................ ................................ ................................ . 127 19.2 priority level structure ................................ ................................ ................................ ....................... 129 19.3 interrupt response time ................................ ................................ ................................ ................... 133 19.4 sfr o f interrupt ................................ ................................ ................................ ................................ ... 133 20 in system programmin g (isp) ................................ ................................ ................................ ............. 139 20.1 isp procedure ................................ ................................ ................................ ................................ ..... 139 20.2 isp command table ................................ ................................ ................................ .......................... 143 20.3 access table of isp programming ................................ ................................ ................................ .. 144 20.4 isp user guide ................................ ................................ ................................ ................................ ... 144 20.5 isp demo code ................................ ................................ ................................ ................................ .. 145 21 power management ................................ ................................ ................................ ................................ 148 21.1 idle mode ................................ ................................ ................................ ................................ .............. 148 21.2 power - down mode ................................ ................................ ................................ .............................. 149
n79e 71 5 datasheet jan. 6 , 201 6 page 4 of 189 revision 1.0 1 22 clock system ................................ ................................ ................................ ................................ ............. 151 22.1 on - chip rc oscillators ................................ ................................ ................................ ...................... 153 22.2 crystal/resonator ................................ ................................ ................................ ............................... 153 23 power monitoring ................................ ................................ ................................ ................................ ... 154 23.1 power - on detection ................................ ................................ ................................ ............................ 154 23.2 brown - out detection ................................ ................................ ................................ ........................... 154 24 reset conditions ................................ ................................ ................................ ................................ ..... 157 24.1 power - on reset ................................ ................................ ................................ ................................ ... 157 24.2 bod reset ................................ ................................ ................................ ................................ ........... 158 24.3 rst pin reset ................................ ................................ ................................ ................................ ..... 159 24.4 watchdog timer reset ................................ ................................ ................................ ...................... 159 24.5 software reset ................................ ................................ ................................ ................................ .... 160 24.6 boot selection ................................ ................................ ................................ ................................ ..... 161 24.7 reset state ................................ ................................ ................................ ................................ .......... 162 25 config bits (config) ................................ ................................ ................................ ................................ 164 25.1 config0 ................................ ................................ ................................ ................................ ............. 164 25.2 config1 ................................ ................................ ................................ ................................ ............. 165 25.3 config2 ................................ ................................ ................................ ................................ ............. 166 25.4 config3 ................................ ................................ ................................ ................................ ............. 167 25.5 config4 ................................ ................................ ................................ ................................ ............. 168 26 instruction sets ................................ ................................ ................................ ................................ ...... 169 27 in - circuit program (icp ) ................................ ................................ ................................ ....................... 173 28 electrical character istics ................................ ................................ ................................ ............. 175 28.1 absolute maximum ratings ................................ ................................ ................................ ............... 175 28.2 dc electrical characteristics ................................ ................................ ................................ ............. 175 28.3 analog electric al characteristics ................................ ................................ ................................ ...... 180 28.3.1 characteristics of 10 - bits sar - adc ................................ ................................ ................. 180 28.3.2 characteristics of 4 ~ 24 mhz crystal ................................ ................................ .............. 181 28.3.3 characteristics of hirc ................................ ................................ ................................ ...... 181 28.3.4 characteristics of lirc ................................ ................................ ................................ ...... 182 29 application circuit for emc immu nity ................................ ................................ ......................... 183 30 package dimensions ................................ ................................ ................................ ............................... 184 30.1 28 - pin sop - 300 mil ................................ ................................ ................................ .......................... 184 30.2 28 - pin tssop - 4.4x9.7 mm ................................ ................................ ................................ ............. 185 30.3 20 - pin sop - 300 mil ................................ ................................ ................................ .......................... 186 30.4 20 - pin tssop - 4.4x6.5mm ................................ ................................ ................................ .............. 187 30.5 16 - pin sop - 150 mil ................................ ................................ ................................ .......................... 188 31 revision history ................................ ................................ ................................ ................................ ....... 189
n79e 71 5 datasheet jan. 6 , 201 6 page 5 of 189 revision 1.0 1 1 general d escription the N79E715 8 - bit turbo 51 (4t mode) microco ntroller is embedded with 16 k bytes flash eprom that can be programmed through universal hardware writer, serial icp (in circuit program) programmer, and software isp function. the instruction sets of the N79E715 are fully compatible with the standard 8052 . the N79E715 contain s 16 k bytes [1] program memory (aprom) and 2 kbytes load flash eprom (ldrom) memory , 256 bytes direct and indirect ram, 256 bytes xram ; 25 i/o with bit - addressable i/o ports; two 16 - bit timers/counters ; 8 - channel multiplexed 10 - bit a/d convert er ; 4 - channel 10 - bit pwm; three serial ports includ ing a spi, i 2 c and an enhanced full duplex serial port; 2 - level bod voltage detection/reset and po w er - on reset (por) . the N79E715 also support s internal rc oscillator 22.1184 mhz that is factory tr immed to 1% at room temperature and v dd = 5v. these peripherals are suppor t ed by 1 4 sources of four - level interrupt capability. to facilitate programming and verification, the flash eprom inside the N79E715 allow s the program memory to be programm ing and read electronically. t he code is once confirm ed. t hus t he user can protect the code for security. the N79E715 microcontroller , featur ing wide operating voltage range, built - in rich analog and digital peripherals and non - volatile flash memory , is widely su it able for general control and home appliance s .
n79e 71 5 datasheet jan. 6 , 201 6 page 6 of 189 revision 1.0 1 2 features ? core ? fully static design 8 - bit turbo 51 (4t) cmos microcontroller ? instruction sets fully compatible with the mcs - 51 ? o perating voltage range ? v dd = 2. 4 v to 5.5v at f sys = 4~ 24 mhz ? operating temperatur e range ? - 40 ? c ~ + 85 ? c ? clock s ystem ? high - speed external oscillator 4~ 24 mhz c rystal and resonator ? high - speed internal rc oscillator 22.1184 mhz ? flexible cpu clock source configurable by config - bits ? 8 - bit programmable cpu clock divider(divm) ? on - chip memory ? 100,000 erase/write cycles ? 16 kbyte s shared by aprom and data flash depend ing on config - bits definition s ? aprom, ldrom and data flash security protection ? flash page size as 128 bytes ? 256 bytes of on - chip direct/indirect ram ? 256 bytes of xram , accessed by mo vx instruction ? on - chip flash programmed through - parallel h/w writer mode - serial in - circuit - program mode (icp) - software implemented isp (in - system - program) ? i/o ports ? up to 25 i/o pins ? all i/o pin besides p1.2 and p1.3 support 4 software configurable output modes ? software selectable ttl or schmitt trigger input type per port ? 14 interrupt source s with four levels of priority ? led drive capability 38 ma on p10, p11, p14, p16, p17 ? led drive capability 20 ma on port 0, 2, 3 pins ? timer/counter ? two set s of 16 - bit t imers/ c ounters ? one 16 - bit timer with three channel of input captures ? watchdog timer ? programmable watchdog 6 - bit timer with divider 256 ? c lock source supported by low - speed internal rc oscillator ? s erial ports (uart, spi, i 2 c) ? one set of enhanced full duplex uart port with framing error detection and automatic address reco g nition. ? s oftware switches two groups of uart pins ? one set of spi with master/slave capability ; s oftware switch es two group s of spi pin s ? one set of i 2 c with master/slave capability
n79e 71 5 datasheet jan. 6 , 201 6 page 7 of 189 revision 1.0 1 ? pwm ? 4 cha nnels 10 - bit pwm outputs with one brake/fault input ? kbi ? 8 - keypad interrupt inputs (kbi) with 8 falling/ rising/ both - edge detection pins selected by software ? a dc ? 10 - bit a/d converter ? up to 150 ksps (sample per second) ? 8 analog input channels ? brown - out de te ct or ? 2 - level ( 3.8 v /2. 7 v) bod detector ? supports interrupt and reset op tions ? por ( power - on reset ) ? threshold voltage level as 2.0v ? built - in power management ? idle mode ? power - down mode with optional ly enabled wdt functions ? strong esd and eft immunity ? development tools ? hardware writer ? icp programmer ? isp update aprom by uart port
n79e 71 5 datasheet jan. 6 , 201 6 page 8 of 189 revision 1.0 1 3 p arts i nformation l ist table 3 - 1 lead free (rohs) parts i nformation l ist part no. aprom ldrom ram data flash package n79e71 5a s28 16kb 2 kb 51 2b share aprom sop - 2 8 pin N79E715as20 16kb 2 kb 512b share aprom sop - 2 0 pin N79E715as 16 16kb 2 kb 512b share aprom sop - 16 pin N79E715at28 16kb 2 kb 512b share aprom tssop - 28 pin N79E715at20 16kb 2 kb 512b share aprom tssop - 20 pin
n79e 71 5 datasheet jan. 6 , 201 6 page 9 of 189 revision 1.0 1 4 block diagram figure 4 - 1 N79E715 function block diagram a l u s t a c k p o i n t e r p s w t 1 r e g i s t e r t 2 r e g i s t e r a c c b i n s t r u c t i o n d e c o d e r & s e q u e n c e r b u s & l o c k c o n t r o l l e r d p t r t i m e r r e g . p c d p t r 1 p o r t 0 l a t c h p o r t 0 i n c r e m e n t o r f l a s h e p r o m p o r t 2 l a t c h p o r t 2 p o w e r c o n t r o l & p o w e r m o n i t o r s f r & r a m a d d r e s s 2 5 6 b y t e s r a m & s f r t i m e r 0 t i m e r 1 i n t e r r u p t u a r t p o r t 1 l a t c h p o r t 1 o s c i l l a t o r x t a l 1 x t a l 2 w a t c h d o g t i m e r r e s e t b l o c k r s t v d d g n d p 0 . 0 | p 0 . 7 p 1 . 0 | p 1 . 7 i 2 c , s p i p w m k b i o n - c h i p r c o s c i l l a t o r a d c 2 5 6 x r a m i n p u t c a p t u r e / t i m e r 2 p 2 . 0 | p 2 . 7 p o r t 3 l a t c h p o r t 3 p 3 . 0 | p 3 . 1 o n - c h i p r c 1 0 k h z
n79e 71 5 datasheet jan. 6 , 201 6 page 10 of 189 revision 1.0 1 5 pin configuration figure 5 - 1 tssop 28 - pin assignment figure 5 - 2 tssop 20 - pin assignment n 7 9 e 7 1 5 a t 2 8 2 8 s p i c l k , k b 0 , p w m 3 , p 0 . 0 i c p c l k , m o s i , p w m 2 , p 1 . 7 i c p d a t , m i s o , p w m 1 , p 1 . 6 v s s x t a l 1 , p 3 . 1 x t a l 2 , c l k o u t , p 3 . 0 s s , s t a d c , i n t 1 , p 1 . 4 s d a , i n t 0 , p 1 . 3 i c 0 , s c l , t 0 , p 1 . 2 p 0 . 1 , a d c 0 , p w m 0 , k b 1 p 0 . 2 , a d c 1 , b r a k e , k b 2 p 0 . 3 , a d c 2 , k b 3 p 0 . 4 , a d c 3 , k b 4 p 0 . 5 , a d c 4 , k b 5 v d d p 0 . 6 , a d c 5 , k b 6 p 0 . 7 , a d c 6 t 1 , k b 7 , i c 1 p 1 . 0 , t x d p 1 . 1 , r x d 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 2 3 4 5 7 8 9 1 0 1 8 1 7 1 1 1 2 1 3 1 4 1 6 1 5 i c 2 , p 2 . 0 p 2 . 1 p 2 . 7 , r x d 2 [ 1 ] p 2 . 6 , a d c 7 , t x d 2 [ 1 ] m o s i 2 [ 2 ] , p 2 . 2 m i s o 2 [ 2 ] , p 2 . 3 p 2 . 5 , s p i c l k 2 [ 2 ] p 2 . 4 , s s 2 [ 2 ] 6 r s t [ 1 ] t h e s e p i n s a r e s w i t c h e d f r o m r x d 2 a n d t x d 2 b y s / w s e t t i n g [ 2 ] t h e s e p i n s a r e s w i t c h e d f r o m m o s i 2 , m i s o 2 , / s s 2 a n d s p i c l k 2 b y s / w s e t t i n g . n 7 9 e 7 1 5 a t 2 0 s p i c l k , k b 0 , p w m 3 , p 0 . 0 i c p c l k , m o s i , p w m 2 , p 1 . 7 i c p d a t a , m i s o , p w m 1 , p 1 . 6 v s s x t a l 1 , p 3 . 1 x t a l 2 , c l k o u t , p 3 . 0 s s , s t a d c , i n t 1 , p 1 . 4 s d a , i n t 0 , p 1 . 3 i c 0 , s c l , t 0 , p 1 . 2 p 0 . 1 , a d c 0 , p w m 0 , k b 1 p 0 . 2 , a d c 1 , b r a k e , k b 2 p 0 . 3 , a d c 2 , k b 3 p 0 . 4 , a d c 3 , k b 4 p 0 . 5 , a d c 4 , k b 5 v d d p 0 . 6 , a d c 5 , k b 6 p 0 . 7 , a d c 6 t 1 , k b 7 , i c 1 p 1 . 0 , t x d p 1 . 1 , r x d 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 3 5 6 7 8 1 2 1 1 9 1 0 4 r s t
n79e 71 5 datasheet jan. 6 , 201 6 page 11 of 189 revision 1.0 1 figure 5 - 3 sop 28 - pin assignment figu re 5 - 4 sop 20 - pin assignment n 7 9 e 7 1 5 a s 2 8 2 8 s p i c l k , k b 0 , p w m 3 , p 0 . 0 i c p c l k , m o s i , p w m 2 , p 1 . 7 i c p d a t , m i s o , p w m 1 , p 1 . 6 v s s x t a l 1 , p 3 . 1 x t a l 2 , c l k o u t , p 3 . 0 s s , s t a d c , i n t 1 , p 1 . 4 s d a , i n t 0 , p 1 . 3 i c 0 , s c l , t 0 , p 1 . 2 p 0 . 1 , a d c 0 , p w m 0 , k b 1 p 0 . 2 , a d c 1 , b r a k e , k b 2 p 0 . 3 , a d c 2 , k b 3 p 0 . 4 , a d c 3 , k b 4 p 0 . 5 , a d c 4 , k b 5 v d d p 0 . 6 , a d c 5 , k b 6 p 0 . 7 , a d c 6 t 1 , k b 7 , i c 1 p 1 . 0 , t x d p 1 . 1 , r x d 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 2 3 4 5 7 8 9 1 0 1 8 1 7 1 1 1 2 1 3 1 4 1 6 1 5 i c 2 , p 2 . 0 p 2 . 1 p 2 . 7 , r x d 2 [ 1 ] p 2 . 6 , a d c 7 , t x d 2 [ 1 ] m o s i 2 [ 2 ] , p 2 . 2 m i s o 2 [ 2 ] , p 2 . 3 p 2 . 5 , s p i c l k 2 [ 2 ] p 2 . 4 , s s 2 [ 2 ] 6 r s t [ 1 ] t h e s e p i n s a r e s w i t c h e d f r o m r x d 2 a n d t x d 2 b y s / w s e t t i n g [ 2 ] t h e s e p i n s a r e s w i t c h e d f r o m m o s i 2 , m i s o 2 , / s s 2 a n d s p i c l k 2 b y s / w s e t t i n g . n 7 9 e 7 1 5 a s 2 0 s p i c l k , k b 0 , p w m 3 , p 0 . 0 i c p c l k , m o s i , p w m 2 , p 1 . 7 i c p d a t a , m i s o , p w m 1 , p 1 . 6 v s s x t a l 1 , p 3 . 1 x t a l 2 , c l k o u t , p 3 . 0 s s , s t a d c , i n t 1 , p 1 . 4 s d a , i n t 0 , p 1 . 3 i c 0 , s c l , t 0 , p 1 . 2 p 0 . 1 , a d c 0 , p w m 0 , k b 1 p 0 . 2 , a d c 1 , b r a k e , k b 2 p 0 . 3 , a d c 2 , k b 3 p 0 . 4 , a d c 3 , k b 4 p 0 . 5 , a d c 4 , k b 5 v d d p 0 . 6 , a d c 5 , k b 6 p 0 . 7 , a d c 6 t 1 , k b 7 , i c 1 p 1 . 0 , t x d p 1 . 1 , r x d 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 3 5 6 7 8 1 2 1 1 9 1 0 4 r s t
n79e 71 5 datasheet jan. 6 , 201 6 page 12 of 189 revision 1.0 1 figure 5 - 5 sop 16 - pin assignment n 7 9 e 7 1 5 a s 1 6 k b 0 , p w m 3 , p 0 . 0 i c p c l k , p w m 2 , p 1 . 7 i c p d a t a , p w m 1 , p 1 . 6 v s s x t a l 1 , p 3 . 1 x t a l 2 , c l k o u t , p 3 . 0 s d a , i n t 0 , p 1 . 3 p 1 . 2 , i c 0 , s c l , t 0 p 0 . 1 , a d c 0 , p w m 0 , k b 1 p 0 . 2 , a d c 1 , b r a k e , k b 2 p 0 . 3 , a d c 2 , k b 3 p 0 . 4 , a d c 3 , k b 4 v d d p 1 . 0 , t x d p 1 . 1 , r x d 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 1 2 3 5 6 7 8 4 r s t
n79e 71 5 datasheet jan. 6 , 201 6 page 13 of 189 revision 1.0 1 table 5 C 1 pin description pin no. symb o l alternate function type description tssop28 / sop28 tssop20 / sop20 sop16 1 2 3 21 15 12 v dd p power supply: supply voltage v dd for operation. 7 5 5 v ss p ground: ground potential 6 4 4 /rst i (st) res et: chip reset pin that is l ow active. 3 1 1 p0.0 pwm3 kb0 spiclk i/o port0: port 0 has 4 - type i/o port. its multifunction pins are for pwm0, pwm3, t1, brake, spiclk, adc0~adc6 and kb0 ~ kb7. adc0 ~adc6: adc channel input. kb0 ~ kb7: key b oard input the p wm0 and pwm3 is pwm output channel. t1: timer 1 external input spiclk: spi - 1 clock pin 26 20 16 p0.1 pwm0 adc0 kb1 i/o 25 15 19 p0.2 brake adc1 kb2 i/o 24 14 18 p0.3 adc2 kb3 i/o 23 13 17 p0.4 adc3 kb4 i/o 22 - 16 p0.5 adc4 kb5 i/o 20 - 14 p0.6 adc5 kb6 i/o 19 - 13 p0.7 t1 adc6 kb7 ic1 i/o 18 11 12 p1.0 txd i/o port1: port 1 has 4 - type i/o port. its multifunction pins are for txd, rxd, t0, /int0, /int1, scl, sda, stadc, icpdat, icpclk and /ss, miso, mosi. the txd and rxd are uart port the scl and sda are i 2 c function with open - drain port. the icpdat and icpclk are icp (in circuit programming) function pin s . the /ss, miso, mosi are spi - 1 function pins. the pwm1 and pwm2 are pwm output channel t0: timer 0 external input ic0/1: input capture pin stadc: adc trigger by external pin 17 10 11 p1.1 rxd i/o 12 9 10 p1.2 t0 scl ic0 d 11 8 9 p1.3 /int0 sda d 10 - 8 p1.4 /int1 stadc /ss i/o 5 3 3 p1.6 pwm1 icpdat miso i/o 4 2 2 p1.7 pwm2 icpclk mosi i/o 1 - - p2.0 ic2 i/o port2: port 2 has 4 - type i/o port. its multifunction pins are for t2, adc7, txd2, rxd2 and mosi2, miso2, /ss2, spiclk2, ic2 the txd2 and rxd2 are uart port by software switch form txd1 and rxd1. the mosi2, miso2, /ss2 and spiclk2 are spi - 2 function 2 - - p2.1 i/o 13 - - p2.2 mosi2 i/o
n79e 71 5 datasheet jan. 6 , 201 6 page 14 of 189 revision 1.0 1 table 5 C 1 pin description pin no. symb o l alternate function type description tssop28 / sop28 tssop20 / sop20 sop16 1 2 3 14 - - p2.3 miso2 i/o pi ns. the spi - 2 ports are by software switched from spi - 1 port. adc7: adc channel input. ic2: input capture pin 15 - - p2.4 /ss2 i/o 16 - - p2.5 spiclk 2 i/o 27 - - p2.6 txd 2 adc7 i/o 28 - - p2.7 rxd2 i/o 9 7 7 p3 .0 xtal2 clkout i/o port3: port 3 has 4 - type i/o port. its multifunction pins are for xtal1, xtal2 and clkout, clkout: f hirc /4 output pin. xtal2: this is the output pin from the internal inverting amplifi er. it emits the inverted signal of xtal2. xtal1: this is the output pin from the internal inverting amplifier. it emits the inverted signal of xtal1. 8 6 6 p3.1 xtal1 i/o [1] i/o type description i: input, o: output, i/o: quasi bi - direction, d: open - drain, p: power pins, st: schmitt trigger.
n79e 71 5 datasheet jan. 6 , 201 6 page 15 of 189 revision 1.0 1 6 memory organization the N79E715 has embedded fl ash eprom includ ing 16 k b ytes application program flash m emory ( aprom ), fixed 2 kbytes load rom flash memory ( ldrom ) and config - bits . the N79E715 also provide s 256 bytes of on - chip d i rect/indirect ram and 256 bytes of xram accessed by movx instruction. aprom block and data flash block comprise the 16 kbytes embe d ded flash. the block size is config - bits /software c onfigurable. the N79E715 is built with a cmos page - erase. the page - erase operation erases all bytes within a page of 128 bytes. figure 6 - 1 N79E715 memory map 0 0 0 0 h 1 6 k b y t e s a p r o m 0 7 f f h c h b d a o r s h b d a 0 0 0 0 h d a t a f l a s h d a t a f l a s h m e m o r y a r e a p a g e 0 = 1 2 8 b p a g e 1 = 1 2 8 b p a g e n = 1 2 8 b d a t a f l a s h 1 2 8 b y t e s / p a g e p r o g r a m m e m o r y s p a c e f l a s h t y p e c o n f i g - b i t s 0 0 f f h 0 0 0 0 h i n d i r e c t r a m a d d r e s s i n g d i r e c t & i n d i r e c t r a m a d d r e s s i n g s f r d i r e c t a d d r e s s i n g o n l y 0 0 h 7 f h 8 0 h f f h d i r e c t / i n d i r e c t r a m a c c e s s e d b y m o v i n s t r u c t i o n 2 5 6 b y t e s o n - c h i p x r a m x r a m a c c e s s e d b y m o v x i n s t r u c t i o n 0 0 0 h 0 f f h d a t a m e m o r y s p a c e s r a m t y p e 1 6 k b 1 6 k b : n 7 9 e 7 1 5 l d r o m 3 f f f h
n79e 71 5 datasheet jan. 6 , 201 6 page 16 of 189 revision 1.0 1 6.1 a prom flash memory the N79E715 has 16 k bytes on - chip program memory. all instructions are fetched for execution from this memory area. the movc i n struction can also read this memory region. the user application program is located in aprom . when cpu boots from aprom (chpcon.b s=0), cpu starts executing the program from address 0000h. if the value of program counter (pc) is over the space of aprom , cpu will execute nop operand and program counter increases one by one until pc reaches 3 fffh then it wraparounds to address 0000h of aprom , the cpu executes the application program again. 6.2 l d rom flash memory the N79E715 has 2 kbytes ldrom . user may develop the isp function in ldrom for updating application program or data flash. similarly, aprom can also re - program ldrom and data flash . the start address of ldrom is at 0 000h corresponding to the physical address of the flash memory. however, when cpu runs in ldrom , cpu automatically re - vectors the ldrom start address to 0000h, therefore user program regards the ldrom as an independent p rogram memory, meanwhile, with all interrupt vectors that cpu provides. 6.3 config - bits there are several bytes of config - bits located config - bits block. the config - bits define the cpu initial setting after power up or reset. only hardware parallel writer or h ardware icp writer can erase/program config - bits. isp program in ldrom can also erase/program config - bits. 6.4 on - chip non - volatile data flash the N79E715 additionally has non - volatile data flash , which is non - volatile so that it remains its content even after the power is off. therefore, in general application the user can write or read data which rules as parameters or constants. by the software path, sp mode can erase, written, or read the data flash only . of course, hardware with parallel programmer/writer or icp programmer can also access the d a ta flash. the data flash size is software adjustable in N79E715 (16 kb) by updating the content of shbda. shbda[7:0] represents the high byte of 16 - bit data flash start address and the low byte is hardware set to 00h . the value of shbda is loaded from the content of config1 (chbda) after all resets. the application program can dynamically adjust the data flash size by resetting shbda value. once the data flash size is changed the aprom size is changed accordingly. shb da has time access protect ion whil e a write to shbda is required.
n79e 71 5 datasheet jan. 6 , 201 6 page 17 of 189 revision 1.0 1 the config bit dfen ( config0 .0) should be programmed as 0 before access ing the data flash block. if dfen remains its un - programmed value 1, aprom will occupy the whole 16 k byte s block in n79 e715 dfen. figure 6 - 2 N79E715 data flash shbda C sfr high byte of data flash starting address ( ta protected ) 7 6 5 4 3 2 1 0 shbda[7:0] [1] r/w address: 9ch reset value: see table 7 C 2 N79E715 s fr description and reset value s a p r o m 0 0 0 0 h [ 1 ] 3 f f f h [ 1 ] t h e a d d r e s s i s [ s h b d a , 0 0 h ] w h i l e d f e n ( c o n f i g 0 . 0 ) i s e n a b l e d . d a t a f l a s h n 7 9 e 7 1 5 c h b d a o r s h b d a
n79e 71 5 datasheet jan. 6 , 201 6 page 18 of 189 revision 1.0 1 bit name description 7:0 shbda[7:0] sfr high byte of data flash starting address this byte is valid only when dfen ( config0 .0) being 0 condition. it is used to dyn amic adjust the starting address of the data flash when the application pr o gram is executing. [1] shbda is loaded from config1 after all resets. 6.5 on - chip xram the N79E715 provide s additional on - chip 256 bytes auxiliary ram called xram to enlarge the ram sp ace. it occupies the address space from 00h through ffh . the 256 bytes of xram are indirectly accessed by move external instruction movx @dptr or movx @ri. (see the demo code below.) note that the stack pointer may not be located in any part of xram. figure 6 - 1 shows the memory map for this product series. xram demo code: mov r0,#23h ;write #5ah to xram with address @23h mov a,#5ah movx @r0,a mov r1,#23h ;read from xram with address @23h movx a,@r1 mov dptr,#0023h ;write #5bh to xram with address @0023h mov a,#5bh movx @dptr,a mov dptr,#0023h ;read from xram with address @0023h movx a,@dptr 6.6 on - chip scratch - pad ram and sfr the N79E715 provide s the on - chip 256 bytes scratch pad ram and special function registers (sfrs) which are accessed by software. the sfrs are accessed only by direct addressing, while the on - chip ram is accessed by either direct or indirect addressing. figure 6 - 3 256 bytes ram and sfr i n d i r e c t r a m a d d r e s s i n g d i r e c t & i n d i r e c t r a m a d d r e s s i n g s f r d i r e c t a d d r e s s i n g o n l y 0 0 h 7 f h 8 0 h f f h
n79e 71 5 datasheet jan. 6 , 201 6 page 19 of 189 revision 1.0 1 since the scratch - pad ram is only 256 byte it can be used only when data contents are small. there are se v eral other special purpose areas within the scratch - pad ram , which are described as follows. figure 6 - 4 data memory and bit - addressable r egion 6.7 working registers there are four sets of working registers, each consisting of eight 8 - bit registers , which are termed as banks 0, 1, 2, and 3. individual registers wit hin these banks can be directly accessed by separate instructions. these individual registers are named as r0, r1, r2, r3, r4, r5, r6 and r7. however, at one time the N79E715 can work with only one particular bank. the bank selection is done by setting rs1 - rs0 bits in the psw. the r0 and r1 registers are used to store the address for indirect accessing. r e g i s t e r b a n k 0 r e g i s t e r b a n k 1 r e g i s t e r b a n k 2 r e g i s t e r b a n k 3 0 3 0 2 0 1 0 0 0 4 0 5 0 6 0 7 0 b 0 a 0 9 0 8 0 c 0 d 0 e 0 f 1 3 1 2 1 1 1 0 1 4 1 5 1 6 1 7 1 b 1 a 1 9 1 8 1 c 1 d 1 e 1 f 2 3 2 2 2 1 2 0 2 4 2 5 2 6 2 7 2 b 2 a 2 9 2 8 2 c 2 d 2 e 2 f 3 3 3 2 3 1 3 0 3 4 3 5 3 6 3 7 3 b 3 a 3 9 3 8 3 c 3 d 3 e 3 f 4 3 4 2 4 1 4 0 4 4 4 5 4 6 4 7 4 b 4 a 4 9 4 8 4 c 4 d 4 e 4 f 5 3 5 2 5 1 5 0 5 4 5 5 5 6 5 7 5 b 5 a 5 9 5 8 5 c 5 d 5 e 5 f 6 3 6 2 6 1 6 0 6 4 6 5 6 6 6 7 6 b 6 a 6 9 6 8 6 c 6 d 6 e 6 f 7 3 7 2 7 1 7 0 7 4 7 5 7 6 7 7 7 b 7 a 7 9 7 8 7 c 7 d 7 e 7 f d i r e c t o r i n d i r e c t a c c e s s i n g r a m i n d i r e c t a c c e s s i n g r a m 0 0 h 0 7 h 2 8 h 0 8 h 0 f h 1 0 h 1 7 h 1 8 h 1 f h 2 0 h 2 1 h 2 2 h 2 3 h 2 4 h 2 5 h 2 6 h 2 7 h 2 9 h 2 a h 2 b h 2 c h 2 d h 2 e h 2 f h 3 0 h 7 f h 8 0 h f f h 0 0 h f f h
n79e 71 5 datasheet jan. 6 , 201 6 page 20 of 189 revision 1.0 1 6.8 bit - addressable locations the scratch - pad ram area from location 20h to 2fh is byte as well as bit - addressable. this means that a bit in this area can be i ndividually addressed. in addition , some of the sfrs are also bit - addressable. the instruction decoder is able to distinguish a bit access from a byte access by the type of the instruction itself. in the sfr area, any existing sfr whose ad dress ends in a 0 or 8 is bit - addressable. 6.9 stack the scratch - pad ram can be used for the stack. this area is selected by the stack pointer (sp), which stores the address of the top of the stack. whenever a jump, call or interrupt is invoked , the return address is placed o n the stack. there is no restriction as to where the stack can begin in the ram. by default , however, the stack pointer contains 07h at reset. the user can then change this to any value desired. the sp will point to the last used value. therefore, the sp w ill be incremented and then address saved onto the stack. conversely, while popping from the stack the contents will be read first, and then the sp is decreased.
n79e 71 5 datasheet jan. 6 , 201 6 page 21 of 189 revision 1.0 1 7 special function register (sfr ) the N79E715 use s special function registers (sfrs) to control and monitor peripherals and their m odes. the sfrs reside in the register locations 80 ~ ff h and are accessed by direct addressing only. some of the sfrs are bit - addressable . this is very useful in cases where user would like to modify a particular bit direct ly without changing other bits . those that are bit - addressable sfrs end their addresses as 0 h or 8 h . the N79E715 contain s all the sfrs present ing in the standard 8051 . however, some additional sfrs are built in . therefore, some of unused byte s in the origi nal 8051 have been given new functions. the sfrs are listed as follows . table 7 C 1 N79E715 special function registers (sfr) mapping f8 adccon0 - - - - - - eip ff f0 b - - spcr spsr spdr p 0 dids eiph f7 e8 eie kbi e kbif kbls0 kbls1 c2l c2h - ef e0 acc adccon1 adch - c0l c0h c1l c1h e7 d8 wdcon0 * pwmpl pwm0l pwm1l pwmcon 0 pwm2l pwm3l pwmcon 1 df d0 psw pwmph pwm0h pwm1h - pwm2h pwm3h pwmcon 2 d7 c8 t2con t2mod rcomp2l rcom2h tl2 th2 - - cf c0 i2con i2addr - - - - - ta c7 b8 ip saden - - i2dat i2sta i2clk i2toc bf b0 p3 p0m1 p0m2 p1m1 p1m2 p2m1 p2m2 iph b7 a8 ie saddr - wdcon1 * - - ispfd ispcn af a0 p2 - auxr1 pmcr * isptrg * - ispal ispah a7 98 scon sbuf - - shbda * - - chpcon * 9f 90 p1 - capcon0 capcon1 c apcon 2 divm p3m1 p3m2 97 88 tcon tmod tl0 tl1 th0 th1 ckcon - 8f 80 p0 sp dpl dph - - - pcon 87 in bold bit - addressable - reserved note: 1. the reserved sfr addresses should be kept in their own initial states. user should never change their values. 2. the sfrs in the column with dark borders are bit - addressable * with ta - protection. (time access protection)
n79e 71 5 datasheet jan. 6 , 201 6 page 22 of 189 revision 1.0 1 table 7 C 2 N79E715 s fr description and reset value s symbol d efinition a ddress msb lsb reset value [1] eip interrupt priority 1 ffh pt2 pspi ppwm pwdi - - pkb pi2 00 00 0000b adccon 0 adc control register 0 f8h (f f ) adc.1 ( fe) adc.0 (fd) adcex (fc) adci (fb) adcs (fa) aadr2 (f9) aadr1 (f8) aadr0 00 00 00 00b eiph interrupt hig h priority 1 f7h pt2h pspih ppwmh pwdih - - pkbh pi2h 0000 0000b p0dids port 0 digital input dis a ble f6h p0dids[7:0] 0000 0000b spdr serial peripheral data register f5h spdr[7:0] 0000 0000 b spsr serial peripheral status register f4h spif wcol spiovf mod f dismodf - - - 0000 0 000b spcr serial peripheral control register f3h ssoe spien lsbfe mstr cpol cpha spr1 spr0 0000 0100b b b register f0h (f7) b.7 (f6) b.6 (f5) b.5 (f4) b.4 (f3) b.3 (f2) b.2 (f1) b.1 (f0) b.0 0000 0000b c2h input capture 2 high eeh c2h[7:0] 0000 0000b c2l input capture 2 low edh c2l[7:0] 0000 0000b kbls1 keyboard level select 1 ech kbls1[7:0] 0000 0000b kbls0 keyboard level select 0 ebh kbls0[7:0] 0000 0000b kbif kbi interrupt flag eah kbif[7:0] 0000 0000b kbie keyboard interrup t en a ble e9h kbie[7:0] 0000 0000b eie interrupt enable 1 e8h (ef) et2 (ee) espi (ed) epwm (ec) ewdi (e7) (e8) ecptf (e9) ekb (e8) ei2 c 0000 0000b c1h input capture 1 high e7h c1h[7:0] 0000 0000b c1l input capture 1 low e6h c1l[7:0] 0000 0000b c0h inpu t capture 0 high e5h c0h[7:0] 0000 0000b c0l input capture 0 low e4h c0l[7:0] 0000 0000b adch adc converter result e2h adc.9 adc.8 adc.7 adc.6 adc.5 adc.4 adc.3 adc.2 0000 0000 b adccon1 adc control register1 e1h adcen - - - - - rcclk adc0sel 0000 0000b acc accumulator e0h (e7) acc.7 (e6) acc.6 (e5) acc.5 (e4) acc.4 (e3) acc.3 (e2) acc.2 (e1) acc.1 (e0) acc.0 0000 0000b pwmcon1 pwm control register 1 dfh bkch bkps bpen bken pwm3b pwm2b pwm1b pwm0b 0000 0000b pwm3l pwm 3 low bits register deh pwm3.7 pwm 3.6 pwm3.5 pwm3.4 pwm3.3 pwm3.2 pwm3.1 pwm3.0 0000 0000b pwm2l pwm 2 low bits register ddh pwm2.7 pwm2.6 pwm2.5 pwm2.4 pwm2.3 pwm2.2 pwm2.1 pwm2.0 0000 0000b pwmcon0 pwm control register 0 dch pwmrun load cf clrpwm pwm3i pwm2i pwm1i pwm0i 0000 0000b pwm 1l pwm 1 low bits register dbh pwm1.7 pwm1.6 pwm1.5 pwm1.4 pwm1.3 pwm1.2 pwm1.1 pwm1.0 0000 0000b pwm0l pwm 0 low bits register dah pwm0.7 pwm0.6 pwm0.5 pwm0.4 pwm0.3 pwm0.2 pwm0.1 pwm0.0 0000 0000b pwmpl pwm counter low regi s ter d9h pwmp0.7 pwmp0.6 pwmp 0.5 pwmp0.4 pwmp0.3 pwmp0.2 pwmp0.1 pwmp0.0 0000 0000b wdcon0 [4][3] watch - dog control 0 d8h (df) wdten (de) wdclr (dd) wdtf (dc) widpd (db) wdtrf (da) wps2 (d9) wps1 (d8) wps0 power - on c000 0000b watch reset c0uu 1uuub other reset c0uu uuuub pwmcon2 pwm control register 2 d7h - - - - fp1 fp0 - bkf 0000 0000b pwm3h pwm 3 high bits register d6h - - - - - - pwm3.9 pwm3.8 0000 0000b pwm2h pwm 2 high bits register d5h - - - - - - pwm2.9 pwm2.8 0000 0000b pwm1h pwm 1 high bits register d3h - - - - - - pwm1.9 pwm1.8 0000 0000b pwm0h pwm 0 high bits register d2h - - - - - - pwm0.9 pwm0.8 0000 00 00b pwmph pwm counter high regi s ter d1h - - - - - - pwmp0.9 pwmp0.8 0000 0000b
n79e 71 5 datasheet jan. 6 , 201 6 page 23 of 189 revision 1.0 1 table 7 C 2 N79E715 s fr description and reset value s symbol d efinition a ddress msb lsb reset value [1] psw program status word d0h (d7) cy (d6) ac (d5) f0 (d4) rs1 (d3) rs0 (d2) ov (d1) f1 ( d0) p 0000 0000b th2 timer 2 msb cdh th2[7:0] 0000 0000b tl2 timer 2 lsb cch tl2[7:0] 0000 0000b rcomp2h timer 2 reload msb cbh rcomp2h[7:0] 0000 0000b rcomp2l timer 2 reload lsb cah rcompl2[7:0] 0000 0000b t2mod timer 2 mode c9h lden t2div[2:0] capcr compcr ldts[1:0] 0000 0000b t2con timer 2 control c8h (cf) tf2 - - - - (ca) tr2 - (c8) 0 000 0 0 0 0b ta timed access protection c7h 1111 1111 b i2addr i2c address c1h addr[7:1] gc 0000 000 0b i2con i2c control register c0h (c 7 ) - (c 6 ) i2cen (c 5 ) sta (c 4 ) sto (c 3 ) si (c 2 ) aa (c 1 ) - (c0 ) - 0000 0000 b i2toc i2c time - out counter register bfh - - - - - i2tocen div i2tof 0000 0000b i2clk i2c clock rate beh i2clk[7:0] 0000 0000b i2sta i2c status register bdh i2sta [7:3 ] 0 0 0 1111 1000b i2dat i2c data register bch i2dat[7:0] 0000 0000 b saden slave address mask b9h saden[7:0] 0000 0000b ip interrupt priority b8h (bf) pcap (be) padc (bd) pbo d (bc) ps (bb) pt1 (ba) px1 (b9) pt0 (b8) px0 0 000 0000b iph interrupt high priority b7h pcaph pad ch pbo d h psh pt1h px1h pt0h px0h 0 000 0000b p2m2 port 2 output mode 2 b6h p2m2[7:0] 0000 00 00b p2m1 port 2 output mode 1 b5h p2m1[7:0] 0000 0000b p1m2 port 1 output mode 2 b4h p1m2.7 p1m2.6 - p1m2.4 p1m2.3 p1m2.2 p1m2.1 p1m2.0 0000 0000b p1m1 port 1 ou tput mode 1 b3h p1m1.7 p1m1.6 - p1m1.4 p1m1.3 p1m1.2 p1m1.1 p1m1.0 0000 0000b p0m2 port 0 output mode 2 b2h p0m2[7:0] 0000 0000b p0m1 port 0 output mode 1 b1h p0m1[7:0] 0000 0000b p3 port3 b0h - - - - - - (b1) x1 (b0) x2 clkout 0000 00 11 b ispcn isp con trol register afh ispa17 ispa16 foen fcen fctrl3 fctrl2 fctrl1 fctrl0 0011 0000b ispfd isp flash data register aeh ispfd[7:0] 0000 0000b wdcon1 [4] watch - dog control1 abh - - - - - - - ewrst 0000 0000b saddr slave address a9h saddr[7:0] 00000000b ie int errupt enable a8h (af) ea (ae) eadc (ad) ebod (ac) es (ab) et1 (aa) ex1 (a9) et0 (a8) ex0 0000 0000b ispah isp flash address high - byte a7h ispah[7:0] 0000 0000b ispal isp flash address low - byte a6h ispal[7:0] 0000 0000b isptrg [4] isp trigger register a4 h - - - - - - - ispgo 0000 000 0b pmcr [2][4] power monitor control register a3h boden bov - borst bof - - bos power - on cc0c 100xb bor reset uu0u 100x b other reset uu 0u 000x b auxr1 aux function register a2h spi_sel uart_sel - - disp26 - 0 dps 0000 0000b p2 port 2 a0h (97) (96) (95) (94) (93) (92) (91) (90) 1111 1111b rl2 cp/
n79e 71 5 datasheet jan. 6 , 201 6 page 24 of 189 revision 1.0 1 table 7 C 2 N79E715 s fr description and reset value s symbol d efinition a ddress msb lsb reset value [1] p27 p26 p25 p24 p23 p22 p21 p20 chpcon [4] chip control 9fh swrst ispf ldue - - - bs [3] ispen power - on 0000 00c0b other reset 000 0 00 c 0b shbda [4] high - byte data flash start address 9ch shbd a[7:0], shbda initial by chbda power on cccc ccccb other reset uuuu uuuub sbuf serial buffer 99h sbuf.7 sbuf.6 sbuf.5 sbuf.4 sbuf.3 sbuf.2 sbuf.1 sbuf.0 0000 0000b scon serial control 98h (9f) sm0/fe (9e) sm1 (9d) sm2 (9c) ren (9b) tb8 (9a) rb8 (99) ti ( 98) ri 0000 0000b p3m2 port 3 output mode 2 97h - - - - - enclk p3m2.1 p3m2.0 00000 000b p3m1 port 3 output mode 1 96h p3s p2s p1s p0s t1oe t0oe p3m1.1 p3m1.0 00000000b divm cpu clock divide regi s ter 95h divm[7:0] 0000 0000b capcon2 input capture contro l 2 94h - enf2 enf1 enf0 - - - - 0000 0000b capcon1 input capture control 1 93h - - cap2ls1[2:0] cap1ls1[2:0] cap1ls1[2:0] 0000 0000b capcon0 input capture control 0 92h - capen2 capen1 capen0 - capf2 capf1 capf0 0000 0000b p1 port 1 90h (97) p17 (96) p 16 - (94) p14 (93) p13 (92) p12 (91) p11 (90) p10 1111 1111b ckcon clock control 8eh - - - t1m t0m - - - 000 0 0 000 b th1 timer high 1 8dh th1[7:0] 0000 0000b th0 timer high 0 8ch th0[7:0] 0000 0000b tl1 timer low 1 8bh tl1[7:0] 0000 0000b tl0 timer low 0 8ah tl0[7:0] 0000 0000b tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 0000 0000b tcon timer control 88h (8f) tf1 (8e) tr1 (8d) tf0 (8c) tr0 (8b) ie1 (8a) it1 (89) ie0 (88) it0 0000 0000b pcon power control 87h smod smod0 - pof gf1 gf0 pd idl powe r - on 0001 0000b other reset 000u 0000b dph data pointer high 83h dph[7:0] 0000 0000b dpl data pointer low 82h dpl[7:0] 0000 0000b sp stack pointer 81h sp[7:0] 0000 0111b p0 port 0 80h (87) p07 (86) p06 (85) p05 (84) p04 (83) p03 (82) p02 (81) p01 (80) p00 1111 1111b note: bits marked in " - " should be kept in their own initial states. user should never change their va l ues. note: [1.] ( ) item means the bit address in bit - addressable sfrs. [2.] bod en , bo v and borst are initialized by config2 at power - on reset, an d keep unchanged at any other resets. if bod en =1, bof will be automatically set by hardware at power - on reset, and keeps unchanged at any other resets. [3.] initialized by power - on reset. wdten =/c wdten ; bs=/cbs; [4.] with ta - protection. (time access protection) [5.] not ation c means the bit is defined by config - bits ; u means the bit is unchanged after any reset except power - on reset. [6.] reset value symbol description. 0: logic 0, 1: logic 1, u: unchanged, x: c: initial by config . .
n79e 71 5 datasheet jan. 6 , 201 6 page 25 of 189 revision 1.0 1 8 general 80 c 51 system control a or acc C accumulator (bit - addressable) 7 6 5 4 3 2 1 0 acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 r/w r/w r/w r/w r/w r/w r/w r/w address: e0h reset value: 0000 0000b bit name description 7:0 acc[7:0] accumulator the a or acc register is the standard 805 1 accumulator for arithmetic operation. b C b register (bit - addressable) 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 r/w r/w r/w r/w r/w r/w r/w r/w address: f0h reset value: 0000 0000b bit name description 7:0 b[7:0] b r egister the b register is the other accumulator of the standard 8051 . it is used mainly for mul and div operations. sp C stack pointer 7 6 5 4 3 2 1 0 sp[7:0] r/w address: 81h reset value: 0000 0111b bit name description 7:0 sp[7:0] stack pointer the stack pointer stores the s cratch - pad ram address where the stack begins. it is incremented before data is stored during push or call instructions. note that the default value of sp is 07h. it causes the stack to begin at location 08h.
n79e 71 5 datasheet jan. 6 , 201 6 page 26 of 189 revision 1.0 1 dpl C data pointer low byte 7 6 5 4 3 2 1 0 d pl [7:0] r/w address: 8 2 h reset value: 0000 0000b bit name description 7:0 dpl [7:0] data pointer low b yte this is the low byte of the standard 8051 16 - bit data pointer. dpl com bined with dph serve as a 16 - bit data pointer dptr to address non - scratch - pad memory or program memory . dph C data pointer high byte 7 6 5 4 3 2 1 0 dph[7:0] r/w address: 83h reset value: 0000 0000b bit name description 7:0 dph[7:0] data pointer high byte this is the high byte of the standard 8051 16 - bit data pointer. dph com bi ned with dpl serve as a 16 - bit data pointer dptr to address non - scratch - pad memory or program memory . psw C program status word (bit - addressable) 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p r/w r/w r/w r/w r/w r/w r/w r address: d0 h reset value: 0000 000 0b bit name description 7 cy carry f lag for a adding or subtracting operation, cy will be set when the previous operation resulted in a carryout from or a borrow - in to the most significant bit, otherwise cleared. if the previous operation is mul or div, c y is always 0. cy is affected by da an instruction that indicates that if the original bcd sum is greater than 100. for a cjne branch, cy will be set if the first unsigned integer value is less than the second one. otherwise, cy will be cleared. 6 ac auxi liary c arry set when the previous operation resulted in a carryout from or a borrow - in to the 4th bit of the low order nibble, otherwise cleared.
n79e 71 5 datasheet jan. 6 , 201 6 page 27 of 189 revision 1.0 1 bit name description 5 f0 user f lag 0 the general - purpose flag that can be set or cleared by the user. 4 rs1 register bank select ing bits the two bits select one of four banks in which r0 ~ r7 locate. rs1 rs0 register bank ram address 0 0 0 00 ~ 07 h 0 1 1 08 ~ 0f h 1 0 2 10 ~ 17 h 1 1 3 18 ~ 1f h 3 rs0 2 ov overflow f lag ov is used for a signed character operands. for an add or addc ins truction, ov will be set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not bit 6. otherwise, ov is cleared. ov indicates a negative number produced as the sum of two positive operands or a positive sum from two negative ope r ands. for a subb, ov is set if a borrow is needed into bit6 but not into bit 7, or into bit7 but not bit 6. otherwise, ov is cleared. ov indicates a negative number produced when a negative value is subtracted from a positive value or a positive resul t when a positive number is subtracted from a negative number. for a mul, if the product is greater than 255 ( 0 0ffh), ov will be set. otherwise, it is cleared. for a div, it is normally 0. however, if b had originally contained 00h, the values returned in a and b will be undefined. meanwhile, the ov will be set. 1 f1 user f lag 1 the g eneral purpose flag that can be set or cleared by the user via software . 0 p parity f lag set to 1 to indicate an odd number of ones in the accumulator. cleared for an even nu mber of ones. it performs even parity check. table 8 C 1 instructions that a ffect f lag s ettings instruction cy ov ac instruction cy ov ac add x [1] x x clr c 0 addc x x x cpl c x subb x x x anl c, bit x mul 0 x anl c, /bit x div 0 x orl c, bit x da a x orl c, /bit x rrc a x mov c, bit x
n79e 71 5 datasheet jan. 6 , 201 6 page 28 of 189 revision 1.0 1 instruction cy ov ac instruction cy ov ac rlc a x cjne x setb c 1 [1] x indicates the modification is depend ent on the result of the instruction pcon C power control 7 6 5 4 3 2 1 0 smod smod0 - pof gf1 gf0 pd idl r/w r/w - r/w r/w r/w r/w r/w address: 87h reset value: see table 7 C 2 N79E715 s fr description and reset value s bit name description 3 gf1 general p urpose f lag 1 the general purpose flag that can be set or cleared by the user. 2 gf0 general p urpose f lag 0 the general purpose flag that can be set or cleared by the user. general 80c51 support one dptr but the N79E715 support two dptrs by switching auxr1.dps. the setting is as follows. auxr1 C aux function resgister - 1 7 6 5 4 3 2 1 0 spi_sel uart_sel - - disp26 - 0 dps r/w r/w - - r/w - r r/w address: a2h reset value: 0000 0000b bit name description 0 dps dual data pointer select ion 0 = s elect dptr of standard 8051. 1 = s elect dptr1
n79e 71 5 datasheet jan. 6 , 201 6 page 29 of 189 revision 1.0 1 9 i/o port s tructure and o peration for N79E715 , there are four i/o ports port 0, port 1, port2 and port 3. if us ing hirc and reset pin configurations, the N79E715 can support up to 25 pins. all i/o pins besides p1.2 and p1.3 can be configured to one of four types by software as shown in the following table. table 9 C 1 setting table for i/o ports structure pxm1.y pxm2.y port i/o mode 0 0 quasi - bidirectional 0 1 push - pull 1 0 input only (high impedance) 1 1 open drain note: p1.2 and p1.3 are no t effect ive in this table. after re set, these pins are in quasi - bidirectional mode except p1.2 and p1.3 pins . the p1.2 and p1.3 are dedicating open - drain pin for i2c interface after reset. each i/o port of N79E715 may be selected to use ttl level inputs or schmitt inputs by p(n)s bit on p3 m1 register; where n is 0, 1 , 2 or 3 . when p(n)s is set to 1, ports are selected schmitt trigger inputs on port(n). the p 3 .0 (xtal2) can be configured as clock output when used hirc or external crystal is clock source, and the frequency of clock output is divided by 4 hirc clock or external crystal . 9.1 quasi - bidirectional output configuration the default port configuration for standard N79E715 i/o ports is q uasi - bidirectional mode that is common on the 80c51 and most of its derivatives. this type rule s as b oth input and output. when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is pulled low, it is driven strongly and able to sink a large current. in the quasi bidirectional i/o structure, th ere are three pull - up transistors. each of them serves different purposes. one of these pull - ups, called the very weak pull - up, is turned on whenever the port latch contains logic 1. the very weak pull - up sources a very small current that will pull the pin high if it is left floating. a second pull - up, called the weak pull - up, is turned on when the outside port pin itself is at logic 1 level. this pull - up provides the pri mary source current for a quasi - bidirectional pin that is outputting 1. if a pin that has logic 1 on it is pulled low by an external device, the weak pull - up turns off, and only the very weak pull - up remains on. to pull the pin low under these conditions, the external device has
n79e 71 5 datasheet jan. 6 , 201 6 page 30 of 189 revision 1.0 1 to sink enough current (larger than i tl ) to overcome the weak pull - up and make the voltage on the port pin below its input threshold (lower than v il ) . the third pull - up is the strong pull - up. this pull - up is used to speed up low - to - high transitions on a quasi - bidirectional port pin when the port latch ch anges from logic 0 to logic 1. when this occurs, the strong pull - up turns on for two - peripheral - clock time to pull the port pin high quickly. then it turns off and weak: pull - up continues remaining the port pin high . the quasi bidirectional port structure is shown below . figure 9 - 1 quasi bi - direction i/o structure 9.1.1 read - modify - write in the standard 8051 instruction set, user should watch out for one kind of instructions, read - modi fy - write instructions. instead of the normal instructions, the read - modify - write instructions read the internal port latch (p x in sfrs) rather than the external port pin state. this kind of instructions read the port sfr value, modify it and write back to the port sfr. read - modify - write instructions are listed as follows. in s truction description anl logical and. (anl px,a and anl px,direct) orl logical or. (orl px,a and orl px,direct) xrl logical exclusive or. (xrl px,a and xrl px,direct) jbc jump if b it = 1 and clear it. (jbc px.y,label) cpl complement bit. (cpl px.y) inc increment. (inc px) dec decrement. (dec px) djnz decrement and jump if not zero. (djnz px,label) p o r t p i n 2 - p e r i p h e r a l - c l o c k d e l a y i n p u t p o r t l a t c h p p p n v d d s t r o n g v e r y w e a k w e a k
n79e 71 5 datasheet jan. 6 , 201 6 page 31 of 189 revision 1.0 1 mov px.y,c move carry bit to px.y. clr px.y clear bit px.y. setb px.y set bit p x.y. the last three seems not obvious ly read - modify - write instructions but actually they are. they read the entire port latch value , modify the changed bit, and then write the new value back to the port latch. 9.2 open drain output configuration the open drain output configuration turns off all pull - ups and only drives the pull - down transistor of the port driver when the port latch contains logic 0. to be used as a logic output, a port configured in this manner should have an external pull - up, typically a resis tor tied to v dd . the pull - down for this mode is the same as for the quasi - bidirectional mode. the open drain port configuration is shown below . figure 9 - 2 open drain output 9.3 push - pull output configuration the push - pull output configuration has the same pull - down structure as both the open drain and the quasi - bidirectional output modes, but provides a continuous strong pull - up when the port latch contains logic 1. the push - pull mod e may be used when more source current is needed from a port output. the push - pull port co n figuration is shown in figure 9 - 2 . the two port pins that cannot be configured are p1.2 (scl) and p1.3 (sda) . the port pins p1.2 and p1.3 are permanently configured as open drain outputs. they may be used as inputs by writing ones to their respective port latches. additionally, port pins p3.0 and p3 .1 are disabled for both input and output if one of the crystal oscillator options is chosen. those options are described in the oscillator se c tion. when port pins are driven high at reset, they are in quasi - bidirectional mode and therefore do not source large amounts of current. every output on the N79E715 may potentially be used as a 38 ma sink led drive output. however, t here is a maximum total output current for all ports which should not be exceeded. all port pins of the N79E715 have slew rate controlled outputs. this is to limit noise generated by quickly switching output signals. the slew rate is factory set to approxi mately 10 ns rise and fall times. p o r t p i n p o r t l a t c h d a t a n i n p u t d a t a
n79e 71 5 datasheet jan. 6 , 201 6 page 32 of 189 revision 1.0 1 the bits in the p 3 m1 register that are not used to control configuration of p 3.1 and p3 .0 are used for other purposes. these bits can enable schmitt trigger inputs on each i/o port, enable toggle outputs from timer 0 and t i m er 1, and enable a clock output if either the hirc or external clock input is being used. the last two functions are described in the timers/counters and oscillator sections respectively. each i/o port of the N79E715 may be selected to use ttl level inpu ts or schmitt inputs with hysteresis. a single co n figuration bit determines this selection for the entire port. figure 9 - 3 push - pull output 9.4 input only configuration by setting t his mode , the ports are only input mode . after setting this mode, the pin will be hi - impendence . p0 C port 0 (bit - addressable) 7 6 5 4 3 2 1 0 p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p01 p00 r/w r/w r/w r/w r/w r/w r/w r/w address: 80 h reset value: 1111 1111b bit name description 7:0 p0[7:0] port 0 port 0 is an 8 - bit quasi bidirectional i/o port. p o r t p i n i n p u t d a t a p o r t l a t c h d a t a p n v d d
n79e 71 5 datasheet jan. 6 , 201 6 page 33 of 189 revision 1.0 1 p1 C port 1 (bit - addressable) 7 6 5 4 3 2 1 0 p17 p16 - p14 p13 p12 p11 p10 r/w r/w - r/w r/w r/w r/w r/w address: 90h reset value: 1111 1111b bit name description 7:0 p1 [7:0] port 1 these pins are in quasi - bidirectional mode except p1.2 and p1.3 pins. the p1.2 and p1.3 are dedicating open - drain pin s for i 2 c interface after reset. p2 C port 2 (bit - addressable) 7 6 5 4 3 2 1 0 p27 p26 p25 p24 p23 p22 p21 p20 r/w r/w r/w r/w r/w r/w r/w r/w address: a0h reset value: 1111 1111b bit name description 7:0 p2[7:0] port 2 port 2 is an 8 - bit quasi bidirectional i/o port. p3 C port 3 (bit - addressable) 7 6 5 4 3 2 1 0 - - - - - - p31 p30 - - - - - - r/w r/w address: b0h rese t value: 0000 0011b bit name description 7:2 - reserved 1 p3.1 x1 or i/o pin by alternative. 0 p3.0 x2 or clkout or i/o pin by alternative.
n79e 71 5 datasheet jan. 6 , 201 6 page 34 of 189 revision 1.0 1 p0m1 C port 0 o utput mode 1 7 6 5 4 3 2 1 0 p0m1.7 p0m1.6 p0m1.5 p0m1.4 p0m1.3 p0m1.2 p0m1.1 p0m1.0 r/w r/w r/ w r/w r/w r/w r/w r/w address: b1h reset value: 0000 0000b p0m2 C port 0 o utput mode2 7 6 5 4 3 2 1 0 p0m2.7 p0m2.6 p0m2.5 p0m2.4 p0m2.3 p0m2.2 p0m2.1 p0m2.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b2h reset value: 0000 0000b p1m1 C port 1 o utput mode 1 7 6 5 4 3 2 1 0 p1m1.7 p1m1.6 - p1m1.4 p1m1.3 p1m1.2 p1m1.1 p1m1.0 r/w r/w - r/w r/w r/w r/w r/w address: b3h reset value: 0000 0000b p1m2 C port 1 o utput mode2 7 6 5 4 3 2 1 0 p1m2.7 p1m2.6 - p1m2.4 p1m2.3 p1m2.2 p1m2.1 p1m2.0 r/w r/w - r/w r/w r/ w r/w r/w address: b4h reset value: 0000 0000b p2m1 C port 2 o utput mode 1 7 6 5 4 3 2 1 0 p2m1.7 p2m1.6 p2m1.5 p2m1.4 p2m1.3 p2m1.2 p2m1.1 p2m1.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b5h reset value: 0000 0000b p2m2 C port 2 o utput mode 2 7 6 5 4 3 2 1 0 p2m2.7 p2m2.6 p2m2.5 p2m2.4 p2m2.3 p2m2.2 p2m2.1 p2m2.0 r/w r/w r/w r/w r/w r/w r/w r/w address: b6h reset value: 0000 0000b p3m1 C port3 output mode 1 7 6 5 4 3 2 1 0 p3s p2s p1s p0s t1oe t0oe p3m1.1 p3m1.0 r/w r/w r/w r/w r/w r/w r/w r/w ad dress: 96h reset value: 0000 0000b bit name description 7 p3s enable schmitt trigger inputs on port 3. 6 p2s enable schmitt trigger inputs on port 2. 5 p1s enable schmitt trigger inputs on port 1.
n79e 71 5 datasheet jan. 6 , 201 6 page 35 of 189 revision 1.0 1 bit name description 4 p0s enable schmitt trigger inputs on port 0. 1 p3m1. 1 c ontrol the output configuration of p3.1. 0 p3m1.0 c ontrol the output configuration of p3.0. p3m2 C port3 output mode2 7 6 5 4 3 2 1 0 - - - - - enclk p3m2.1 p3m2.0 - - - - - r/w r/w r/w address: 97h reset value: 0000 0000b bit name description 7:3 - reserved 0 enclk c lock output to xtal2 pin (p3.0) enable if the clock is from hirc , the frequency of p3.0 is f hirc /4. 1 p3m2.1 refer to table 9 - 1 setting table for i/o port s tructure 0 p3m2.0
n79e 71 5 datasheet jan. 6 , 201 6 page 36 of 189 revision 1.0 1 10 timers/counters the N79E715 has three 16 - bi t programmable timer s /counters. 10.1 timer s /counters 0 and 1 timer/counter 0 and 1 in N79E715 are two 16 - bit timer s /c ounters. each of them has two 8 - bit registers that form the 16 - bit counting register. for timer/coun ter 0 they are t h0, the upper 8 - bi t register, and tl0, the lower 8 - bit register. similar timer/counter 1 has two 8 - bit registers, th1 and tl1. tcon and tmod can configure modes of timer/counter 0 and 1. they have additional timer 0 or timer 1 overflow toggle output enable feature as compare to conventional ti m ers/counters . this timer overflow toggle output can be configured to automatically toggle t0 or t1 pin output whenever a timer overflow occurs. when configured as a timer, the timer counts clock cycles. the timer c lock can be programmed to be thought of as 1/12 of the clock system or 1/4 of the clock system . in the counter mode, the register is incr e mented on the falling edge of the external input pin, t0 in case of timer 0, and t1 for timer 1. the t0 and t1 input s are sampled in every machine - cycle at c4. if the sampled value is high in one machine - cycle and low in the next, then a valid high to low transition on the pin is recognized and the count register is incremented. since it takes two machine - cycles to reco gnize a negative transition on the pin, the maximum rate at which counting will take place is 1/24 of the master clock frequency. in either the timer or counter mode, the count register will be updated at c3. therefore, in the timer mode, the recogni zed negative transition on pin t0 and t1 can cause the count register value to be updated only in the machine - cycle following the one in which the negative edge was detected. the timer or counter function is selected by the bit in the tmod special function register. each timer/counter has one selection bit for its own; bit 2 of tmod selects the function for timer/counter 0 and bit 6 of tmod selects the function for timer/counter 1. in addition each timer/counter can be set to op erate in any one of four possible modes. the mode selection is done by bits m0 and m1 in the tmod sfr. the N79E715 can operate like the standard 8051/52 family, counting at the rate of 1/12 of the clock speed, or in turbo mode, counting at the rate of 1/4 clock speed. the speed is controlled by the t0m and t1m bits in ckcon, and the default value is zero, which uses the standard 8051/52 speed. t c/
n79e 71 5 datasheet jan. 6 , 201 6 page 37 of 189 revision 1.0 1 ckcon C clock control 7 6 5 4 3 2 1 0 - - - t1m t0m - - - - - - r/w r/w - - - address: 8eh reset value: 0000 00 00b bit name description 7:5 - reserved 4 t1m timer 1 clock selection 0 = timer 1 uses a divide by 12 clocks. 1 = timer 1 uses a divide by 4 clocks. 3 t0m timer 0 clock selection 0 = timer 0 uses a divide by 12 clocks. 1 = timer 0 uses a divide by 4 cloc ks. 2:0 - reserved tmod C timer 0 and 1 mode 7 6 5 4 3 2 1 0 gate m1 m0 gate m1 m0 r/w r/w r/w r/w r/w r/w r/w r/w address: 89h reset value: 0000 0000b bit name description 7 gate timer 1 gate c ontrol 0 = timer 1 will clock when tr1 = 1 regardless of logic level. 1 = timer 1 will clock only when tr1 = 1 and is logic 1. 6 timer 1 counter/timer selection 0 = timer 1 is incremented by inte rnal peripheral clocks. 1 = timer 1 is incremented by the falling edge of the external pin t1. 5 m1 timer 1 mode selection m 1 m 0 timer 1 mode 0 0 mode 0: 8 - bit timer/counter with 5 - bit pre - scalar (tl1[4:0]) 0 1 mode 1: 16 - bit timer/counter 1 0 mode 2 : 8 - bit timer/counter with auto - reload from th1 1 1 mode 3 : timer 1 halted 4 m0 3 gate timer 0 gate control 0 = timer 0 will clock when tr0 = 1 regardless of logic level. 1 = timer 0 will clock only when tr 0 = 0 and is logic 1. t c/ t c/ 1 int 1 int t c/ nt0 i 0 int
n79e 71 5 datasheet jan. 6 , 201 6 page 38 of 189 revision 1.0 1 bit name description 2 timer 0 counter/timer selection 0 = timer 0 is incremented by internal peripheral clocks. 1 = timer 0 is incremented by the falling edge of the external pin t0. 1 m1 timer 0 mode selection m 1 m 0 timer 0 mode 0 0 mode 0: 8 - bit timer/counter with 5 - bit pre - scalar (tl0[4:0]) 0 1 mode 1: 16 - bit timer/counter 1 0 mode 2 : 8 - bit timer/counter with auto - reload from th0 1 1 mode 3 : tl0 as a 8 - bit timer/counter and th0 as a 8 - bit timer 0 m0 tcon C timer 0 and 1 control (bit - addressable) 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 r/w r/w r/w r/w r/w r/w r/w r/w address: 8 8 h reset value: 0000 0000b bit name description 7 tf1 timer 1 o verflow f lag this bit is set when timer 1 overflows. it is automaticall y cleared by hardware when the program executes the timer 1 interrupt service routine. software can also set or clear this bit. 6 tr1 timer 1 r un c ontrol 0 = timer 1 is halted. clearing this bit will halt timer 1 and the current count will be preserved in th1 and tl1. 1 = timer 1 is enabled. 5 tf0 timer 0 o verflow f lag this bit is set when timer 0 overflows. it is automatically cleared via hardware when the program executes the timer 0 interrupt service routine. software can also set or clear this bit. 4 tr0 timer 0 r un c ontrol 0 = timer 0 is halted. clearing this bit will halt timer 0 and the current count will be preserved in th0 and tl0. 1 = timer 0 is enabled. t c/
n79e 71 5 datasheet jan. 6 , 201 6 page 39 of 189 revision 1.0 1 tl0 C timer 0 low byte 7 6 5 4 3 2 1 0 tl0 [7:0] r/w address: 8 a h reset value: 0000 0000b bit name description 7:0 tl0[7:0] timer 0 l ow b yte the tl0 register is the low byte of the 16 - bit timer 0. th0 C timer 0 high byte 7 6 5 4 3 2 1 0 th0[7:0] r/w address: 8ch reset value: 0000 0000b bit name description 7:0 th0[7:0] timer 0 h igh b yte the th0 register is the high byte of the 16 - bit timer 0. tl1 C timer 1 low byte 7 6 5 4 3 2 1 0 tl1[7:0] r/w address: 8bh reset value: 0000 0000b bit name description 7:0 tl1[7:0] timer 1 l ow b yte the tl1 register is the low byte of the 16 - bit timer 1 . th 1 C timer 1 high byte 7 6 5 4 3 2 1 0 th1[7:0] r/w address: 8dh reset value: 0000 0000b bit name description 7:0 th1[7:0] timer 1 h igh b yte the th1 register is the high byte of the 16 - bit timer 1.
n79e 71 5 datasheet jan. 6 , 201 6 page 40 of 189 revision 1.0 1 p3m1 C port3 output mode1 7 6 5 4 3 2 1 0 p3s p2 s p1s p0s t1oe t0oe p3m1.1 p3m1.0 r/w r/w r/w r/w r/w r/w r/w r/w address: 96h reset value: 0000 0000b bit name description 3 t1oe p0.7 pin is toggled whenever timer 1 overflows. the output frequency is therefore one half of the timer 1 overflow rate. 2 t0oe p1.2 pin is toggled whenever timer 0 overflows. the output frequency is therefore one - half of the timer 0 overflow rate. 10.1.1 mode 0 (13 - bit timer) in mode 0, the timers/counters act as a 8 - bit counter with a 5 - bit, divide by 32 pre - scale. in this mode we have a 13 - bit timer/counter. the 13 - bit counter consists of 8 bits of thx and 5 lower bits of tlx. the upper 3 bits of tlx are ignored. the negative edge of the clock is increments count in the tlx register. when the fifth bit in tlx moves from 1 to 0, then the count in the thx register is incremented. when the count in thx moves from ffh to 00h, then the overflow flag tfx in tcon sfr is set. the counted input is enabled only if trx is set and either gate = 0 or = 1. when is set to 0, then it will count clock cycles, and if is set to 1, then it will count 1 to 0 transitions on t0 (p1.2) for timer 0 and t1 (p0.7) for timer 1. when the 13 - bit count reaches 1fffh , the next count will cause it to rollover to 0000h. the timer overflow flag tfx of the relevant timer is set and if enabled an interrupts will occur. figure 10 - 1 timers/counters 0 and 1 in mode 0 intx t c/ t c/ f sys 1 / 12 0 1 0 4 7 0 7 tfx th 0 ( th 1 ) tl 0 ( tl 1 ) interrupt t 0 / t 1 ( c / t = tmod . 6 ) c / t = tmod . 2 gate int 0 / int 1 tf 0 ( tf 1 ) tr 0 / tr 1 1 / 4 0 1 t 0 m = ckcon . 3 ( t 1 m = ckcon . 4 ) 0 1 1 t 0 oe p 1 . 2 ( p 0 . 7 ) pin p 1 . 2 ( p 0 . 7 ) sfr ( t 1 oe ) t 0 oe ( t 1 oe ) en
n79e 71 5 datasheet jan. 6 , 201 6 page 41 of 189 revision 1.0 1 10.1.2 mode 1 ( 16 - bit timer) mode 1 is similar to mode 0 except that the counting register s are fully used a s a 16 - bit counter. rollover o c curs when a count moves ffff h to 0000h . the t imer overflow flag tfx of the relevant timer/counter is set and an interrupt will occur s if enabled . figure 10 - 2 timers/counters 0 and 1 in mode 1 10.1.3 mode 2 (8 - bit auto - reload timer) in mode 2, the timer / counter is in a uto - reload mode . in this mode, tlx acts as an 8 - b it count register whereas thx holds the reload value. when the tlx register overflows from ffh to 00h , the tfx bit in tcon is set and tlx is reloaded with the contents of thx and the counting process continues from here. the reload operation leaves the con tents of the thx register unchanged. this feature is best suitab le for uart baud rate generator f or it runs without continuous software intervention. note that only timer1 can be the baud rate source for uart. counting is enabled by the trx bit and proper setting of gate and pins. the functions of gate and pins are just the same as mode 0 and 1. f sys 1 / 12 0 1 0 4 7 0 7 tfx th 0 ( th 1 ) tl 0 ( tl 1 ) interrupt t 0 / t 1 ( c / t = tmod . 6 ) c / t = tmod . 2 gate int 0 / int 1 tf 0 ( tf 1 ) tr 0 / tr 1 1 / 4 0 1 t 0 m = ckcon . 3 ( t 1 m = ckcon . 4 ) 0 1 1 t 0 oe p 1 . 2 ( p 0 . 7 ) pin p 1 . 2 ( p 0 . 7 ) sfr ( t 1 oe ) t 0 oe ( t 1 oe ) en intx 0 1 0 7 0 7 t f x t h 0 ( t h 1 ) t l 0 ( t l 1 ) i n t e r r u p t t 0 o e t 0 / t 1 ( c / t = t m o d . 6 ) c / t = t m o d . 2 g a t e i n t 0 / i n t 1 p 1 . 2 ( p 0 . 7 ) t f 0 ( t f 1 ) t r 0 / t r 1 ( t 1 o e ) f s y s 1 / 1 2 0 1 / 4 0 1 t 0 m = c k c o n . 3 ( t 1 m = c k c o n . 4 )
n79e 71 5 datasheet jan. 6 , 201 6 page 42 of 189 revision 1.0 1 figure 10 - 3 timer/counter 0 and 1 in mode 2 10.1.4 mode 3 ( two separate 8 - bit timers) mode 3 has different operating methods for the two timers/counters . for timer/counter 1, mode 3 simply free z es the counter. timer/counter 0, however, configures tl0 and th0 as two separate 8 bit count registers in this mode. the logic for this mode is shown in the following figure. tl0 uses the timer/counter 0 control bits , gate, tr0, and tf0. the tl0 can be used to count clock cycles (clock/12 or clock/4) or 1 - to - 0 transiti ons on pin t0 as determined by c/t (tmod.2). th0 is forced as a clock cycle counter (clock/12 or clock/4) and takes over the use of tr1 and tf1 from timer/counter 1. mode 3 is used in cases where an extra 8 bit timer is needed. with timer 0 in mode 3, time r 1 can still be used in modes 0, 1 and 2, but its flexibility is somewhat limited. while its basic functionality is maintained, it no longer has control over its overflow flag tf1 and the enable bit tr1. timer 1 can still be used as a timer/counter and re tains the use of gate and int1 pin. in this condition it can be turned on and off by switching it out of and into its own mode 3. it can also be used as a baud rate generator for the serial port. figure 10 - 4 timer/counter 0 in mode 3 t c/ int0 0 1 0 7 0 7 t f 0 t h 0 t l 0 i n t e r r u p t t 0 = p 1 . 2 c / t = t m o d . 2 g a t e = t m o d . 3 i n t 0 = p 1 . 3 t r 0 = t c o n . 4 t r 1 = t c o n . 6 t f 1 i n t e r r u p t f s y s 1 / 1 2 0 1 / 4 0 1 t 0 m = c k c o n . 3 ( t 1 m = c k c o n . 4 ) t o g g l e ( r e f e r t o m o d e 0 ) t 0 o e p 1 . 2 p i n p 1 . 2 s f r t o g g l e ( r e f e r t o m o d e 0 ) t 1 o e p 0 . 7 p i n p 0 . 7 s f r
n79e 71 5 datasheet jan. 6 , 201 6 page 43 of 189 revision 1.0 1 10.2 timer/counter 2 timer 2 is a 16 - bit up counter cascaded with th2 , the upper 8 bits register, and tl2 , the lower 8 - bit register . equipped with rcomp2h and rcomp2l , timer 2 can operate under compare mo de and auto - reload mode. the additional 3 - channel input capture module makes timer 2 detect and measure the width or period of input pulses. the results of 3 input captures are stores in c0h and c0l, c1h and c1l, c2h and c2l individually. the clock source of timer 2 is from the clock system pre - scaled by a clock divider with 8 different scales for wide field application. the clock is enabled when tr2 ( t2con .2) is 1, and disabled when tr2 is 0. the following registers are related to timer 2 function. t2con C timer 2 control (bit - addressable) 7 6 5 4 3 2 1 0 tf2 - - - - tr 2 - r/w - - - - r/w - r/w address: c 8h reset value: 0000 0000b bit name description 7 tf 2 timer 2 overflow f lag this bit is set when timer 2 overflows or a compare match occurs. if the timer 2 interrupt and the global interrupt are enable, setting this bit will make cpu execute timer 2 interrupt service routine. this bit is not automatically cleared via hardware and should be cleared via software. 6:3 - reserved 2 tr2 timer 2 run control 0 = timer 2 is halted. clearing this bit will halt timer 2 and the current count will be preserved in th2 and tl2 . 1 = timer 2 is enabled. 1 - reserved 0 timer 2 capture or reload selection this bit selects whether timer 2 functions in compare or auto - reload mode. 0 = auto - reload on timer 2 overflow or any input capture event. 1 = compare mode of timer 2. t2mod C timer 2 mode 7 6 5 4 3 2 1 0 lden t2div[2:0] capcr compcr ldts[1:0] r/w r/w r/w r/w r/w r/w r /w r/w address: c 9h reset value: 0000 0000b bit name description 7 lden auto - reload enable 0 = disable reloading rcomp2h and rcomp2l to th2 and tl2 on timer 2 overflow or any input capture event. 1 = en able reloading rcomp2h and rcomp2l to th2 and tl2 on timer 2 overflow or any input capture event . 2 rl cp/ 2 rl cp/
n79e 71 5 datasheet jan. 6 , 201 6 page 44 of 189 revision 1.0 1 bit name description 6:4 t2 div[2:0] timer 2 clock d ivider 0 00 = timer 2 clock divider is 1/4. 0 01 = timer 2 clock divider is 1/8. 0 10 = timer 2 clock divider is 1/16. 0 11 = timer 2 clock divider is 1/32. 100 = timer 2 clock divide r is 1/64. 101 = timer 2 clock divider is 1/128. 110 = timer 2 clock divider is 1/256. 111 = timer 2 clock divider is 1/512. 3 capcr capture auto - clear this bit enables auto - clear timer 2 value in th2 and tl2 when a determined i n put capture event occurs. 0 = timer 2 continues counting when a capture event occurs. 1 = timer 2 value is auto - cleared as 0000h when a capture event occurs. 2 compcr compare match auto - clear this bit enables auto - clear timer 2 value in th2 and tl2 when a compare match occurs. 0 = timer 2 continues counting when a compare match occurs. 1 = timer 2 value is auto - cleared as 0000h when a compare match occurs. 1:0 ldts[1:0] auto - reload trigger selection these bits select the reload trigger event. 00 = reload when timer 2 overflows. 01 = reload when input capture 0 event occurs. 10 = reload when input capture 1 event occurs. 11 = reload when input capture 2 event occurs. rcomp2l C timer 2 reload/compare low byte 7 6 5 4 3 2 1 0 rcomp2l [7:0] r/w address: c ah reset value: 0000 0000b b it name description 7:0 rcomp2l [7:0] timer 2 reload / compare low byte th is register stores the low byte of compare value when timer 2 is configured in compare mode , i t holds the low byte of the reload value when auto - reload mode. rcomp2h C timer 2 reload/ compare high byte 7 6 5 4 3 2 1 0 rcomp2h [7:0] r/w address: c bh reset value: 0000 0000b bit name description 7:0 rcomp2h [7:0] timer 2 reload / compare high byte th is register stores the high byte of compare value when timer 2 is confi g ured in compare mod e. a lso, it holds the high byte of the reload value when auto - reload mode.
n79e 71 5 datasheet jan. 6 , 201 6 page 45 of 189 revision 1.0 1 tl2 C timer 2 low byte 7 6 5 4 3 2 1 0 tl2 [7:0] r/w address: c c h reset value: 0000 0000b bit name description 7:0 tl2 [7:0] timer 2 l ow b yte the tl2 register is the low byte of the 16 - bit timer 2. th2 C timer 2 high byte 7 6 5 4 3 2 1 0 th2 [7:0] r/w address: c d h reset value: 0000 0000b bit name description 7:0 th2 [7:0] timer 2 high byte the th2 register is the high byte of the 16 - bit timer 2. timer/counter 2 provides three operating mode which can be selected by control bits in t2con and t2mod as shown in the table below. note that the th2 and tl2 are accessed separately. it is strongly recommended that user stop timer 2 temporally for a reading from or writing to th2 and t l2 . the free - running reading or wri t ing may cause unpredictable situation. table 1 0 C 1 timer 2 operating modes timer 2 mode (t 2 con.0) lden (t 2 mod. 7 ) input capture 0 0 auto - reload 0 1 c ompare 1 x 10.2.1 input capture mode the input capture module with timer 2 implements the input capture mode. timer 2 should be configured by clearing and lden bit to enter input capture mode. the input capture module is configured through capcon0~2 registers. the input capture module supports 3 - channel inputs (ic0, ic1, and ic2 pins) that share i/o pin p 1.2, p 0.7 and p2.0 . each input channel con tains its own schmitt trigger input. the noise filter for each channel is enabled via setting en f0~2 (capcon2[6:4]). it filters input glitches smaller than 4 cpu clocks. input capture 0~2 have independent edge detector but share with unique timer 2. the trigger edge is also configured individually by setting capcon1. it supports positive edge capture , negative edge capture, or both edge captures . each input capture channel has its own enabling bit capen0~2 (capcon0[6:4]). rl2 cp/ 2 rl cp/
n79e 71 5 datasheet jan. 6 , 201 6 page 46 of 189 revision 1.0 1 while any input capture channel is enabled and the selected edge trigger occurs, the content of the free ru n ning timer 2 counter, t h2 and tl2 , will be captured, transferred, and stores into the capture registers cnh and cnl. the edge triggering also causes capfn (capcon0.n) is set by hardware. the interrupt will also be generated if ecp tf (eie. 2 ) and ea bit are both set. for three inp ut capture flags shares the same interrupt vector, the user should check capfn to confirm which channel comes the input capture edge. these flags should be cleared by software. the bit capcr ( t2mod .3) benefits the implement of period calculation. setting c apcr makes the hardware clear timer 2 as 0000h automatically after the value of th2 and tl2 have been captured after an input ca p ture edge event occurs. it eliminates the routine software overhead of writing 16 - bit counter or an arithmetic subtraction. figure 10 - 5 timer 2 input capture and auto - reload mode function block t f 2 t i m e r 2 i n t e r r u p t p r e - s c a l a r 1 / 4 ~ 1 / 5 1 2 f s y s r c o m p 2 h t 2 d i v [ 2 : 0 ] ( t 2 m o d [ 6 : 4 ] ) r c o m p 2 l t h 2 t l 2 0 0 0 1 1 0 1 1 c a p f 0 e v e n t c a p f 1 e v e n t c a p f 2 e v e n t l d e n ( t 2 m o d . 7 ) l d t s [ 1 : 0 ] ( t 2 m o d [ 1 : 0 ] ) t r 2 ( t 2 c o n . 2 ) t i m e r 2 m o d u l e c 0 h c 0 l n o i s e f i l t e r e n f 0 ( c a p c o n 2 . 4 ) o r [ 0 0 ] [ 0 1 ] [ 1 0 ] c a p 0 l s [ 1 : 0 ] ( c a p c o n 1 [ 1 : 0 ] ) c a p e n 0 ( c a p c o n 0 . 4 ) c a p f 0 i n p u t c a p t u r e 0 m o d u l e i n p u t c a p t u r e 1 m o d u l e i n p u t c a p t u r e 2 m o d u l e i c 0 ( p 1 . 2 ) i c 1 ( p 0 . 7 ) i c 2 ( p 2 . 0 ) i n p u t c a p t u r e f l a g s c a p f [ 2 : 0 ] c a p c r ( t 2 m o d . 3 ) c a p f 0 e v e n t c a p f 1 e v e n t c a p f 2 e v e n t c l e a r t i m e r 2
n79e 71 5 datasheet jan. 6 , 201 6 page 47 of 189 revision 1.0 1 capcon0 C input capture control 0 7 6 5 4 3 2 1 0 - capen2 capen1 capen0 - capf2 capf1 capf0 - r/w r/w r/w - r/w r/w r/w address: 92h reset value: 0000 0000b bit name description 7 - reserved 6 capen2 input capture 2 enable 0 = disable i nput capture channel 2 . 1 = enable i nput capture channel 2 . 5 capen1 input capture 1 enable 0 = disable i nput capture channe l 1. 1 = enable i nput capture channel 1. 4 capen0 input capture 0 enable . 0 = disable i nput capture channel 0. 1 = enable i nput capture channel 0. 3 - reserved 2 capf2 input capture 2 flag this bit is set by hardware if the determined edge of input capt ure 2 occurs. this bit should cleared by software. 1 capf1 input capture 1 flag this bit is set by hardware if the determined edge of input capture 1 occurs. this bit should cleared by software. 0 capf0 input capture 0 flag this bit is set by hardware if the determined edge of input capture 0 occurs. this bit should cleared by software. capcon1 C input capture control 1 7 6 5 4 3 2 1 0 - - cap2ls[1:0] cap1ls[1:0] cap0ls[1:0] - - r/w r/w r/w r/w r/w r/w address: 9 3 h reset value: 0000 0000b bit name des cription 7:6 - reserved 5:4 cap2ls[1:0] input capture 2 level selection 0 0 = falling edge. 0 1 = rising edge. 10 = either rising or falling edge. 11 = reserved 3:2 cap1ls[1:0] input capture 1 level selection 0 0 = falling edge. 0 1 = rising edge. 10 = eith er rising or falling edge. 11 = reserved 1:0 cap0ls[1:0] input capture 0 level selection 0 0 = falling edge.
n79e 71 5 datasheet jan. 6 , 201 6 page 48 of 189 revision 1.0 1 bit name des cription 0 1 = rising edge. 10 = either r ising or falling edge. 11 = reserved capcon2 C input capture control 2 7 6 5 4 3 2 1 0 - enf2 enf1 enf0 - - - - - r/w r/w r/w - - - - address: 9 4 h reset value: 0000 0000b bit name description 7 - reserved 6 enf2 n oise filer on input capture 2 enable 0 = disable noise filter on input capture channel 2. 1 = enable noise filter on input capture channel 2. 5 enf1 noi se filer on input capture 1 enable 0 = disable noise filter on input capture channel 1. 1 = enable noise filter on input capture channel 1. 4 enf0 noise filer on input capture 0 enable 0 = disable noise filter on input capture channel 0. 1 = enable noise filter on input capture channel 0. 3:0 - reserved c0l C capture 0 low byte 7 6 5 4 3 2 1 0 c0l[7:0] r/w address: e4h reset value: 0000 0000 b bit name description 7:0 c0l[7:0] input capture 0 result low byte the c0l register is the low byte of the 16 - bit result captured by input capture 0 . c0h C capture 0 high byte 7 6 5 4 3 2 1 0 c0h[7:0] r/w address: e5h reset value: 0000 0000 b bit name description 7:0 c0h[7:0] input capture 0 result high byte the c0h register is the high byte of the 16 - bit resu lt captured by input capture 0 .
n79e 71 5 datasheet jan. 6 , 201 6 page 49 of 189 revision 1.0 1 c1l C capture 1 low byte 7 6 5 4 3 2 1 0 c1l[7:0] r/w address: e6h reset value: 0000 0000 b bit name description 7:0 c1l[7:0] input capture 1 result low byte the c1l register is the low byte of the 16 - bit result captured by input capture 1 . c1h C capture 1 high byte 7 6 5 4 3 2 1 0 c1h[7:0] r/w address: e7h reset value: 0000 0000 b bit name description 7:0 c1h[7:0] input capture 1 result high byte the c1h register is the high byte of the 16 - bit result captured by inpu t capture 1 . c2l C capture 2 low byte 7 6 5 4 3 2 1 0 c2l[7:0] r/w address: edh reset value: 0000 0000 b bit name description 7:0 c2l[7:0] input capture 2 result l ow byte the c2l register is the low byte of the 16 - bit result captured by input capture 2 . c2h C capture 2 high byte 7 6 5 4 3 2 1 0 c2h[7:0] r/w address: eeh reset value: 0000 0000 b bit name description 7:0 c2h[7:0] input capture 2 result high byte the c2h register is the high byte of the 16 - bit result captured by input capture 2 . 10.2.2 auto - reload mode timer 2 can be configured as auto - reload mode by clearing and setting lden bit. in this mode rcomp2h and rcomp2l registers stores the reload value. the contents in rcomp2h and rcom3l tran s fer into th2 and tl2 once the au to - reload event occurs. the event can be the timer 2 2 rl cp/
n79e 71 5 datasheet jan. 6 , 201 6 page 50 of 189 revision 1.0 1 overflow or one of the triggering event on any of enabled input capture channel depending on the ldts[1:0] ( t2mod [1:0]) selection. note that once capcr (t2mod.3) is set, an input capture event only clear s th2 and tl2 without reloading rcomp2h and rcomp2l contents. 10.2.3 compare mode timer 2 can also be configured simply as the compare mode by setting . in this mode rcomp2h and rcomp2l registers serve as the compare value registers. as time r 2 up counting, th2 and tl2 match rcomp2h and rcomp2l , tf3 ( t2con .7) will be set by hardware to indicate a compare match event. setting compcr ( t2mod .2) makes the hardware to clear timer 2 counter as 0000h automatically after a compare match has occurred. figure 10 - 6 timer 2 compare mode function block 2 rl cp/ t f 2 t i m e r 2 i n t e r r u p t p r e - s c a l a r 1 / 4 ~ 1 / 5 1 2 f s y s r c o m p 2 h t 2 d i v [ 2 : 0 ] ( t 2 m o d [ 6 : 4 ] ) r c o m p 2 l t h 2 t l 2 t r 2 ( t 2 c o n . 2 ) t i m e r 2 m o d u l e c o m p c r ( t 2 m o d . 2 ) c l e a r t i m e r 2 =
n79e 71 5 datasheet jan. 6 , 201 6 page 51 of 189 revision 1.0 1 11 watchdog timer (wdt) the N79E715 provide s one watchdog counter to serve as a system monitor, which improve the reliability of th e system. watchdog timer is useful for systems that are susceptible to noise, power glitches, or ele c trostatic discharge. the periodic interrupt of watchdog timer can also serve as an event timer or a durational system supervisor in a monitoring system whi ch generally operates in idle or power - down mode . the watchdog timer is basic a setting of divider that divides an internal low speed clock source. the divider output is s e lectable and determines the time - out interval. when the time - out interval is fulfill ed, it will wake the system up from idle or power - down mode and an interrupt event will occur. if watchdog timer reset is enabled, a system reset will occur after a period of delay if without any software response. figure 11 - 1 watchdog timer 11.1 function al description the watchdog timer should first be reset 00h by using wdclr(wdcon0.6) to ensure that the timer starts from a known state. after disable watchdog timer through clearing w dten (wdcon 0 .7) will also clear this counter. the wdclr bit is used to reset the watchdog timer. this bit is self - cleared thus the user doesnt need to clear it. after writing 1 to wdclr, the hardware will automatically clear it. after wdten set as 1, the watchdog timer starts counting. the time - out interval is selected by the three bits wps2, wps1, and wps0 (wdcon0[2:0]). when the selected time - out occurs, the watchdog timer will set the interrupt flag wdtf (wdcon0.5). the watchdog timer interrupt enable b it locates at eie .4 register. if watchdog timer reset is enabled by writing logic 1 to ewrst (wdcon1.0) bit. an additional 512 clocks of lirc d elays to expect a counter clearing by setting w p s 2 , w p s 1 , w p s 0 s e l e c t 1 / 2 1 / 1 1 / 1 2 8 1 / 2 5 6 1 / 6 4 1 / 3 2 1 / 1 6 1 / 8 p r e - s c a l a r i n t e r n a l o s c ( 1 0 k h z ) e n w d t w d t f d e l a y 5 1 2 c l o c k ( l i r c ) w c l r c l o c k ( w r i t t e n ' 1 ' b y s o f t w a r e ) e w r s t 6 - b i t c o u n t e r . . . . c l e a r w d t c o u n t e r o v e r f l o w c h e c k i n g o v e r f l o w 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 : o n 0 : o f f f l i r c w d t i n t e r r u p t e w d i w d t r e s e t w d t r f ( e i e . 4 ) i d l ( p c o n . 0 ) p d ( p c o n . 1 ) w i d p d
n79e 71 5 datasheet jan. 6 , 201 6 page 52 of 189 revision 1.0 1 wdclr. if there is no wdclr setting during this 512 - clock period, a reset will happen. once a reset due to watchdog timer occurs, the watchdog timer reset flag wdtrf (wdcon0.3) will be set. this bit keeps unchanged after any reset other than a power - on reset. the user may clear wdtrf via software. in general, software sho uld restart the counter to put it into a known state by setting wdclr. the watchdog timer also provides a widpd bit (wdcon 0 .4) to allow the watchdog timer contin u ing running after the system enters idle or power - d own operating mode. the hardware automatica lly clears wdt counter after entering or being woken - up from idle or power - down mode . it prevents unconscious system reset. wdcon0 C watchdog timer control (ta p rotected) 7 6 5 4 3 2 1 0 wdten wdclr wdtf widpd wdtrf wps2 wps1 wps0 r/w w r/w r/w r/w r/w r /w r/w address: d8h reset value: see table 7 C 2 N79E715 s fr description and reset value s bit name description 7 wdten wdt ena ble wdten is initialized by inverted c wdten ( config3 , bit - 7) at any other resets . 0 = disable wdt at power - on reset. 1 = enable wdt at power - on reset. 6 wdclr wdt counter clear writing 1 to clear the wdt counter to 0000h. note that this bit is written - only and has no need to be cleared by being written 0. 5 wdtf wdt interrupt flag t his bit will be set by hardware when wdt counter ove r flows. 4 widpd w dt running in idle and power - d own mode this bit decides whether watchdog timer runs in idle or power - down mode . 0 = wdt counter is halted while cpu is in idle or power - down mode . 1 = wdt keeps running while cpu is in idle or power - down mode .
n79e 71 5 datasheet jan. 6 , 201 6 page 53 of 189 revision 1.0 1 bit name description 3 wdtrf wdt reset flag when the mcu resets itself, this bit is set by hardware. the bit should be cleared by software. if ewrst = 0, the interrupt flag wdtf wont be set by hardware, and the mcu will reset itself right away. if ewrst = 1, the interrupt flag wdtf will be set by hardware and the mcu will jump into wdts interrupt service routine if wdt interrupt is enabled, and the mcu wont reset itself until 512 cpu clocks elapse. in other words, in t his cond i tion, the user also needs to clear the wdt counter (by writing 1 to wdclr bit) during this period of 512 cpu clocks, or the mcu will also reset itself when 512 cpu clocks elapse. 2:0 wps[2:0] wdt pre - scalar selection use these bits to select w dt time - out period. the wdt time - out period is determined by the formula , where f lirc is the frequency of the wdt clock source. the following table shows an example of wdt timeout period for different f lirc . [1] wdten is initialized by reloading the inversed value of cwdten ( config3 .7) after all resets. [2] widpd and wps[2:0] are cleared after power - on reset and keep unchanged after any other resets. [3] wdtrf will be cleared after power - on reset, be set after watchdog timer reset, a nd remains unchanged after any other resets. wdcon1 C watchdog timer control ( ta protected ) 7 6 5 4 3 2 1 0 - - - - - - - ewrst - - - - - - - r/w address: ab h reset value: 0000 0000b bit name description 0 ewrst 0 = disable wdt reset funct i on. 1 = en able wdt reset funct i on. [1] ewrst is cleared after power - on reset and keeps unchanged after any other resets. the watchdog time - out interval is determined by the formula . w here f lirc is the frequency of li rc. the following table s hows an example of the watchdog time - out interval under different f lirc and pre - scalars. ) scalar e pr f ( 64 = lirc ) scalar e pr f ( 64 = lirc
n79e 71 5 datasheet jan. 6 , 201 6 page 5 4 of 189 revision 1.0 1 eie C extensive interrupt enable 7 6 5 4 3 2 1 0 et2 espi epwm ewdi - ecptf ekb ei2 c r/w r/w r/w r/w - r/w r/w r/w address: e8h reset value: 0000 0000b bit name des cription 4 ewdi 0 = disable watchdog timer interrupt. 1 = enable watchdog timer interrupt. the watchdog timer time - out selection will result in different time - out values depending on the clock speed. the reset, when enabled, will occur when 512 clock s after time - out has occurred. table 11 - 1 time - out values for the watchdog timer (wps2,wps1,wps0) pre - s cal a r wdt interrupt time - out reset time - out number of clocks time number of clocks time (0,0,0) 1/1 2 6 6.4ms 2 6 +512 57.6ms (0,0,1) 1/2 2x 2 6 12.8ms 2x 2 6 +512 64ms (0,1,0) 1/8 8x 2 6 51.2ms 8x 2 6 +512 102.4ms (0,1,1) 1/16 16x 2 6 102.40ms 16x 2 6 +512 153.6ms (1,0,0) 1/32 32x 2 6 204.80ms 32x 2 6 +512 256ms (1,0,1) 1/64 64x 2 6 409.60ms 64x 2 6 +512 460.8ms (1,1,0) 1/12 8 128x 2 6 819.20ms 128x 2 6 +512 870.4ms (1,1,1) 1/256 256x 2 6 1.638s 256x 2 6 +512 1.6892s 11.2 applications of watchdog timer reset the main application of the watchdog timer with time - out reset enabling is for the system monitor. this is i m portant in real - time co ntrol applications. in case of some power glitches or electro - magnetic interference, the processor may begin to execute erroneous codes and operate in an unpredictable state. if this is left u n checked the entire system may crash. using the watchdog timer d uring software development will require the user to select ideal watchdog reset locations for inserting instructions to reset the watchdog timer. by inser t ing the instruction setting wdclr, it will allow the code to run
n79e 71 5 datasheet jan. 6 , 201 6 page 55 of 189 revision 1.0 1 without any watchdog timer reset. ho wever if any erroneous code executes by any power of other interference, the instructions to clear the watchdog timer counter will not be executed at the required instants. thus the watchdog timer reset will occur to reset the system start from an erroneou sly executing condition. the user should remember that wdcon 0 requires a timed access writing. 11.3 applications of watchdog timer interrupt there is another application of the watchdog timer, which is used as a simple timer. the wdtf flag will be set while the watchdog timer completes the selected time interval. the software polls the wdtf flag to detect a time - out and the wdclr allows software to restart the timer. the watchdog timer can also be used as a very long timer. every time the time - out occurs, an int errupt will occur if the individual interrupt ewd i (eie.4) and global interrupt enable ea is set. in some application of low power consumption, the cpu usually stays in idle mode when nothing needs to be served to save power consumption. after a while the cpu will be woken up to check if anything needs to be served at an interval of programmed period implemented by timer 0, 1 or 2. however, the current consumption of idle mode still keeps at a ma level. to further reducing the current consumption to a level, the cpu should stay in power - down mode when nothing needs to be served, and has the ability of waking up at a pr o grammable interval. the N79E715 is equipped with this useful function. it provides a very low power lirc . along with the low power consu mption application, the watchdog timer needs to count under idle and power - down mode and wake cpu up from idle or power - down mode . the demo code to a c complish this feature is shown below. the demo code of watchdog timer wakes cpu up from power down. or g 0000h ljmp start org 0053h ljmp wdt_isr org 0100h wdt_isr: clr ea mov ta,#0aah mov ta,#55h orl wdcon0,#01000000b ;clear watchdog timer counter inc acc mov p0,acc setb ea clr ea mov ta,#0aah mov ta,#55h anl wdcon0,#11011111b ;clear watchdog timer interrupt flag setb ea reti
n79e 71 5 datasheet jan. 6 , 201 6 page 56 of 189 revision 1.0 1 start: mov ta,#0aah mov ta,#55h orl wdcon0,#01000000b ;clear watchdog timer co unter mov ta,#0aah mov ta,#55h orl wdcon0,#10000000b ;enable watchdog timer to run check_clear: mov a,wdcon0 jb acc.6,check_clear mov ta,#0aah mov ta,#55h orl wdcon0,#00000111b ;choose interval length mov ta,#0aah mov ta,#55h anl wdcon1,#11111110b ;disable watchdog timer reset setb ewdi ;enable watchdog timer interrupt mov ta,#0aah mov ta,#55h setb widpd setb ea ;******************************************************************** ;enter power - down mode ;******************************************************************** loop: orl pcon,#02h ljmp loop end
n79e 71 5 datasheet jan. 6 , 201 6 page 57 of 189 revision 1.0 1 12 serial port (uart) the n79e 715 include s one enhanced full duplex serial port with automatic address recognition and framing error detection. the serial port supports three modes of full duplex uart (universal asynchr o nous receiver and transmitter) in mode 1, 2, and 3. this means it can transmit and receive simultaneously. the serial port is also receiving - buffered, which mean s that it can commence reception of a second byte before a previously received byte has been read from the register. the receiving and transmitting registers are both a c cessed at sbuf. writing to sbuf loads the transmitting register, and reading sbuf accesses a physically separate receiving register. there are four operation modes in serial port. in all four modes, transmission init i ates by any instruction that us es sbuf as a destination register. note that before serial port function works, the port latch bits of rx d and txd pins have to be set to 1. uart_sel (auxr1.6) support s software switches two groups of uart pin. scon C serial port control (bit - addressable) 7 6 5 4 3 2 1 0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri r/w r/w r/w r/w r/w r/w r/w r/w address: 98h reset value: 0000 0000b bit name description 7 sm0/fe serial port m ode selection smod0 (pcon.6) = 0: see table 12 C 1 serial port mode description for details. smod0 (pcon.6) = 1: sm0/fe bit is used as frame error (fe) status flag. 0 = frame error (fe) does not occur. 1 = frame error (fe) occurs and is detected. 6 sm1 5 sm2 multiprocessor communication mode enable th e function of this bit is dependent on the serial port mode. mode 0: this bit select the baud rate between f sys /12 and f sys /4. 0 = the clock runs at f sys /12 baud rate. it maintains standard 8051 compatibility . 1 = the clock runs at f sys /4 baud rate for f aster serial communication. mode 1: this bit checks valid stop bit. 0 = reception is always valid no matter the logic level of stop bit. 1 = reception is valid only when the received stop bit is logic 1 and the received data matches given or broadcast address. mode 2 or 3: for multiprocessor communication. 0 = reception is always valid no matter the logic level of the 9 th bit. 1 = reception is valid only when the received 9 th bit is logic 1 and the received data matches given or broadcast address.
n79e 71 5 datasheet jan. 6 , 201 6 page 58 of 189 revision 1.0 1 bit name description 4 ren receiving e nable 0 = serial port reception is disabled. 1 = serial port reception is enabled in mode 1,2, and 3. in mode 0, clearing and then s etting ren initiate s one - byte reception . after reception is complete, this bit will not be cleared via hard ware. the user should clear and set ren again via software to triggering the next byte reception. 3 tb8 9 th transmitted b it this bit defines the state of the 9 th transmission bit in serial port mode 2 and 3. it is not used in mode0 and 1. 2 rb8 9 th recei ved bit the bit identifies the logic level of the 9 th received bit in modes 2 and 3. in mode 1, if sm2 0, rb8 is the logic level of the received stop bit. rb8 is not used in mode 0. 1 ti transmission interrupt flag this flag is set via hardware when a byt e of data has been transmitted by the uart after the 8 th bit in mode 0 or the last bit of data in other modes. when the uart interrupt is enabled, setting this bit causes the cpu to execute the uart interrupt service routine. this bit should be cleared man ually via software. 0 ri receiving interrupt flag this flag is set via hardware when a 8 - bit or 9 - bit data has been received by the uart after the 8 th bit in mode 0, after sampling the stop bit in mode 1, or after sampling the 9 th bit in mode 2 and 3. sm2 bit has restriction for exception. when the uart interrupt is enabled, setting this bit causes the cpu to execute to the uart interrupt service routine. this bit should be cleared manually via sof t ware. table 12 C 1 serial port mode description mod e sm 0 sm 1 description frame bits baud rate 0 0 0 synchronous 8 f sys divided by 12 or by 4 [1] 1 0 1 asynchronous 10 timer 1 overflow rate divided by 32 or divided by 16 [2] 2 1 0 asynchronous 11 f sys divided by 64 o r 32 [2] 3 1 1 asynchronous 11 timer 1 overflow rate divided by 32 or divided by 16 [2] [1] while sm2 (scon.5) is logic 1. [2] while smod (pcon.7) is logic 1. pcon C power control 7 6 5 4 3 2 1 0 smod smod0 - pof gf1 gf0 pd idl r/w r/w - r/w r/w r/w r/w r/w address: 87h reset value: see table 7 C 2 N79E715 s fr description and reset value s bit name description 7 smod serial port d ouble b aud r ate e nable setting this bit doubles the serial port baud rate in uart mode 2 and mode 1 or 3 only if timer 1 overflow is used as the baud rate source. see table 12 C 1 serial port mode description for details.
n79e 71 5 datasheet jan. 6 , 201 6 page 59 of 189 revision 1.0 1 bit name description 6 smod0 framing e rror d etection enable 0 = framing error detection is disa bled. sm0/fe (scon.7) bit is used as sm0 as standard 80c51 function. 1 = framing error detection is enabled. sm0/fe bit is used as frame error (fe) status fla g. sbuf C serial data buffer 7 6 5 4 3 2 1 0 sbuf[7:0] r/w address: 99h reset value: 0000 0000 b bit name description 7:0 sbuf[7:0] serial data buffer this byte actually consists of two separate registers. one is the receiving resister, and the other is the transmitting buffer. when data is moved to sbuf, it goes to the transmitting buffer and is s hifted for serial transmission. when data is moved from sbuf, it comes from the receiving buffer. the transmission is initiated through moving a byte to sbuf. auxr1 C aux function resgister - 1 7 6 5 4 3 2 1 0 spi_sel uart_sel - - disp26 - 0 dps r/w r/w - - r/w - r r/w address: a2h reset value: 0000 0000b bit name description 6 uart_sel 0 = select p1.0, p1.1 as uart pins. 1 = select p2.6, p2.7 as uart pins. 12.1 mode 0 mode 0 provides synchronous communication with external devices. serial data enters and e xits through rxd pin. txd outputs the shift clock. 8 bits are transmitted or received. mode 0 therefore provides half - duplex communication because the transmitting or receiving data is via the same data line rxd. the baud rate is enhanced to be selected as f sys /12 if sm2 (scon.5) is 0 or as f sys /4 if sm2 is 1. note that whenever transmi t ting or receiving, the serial clock is always generated by the microcontroller. thus any device on the serial port in mode 0 should accept the microcontroller as the master. figure 12 - 1 shows a simplified functional di a gram of the serial port in mode 0 and associated timing.
n79e 71 5 datasheet jan. 6 , 201 6 page 60 of 189 revision 1.0 1 figure 12 - 1 serial port mode 0 function block
n79e 71 5 datasheet jan. 6 , 201 6 page 61 of 189 revision 1.0 1 as shown , ther e is one bidirectional data line (rxd) and one shift clock line (txd). the shift clock is used to shift data in or out of the serial port controller bit by bit for a serial communication. data bits enter or exit lsb first. the band rate is equal to the shi ft clock frequency. transmission is initiated by any instruction writes to sbuf. the control block will then shift out the clock and begin to transfer data until all 8 bits are complete. then the transmitted flag ti (scon.1) will be set 1 to ind i cate one b yte transmitting complete. reception is initiated by clearing and then setting ren (scon.4) while ri (scon..0) is 0. this condition tells the serial port controller that there is data to be shifted in. this process will continue until 8 bits have been r e ce ived. then the received flag ri will be set as 1. note that ren will not be cleared via hardware. the user should first clear ri, clear ren and then set ren again via software to triggering the next byte reception. 12.2 mode 1 mode 1 supports asynchronous, full duplex serial communication. the asynchronous mode is commonly used for communication with pcs, modems or other similar interfaces. in mode 1, 10 bits are transmitted (through txd) or received (through rxd) including a start bit (logic 0), 8 data bits (ls b first) and a stop bit (logic 1). the baud rate is determined by the timer 1. smod (pcon.7) setting 1 makes the baud rate double while timer 1 is selected as the clock source. figure 12 C 12 - 2 shows a simplified fun ctional diagram of the serial port in mode 1 and associated timings for transmitting and receiving.
n79e 71 5 datasheet jan. 6 , 201 6 page 62 of 189 revision 1.0 1 figure 12 C 12 - 2 serial port mode 1 function block and timing diagram
n79e 71 5 datasheet jan. 6 , 201 6 page 63 of 189 revision 1.0 1 transmission is initiated by any wri ting instructions to sbuf. transmission takes place on txd pin. first the start bit comes out, the 8 - bit data follows to be shifted out and then ends with a stop bit. after the stop bit a p pears, ti (scon.1) will be set to indicate one byte transmission com plete. all bits are shifted out depending on the rate determined by the baud rate generator. once the baud rate generator is activated and ren (scon.4) is 1, the reception can begin at any time. r e ception is initiated by a detected 1 - to - 0 transition at rxd . data will be sampled and shifted in at the selected baud rate. in the midst of the stop bit, certain conditions should be met to load sbuf with the received data: 1. ri (scon.0) = 0, and 2. either sm2 (scon.5) = 0, or the received stop bit = 1 while sm2 = 1. if these conditions are me t, t he sbuf will be loaded with the received data, the rb8 (scon.2) with stop bit, and ri will be set. if these conditions fail, there will be no data loaded and ri will remain 0. after above receiving progress, the serial co ntrol will look forward another 1 - 0 transition on rxd pin to start next data rece p tion. 12.3 mode 2 mode 2 supports asynchronous, full duplex serial communication. different from mode1, there are 11 bits to be transmitted or received. they are a start bit (logi c 0), 8 data bits (lsb first), a programmable 9 th bit tb8 or rb8 bit and a stop bit (logic 1). the most common use of 9 th bit is to put the parity bit in it. the baud rate is fixed as 1/32 or 1/64 the system clock frequency depending on smod bit. figure 12 - 3 shows a simplified functional diagram of the serial port in mode 2 and associated timings for transmitting and receiving.
n79e 71 5 datasheet jan. 6 , 201 6 page 64 of 189 revision 1.0 1 figure 12 - 3 serial port mode 2 functio n block and timing diagram
n79e 71 5 datasheet jan. 6 , 201 6 page 65 of 189 revision 1.0 1 transmission is initiated by any writing instructions to sbuf. transmission takes place on txd pin. first the start bit comes out, the 8 - bit data and bit tb8 (scon.3) follows to be shifted out and then ends with a stop bit. after the stop bit appears, ti will be set to indicate the transmission complete. while ren is set, the reception is allowed at any time. a falling edge of a start bit on rxd will initiate the reception progress. data will be sampled and shifted in at the selec ted baud rate. in the midst of the 9 th bit, ce r tain conditions should be met to load sbuf with the received data: 1. ri (scon.0) = 0, and 2. either sm2(scon.5) = 0, or the received 9 th bit = 1 while sm2 = 1. if these conditions are met, the sbuf will be lo aded with the received data, the rb8(scon.2) with tb8 bit and ri will be set. if these conditions fail, there will be no data loaded and ri will remain 0. after above receiving progress, the serial control will look forward another 1 - 0 transition on rxd pi n to start next data rece p tion. 12.4 mode 3 mode 3 has the same operation as mode 2, except its baud rate clock source. as shown is figure 12 - 4 , mode 3 uses timer 1 overflow as its baud rate clock.
n79e 71 5 datasheet jan. 6 , 201 6 page 66 of 189 revision 1.0 1 figure 12 - 4 serial port mode 3 function block
n79e 71 5 datasheet jan. 6 , 201 6 page 67 of 189 revision 1.0 1 12.5 baud rates table 12 C 2 uart baud rate formulas uart m ode baud r ate c lock s ource baud rate 0 oscillator or [1] 2 oscillator 1 or 3 timer/counter 1 overflow [2] or [3] [1] while sm2 (scon.5) is set as logic 1. [2] timer 1 is configured as a timer in auto - reload mode (mode 2). [3] while t1m (ckcon.4) is set as logic 1. note that in using timer 1 as the baud rate generator, the interrupt should be disabled. the timer itself can be configured for either timer or counter operation. and timer 1 can be in any of its 3 running m odes. in the most typical applications, it is configured for timer operation, in the auto - reload mode (mode2). if timer 1 is used as the baud rate generator, the reloaded value is stored in th1. therefore the baud rate is determined by th1 value. table 12 C 3 lists various commonly used baud rates and how they can be obtained from timer 1. in this mode, timer 1 operates with divided - by - 12 pre - scale, as an auto - reload timer with smod (pcon.7) is 0. if smod is 1, the baud rate will be doubled. table 12 C 3 timer 1 generated commonly used baud rates th1 reload value oscillator frequency (mhz) baud rate 11.0592 14.7456 18.432 22.1184 57600 ffh 38400 ffh 19200 feh fdh 9600 fdh fch fbh fah 4800 fah f8h f6h f4h 2400 f4h f0h ech e8h 1200 e8h e0h d8h d0h 12 / f sys 4 / f sys sys smod f 64 2 ? ? ? 1 th 256 12 f 32 2 sys smod ? ? ? ? ? 1 th 256 4 f 32 2 sys smod ? ? ?
n79e 71 5 datasheet jan. 6 , 201 6 page 68 of 189 revision 1.0 1 12.6 framing error detection framing error detection is provided for asynchronous modes (mode 1, 2 and 3.) the framing error occurs when a valid stop bit is not detec ted due to the bus noise or contention. the uart can detect a framing error and notify the software. the framing error bit, fe, is located in scon.7. this bit normally serves as sm0. while the framing error detection enable bit smod0 (pcon.6) is set 1, it serves as fe flag. actually sm0 and fe locate in different re g isters. the fe bit will be set 1 via hardware while a framing error occurs. it should be cleared via software. note that smod0 should be 1 while reading or writing to fe. if fe is set, any of th e f ollowing frames received without any error will not clear the fe flag. the clearing has to be done via software. 12.7 multiprocessor communication the communication feature of the N79E715 enables a master device send a multiple frame serial message to a slav e device in a multi - slave configuration. it does this without interrupting other slave d e vices that may be on the same serial line. uart mode 2 or 3 mode can use this feature only. after 9 data bits are received. the 9 th bit value is written to rb8 (scon.2 ). the user can enable this function by se t ting sm2 (scon.5) as logic 1 so that when the stop bit is received, the serial interrupt will be generated only if rb8 is 1. when the sm2 bit is 1, serial data frames that are received with the 9 th bit as 0 do not generate an interrupt. in this case, the 9 th bit simply separates the a d dress from the serial data. when the master device wants to transmit a block of data to one of several slaves on a serial line, it first sends out an address byte to identify the targ et slave. note that in this case, an address byte differs from a data byte: in an address byte, the 9 th bit is 1 and in a data byte, it is 0. the address byte interrupts all slaves so that each slave can examine the received byte and see if it is being add ressed. the addressed slave then clears its sm2 bit and prepares to receive incoming data bytes. the sm2 bits of slaves that were not addressed remain set, and they continue operating normally while ignoring the incoming data bytes. follow the steps below to configure multiprocessor communications: 1. set all devices (masters and slaves) to uart mode 2 or 3. 2. write the sm2 bit of all the slave devices to 1. 3. the master device's transmission protocol is:
n79e 71 5 datasheet jan. 6 , 201 6 page 69 of 189 revision 1.0 1 C first byte: the address, identifying the target sl ave device, (9 th bit = 1). C next bytes: data, (9 th bit = 0). 4. when the target slave receives the first byte, all of the slaves are interrupted because the 9 th data bit is 1. the targeted slave compares the address byte to its own address and then clears i ts sm2 bit to receiving i n coming data. the other slaves continue operating normally. 5. after all data bytes have been received, set sm2 back to 1 to wait for next address. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. for mode 1 r e ception, if sm2 is 1, the receiving interrupt will not be issue unless a valid stop bit is received. 12.8 automatic address recognition the automatic address recognition is a feature which enhances the multiprocessor communication featur e by allowing the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which pa sses by the serial port. only when the serial port recognizes its own a d dress, the receiver sets ri bit to request an interrupt. the automatic address recognition feature is enabled when the multiprocessor communication feature is enabled. (sm2 is set.) if desired, the user may enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place of the ninth data bit. ri is set only when the received command frame address matches the devices address and is termina ted by a valid stop bit. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast addr ess. two sfrs are used to define the slave address, saddr, and the slave address mask, saden. saden is used to define which bits in the saddr are to be used and which bits are dont care. the saden mask can be logically anded with the saddr to create the given address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others.
n79e 71 5 datasheet jan. 6 , 201 6 page 70 of 189 revision 1.0 1 saddr C slave address 7 6 5 4 3 2 1 0 saddr[7:0] r/w address: a9h reset value: 0000 0000b bit name description 7:0 saddr[7:0] slave address this byte specifies the microcontrollers own slave address for uart multipr o cessor communication. saden C slave address mask 7 6 5 4 3 2 1 0 saden[7:0] r/w address: b9h reset value: 0000 0000b b it name description 7:0 saden[7:0] slave address mask this byte is a mask byte that contains dont - care bits (defined by zeros) to form the devices given address. the dont - care bits provide the flexibility to address one or more slaves at a time. th e following examples will help to show the versatility of this scheme. example 1, slave 0: saddr = 11000000b saden = 11111101b given = 110000x0b example 2, slave 1: saddr = 11000000b saden = 11111110b given = 1100000xb in the above example saddr is the s ame and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010b since slave 1 requires a 0 in b it 1. a unique address for slave 1 would be 11000001b since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000b. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:
n79e 71 5 datasheet jan. 6 , 201 6 page 71 of 189 revision 1.0 1 example 1, slave 0: saddr = 11000000b saden = 11111001b given = 11000xx0b example 2, slave 1: saddr = 11100000b saden = 11111010b given = 11100x0 xb example 3, slave 2: saddr = 11000000b saden = 11111100b given = 110000xxb in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 11100110b. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 11100101b. slave 2 requires that bit 2 = 0 and its unique address is 11100011b. to select slaves 0 and 1 and exclude slave 2 use address 11100100b, since it is necessary to make bit 2 = 1 to exc lude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are treated as dont care . in most cases, interpreting the dont care as ones, the broa d cast address will be ffh. on reset , saddr and saden are initialized to 00h. this produces a given address of all dont care as well as a broadcast address of all xxxxxxxxb (all dont care bits). this effectively disables the automatic addressing mode and allows the microcontroller to use standard uart drivers which do not make use of this fe a ture.
n79e 71 5 datasheet jan. 6 , 201 6 page 72 of 189 revision 1.0 1 13 serial peripheral interface (spi) 13.1 features the N79E715 exist s a serial peripheral interface (spi) block to support high - speed serial communic a tion. spi is a full - duplex, high - speed , synchr onous communication bus between mcus or other peripheral d e vices such as serial eeprom , lcd driver, or d/a con verter . it provides either master or slave mode, high - speed rate up to f sys / 16 f or master mode and f sys /4 for slave mode , transfer complete and wr ite collision flag. for a multi - m aster system, spi supports master mode fault to protect a multi - master conflict. 13.2 functional description figure 13 - 1 spi block d iagram d i v i d e r / 1 6 , / 3 2 , / 6 4 , / 1 2 8 s e l e c t 8 - b i t s h i f t r e g i s t e r r e a d d a t a b u f f e r m s b l s b p i n c o n t o r l l o g i c m i s o m o s i s p c l k s s s p i s t a t u s c o n t r o l l o g i c s p i s t a t u s r e g i s t e r s p i c o n t r o l r e g i s t e r c l o c k l o g i c s m m s c l o c k s p i f w c o l s p i o v f m o d f d i s m o d f s p i i n t e r r u p t r e q u e s t s p i e n m s t r m s t r s s o e d i s m o d f s p r 0 s p r 1 s p r 0 s p r 1 c p h a c p o l m s t r l s b f e s p i e n s s o e s p i e n i n t e r n a l d a t a b u s f s y s
n79e 71 5 datasheet jan. 6 , 201 6 page 73 of 189 revision 1.0 1 figure 13 C 1 shows spi block diagram and provides an overview of spi architecture in this device. the main blocks of spi are the spi control register logic , spi status logic, clock rate control logic, and pin control logic . for a serial data transfer or receiving, the spi block exists a shift register and a read data buffer. it is single buffered in the transmit direction and double buffered in the receiv ing direction. transmit data cannot be written to the shifter until the previous transfer is compl ete. receiv ing logic consist s of parallel read data buffer so the shift r egister is free to accept a second data, as the first received data will be transferred to the read data buf f er. the four pins of spi interface are master - in/slave - out (miso), master - out/slave - in (mosi), shift clock (s pcl k), and slave select ( ). the mosi pin is used to transfer a 8 - bit data in series from the master to the slave. therefore, mosi is an output pin for master device and a input for slave. respectivel y , the miso is used to receive a serial dat a from the slave to the master. the s pclk pin is the clock output in master mode, but is the clock input in slave mode. the shift clock is used to synchronize the data movement both in and out of the devices throu gh their mosi and miso pins. the shift clock is driven by the master mode device for eight clock cycles which exchanges one byte data on the serial lines. for the shift clock is always produced out of the master device, the system should never exist more t han one device in master mode for avoiding device conflict. it is strongly reco m mended that t he schmitt trigger input buffer be enabled. each slave peripheral is selected by one slave select pin ( ). the signal should stay low for any slave a c cess. when is driven high, the slave device will be inactivated. if the system is multi - slave, there should be only one slave device selected at the same time. in the master mode mcu , the pin does not f unction and it can be configured as a general purpose i/o. however, can be used as master mode fault detection (s ee section 13.7 mode fault detection ) via software setting if multi - master environment exists. t he N79E715 also provide s auto - activating function to toggle between each byte - transfer. ss ss
n79e 71 5 datasheet jan. 6 , 201 6 page 74 of 189 revision 1.0 1 figure 13 - 2 spi multi - master, multi - slave interconnection figure 13 - 2 shows a typical interconnection of spi devices. the bus generally connects devices together through three signal wires, mosi to mosi, miso to miso , and s p c l k to s p c l k. the master devices select the individual slave devices by using four pins of a parallel port to control the four pins. mcu1 and mcu2 play either master or slave mode. the should be configu red as master mode fault detection to avoid mu l ti - master conflict. figure 13 - 3 spi single - master, single - slave interconnection figure 13 - 3 shows the simplest spi system interconnection, single - master and signal - slave. during a transfer, the master shifts data out to the slave via mosi line. while simultaneously, the master shifts data in from the slave via miso line. the two shift register s in the master mcu and the slave mcu can be considered as one 16 - bit circular shift register. therefore, while a transfer data pushed from master into slave, the data in slave will also be pulled in master device respectively . the transfer effectively exc hanges the data which was in the spi shift registers of the two mcu s . ss m i s o m o s i s p c l k s s i / o p o r t 0 1 2 3 i / o p o r t 0 1 2 3 s o s i s c k s s s l a v e d e v i c e 1 m a s t e r / s l a v e m c u 1 m i s o m o s i s p c l k s s m a s t e r / s l a v e m c u 2 s o s i s c k s s s l a v e d e v i c e 2 s o s i s c k s s s l a v e d e v i c e 3 s p i c l o c k g e n e r a t o r m i s o m i s o m o s i m o s i s p c l k s p c l k v s s s s s s 7 6 5 4 3 2 1 0 s p i s h i f t r e g i s t e r 7 6 5 4 3 2 1 0 s p i s h i f t r e g i s t e r m a s t e r m c u s l a v e m c u * * s s c o n f i g u r a t i o n f o l l o w s d i s m o d f a n d s s o e b i t s .
n79e 71 5 datasheet jan. 6 , 201 6 page 75 of 189 revision 1.0 1 by default , spi data is transferred msb first. if the lsbfe (spcr.5) is set, spi data shifts lsb first. this bit does not affect the position of the msb and lsb in the data register. no te that all following d e scription and figures are under the condition of lsbfe logic 0. msb is transmitted and received first. 13.3 spi control registers there are three spi registers to support its operations, they are spi control register (spcr) , spi status r egi s ter (spsr) , and spi data register (spdr) . these registers provide control, status, data storage functions , and clock rate selection. the following regis ters relate to spi function. spi_sel (auxr1.7) support s software switches between two groups of spi pin. auxr1 C aux function resgister - 1 7 6 5 4 3 2 1 0 spi_sel uart_sel - - disp26 - 0 dps r/w r/w - - r/w - r r/w address: a2h reset value: 0000 0000b bit name description 7 spi_sel 0 = select p1.7, p1.6, p1.4, and p0.0 as spi pins. 1 = select p2.2, p2 .3, p2.4, and p2.5 as spi pins. spcr C serial peripheral control register 7 6 5 4 3 2 1 0 ssoe spien lsbfe mstr cpol cpha spr1 spr0 r/w r/w r/w r/w r/w r/w r/w r/w address: f3 h reset value: 00 00 0000b bit name description 7 ssoe slave select output en able this bit is used in combination with the dismodf (spsr.3) bit to determine the feature of pin . this bit takes effect only under mstr = 1 and dismodf = 1 condition. 0 = functions as a general purpose i/o pi n. 1 = automatically goes low for each transmission when selecting external slave device and goes high during each idle state to de - select the slave device. ss ss
n79e 71 5 datasheet jan. 6 , 201 6 page 76 of 189 revision 1.0 1 bit name description 6 spien spi enable 0 = disable spi function. 1 = enable spi function. 5 ls bfe lsb first enable 0 = the spi data is transferred msb first. 1 = the spi data is transferred lsb first. 4 mstr master mode enable this bit switches the spi operating between master and slave modes. 0 = the spi is configured as slave mode. 1 = the spi i s configured as master mode. 3 cpol spi clock polarity selection cpol bit determines the idle state level of the spi clock. refer to figure 13 - 4 spi clock format 0 = spi clock is low in idle state. 1 = spi clock i s high in idle state. 2 cpha spi c lock p hase s elect ion cpha bit determines the data sampling edge of the spi clock. refer to figure 13 - 4 spi clock format . 0 = the data is sampled on the first edge of the spi clock . 1 = the data is sampled on the second edge of the spi clock. 1 spr1 spi clock rate selection the two bits select four grades of spi clock divider. spr 1 spr 0 divider spi clock rate 0 0 16 1.25m bit/s 0 1 32 625k bit/s 1 0 64 312k bit/s 1 1 128 156k bit/s the clock rates above are illustrated under f sys = 20 mhz condition. 0 spr0 table 13 C 1 slave select pin configuration dismodf ssoe master mode (mstr = 1) slave mode (mstr = 0) 0 x input for mode fault input for slave select 1 0 general purpose i/o ss ss
n79e 71 5 datasheet jan. 6 , 201 6 page 77 of 189 revision 1.0 1 1 1 automatic output spsr C serial peripheral status register 7 6 5 4 3 2 1 0 spif wcol spiovf modf dismodf - - - r/w r/w r/w r/w r/w - - - address: f4h reset value: 0000 0000b bit name description 7 spif spi complete f lag this bit is set to logic 1 via hardware while an spi data transfer is complete or an receiving data has been moved into the spi read buffer . if espi ( eie .6 ) and ea are enabled, an spi interrupt will be required. this bit should be cleared via sof t ware . attempting to write to spdr is inhibited if spif is set. 6 wcol write collision error flag this bit indicates a write collision event. once a write collision event occurs, this bit will be set. it should be cleared via software . 5 spiovf spi overrun error flag this bit indicates an overrun event. once an overrun event occurs, this bit will be set. if espi and ea are enabled, an spi interrupt wi ll be required. this bit should be cleared via software . 4 modf mode fault error flag this bit indicates a mode fault error event. if pin is configured as mode fault input (mstr = 1 and dismodf = 0) and is pul led low by external d e vices, a mode fault error occurs. instantly modf will be set as logic 1. if espi and ea are enabled, an spi interrupt will be required. this bit should be cleared via software . 3 dismodf mode fault error detection disable this bit is used in combination with the ssoe (spcr.7) bit to determine the fe a ture of pin . dismodf affects only in master mode (mstr = 1). 0 = mode fault detection is not disabled. serves as input pin for mode fault de te ction disregard of ssoe. 1 = mode fault detection is disabled. the feature of follows ssoe bit. 2:0 - reserved ss ss
n79e 71 5 datasheet jan. 6 , 201 6 page 78 of 189 revision 1.0 1 spdr C serial peripheral data register 7 6 5 4 3 2 1 0 spdr[7:0] r/w address: f5h reset value: 0000 0000b bit name de scription 7:0 spdr[7:0] serial peripheral data this byte is used for transmitting or receiving data on spi bus. a write of this byte is a write to the shift register. a read of this byte is actually a read of the read data buffer. in master mode, a write to this register initiates transmission and reception of a byte simultaneously. 13.4 operating modes 13.4.1 master mode the spi can operate in master mode while mstr (spcr.4) is set as 1. only one m aster spi device can init i ate transmission s . a transmission always be gins by master through writing to spdr. the byte written to spdr begin s shifting out on mosi pin under the control of spclk. simultaneously, another byte shifts in from the slave on the miso pin. after 8 - bit data transfer complete, spif (spsr.7) will autom atically set via hardware to indicate one byte data transfer complete. at the same time, the data received from the slave is also transferred in spdr. the user can clear spif and read data out of spdr. 13.4.2 slave mode when mstr is 0, the spi operates in slave mode. t he spclk pin becomes input and it will be clock ed by another m aster spi device. the pin also becomes input. the master device cannot exchange data with the slave device until the pin of the slave device is externally pulled low. before data transmissions o c curs, the of the slave device should be pulled and remain low until the transmission is complete. if goes high, the spi is forced into idle state. if the is force to high at the middle of transmission, the transmission will be aborted and the rest bits of the receiving shifter buffer will be high and goes into idle state. in slave mode, d ata flows from the m aster to the s lave on mosi pi n and flows from the s lave to the m aster on miso pin. the data enters the shift register under the control of the spclk from the master device. after one byte is received in the shift register, it is immediately moved into the read data buffer and the spif bit is set. a read of the spdr is actually a read of the read data buffer. to prevent an ss
n79e 71 5 datasheet jan. 6 , 201 6 page 79 of 189 revision 1.0 1 overrun and the loss of the byte that caused by the overrun, the slave should read spdr out and the first spif should be cleared before a second transfer of data from the master device comes in the read data buffer . 13.5 clock formats and data transfer to accommodate a wide variety of synchronous serial peripherals, the spi has a clock polarity bit cpol (spcr.3) and a clock phase bit cpha (spcr.2) . figure 13 - 4 spi clock format shows that cpol and cpha compose four different clock formats. the cpol bit denotes the spclk line level in isp idle state . the cpha bit defines the edge on which the mosi and miso lines are sampled. the cpol a nd cpha should be identical for the master and slave devices on the same system. communicating in d ifferent data formats with one another will result in undetermined result s . figure 13 - 4 spi clock format in spi, a master device always initiates the transfer . if spi is selected as master mode (mstr = 1) and en a bled (spien = 1), writing to the spi data register (spdr) by the master device starts the spi clock and data transfer. afte r shifting one byte out and receiving o ne byte in, the spi clock stops and spif (spsr.7) in both master and slave are set. if spi interrupt enable bit espi ( eie .6 ) is set 1 and global interrupt is enabled (ea = 1), the interrupt service routine (isr) of sp i will be executed. concerning the slave mode, the signal needs to be taken care . as shown in figure 13 - 4 spi clock format , when cpha = 0, the first spclk edge is the sampling strobe of msb ( for an example of lsbfe = 0, msb first). therefore, the slave should shift its msb data before the first spclk edge. t he falling edge of is used for preparing the msb on miso line. the pin therefore should togg le high and then low between each successive serial byte. furthermore , if the slave writes data to the spi data register (spdr) while is low, a write collision error occurs. ss c p h a = 0 c p h a = 1 s a m p l e c p o l = 0 c p o l = 1 c l o c k p h a s e ( c p h a ) c l o c k p o l a r i t y ( c p o h ) s a m p l e s a m p l e s a m p l e
n79e 71 5 datasheet jan. 6 , 201 6 page 80 of 189 revision 1.0 1 when cpha = 1, the sampling edge thus locates on the second edge of spclk clock. the slave uses the first spclk clock to shift msb out rather than the falling edge. therefore, the line can remain low between successive transfers. this format may be preferred in systems having single fixed master and single fixed slave. the line of the unique slave device can be tied to v ss as long as only cpha = 1 clock mode is used. note: the spi should be configured before it is enabled (spien = 1) , or a change of lsbfe, mstr, cpol, cpha and spr[1:0] will abort a transmission in progress and force the spi system into idle state. prior to any configuration bit changed, spien should be disabled first. figure 13 - 5 spi clock and data format with c ph a = 0 ss s p c l k c y c l e s s p c l k ( c p o l = 0 ) m o s i s s o u t p u t o f m a s t e r [ 2 ] s p i f ( m a s t e r ) 1 2 3 4 5 6 7 8 s p c l k ( c p o l = 1 ) t r a n s f e r p r o g r e s s [ 1 ] ( i n t e r n a l s i g n a l ) m s b m i s o 6 5 4 3 2 1 l s b m s b i n p u t t o s l a v e s s l s b 6 5 4 3 2 1 s p i f ( s l a v e ) [ 1 ] t r a n s f e r p r o g r e s s s t a r t s b y a w r i t i n g s p d r o f m a s t e r m c u . [ 2 ] s s a u t o m a t i c o u t p u t a f f e c t s w h e n m s t r = d i s m o d f = s s o e = 1 . s p c l k c y c l e s
n79e 71 5 datasheet jan. 6 , 201 6 page 81 of 189 revision 1.0 1 figure 13 - 6 spi clock and data format with c ph a = 1 13.6 slave select pin configuration t he N79E715 spi provides a flexib le pin feature for different system requirements. when the spi o p erates as a slave, pin always rules as slave select input. when the master mode is enabled, has three different functions according to dismodf (spsr.3) and ssoe (spcr.7). by default, dismodf is 0. it means that the mode fault detection activate s . is configured as a input pin to check if the mode fault a p pears. on the contrary, if dismodf is 1, mode faul t is inactivated and the ssoe bit takes over to control the function of the pin. while ssoe is 1, it means the slave select signal will generate automatically to select a slave device. the as output pin of the master usually connect s with the input pin of the s lave d e vice. the output automatically goes low for each transmission when selecting external slave device and goes high during each idl e state to de - select the slave device. while ssoe is 0 and dismodf is 1, is no more used by the spi and reverts to be a general purpose i/o pin. ss t r a n s f e r p r o g r e s s [ 1 ] ( i n t e r n a l s i g n a l ) s p c l k c y c l e s s p c l k ( c p o l = 0 ) m o s i s s o u t p u t o f m a s t e r [ 2 ] s p i f ( m a s t e r ) 1 2 3 4 5 6 7 8 s p c l k ( c p o l = 1 ) m s b m i s o 6 5 4 3 2 1 l s b m s b i n p u t t o s l a v e s s l s b 6 5 4 3 2 1 s p i f ( s l a v e ) [ 1 ] t r a n s f e r p r o g r e s s s t a r t s b y a w r i t i n g s p d r o f m a s t e r m c u . [ 2 ] s s a u t o m a t i c o u t p u t a f f e c t s w h e n d i s m o d f = s s o e = m s t r = 1 . [ 3 ] i f s s o f s l a v e i s l o w , t h e m i s o w i l l b e t h e l s b o f p r e v i o u s d a t a . o t h e r w i s e , m i s o w i l l b e h i g h . [ 4 ] w h i l e s s s t a y s l o w , t h e l s b w i l l l a s t i t s s t a t e . o n c e s s i s r e l e a s e d t o h i g h , m i s o w i l l s w i t c h t o h i g h l e v e l . [ 3 ] [ 4 ] s p c l k c y c l e s ss
n79e 71 5 datasheet jan. 6 , 201 6 page 82 of 189 revision 1.0 1 13.7 mode fault detection the mode fault detection is useful in a system where more than one spi devices might become masters at the same time. it may induce data contention . a mode fault error occurs once the is pulled low by others. it indicates that some other spi device is trying to address this master as if it is a slave. instantly t he mstr an d spien control bits in the spcr are cleared via hardware to disable spi , mode fault flag modf (spsr.4) is set and an interrupt is generated if espi ( eie .6 ) and ea are enabled. 13.8 write collision error the spi is signal buffered in the transfer direc tion and double buffered in the receiving direction. new data for transmission cannot be written to the shift register until the previous transaction is complete. write collision occurs while an attempt was made to write data to the spdr while a transfer was in pr ogress. spdr is not double buffered in the transmit direction. any writing to spdr cause data to be written directly into the spi shift register . once a write collision error is generated , wcol (spsr.6) will be set as 1 via hardware to indicate a write col lision . in this case, t he current transferring data continues its transmission. however the new data that caused the collision will be lost . although the spi logic can detect write collisions in both master and slave modes, a write collision is normally a slave error because a slave has no indicator when a master initiates a transfer. during the receive of slave, a write to spdat causes a write collision under slave mode. wcol flag needs to be cleared via software. 13.9 overrun error for receiving data, the spi is double buffered in the receiving direction. t he received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial byte . however, the received data should be read from spdr before the next data has been comple tely shifted in. as long as the first byte is read out of the read data buffer and spif is cleared before the next byte is ready to be transferred, no overrun error cond i tion occurs. otherwise t he overrun error occurs. in this condition, the s econd byte da ta will not be successfully received to the read data register and the previous data will remain. if overrun occur, spiovf (spsr.5) will be set via hardware . this will also require an interrupt if enabled. figure 13 - 7 spi overrun waveform shows the relationship between the data receiving and the overrun error. ss
n79e 71 5 datasheet jan. 6 , 201 6 page 83 of 189 revision 1.0 1 figure 13 - 7 spi overrun waveform 13.10 spi i nterrupt s three spi status flags , spif, mo df, and spiovf, can generate a n spi event interrupt requests. all of them locate in spsr. spif will be set after completion of data transfer with external device or a new data have been received and copied to spdr. modf becomes set to indicate a low level on causing the mode fault state. spiovf denotes a receiving overrun error. if spi interrupt mask is enable d via setting espi ( eie . 6 ) and ea is 1 , cpu will executes the spi interrupt service routine once any of the three flags is set. the user needs to check flags to determine what event caused the interrupt. the three flags are software clear ed . figure 13 - 8 spi i nterrupt r equest ss s h i f t i n g d a t a [ n ] i n s h i f t i n g d a t a [ n + 1 ] i n s p i f d a t a [ n ] d a t a [ n ] r e a d d a t a b u f f e r s h i f t r e g i s t e r s h i f t i n g d a t a [ n + 2 ] i n s p i o v f d a t a [ n + 2 ] d a t a [ n ] r e c e i v i n g b e g i n s d a t a [ n + 1 ] r e c e i v i n g b e g i n s d a t a [ n + 2 ] r e c e i v e i n g b e g i n s [ 1 ] w h e n d a t a [ n ] i s r e c e i v e d , t h e s p i f w i l l b e s e t . [ 2 ] i f s p i f i s n o t c l e a r b e f o r e d a t a [ n + 1 ] p r o g r e s s d o n e , t h e s p i o v f w i l l b e s e t . d a t a [ n ] w i l l b e k e p t i n r e a d d a t a b u f f e r b u t d a t a [ n + 1 ] w i l l b e l o s t . [ 3 ] s p i f a n d s p i o v f m u s t b e c l e a r e d b y s o f t w a r e . [ 4 ] w h e n d a t a [ n + 2 ] i s r e c e i v e d , t h e s p i f w i l l b e s e t a g a i n . [ 1 ] [ 2 ] [ 3 ] [ 3 ] [ 4 ] s p i f d i s m o d f m s t r e s p i ( e i e . 6 ) s p i i n t e r r u p t r e q u e s t s p i o v f m o d e f a u l t d e t e c t i o n s s m o d f e a
n79e 71 5 datasheet jan. 6 , 201 6 page 84 of 189 revision 1.0 1 org 0000h ljm p start org 004bh ljmp spi_isr org 0100h spi_isr: anl spsr,#7fh reti start: anl spcr,#0dfh ;msb first anl spcr,#0f7h ;the spi clock is low in idle mode orl spcr,#04h ; the data is sample on the second edge of spi clock orl spcr,#10h ;spi in master mode anl spcr,#0fch ;spi clock = fosc/16 setb espi ;enable spi interrupt setb ea orl spcr,#40h ;enab le spi function mov spdr,#90h ;send 0x90 to slave orl pcon,#01h ;enter idle mode sjmp $ end
n79e 71 5 datasheet jan. 6 , 201 6 page 85 of 189 revision 1.0 1 14 keyboard interrupt (kbi) the N79E715 provide s the 8 keyboard interrupt function to detect keypad status whic h key is acted, and allow a single interrupt to be generated when any key is pressed on a keyboard or keypad connected to specific pins of the N79E715 , as shown in the following figure. this interrupt may be used to wake up the cpu from idle or power - down mode , after chip is in power - d own or idle mode . keyboard function is supported through by port 0. it can allow any or all pins of port 0 to be enabled to cause this interrupt. port pins are enabled by the setting of bits of kbi0 ~ kbi7 in the kbi register , as shown in the following figure. the keyboard interrupt flag, kbif[7:0] in the kbif( ea h), is set when any enabled pin is triggered while the kbi interrupt function is active, an interrupt will be generated if it has been enabled. the kbif[7:0] bit is se t by hardware and should be cleared by software. to determine which key was pressed, the kbi will allow the i n terrupt service routine to poll port 0. kbi supports four triggered conditions low level, falling edge, rising edge and either rising or fallin g edge detection. the triggered condition of each port pin is individ ually controlled by two bits kbl s 1( ec h).x and k bl s 0( eb h).x where x is 0 to 7. a fter trigger occur s and two machine s pass , kbif assert. kbi is generally used to detect an edge transient f rom peripheral devices like keyboard or keypad. during idle state, the system prefers to enter power - down mode to minimize power consumption and waits for event tri g ger. the N79E715 support s kbi interrupt waking up mcu from power down . note that if kbi is selected as any of edge trigger mode, restrictions should be followed to make power down woken up valid. for a falling edge waking up, pin state should be high at the moment of entering power - down mode . r e spectively, pin state should be low for a rising ed ge waking up.
n79e 71 5 datasheet jan. 6 , 201 6 page 86 of 189 revision 1.0 1 figure 14 - 1 keyboard interrupt detect ion kbi . 0 kbi . 5 eie . ekb kbi i nterrupt request p 0 . 5 p 0 . 0 kbi . 6 kbi . 7 p 0 . x p 0 . 6 p 0 . 3 kbi . 2 kbi . 3 p 0 . 2 kbi . 4 p 0 . 4 kbi . 1 p 0 . 1 [ 00 ] [ 01 ] [ 11 ] [ kbis 1 . x , kbis 0 . x ] or low - level [ 10 ] p 0 . 7 low - level / edge detect low - level / edge detect low - level / edge detect low - level / edge detect low - level / edge detect low - level / edge detect low - level / edge detect low - level / edge detect kbi low - leve / edge detect selection x = 0 ~ 7 kbi f . 7 kbi f . 6 kbi f . 5 kbi f . 4 kbi f . 3 kbi f . 2 kbi f . 1 kbi f . 0
n79e 71 5 datasheet jan. 6 , 201 6 page 87 of 189 revision 1.0 1 table 14 C 1 configuration for different kbi level select ion kb l s1.n kb l s0.n kbi channel n type 0 0 falling edge 0 1 rising edge 1 0 either falling or rising edge 1 1 low level kbi e C key b oard interrupt enable register 7 6 5 4 3 2 1 0 kbi e .7 kbi e .6 kbi e .5 kbi e .4 kbi e .3 kbi e .3 kbi e .1 kbi e .0 r/w r/w r/w r/w r/w r/w r/w r/w a ddress: e9h reset value: 0000 0000b bit name description 7:0 kbi e key b oard interrupt enable p0[7:0] as a cause of a keyboard interrupt. kbif C keyboard interface flags 7 6 5 4 3 2 1 0 kbif[7:0] r (level) r/w (edge) address: eah reset value: 0000 0000 b bit name description 7:0 kbifn keyboard interface channel n flag if any edge trigger mode of kbi is selected, this flag will be set by hardware if kbi channel n (p0.n) detects a type defined edge. this flag should be cleared by sof t ware. if the low level trigger mode of kbi is selected, this flag follows the inverse of the input signals logic level on kbi channel n (p0.n)l. software cannot control it. kbls0 C keyboard level select 0 [1] 7 6 5 4 3 2 1 0 kbls0[7:0] r/w address: ebh reset value: 0000 000 0 b bit name description 7:0 kbls0[7:0] keyboard level select 0
n79e 71 5 datasheet jan. 6 , 201 6 page 88 of 189 revision 1.0 1 kbls1 C keyboard level select 1 [1] 7 6 5 4 3 2 1 0 kbls1[7:0] r/w address: ech reset value: 0000 0000 b bit name description 7:0 kbls1[7:0] keyboard level select 1 [1] kbls1 and kbls0 ar e used in combination to determine the input type of each channel of kbi (on p0). refer to table 14 C 1 configuration for different kbi level select .
n79e 71 5 datasheet jan. 6 , 201 6 page 89 of 189 revision 1.0 1 15 analog - to - digital converter (adc) the adc contains a dac which con verts the contents of a successive approximation register to a voltage (v dac ) which is compared to the analog input voltage (vin). the output of the comparator is fed to the succe s sive approximation control logic which controls the successive approximation register. a conversion is initiated by setting adcs in the adccon 0 register. adcs can be set by software only or by either hardware or software. note that when the adc function is disabled, all adc related sfr bits will be unavailable and will not a f fect any other cpu functions. the power of adc block is approached to zero. the software only start mode is selected when control bit adccon 0 .5 (adcex) =0. a conversion is then started by setting control bit adccon 0 .3 (adcs) the hardware or software start mod e is selected when adccon 0 .5 (adcex) =1, and a conversion may be started by setting adccon 0 .3 as above or by applying a rising edge to external pin stadc. when a conversion is started by applying a rising edge, a low level should be applied to stadc for at least one machine - cycle followed by a high level for at least one m a chine - cycle. the low - to - high transition of stadc is recognized at the end of a machine - cycle, and the conversion co m mences at the beginning of the next cycle. when a conversion is initia ted by software, the conversion starts at the beginning of the machine - cycle which follows the instruction that sets adcs. adcs is actually implemented with tpw flip - flops: a command flip - flop which is affected by set operations, and a status flag which is a c cessed during read operations. the next two machine - cycles are used to initiate the converter. at the end of the first cycle, the adcs status flag is set end a value of 1 will be returned if the adcs flag is read while the conversion is in progress. sa m pling of the analog input commences at the end of the second cycle. during the next eight machine - cycles, the voltage at the p reviously selected pin of port 0 is sampled, and this input voltage should be stable to obtain a useful sample. in any event, the input voltage slew rate should be less than 10v/ms to prevent an undefined result. the successive approximation control logic first sets the most significant bit and clears all other bits in the su c cessive approximation register (10 0000 0000b). the output of the dac (50% full scale) is compared to the input voltage vin. if the input voltage is greater than v dac , the bit remains set; otherwise i t is cleared.
n79e 71 5 datasheet jan. 6 , 201 6 page 90 of 189 revision 1.0 1 the successive approximation control logic now sets the next most significant bit (11 0000 00 00b or 01 0000 0000b, depending on the previous result), and the v dac is compared to vin again. if the input voltage is greater than v dac , the bit remains set; otherwise it is cleared. this process is repeated until all ten bits have been tested, at which stage the result of the conversion is held in the successive approximation register. the co n version takes four machine - cycles per bit. the end of the 10 - bit conversion is flagged by control bit adccon 0 .4 (adci). the upper 8 bits of the result are held in special function register adch, and the two remaining bits are held in adccon 0 .7 (adc.1) and adccon 0 .6 (adc.0). the user may ignore the two least significant bits in adccon 0 and use the adc as an 8 - bit converter (8 upper bits in adch). in any event, the t otal actual conversion time is 35 machine - cycles. adc will be set and the adcs status flag will be reset 35 cycles after the adcs is set. control bits adccon 0 .0 ~ adccon 0 .2 are used to control an analog multiplexer which selects one of 8 an a log channels. an adc conversion in progress is unaffected by an external or software adc start. the result of a completed conversion remains unaffected provided adci = logic 1; a new adc conversion already in pr o gress is aborted when entering i dle or power - down mode . t he result of a completed conversion (adci = logic 1) remains unaffected when entering i dle mode. when adc c on 0 .5 (adcex) is set by external pin to start adc conversion, after the N79E715 enters idle mode, p1.4 can start adc conversion at least one machine - cycle. figure 15 - 1 successive approximation adc the adc circuit has its own supply pins (av dd and av ss ) and one pins (vref+) connected to each end of the dacs resistance - ladder that the av dd and vref+ are connected to v dd and av ss is connected to v ss . the la d der has 1023 equally spaced taps, separated by a resistance of r. the first tap is located 0.5r above a v ss , and the last tap is located 0.5r below vref+. this gives a to tal ladder resistance of 1024r. this structure ensures that the dac is monotonic and results in a symmetrical quantization error. d a c m s b l s b s u c c e s s i v e a p p r o x i m a t i o n r e g i s t e r v i n + - c o m p a r a t o r s t a r t r e a d y ( s t o p ) s u c c e s s i v e a p p r o x i m a t i o n c o n t r o l l o g i c v d a c
n79e 71 5 datasheet jan. 6 , 201 6 page 91 of 189 revision 1.0 1 for input voltages between a v ss and [(vref+) + ? lsb], the 10 - bit result of an a/d conversion will be 0000000000b = 000h. fo r input voltages between [(vref+) C 3/2 lsb] and vref+, the result of a conversion will be 1111111111b = 3ffh. avref+ and av ss may be between av dd + 0.2v and av ss C 0.2 v. avref+ should be positive with respect to av ss , and the input voltage (vin) should b e between avref+ and av ss . the result can always be calculated according to the following formula: result = figure 15 - 2 adc block diagram vdd vin 1024 ? 1 0 - b i t s a d c b l o c k a d c . [ 9 : 0 ] a d c i [ 3 ] ( a d c c o n 0 . 4 ) a d c s [ 1 ] ( a d c c o n 0 . 3 ) v d d v r e f v s s a a d r [ 2 : 0 ] a d c c o n 0 [ 2 : 0 ] a n a l o g i n p u t m u l t i p l e x e r 0 1 p 1 . 4 a d c e x ( a d c c o n 0 . 5 ) a d c c l k a d c c o n v e r s i o n b l o c k a d c e n ( a d c c o n 1 . 7 ) a d c 1 ( p 0 . 2 ) a d c 2 ( p 0 . 3 ) a d c 3 ( p 0 . 4 ) a v s s a v d d [ 1 ] . w r i t e t o a d c s t o s t a r t a d c c o n v e r t i o n [ 2 ] . r e a d f r o m a d c s t o m o n i t o r a d c c o n v e r t i o n f i n i s h e d o r n o t . n o t e : a d c s [ 2 ] 0 1 f s y s / 4 r c c l k ( a d c c o n 1 . 1 ) r c 2 2 m h z / 4 o r r c 1 1 m h z / 2 c p u c l k r c o s c a d c 4 ( p 0 . 5 ) a d c 5 ( p 0 . 6 ) a d c 6 ( p 0 . 7 ) a d c 7 ( p 2 . 6 ) a d c 0 ( p 0 . 1 ) 0 1 b a n d - g a p ( 1 . 3 v ) [ 3 ] . r e a d f r o m a d c i t o m o n i t o r a d c c o n v e r t i o n f i n i s h e d o r n o t . a d c 0 s e l ( a d c c o n 1 . 0 )
n79e 71 5 datasheet jan. 6 , 201 6 page 92 of 189 revision 1.0 1 adccon 0 C adc control register 0 7 6 5 4 3 2 1 0 adc.1 adc.0 adcex adci adcs aadr2 aadr1 aadr0 r/w r/w r/w r/w r/w r/w r/w r/w address: f8h reset value: 0000 0000b bit name description 7 adc.1 adc conversion result. 6 adc.0 adc conversion result. 5 adcex 0 = disab le external start of conversion by p1.4. 1 = enable external start of conversion by p1.4. the stadc signal at least 1 machine - cycle. 4 adci 0 = the adc is not busy. 1 = the adc conversion result is ready to be read. an interrupt is invoked if it is enabl ed. it can not set by software. 3 adcs adc start and status: set this bit to start an a/d conversion. it may also be set by stadc if adcex is 1. this signal remains high while the adc is busy and is reset right after adci is set. notes: it is recomme nded to clear adci before adcs is set. however, if adci is cleared and adcs is set at the same time, a new a/d conversion may start on the same channel. software clearing of adcs will abort conversion in progress. adc cannot start a new conversion while a dcs or adci is high. 2 aadr2 adc input select. 1 aadr1 adc input select. 0 aadr0 adc input select. adci adcs adc status 0 0 adc not busy; a conversion can be started. 0 1 adc busy; start of a new conversion is blocked 1 0 conversion completed; the start of a new conversion requires adci = 0 1 1 conversion completed; the s tart of a new conversion requires adci = 0 if adc is cleared by software while adcs is set at the same time, a new a/d conversion with the same cha n nel number may be started. howe ver, it is recommended to reset adci before adcs is set. addr2, aadr1, aadr0: adc analog input channel select bits: these bits can only be changed when adci and adcs are both zero. aadr2 aadr1 aadr0 selected analog channel 0 0 0 adc0 (p0.1)
n79e 71 5 datasheet jan. 6 , 201 6 page 93 of 189 revision 1.0 1 0 0 1 a dc1 (p0.2) 0 1 0 adc2 (p0.3) 0 1 1 adc3 (p0.4) 1 0 0 adc4 (p0.5) 1 0 1 adc5 (p0.6) 1 1 0 adc6 (p 0.7 ) 1 1 1 adc7 (p2. 6 ) adch C adc converter result register 7 6 5 4 3 2 1 0 adc.9 adc.8 adc.7 adc.6 adc.5 adc.4 adc.3 adc.2 r/w r/w r/w r/w r/w r/w r/w r/w address: e2 h reset value: 00 00 0000b bit name description 7:0 adc h adc conversion result bits [9:2] adccon 1 C adc control register 7 6 5 4 3 2 1 0 adcen - - - - - rcclk adc0sel r/w - - - - - r/w r/w address: e1 h reset value: 0000 0000b bit name description 7 adcen 0 = disable adc circuit. 1 = enable adc circuit. 6 :2 - reserved 1 rcclk 0 = the f sys /4 clock is used as adc clock. 1 = the f hirc / 2 clock is used as adc clock. 0 adc0sel 0 = select adc channel 0 as input. 1 = select band - gap ( ~ 1. 3 v) as input. p0dids C port0 digital input disable 7 6 5 4 3 2 1 0 p0dids[7:0] r/w r/w r/w r/w r/w r/w r/w r/w address: f6h reset value: 0000 0000b bit name description 7:0 p0dids.x 1 = disable digital function for each port0. 0 = enable digital functio n for each port0.
n79e 71 5 datasheet jan. 6 , 201 6 page 94 of 189 revision 1.0 1 auxr1 C aux function resgister - 1 7 6 5 4 3 2 1 0 spi_sel uart_sel - - disp26 - 0 dps r/w r/w - - r/w - r r/w address: a2h reset value: 0000 0000b bit name description 3 disp26 0 = enable p2.6 digital input and output. 1 = disable p2 .6 digital input and output for adc channel 7 used. the demo code of adc channel 0 with clock source = fsys/4 is as follows : org 0000h ljmp start org 005bh ;adc interrupt service routine clr adci ;clear a dc flag reti start: orl p0dids,#0 2 h ; disable digital function for p0.1 orl p0m1,#0 2 h ; adc0(p0.1) is input - only mode anl p0m2,#0f d h anl adc c on 0 ,#0f 8h ;adc0(p0.1) as adc channel anl adccon1 ,#0fdh ; the fsys/4 clock is used as adc clock. setb eadc ;enable adc interrupt setb ea orl adccon1,#80h ;enable adc function convert_loop: setb adcs ; trigger adc orl pcon,# 01h ;enter idle mode mov p0,adch ;converted data put in p0 and p1 mov p1,adcl sjmp convert_loop end
n79e 71 5 datasheet jan. 6 , 201 6 page 95 of 189 revision 1.0 1 16 inter - integrated circuit (i 2 c) 16.1 features the inter - integrated circuit (i 2 c) bus serves as a serial interface betwee n the microcontroller and the i 2 c d e vices such as eeprom, lcd module, and so on. the i 2 c bus used two wires design (a serial data line sda and a serial clock line scl) to transfer information between devices. the i 2 c bus uses bidirectional data transfer be tween masters and slaves. there is no central master and the multi - master system is allowed by arbitration between simultaneously transmitting masters. the serial clock synchronization allows devices with different bit rates to communicate via one serial b us. the i 2 c bus supports four transfer modes including master transmitter mode, master receiver mode, slave receiver mode, and slave transmitter mode. the i 2 c interface only supports 7 - bit addressing mode and general call can be accepted. the i 2 c can meet both standard (up to 100kbps) and fast (up to 400kbps) speeds. 16.2 function al description for the bidirectional transfer operation, the sda and scl pins should be connected to open - drain pads. this i m plements a wired - and function which is essential to the oper ation of the interface. a low level on a i 2 c bus line is generated when one or more i 2 c devices output a 0. a high level is generated when all i 2 c devices output 1, allowing the pull - up resistors to pull the line high. in N79E715 , the user should set o utput latches of p 1.2 and p 1.3 . as logic 1 before enabling the i 2 c function by setting i2cen (i2con.6). the p 1.2 and p 1.3 are configured as the open - drain i/o once the i 2 c function is enabled. the p 1 m2 and p 1 m1 will also be re - configured. it is strongly re commended that t he schmitt trigger input buffer be enabled by setting p1s for improved glitch suppression. s d a s c l n 7 9 e 7 1 5 s d a s c l s l a v e d e v i c e s d a s c l o t h e r m c u s d a s c l v d d r u p r u p
n79e 71 5 datasheet jan. 6 , 201 6 page 96 of 189 revision 1.0 1 figure 16 - 1 i 2 c bus interconnection the i 2 c is considered free when bot h lines are high. meanwhile, any device which can operate as a master can occupy the bus and generate one transfer after generating a start condition. the bus now is considered busy before the transfer ends by sending a stop condition. the master generates all of the serial clock pulses and the start and stop condition. however if there is no start condition on the bus, all devices serve as not addressed slave. the hardware looks for its own slave address or a general call address. (the general call address detection may be enabled or disabled by gc (i2addr.0).) if the matched address is received, an interrupt is requested. every transaction on the i 2 c bus is 9 bits long, consisting of 8 data bits (msb first) and a single acknowledge bit. the number of byte s per transfer (defined as the time between a valid start and stop condition) is u n restricted but each byte has to be followed by an acknowledge bit. the master device generates 8 clock pulse to send the 8 - bit data. after the 8 th falling edge of the scl li ne, the device outputting data on the sda changes that pin to an input and reads in an acknowledge value on the 9 th clock pulse. after 9 th clock pulse, the data receiving device can hold scl line stretched low if next receiving is not prepared ready. it fo rces the next byte transaction suspended. the data transaction continues when the receiver releases the scl line. figure 16 - 2 i 2 c bus protocol 16.2.1 start and stop condition s the proto col of the i 2 c bus defines two states to begin and end a transfer, start (s) and stop (p) cond i tions. a start condition is defined as a high - to - low transition on the sda line while scl line is high. t he stop condition is defined as a low - to - high transition on the sda line while scl line is high. a start or a stop condition is always generated by the master and i 2 c bus is considered busy after a start condition and free after a stop condition. after issuing the stop condition successful, the original master device will release the control authority and turn back as a not addressed slave. consequently, the original addressed slave will become a not addressed slave. the i 2 c bus is free and listens to next start condition of next tran s fer. s d a s c l m s b l s b a c k 1 2 8 9 s t a r t c o n d i t i o n s t o p c o n d i t i o n
n79e 71 5 datasheet jan. 6 , 201 6 page 97 of 189 revision 1.0 1 a data transfer is alw ays terminated by a stop condition generated by the master. however, if a master still wishes to communicate on the bus, it can generate a repeated start (sr) condition and address the pervious or another slave without first generating a stop condition. va rious combinations of read/write formats are then possible within such a transfer. figure 16 - 3 start, repeated start, and stop conditions 16.2.2 7 - bit address with data format following the start condition is generated, one byte of special data should be transmitted by the master. it includes a 7 - bit long slave address (sla) following by an 8 th bit, which is a data direction bit (r/w), to address the target slave device and determine the direction of data flow. if r/w bit is 0, it indicates that the master will write information to a selected slave, and if this bit is 1, it indicates that the master will read information from the slave. an address packet consisting of a slave address and a read (r) or a write (w) bit is called sla+r or sla+w, respectively. a transmission basically consists of a start condition, a sla+r/w, one or more data packets and a stop condition. after the specified slave is addressed by sla+r/w, the second and follow ing 8 - bit data bytes issue by the master or the slave devices according to the r/w bit configuration. there is an exception called general call address which can address all devices by giving the first byte of data all 0. a general call is used when a ma ster wishes to transmit the same message to several slaves in the system. when this address is used, other devices may respond with an acknowledge or ignore it according to individual software configuration. if a device response the general call, it operat es like in the slave - receiver mode. s d a s c l s t a r t s t o p s t a r t r e p e a t e d s t a r t s t o p
n79e 71 5 datasheet jan. 6 , 201 6 page 98 of 189 revision 1.0 1 figure 16 - 4 data format of i 2 c transfer during the data transaction period, the data on the sda line should be stable during the high period o f the clock, and the data line can only change when scl is low. 16.2.3 acknowledge the 9 th scl pulse for any transferred byte is dedicated as an acknowledge (ack). it allows receiving devices (which can be the master or slave) to respond back to the transmitter ( which can also be the master or slave) by pulling the sda line low. the acknowledge - related clock pulse is generated by the master. the transmitter should release control of sda line during the acknowledge clock pulse. the ack is an active - low signal, pull ing the sda line low during the clock pulse high duty, indicates to the transmitter that the device has r e ceived the transmitted data. commonly, a receiver which has been addressed is requested to generate an ack after each byte has been received. when a s lave receiver does not acknowledge (nack) the slave address, the sda line should be left high by the slave so that the mater can generate a stop or a repeated start cond i tion. if a slave - receiver does acknowledge the slave address, it switches itself to no t addressed slave mode and cannot receive any more data bytes. this slave leaves the sda line high. the master should generate a stop or a repeated start condition. if a master - receiver is involved in a transfer, because the master controls the number of b ytes in the transfer, it should signal the end of data to the slave - transmitter by not generating an acknowledge on the last byte. the slave - transmitter then switches to not addressed mode and release the sda line to allow the master to gene r ate a stop or a repeated start condition. s d a s c l 1 - 7 8 9 8 9 1 - 7 1 - 7 8 9 a d d r e s s w / r a c k s p d a t a a c k d a t a a c k
n79e 71 5 datasheet jan. 6 , 201 6 page 99 of 189 revision 1.0 1 figure 16 - 5 acknowledge bit 16.2.4 arbitration a master may start a transfer only if the bus is free. it is possible for two or more masters to generate a st art condition. in these situations, an arbitration scheme takes place on the sda line, while scl is high. during arbitration, the first of the competing master devices to place a '1' (high) on sda while another master tran s mits a '0' (low) switches off its data output stage because the level on the bus does not match its own level. the arbitration lost master switches to the not addressed slave immediately to detect its own slave address in the same serial transfer whether it is being addressed by the winni ng master. it also releases sda line to high level for not affecting the data transfer initiated by the winning master. however, the arbitration lost master continues scl line to generate the clock pulses until the end of the byte in which it loses the arb itration. if the a d dress matches the losing masters own slave address, it switches to the addressed - slave mode. arbitration is carried out by all masters continuously monitoring the sda line after outputting data. if the value read from the sda line does not match the value the master had output, it has lost the arbitration. note that a master can only lose arbitration when it outputs a high sda value while another master outputs a low value. arbitration will continue until only one master remains, and thi s may take many bits. if several masters are tr y ing to address the same slave, arbitration will continue into the data packet. arbitration can take place over several bits. its first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits or acknowledge bit. s d a o u t p u t b y t r a n s m i t t e r s c l f r o m m a s t e r 1 2 8 9 s t a r t c o n d i t i o n s d a o u t p u t b y r e c e i v e r s d a = 0 , a c k n o w l e d g e ( a c k ) s d a = 1 , n o t a c k n o w l e d g e ( n a c k ) c l o c k p u l s e f o r a c k n o w l e d g e b i t
n79e 71 5 datasheet jan. 6 , 201 6 page 100 of 189 revision 1.0 1 figure 16 - 6 arbitration procedure of two masters since the control of i 2 c bus is decided solely by the address or master code and data sent by competing ma s ters, there is no central master, nor any order of priority on the bus. slaves are not involved in the arbitration procedure. 16.3 control registers of i 2 c there are five control reg isters to interface the i 2 c bus. they are i2con, i2sta , i2dat, i2addr, i2clk, and i2tmr. these registers provide protocol control, status, data transmit and receive functions, clock rate config u ration, and timeout notification. the following registers rela te to i 2 c function. i2con C i 2 c control 7 6 5 4 3 2 1 0 - i2cen sta sto si aa - - - r/w r/w r/w r/w r/w - - address: c0h reset value: 0000 0000b bit name description 7 - reserved 6 i2cen i 2 c bus enable 0 = i 2 c bus is disabled. 1 = i 2 c bus is enabled. before enabling the i 2 c, px.x and px.x port latches should be set to logic 1. once the i 2 c bus is enabled , sda pin (px.x) and scl pin (px.x) will be automat i cally switched to the open - drain mode. pxm2 and pxm1 registers will also be re - configured according ly. d a t a 1 f r o m m a s t e r 1 s t a r t c o n d i t i o n m a s t e r 1 l o s e s a r b i t r a t i o n f o r d a t a 1 s d a i t i m m e d i a t e l y s w i t c h e s t o n o t a d d r e s s e d s l a v e a n d o u t p u t s h i g h l e v e l d a t a 2 f r o m m a s t e r 2 s d a l i n e s c l l i n e
n79e 71 5 datasheet jan. 6 , 201 6 page 101 of 189 revision 1.0 1 bit name description 5 sta start flag when sta is set, the i 2 c generates a start condition if the bus is free. if the bus is busy, the i 2 c waits for a stop condition and generates a start condition fo l lowing. if sta is set while the i 2 c is already in master mode and one o r more bytes have been transmitted or received, the i 2 c generates a repeated start condition. note that sta can be set anytime even in a slave mode, but sta is not hardware automatically cleared after start or repeated start condition has been detec t ed. th e user should take care of it by clearing sta manually. 4 sto stop f lag when sto is set if the i 2 c is in master mode , a stop condition is transmitted to the bus. sto is automatically cleared by hardware once the stop condition has been detected on the bus . the sto flag setting is also used to recover the i 2 c device from the bus error state ( i2sta as 00h). in this case, no stop condition is transmitted to the i 2 c bus. if the sta and sto bits are both set and the device is original in master mode , the i 2 c bu s will generate a stop condition and immediately follow a start cond i tion. if the device is in slave mode, sta and sto simultaneous setting should be avoid from issuing illegal i 2 c frames. 3 si serial interrupt f lag the si flag is set by hardware when one of 25 possible i 2 c status (besides f8h status) is entered. after si is set, the software should read i2sta register to determine which step has been passed and take actions for next step. si is cleared by software. before the si is cleared, the low period of scl line is stretched. the transaction is suspended. it is useful for the slave device to deal with previous data bytes until ready for receiving the next byte. the serial transaction is suspended until si is cleared by software. after si is cleared, i 2 c bus will continue to generate start or repeated start condition, stop condition, 8 - bit data, or so on depending on the software configuration of controlling byte or bits. therefore the user should take care of it by preparing suit a ble setting of registe rs before si is software cleared. 2 aa acknowledge assert flag if the aa flag is set, an ack (low level on sda) will be returned during the acknowledge clock pulse of the scl line while the i 2 c device is a receiver which can be a master, an addressed slav e, an own - address - matching slave, or a gen e ra - call acceptable slave. if the aa flag is cleared, a nack (high level on sda) will be returned during the acknowledge clock pulse of the scl line while the i 2 c device is a receiver which can be a master, an addr essed slave. a device with its own aa flag cleared will ignore its own salve address and the general call. consequently, si will note be asserted and no interrupt is requested. note that if an addressed slave does not return an ack under slave receiver mod e or not receive an ack under slave transmitter mode, the slave device will become a not addressed slave. it cannot receive any data until its aa flag is set and a ma s ter addresses it again. there is a special case of i2sta value c8h occurs under slave tra nsmitter mode. before the slave device transmit the last data byte to the master, aa flag can be cleared as 0. then after the last data byte transmitted, the slave device will actively switch to not addressed slave mode of disconnecting with the master. th e further reading of the master will be all ffh. 1:0 - reserved
n79e 71 5 datasheet jan. 6 , 201 6 page 102 of 189 revision 1.0 1 i2sta C i 2 c status 7 6 5 4 3 2 1 0 i2sta [7:3 ] 0 0 0 r r r r address: bdh reset value: 1111 1000b bit name description 7:3 i2sta [ 7:3 ] i 2 c status code the most five bits of i2sta contains the status code. there are 26 possible st a tus codes. when i2sta is f8h, no relevant state information is available and si flag keeps 0. all other 25 status codes correspond to the i 2 c states. when each of the status is entered, si will be set as logic 1 an d a interrupt is requested. 2:0 - reserved the least three bits of i2sta are always read as 0. i2dat C i 2 c data 7 6 5 4 3 2 1 0 i2dat[7:0] r/w address: bch reset value: 0000 0000b bit name description 7:0 i2dat[ 7 :0] i 2 c data i2dat contains a byte of the i 2 c data is going to t rans mit or a byte has just received. data in i2dat remains as long as si is logic 1. the result of reading or writing i2dat during i 2 c transmit progress is unpredicted. while data in i2dat shift out, data on the bus is simultaneou sly being shifted into update i2dat. i2dat always shows the last byte that presented on the i 2 c bus. thus the event of lost arbitration, the original value of i2dat changes after the transaction. i2addr C i 2 c own slave address 7 6 5 4 3 2 1 0 i2 addr[7:1] gc r/w r/w address: c 1 h reset value: 0000 0000b bit name description 7:1 i2 addr[7:1] i 2 c devices own slave address in master mode: these bits have no effect. in slave mode: the 7 bits define the slave address of this i 2 c device by the user . the master should address this i 2 c device by sending the same address in the first byte data after a start or a repeated start condition. if the aa flag is set, this i 2 c device will acknowledge the master after receiving its own address and become an a d dressed slave . otherwise, the addressing from the master will be ignored.
n79e 71 5 datasheet jan. 6 , 201 6 page 103 of 189 revision 1.0 1 bit name description 0 gc general call bit in master mode: this bit has no effect. in slave mode: 0 = general call is always ignored . 1 = general call is recognized if aa flag is 1; otherwise, it is ignored if aa is 0. i2clk C i 2 c clock 7 6 5 4 3 2 1 0 i2clk[7:0] r/w address: be h reset value: 0000 1110b bit name description 7:0 i2clk[7:0] i 2 c clock setting in master mode : this register determines the clock rate of i 2 c bus when the device is in master mode . the c lock rate follows the formula below. the default value will make the clock rate of i 2 c bus 400kbps if the clock system 24 mhz with divm 1/4 mode is used. note that the i2clk value of 00h and 01h are not valid. this is an implement li m i tation. in slave mode: this byte has no effect. in slave mode, the i 2 c device will automatically synchr o nize with any given clock rate up to 400kps. 16.4 operation modes in i 2 c protocol definition s , there are four operating modes including master transmitte r, master receiver, slave receive, and slave transmitter. there is also a special mode called general call. its operation is similar to ma s ter transmitter mode. 16.4.1 master transmitter mode in m aster transmitter mode, several bytes of data are transmitted to a slave receiver. the master should prepare by setting desired clock rate in i2clk and enabling i 2 c bus by writing i2cen (i2con.6) as logic 1. the master transmitter mode may now be entered by setting sta (i2con.5) bit as 1. the hardware will test the bus an d generate a start condition as soon as the bus becomes free. after a start condition is successfully produced, the si flag (i2con.3) will be set and the status code in i2sta show 08h. the progress is conti n ued by loading i2dat with the target slave addres s 1) (i2clk 4 f f sys c i 2 ? ? ?
n79e 71 5 datasheet jan. 6 , 201 6 page 104 of 189 revision 1.0 1 and the data direction bit write (sla+w). the si bit should then be cleared to commence sla+w transaction. after the sla+w byte has been transmitted and an acknowledge (ack) has been returned by the addressed slave device, the si flag is set again and i2sta is read as 18h. the appropriate action to be taken follows the user defined communication protocol by sending data continuously. after all data is transmitted, the master can send a stop condition by setting sto (i2con.4) and then clearing si to term inate the transmission. a r e peated start condition can also be generated without sending stop condition to immediately initial another transmission. figure 16 - 7 flow and status o f master transmitter mode 0 8 h a s t a r t h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , x ) i 2 d a t = s l a + w s l a + w w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , x ) a s t a r t w i l l b e t r a n s m i t t e d 1 8 h s l a + w h a s b e e n t r a n s m i t t e d a c k h a s b e e n r e c e i v e d o r 2 0 h s l a + w h a s b e e n t r a n s m i t t e d n a c k h a s b e e n r e c e i v e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , x ) a r e p e a t e d s t a r t w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , x ) i 2 d a t = d a t a b y t e d a t a b y t e w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 1 , 0 , x ) a s t o p w i l l b e t r a n s m i t t e d a s t o p h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 1 , 1 , 0 , x ) a s t o p f o l l o w e d b y a s t a r t w i l l b e t r a n s m i t t e d a s t o p h a s b e e n t r a n s m i t t e d 2 8 h d a t a b y t e h a s b e e n t r a n s m i t t e d a c k h a s b e e n r e c e i v e d o r 3 0 h d a t a b y t e h a s b e e n t r a n s m i t t e d n a c k h a s b e e n r e c e i v e d 1 0 h a r e p e a t e d s t a r t h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , x ) i 2 d a t = s l a + r s l a + r w i l l b e t r a n s m i t t e d 3 8 h a r b i t r a t i o n l o s t i n s l a + w o r d a t a b y t e t o m a s t e r r e c e i v e r 6 8 h o r 7 8 h a r b i t r a t i o n l o s t a n d a d d r e s s e d a s s l a v e r e c e i v e r a c k h a s b e e n t r a n s m i t t e d o r b 0 h a r b i t r a t i o n l o s t a n d a d d r e s s e d a s s l a v e t r a n s m i t t e r a c k h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , x ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , x ) a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 1 ) i 2 d a t = s l a + w s l a + w w i l l b e t r a n s m i t t e d m r m t t o c o r r e s p o n d i n g s l a v e m o d e
n79e 71 5 datasheet jan. 6 , 201 6 page 105 of 189 revision 1.0 1 16.4.2 master receiver mode in m aster receiver mode, several bytes of data are received from a slave transmitter. the transaction is initialized just as the master transmitter mode. following the start condition, i2dat should be loaded w ith the target slave address and the data direction bit read (sla+r). after the sla+r byte is transmitted and an acknowledge bit has been returned, the si flag is set again and i2sta is read as 40h. si flag should then be cleared to receive data from the slave transmitter. if aa flag (i2con.3) is set, the master receiver will acknowledge the slave transmitter. if aa is cleared, the master receiver will not acknowledge the slave and release the slave transmitter as a not addressed slave. after that, the ma ster can generate a stop condition or a repeated start condition to terminate the transmission or initial another one. 0 8 h a s t a r t h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , x ) i 2 d a t = s l a + r s l a + r w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , x ) a s t a r t w i l l b e t r a n s m i t t e d 4 0 h s l a + r h a s b e e n t r a n s m i t t e d a c k h a s b e e n r e c e i v e d o r 4 8 h s l a + r h a s b e e n t r a n s m i t t e d n a c k h a s b e e n r e c e i v e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , x ) a r e p e a t e d s t a r t w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) d a t a b y t e w i l l b e r e c e i v e d a c k w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 1 , 0 , x ) a s t o p w i l l b e t r a n s m i t t e d a s t o p h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 1 , 1 , 0 , x ) a s t o p f o l l o w e d b y a s t a r t w i l l b e t r a n s m i t t e d a s t o p h a s b e e n t r a n s m i t t e d 5 0 h d a t a b y t e h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = d a t a b y t e 1 0 h a r e p e a t e d s t a r t h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , x ) i 2 d a t = s l a + w s l a + w w i l l b e t r a n s m i t t e d 3 8 h a r b i t r a t i o n l o s t i n s l a + w o r n a c k b i t t o m a s t e r t r a n s m i t t e r ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , x ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , x ) a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 0 ) d a t a b y t e w i l l b e r e c e i v e d n a c k w i l l b e t r a n s m i t t e d 5 8 h d a t a b y t e h a s b e e n r e c e i v e d n a c k h a s b e e n t r a n s m i t t e d i 2 d a t = d a t a b y t e 6 8 h o r 7 8 h a r b i t r a t i o n l o s t a n d a d d r e s s e d a s s l a v e r e c e i v e r a c k h a s b e e n t r a n s m i t t e d o r b 0 h a r b i t r a t i o n l o s t a n d a d d r e s s e d a s s l a v e t r a n s m i t t e r a c k h a s b e e n t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 1 ) i 2 d a t = s l a + r s l a + r w i l l b e t r a n s m i t t e d m r m t t o c o r r e s p o n d i n g s l a v e m o d e
n79e 71 5 datasheet jan. 6 , 201 6 page 106 of 189 revision 1.0 1 figure 16 - 8 flow and status of master receiver mode 16.4.3 slave r eceiver mode in s lave receiver mode, several bytes of data are received form a master transmitter. before a transmission is commenced, i2addr should be loaded with the address to which the device will respond when addressed by a master. i2clk does not affe ct in slave mode. the aa bit should be set to enable acknow l edging its own slave address or general call. after the initialization above, the i 2 c wait until it is addressed by its own address with the data direction bit write (sla+w) or by general call a ddressing. the slave receiver mode may also be entered if arbitration is lost. after the slave is addressed by sla+w, it should clear its si flag to receive the data from the master transmi t ter. if the aa bit is 0 during a transaction, the slave will retur n a non - acknowledge after the next received data byte. the slave will also become not addressed and isolate with the master. it cannot receive any byte of data with i2dat remaining the previous byte of data which is just received. ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) i f o w n s l a + w i s r e c e i v e d , a c k w i l l b e t r a n s m i t t e d 6 0 h o w n s l a + w h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = o w n s l a + w o r 6 8 h a r b i t r a t i o n l o s t a n d o w n s l a + w h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = o w n s l a + w ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 0 ) d a t a b y t e w i l l b e r e c e i v e d n a c k w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 0 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; n o r e c o g n i t i o n o f o w n s l a o r g e n e r a l c a l l ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; o w n s l a w i l l b e r e c o g n i z e d ; g e n e r a l c a l l w i l l b e r e c o g n i z e d i f g c = 1 8 8 h d a t a b y t e h a s b e e n r e c e i v e d n a c k h a s b e e n t r a n s m i t t e d i 2 d a t = d a t a b y t e a 0 h a s t o p o r r e p e a t e d s t a r t h a s b e e n r e c e i v e d ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 1 ) d a t a b y t e w i l l b e r e c e i v e d a c k w i l l b e t r a n s m i t t e d 8 0 h d a t a b y t e h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = d a t a b y t e ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , 0 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; n o r e c o g n i t i o n o f o w n s l a o r g e n e r a l c a l l ; a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , 1 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; o w n s l a w i l l b e r e c o g n i z e d ; g e n e r a l c a l l w i l l b e r e c o g n i z e d i f g c = 1 ; a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e
n79e 71 5 datasheet jan. 6 , 201 6 page 107 of 189 revision 1.0 1 figure 16 - 9 flow and status of slave receiver mode 16.4.4 slave transmitter mode in s lave transmitter mode, several bytes of data are transmitted to a master receiver. after i2addr and i2con values are given, t he i 2 c wait until it is addressed by its own address with the data direction bit read (sla+r). the slave transmitter mode may also be entered if arbitration is lost. after the slave is addressed by sla+w, it should clear its si flag to transmit the data to the master transmitter. normally the master receiver will return an acknowledge after every byte of data is transmitted by the slave. if the acknowledge is not received, it will transmit all 1 data if it continues the transaction. it becomes a not a d d ressed slave. if the aa flag is cleared during a transaction, the slave transmit the last byte of data. the next transmitting data will be all 1 and the slave becomes not addressed. figure 16 - 10 flow and status of slave transmitter mode ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) i f o w n s l a + r i s r e c e i v e d , a c k w i l l b e t r a n s m i t t e d a 8 h o w n s l a + r h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = o w n s l a + r o r b 0 h a r b i t r a t i o n l o s t a n d o w n s l a + r h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = o w n s l a + r ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , x ) i 2 d a t = d a t a b y t e d a t a b y t e w i l l b e t r a n s m i t t e d n a c k w i l l b e r e c e i v e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 0 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; n o r e c o g n i t i o n o f o w n s l a o r g e n e r a l c a l l ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; o w n s l a w i l l b e r e c o g n i z e d ; g e n e r a l c a l l w i l l b e r e c o g n i z e d i f g c = 1 c 0 h d a t a b y t e h a s b e e n t r a n s m i t t e d n a c k h a s b e e n r e c e i v e d a 0 h a s t o p o r r e p e a t e d s t a r t h a s b e e n r e c e i v e d ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 1 ) i 2 d a t = d a t a b y t e d a t a b y t e w i l l b e t r a n s m i t t e d a c k w i l l b e r e c e i v e d b 8 h d a t a b y t e h a s b e e n t r a n s m i t t e d a c k h a s b e e n r e c e i v e d ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , 0 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; n o r e c o g n i t i o n o f o w n s l a o r g e n e r a l c a l l ; a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , 1 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; o w n s l a w i l l b e r e c o g n i z e d ; g e n e r a l c a l l w i l l b e r e c o g n i z e d i f g c = 1 ; a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 0 ) i 2 d a t = l a s t d a t a b y t e d a t a b y t e w i l l b e t r a n s m i t t e d a c k w i l l b e r e c e i v e d c 8 h l a s t d a t a b y t e h a s b e e n t r a n s m i t t e d a c k h a s b e e n r e c e i v e d
n79e 71 5 datasheet jan. 6 , 201 6 page 108 of 189 revision 1.0 1 16.4.5 general call the general call is a special condition of slave receiver mode by sending all 0 data in slave address with data direction bit. the slave addressed by a general call has different s tatus codes in i2sta with normal slave receiver mode. the general call may also be produced if arbitration is lost. figure 16 - 11 flow and status of general call mode 16.4.6 miscellaneou s states there are two i2sta status codes that do not correspond to the 24 defined states, which are mentioned in previous sections. these are f8h and 00h states. the first status code f8h indicates that no relevant information is available during each tra nsaction. mea n while, the si flag is 0 and no i 2 c interrupt is required. ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) i f g e n e r a l c a l l i s r e c e i v e d , a c k w i l l b e t r a n s m i t t e d 7 0 h g e n e r a l c a l l h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = 0 0 h o r 7 8 h a r b i t r a t i o n l o s t a n d g e n e r a l c a l l h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = 0 0 h ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 0 ) d a t a b y t e w i l l b e r e c e i v e d n a c k w i l l b e t r a n s m i t t e d ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 0 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; n o r e c o g n i t i o n o f o w n s l a o r g e n e r a l c a l l ( s t a , s t o , s i , a a ) = ( 0 , 0 , 0 , 1 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; o w n s l a w i l l b e r e c o g n i z e d ; g e n e r a l c a l l w i l l b e r e c o g n i z e d i f g c = 1 9 8 h d a t a b y t e h a s b e e n r e c e i v e d n a c k h a s b e e n t r a n s m i t t e d i 2 d a t = d a t a b y t e a 0 h a s t o p o r r e p e a t e d s t a r t h a s b e e n r e c e i v e d ( s t a , s t o , s i , a a ) = ( x , 0 , 0 , 1 ) d a t a b y t e w i l l b e r e c e i v e d a c k w i l l b e t r a n s m i t t e d 9 0 h d a t a b y t e h a s b e e n r e c e i v e d a c k h a s b e e n t r a n s m i t t e d i 2 d a t = d a t a b y t e ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , 0 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; n o r e c o g n i t i o n o f o w n s l a o r g e n e r a l c a l l ; a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e ( s t a , s t o , s i , a a ) = ( 1 , 0 , 0 , 1 ) n o t a d d r e s s e d s l a v e w i l l b e e n t e r e d ; o w n s l a w i l l b e r e c o g n i z e d ; g e n e r a l c a l l w i l l b e r e c o g n i z e d i f g c = 1 ; a s t a r t w i l l b e t r a n s m i t t e d w h e n t h e b u s b e c o m e s f r e e
n79e 71 5 datasheet jan. 6 , 201 6 page 109 of 189 revision 1.0 1 the other status code 00h means a bus error has occurred during a transaction. a bus error is caused by a start or stop condition appearing temporarily at an illegal position such as t he second through eighth bits in an address byte or a data byte including the acknowledge bit. when a bus error occurs, the si flag is set immediately. when a bus error is detected on the i 2 c bus, the operating device immediately switches to the not addres sed salve mode, release sda and scl lines, sets the si flag, and loads i2sta 00h. to recover from a bus error, the sto bit should be set as logic 1 and si should be cleared. after that, sto is cleared by hardware and release the i 2 c bus without issuing a r eal stop condition waveform. there is a special case if a start or a repeated start condition is not successfully generated for i 2 c bus is obstructed by a low level on sda line e.g. a slave device out of bit synchronization, the problem can be solved by tr ansmitting additional clock pulses on the scl line. the i 2 c hardware transmits additional clock pulses when the sta bit is set, but no start condition can be generated because the sda line is pulled low. when the sda line is eventually released, a normal s tart condition is transmitted, state 08h is entered, and the serial transaction continues. if a repeated start condition is transmitted while sda is obstructed low, the i 2 c hardware also performs the same action as above. in this case, state 08h is entered instead of 10h after a successful start condition is transmitted. note that the software is not involved in solving these bus pro b lems. 16.5 typical structure of i 2 c interrupt service routine the following software example in c language for k eil c51 compiler s hows the typical structure of the i 2 c i n terrupt service routine including the 26 state service routines and may be used as a base for user applications. user can follow or modify it for their own application. if one or more of the five modes are not used, the ass o ciated state service routines may be removed, but care should be taken that a deleted routine can never be invoked. void i2c_isr (void) interrupt 6 { switch (i2sta) { //=============================================== //bus error, always put i n isr for noise handling //=============================================== case 0x00: /*00h, bus error occurs*/ sto = 1; //recover from bus error break; //=========== //master mode //=========== case 0x08: /*08h, a start transmitt ed*/ sta = 0; //sta bit should be cleared by software
n79e 71 5 datasheet jan. 6 , 201 6 page 110 of 189 revision 1.0 1 i2dat = sla_addr1; //load sla+w/r break; case 0x10: /*10h, a repeated start transmitted*/ sta = 0; i2dat = sla_addr2; break; //======================= //master transmitter mode //======================= case 0x18: /*18h, sla+w transmitted, ack received*/ i2dat = next_send_data1; //load data break; case 0x20: /*20h, sla+w transmitted, nack received*/ sto = 1; //transmit stop aa = 1; //ready for ack own sla+w/r break; case 0x28: /*28h, data transmitted, ack received*/ if (conti_tx_data) //if continuing to send data i2dat = next_send_data2; else //if no data to be sent { sto = 1; aa = 1; } break; case 0x30: /*30h, data transmitted, nack received*/ sto = 1; aa = 1; break; //=========== //master mode //=========== case 0x38: /*38h, arbitration lost*/ sta = 1; //retry to transmit start if bus free break; //==================== //m aster receiver mode //==================== case 0x40: /*40h, sla+r transmitted, ack received*/ aa = 1; //ack next received data break; case 0x48: /*48h, sla+r transmitted, nack received*/ sto = 1; aa = 1; break; case 0x50: /*50h, data received, ack transmitted*/ data_received1 = i2dat; //store received data if (to_rx_last_data1) //if last data will be received aa = 0; //not ack next received data else //if continuing receiving data aa = 1; break; c ase 0x58: /*58h, data received, nack transmitted*/
n79e 71 5 datasheet jan. 6 , 201 6 page 111 of 189 revision 1.0 1 data_received_last1 = i2dat; sto = 1; aa = 1; break; //==================================== //slave receiver and general call mode //==================================== case 0x60: /*60h, own sla+w received, ack returned*/ aa = 1; break; case 0x68: /*68h, arbitration lost in sla+w/r own sla+w received, ack returned */ aa = 0; //not ack next received data after //arbitration lost sta = 1; //retry to transmit start if bus free break; case 0x70: / / 70h, general call received, ack returned aa = 1; break; case 0x78: /*78h, arbitration lost in sla+w/r general call received, ack returned*/ aa = 0; sta = 1; break; case 0x80: /*80h, previous own sla+w, data received, ack returned*/ data_received2 = i2dat; if (to_rx_last_data2) aa = 0; else aa = 1; break; case 0x88: /*88h, previous own sla+w, data received, nack returned, not addressed slave mode entered*/ data_received_last2 = i2dat; aa = 1; //wait for ack next master addressing break; case 0x90: /*90h, previous general call, data received, ack returned*/ data_received3 = i2dat; if (to_rx_last_data3) aa = 0; else aa = 1; break; case 0x98: /*98h, previous general call, data received, nack returned, not addressed slave mode entered*/ data_received_last3 = i2dat; aa = 1; break;
n79e 71 5 datasheet jan. 6 , 201 6 page 112 of 189 revision 1.0 1 //========= = //slave mode //========== case 0xa0: /*a0h, stop or repeated start received while still addressed slave mode*/ aa = 1; break; //====================== //slave transmitter mode //====================== case 0xa8: /*a8h, own sla+r received, ack returned*/ i2dat = next_send_data3; aa = 1; //when aa is 1, not last data to be //transmitted break; case 0xb0: /*b0h, arbitration lost in sla+w/r own sla+r received, ack returned */ i2dat = dum my_data; aa = 0; //when aa is 0, last data to be //transmitted sta = 1; //retry to transmit start if bus free break; case 0xb8: /*b8h, previous own sla+r, data transmitted, ack received*/ i2dat = next_send_data4; i f (to_tx_last_data) //if last data will be transmitted aa = 0; else aa = 1; break; case 0xc0: /*c0h, previous own sla+r, data transmitted, nack received, not addressed slave mode entered*/ aa = 1; break; case 0 xc8: /*c8h, previous own sla+r, last data trans - mitted, ack received, not addressed slave mode entered*/ aa = 1; break; }//end of switch (i2sta) si = 0; //si should be the last step of i2c isr while(sto); //wait for stop transmitted or bus error //free, sto is cleared by hardware }//end of i2c_isr
n79e 71 5 datasheet jan. 6 , 201 6 page 113 of 189 revision 1.0 1 16.6 i 2 c time - out there is a 14 - bit time - out counter which can be used to deal with the i 2 c bus hang - up. if the time - out counter is enabled, the counter starts up counti ng until it overflows. meanwhile tif will be set by hardware and requests i 2 c interrupt. when time - out counter is enabled, setting flag si to high will reset counter and restart counting up after si is cleared. if the i 2 c bus hangs up, it causes the si fla g not set for a period. the 14 - bit time - out counter will overflow and require the interrupt service. figure 16 - 12 i 2 c time - out count i2toc C i 2 c time - out counter 7 6 5 4 3 2 1 0 - - - - - i2tocen div i2t o f - - - - - r/w r/w r/w address: bf h reset value: 0000 0000b bit name description 7:3 - reserved 2 i2tocen i 2 c time - out counter e nable 0 = the i 2 c time - out counter is disabled. 1 = the i 2 c time - out counter is enabled. 1 div i 2 c time - out counter clock d ivider 0 = the divider of i 2 c time - out counter is 1/1 of f sys . 1 = the divider of i 2 c time - out counter is 1/4 of f sys . 0 i2t o f i 2 c time - out counter overflow f lag i2t o f flag is set by hardware if 14 - bit i 2 c time - out counter over flows. i2t o f flag is cleared by software. 16.7 i 2 c interrupts there are two i 2 c flags, si and i2t o f. both of them can generate an i 2 c event interrupt requests. if i 2 c inte r rupt mask is enabled via setting ei2c (eie. 0 ) and ea is 1, cpu will executes the i 2 c int errupt 1 0 f s y s 1 / 4 1 4 - b i t i 2 c t i m e - o u t c o u n t e r i 2 t f c l e a r c o u n t e r i 2 t m r e n d i v i 2 c e n s i
n79e 71 5 datasheet jan. 6 , 201 6 page 114 of 189 revision 1.0 1 service routine once any of the two flags is set. the user needs to check flags to determine what event caused the interrupt. both of i 2 c flags are cleared by software.
n79e 71 5 datasheet jan. 6 , 201 6 page 115 of 189 revision 1.0 1 17 pulse width modulated (pwm) 17.1 features the pwm (pulse width modulation) signal is a useful control solution in wide application field. it can used on motor driving, fan control, backlight brightness tuning, led light dimming, or simulating as a simple digital to analog converter output through a low pass filter circuit. the N79E715 prov ide s four channels, maximum 10 - bit pwm output. 17.2 functional description the N79E715 contain s four pulse width modulated (pwm) channels which generate pulses of programmable length and interval. the output for pwm0 is on p0.1, pwm1 on p1.6, pwm2 on p1.7 and p wm3 on p0.0. after chip reset the internal output of the each pwm channel is a 1. in this case before the pin will reflect the state of the internal pwm output a 1 should be written to each port bit that serves as a pwm output. a block diagram is shown in figure 17 - 1 . the interval between successive outputs is controlled by a 10 C bit down counter which uses configurable internal clock pre - scalar as its input. the pwm cou n ter clock has the frequency as the clock s ource f pwm = f sys / pre - scalar . when the counter reaches underflow it is reloaded with a user selectable value. this mechanism allows the user to set the pwm frequency at any i n teger sub C multiple of the microcontroller clock frequency. the repetition frequen cy of the pwm is given by: pwm frequency = , pwm active level duty = . where pwmp is contained in pwmph and pwmpl as described in the following. pwmpl C pwm counter low bits register 7 6 5 4 3 2 1 0 pwmp.7 pwm p.6 pwmp.5 pwmp.4 pwmp.3 pwmp.2 pwmp.1 pwmp.0 r/w r/w r/w r/w r/w r/w r/w r/w address: d9h reset value: 0000 0000b bit name description 7:0 pwmp l pwm counter bits register bit[7:0] pwmph C pwm counter high bits register 7 6 5 4 3 2 1 0 - - - - - - pwm p. 9 pwmp. 8 pwmp + 1 f pwm pwmp + 1 pwmn
n79e 71 5 datasheet jan. 6 , 201 6 page 116 of 189 revision 1.0 1 - - - - - - r/w r/w address: d1h reset value: 0000 0000b bit name description 7:2 - reserved 1:0 pwmp h pwm counter bits register bit[9:8] the user should follow the initialization steps below to start generating the pwm signal output. in t he first step by setting clrpwm (pwmcon0.4), it ensures the 10 - bit down counter a determined value. after setting all period and duty registers, pwmrun (pwmcon0.7) can be set as logic 1 to trigger the 10 - bit down counter running. in the beginning the pwm o utput remains high until the counter value is less than the value in duty control registers of pwmnh and pwmnl . at this point the pwm output goes low until the next underflow. when the 10 - bit down counter underflows, pwmp buffer register will be reloaded i n 10 - bit down counter. it continues pwm signal output by repeating this routine. the hardware for all period and duty control registers is double buffered designed. therefore the pwmp and pwmn registers can be written to at any time, but the period and dut y cycle of pwm will not updated immediately until the l oad (pwmcon0.6) is set and previous period is complete. this allows updating the pwm per i od and duty glitch less operation. pwm0l C pwm 0 low register 7 6 5 4 3 2 1 0 pwm 0 .7 pwm 0 .6 pwm 0 .5 pwm 0 .4 pwm 0 . 3 pwm 0 .2 pwm 0 .1 pwm 0 .0 r/w r/w r/w r/w r/w r/w r/w r/w address: dah reset value: 0000 0000b bit name description 7:0 pwm0 l pwm 0 low bits register bit[7:0]. pwm0h C pwm 0 high register 7 6 5 4 3 2 1 0 - - - - - - pwm 0 . 9 pwm 0 . 8 - - - - - - r/w r/w ad dress: d2h reset value: 0000 0000b bit name description 7:2 - reserved 1:0 pwm0 h pwm 0 high bits register bit[9:8]. pwm1l C pwm 1 low register 7 6 5 4 3 2 1 0 pwm 1 .7 pwm 1 .6 pwm 1 .5 pwm 1 .4 pwm 1 .3 pwm 1 .2 pwm 1 .1 pwm 1 .0
n79e 71 5 datasheet jan. 6 , 201 6 page 117 of 189 revision 1.0 1 r/w r/w r/w r/w r/w r/w r/w r/w add ress: dbh reset value: 0000 0000b bit name description 7:0 pwm1l pwm 0 low bits register bit[7:0]. pwm1h C pwm 1 high register 7 6 5 4 3 2 1 0 - - - - - - pwm 1 . 9 pwm 1 . 8 - - - - - - r/w r/w address: d3h reset value: 0000 0000b bit name description 7:2 - reserved 1:0 pwm1h pwm 1 high bits register bit[9:8] pwm2l C pwm 2 low register 7 6 5 4 3 2 1 0 pwm 2 .7 pwm 2 .6 pwm 2 .5 pwm 2 .4 pwm 2 .3 pwm 2 .2 pwm 2 .1 pwm 2 .0 r/w r/w r/w r/w r/w r/w r/w r/w address: ddh reset value: 0000 0000b bit name description 7:0 p wm2l pwm 2 low bits register bit[7:0] pwm2h C pwm 2 high register 7 6 5 4 3 2 1 0 - - - - - - pwm 2 . 9 pwm 2 . 8 - - - - - - r/w r/w address: d5h reset value: 0000 0000b bit name description 7:2 - reserved 1:0 pwm2h pwm 2 high bits register bit[9:8] pwm3 l C pwm 3 low register 7 6 5 4 3 2 1 0 pwm 3 .7 pwm 3 .6 pwm 3 .5 pwm 3 .4 pwm 3 .3 pwm 3 .2 pwm 3 .1 pwm 3 .0 r/w r/w r/w r/w r/w r/w r/w r/w address: deh reset value: 0000 0000b bit name description 7:0 pwm3l pwm 0 low bits register bit[7:0]
n79e 71 5 datasheet jan. 6 , 201 6 page 118 of 189 revision 1.0 1 pwm3h C pwm 3 high regi ster 7 6 5 4 3 2 1 0 - - - - - - pwm 3 . 9 pwm 3 . 8 - - - - - - r/w r/w address: d6h reset value: 0000 0000b bit name description 7:2 - reserved 1:0 pwm3h pwm 3 high bits register bit[9:8]
n79e 71 5 datasheet jan. 6 , 201 6 page 119 of 189 revision 1.0 1 figure 17 - 1 pwm block diagram a compare value greater than the counter reloaded value is in the pwm output being permanently low. in addition , there are two special cases. a compare value of all zeroes, 000h, causes the output
n79e 71 5 datasheet jan. 6 , 201 6 page 120 of 189 revision 1.0 1 to remain perma nen t ly high. a compare value of all ones, 3ffh, results in the pwm output remaining permanently low. again the compare value is loaded into a compare register. the transfer from this holding register to the actual compare register is under program control. the register assignments are shown below where the number immediately following pwmn identifies the pwm output. therefore, the pwm0 controls the width of pwm0, pwm1 the width of pwm1 etc. the overall functioning of the pwm module is controlled by the c ontents of the pwmcon0 register. the o p eration of most of the control bits is straightforward. for example, there is an invert bit for each output which causes results in the output to have the opposite value compared to its non - inverted output. the transf er of the data from the counter and compare registers to the control registers is controlled by the pwmcon0.6 ( load ) while pwmcon0.7 (pwmrun) allows the pwm to be either in the run or idle state. the user can monitor when underflow causes the transfer to o ccur by monitoring the transfer bit pwcon1.6 (load) or pwmcon0.5 (cf flag). note that cf does not assert interrupt. when the transfer takes place the pwm logic automatically resets those bits by the next clock cycle. a loading of new period and duty by set ting load should be ensured complete by monitoring it and waiting for a hardware automatic clearing load bit. any updating of pwm control registers during load bit as logic 1 will cause unpredictable output. pwmcon0 C pwm control register 0 7 6 5 4 3 2 1 0 pwmrun load cf clrpwm pwm3i pwm2i pwm1i pwm0i r/w r/w r/w r/w r/w r/w r/w r/w address: dch reset value: 0000 0000b bit name description 7 pwmrun 0 = pwm is not running. 1 = pwm counter is running. 6 load 0 = the registers value of pwmp and comparator s are never loaded to counter and comparator registers. 1 = the pwmp register will be load value to counter register after counter unde r flow, and hardware will clear by next clock cycle. 5 cf 10 - bit counter overflow flag: 0 = 10 - bit counter down count is not underflow. 1 = 10 - bit counter down count is underflow. 4 clrpwm 1 = clear 10 - bit pwm counter to 000h. 3 pwm3i 0 = pwm3 output is non - inverted. 1 = pwm3 output is inverted.
n79e 71 5 datasheet jan. 6 , 201 6 page 121 of 189 revision 1.0 1 bit name description 2 pwm2i 0 = pwm2 output is non - inverted. 1 = pwm2 output is inverted. 1 pw m1i 0 = pwm1 output is non - inverted. 1 = pwm1 output is inverted. 0 pwm0i 0 = pwm0 output is non - inverted. 1 = pwm0 output is inverted. the fact that the transfer from the counter and pwmn register to the working registers (10 - bit counter and compare re gister) only occurs when there is an underflow in the counter results in the need for the users pr o gram to observe the following precautions. if pwmcon0 is written with load set without run being enabled the transfer will never take place. thus if a subse quent write sets run without load the compare and counter values will not be those expected. if load and run are set, and prior to underflow there is a subsequent load of pwmcon0 which sets run but not load, the load will never take place. again the compar e and counter values that existed prior to the update attempt will be used. as outlined above the load bit can be polled to determine when the load occurs. unless there is a compe l ling reason to do otherwise, it is recommended that both pwmrun (pwmcon0.7), and load (pwmcon0.6) be set when pwmcon0 is written. when the pwmrun bit, pwmcon0.7 is cleared the pwm outputs take on the state they had just prior to the bit being cleared. in general , this state is not known. to place the outputs in a known state when pwmrun is cleared the compare registers can be written to either the always 1 or always 0 so the output will have the output desired when the counter is halted. after this pwmcon0 should be written with the load and run bits are enabled. after this is done pwmcon0 is polled to find that the load or cf flag has taken place. once the load has occurred the run bit in pwmcon0 can be cleared. the outputs will retain the state they had just prior to the run being cleared. if the brake pin (see discussion belo w in section concerning the operation of pwmcon1) is not used to control the brake function, the brake when not running function can be used to cause the outputs to have a given state when the pwm is halted. this approach should be used only in time crit ical situations when there is not sufficient time to use the approach outlined above since going from the brake state to run without causing an undefined state on the outputs is not straightforward. a discu s sion on this topic is included in the pwmcon1 sec tion . pwmcon1 C pwm control register 1 7 6 5 4 3 2 1 0 bkch bkps bpen bken pwm3b pwm2b pwm1b pwm0b
n79e 71 5 datasheet jan. 6 , 201 6 page 122 of 189 revision 1.0 1 r/w r/w r/w r/w r/w r/w r/w r/w address: dfh reset value: 0000 0000b bit name description 7 bkch see the following table ( when bken is set ) . 6 bkps 0 = brake is asserted if p0.2 is low. 1 = brake is asserted if p0.2 is high 5 bpen see the following table ( when bken is set ) . 4 bken 0 = brake is never asserted. 1 = brake is enabled, and see the following table . 3 pwm3b 0 = pwm3 output is low, when brake is asserted. 1 = pwm3 output is high, when brake is asserted. 2 pwm2b 0 = pwm2 output is low, when brake is asserted. 1 = pwm2 output is high, when brake is asserted. 1 pwm1b 0 = pwm1 output is low, when brake is asserted. 1 = pwm1 output is high, when brake is asserted. 0 pwm0b 0 = pwm0 output is low, when brake is asserted. 1 = pwm0 output is high, when brake is asserted. brake condition t able bpen bkch break condition s 0 0 brake on (software brake and keeping brake) 0 1 on, when pwm is not runnin g (pwmrun=0), the pwm output condition is follow pwmnb setting. off, when pwm is running (pwmrun=1). 1 0 brake on, when break pin asserted, no pwm output, the bit of pwmrun will be cleared and bkf flag will be set. t he pwm output condition is follow pwmnb setting. 1 1 no t active. pwmcon2 C pwm control register 2 7 6 5 4 3 2 1 0 - - - - fp1 fp0 - bkf - - - - r/w r/w - r/w address: d7h reset value: 0000 0000b bit name description 7:4 - reserved
n79e 71 5 datasheet jan. 6 , 201 6 page 123 of 189 revision 1.0 1 bit name description 3:2 fp[1:0] select pwm frequency pre - scalar select bits. the clock source of pre - scalar , fpwm is in phase with f sys if pwmrun=1. fp[1:0] fpwm 00 f sys (default) 01 f sys /2 10 f sys /4 11 f sys /16 1 - reserved 0 bkf e xternal b rake p in f lag 0 = pwm is not brake. 1 = pwm is brake by external brake pin. it w ill be cleared by software. the brake function, which is controlled by the contents of the pwmcon1 register, is somewhat unique. in general when brake is asserted the four pwm outputs are forced to a user selected state, namely the state selected by pwmc on1 bits 0 to 3. as shown in the description of the operation of the pwmcon1 register if pwmcon1.4 is a 1 brake is asserted under the control pwmcon1.7, bkch, and pwmcon1.5, bpen. as shown if both are a 0 brake is asserted. if pwmcon1.7 is a 1 brake is asserted when the run bit, pwmcon0.7, is a 0. if pwmcon1.6 is a 1 brake is asserted when the brake pin, p0.2, has the same polarity as pwmcon1.6. when brake is asserted in response to this pin the run bit, pwmcon0.7, is automat i cally cleared and bkf (pwmcon2.0) flag will be set. the combination of both pwmcon1.7 and pwmcon1.5 being a 1 is not allowed. since the brake pin being asserted will automatically clear the run bit of pwmcon0.7and bkf(pwmcon2.0) flag will be set, the user program can poll thi s bit or enable pwms brake interrupt to determine when the brake pin causes a brake to occur. the other method for detecting a brake caused by the brake pin would be to tie the brake pin to one of the external interrupt pins. this latter approach is neede d if the brake signal can be of insufficient length to ensure that it can be captured by a polling routine. when, after being asserted, the cond i tion causing the brake is removed, the pwm outputs go to whatever state that had immediately prior to the brake . this means that to go from brake being asserted to having the pwm run without going through an indeterminate state care should be taken. if the brake pin causes brake to be asserted the following prot o type code will allow the pwm to go from brake to run smoothly by software polling bkf flag or enable pwms inte r rupt. note that if a narrow pulse on the brake pin causes brake to be asserted, it may not be possible to go through the above code before the end of the pulse. in this case, in addition to the cod e shown, an external latch on the brake pin may be required to ensure that there is a smooth transition in going from brake to run.
n79e 71 5 datasheet jan. 6 , 201 6 page 124 of 189 revision 1.0 1 pwm demo code is as follows : org 0h sjmp start org 100h start: mov pwmph,#0 ;pwm freq uency = fsys/(1+pwmp) mov pwmpl,#0ffh ;if fsys=20mhz, pwm frequency=78.1khz mov pwm0h,#0 mov pwm0l,#080h ;pwm0(p0.1) duty = pwm0/(1+pwmp) mov pwm1h,#0 mov pwm1l,#0a0h ;pwm1(p1.6) d uty = pwm1/(1+pwmp) mov pwm2h,#0 mov pwm2l,#0c0h ;pwm2(p1.7) duty = pwm2/(1+pwmp) mov pwm3h,#0 mov pwm3l,#0f0h ;pwm3(p0.0) duty = pwm3/(1+pwmp) orl pwmcon0,#0d0h ;start pwm mov pwmcon1,#30h ;pwm will be stopped when p0.2 is low level. ;pwm output condition is follow pwmnb setting. ;in this case, pwm0b=pwm1b=pwm2b=pwm3b=0 end
n79e 71 5 datasheet jan. 6 , 201 6 page 125 of 189 revision 1.0 1 18 timed access protection (ta) the N79E715 has several features like the watchdog timer, the isp function, boot select control, etc. are crucial to proper operation of the system. if leaving these control registers unprotected, errant code may write undetermined value into them, it results in incorrect operation and loss of control. to prevent this risk, the N79E715 has a protection scheme which limits the write access to critical sfrs. this protection scheme is done using a timed access. the following registers a re related to ta process. ta C timed access 7 6 5 4 3 2 1 0 ta[7:0] w address: c7h reset value: 1111 1111b bit name description 7:0 ta[7:0] timed a ccess the timed a ccess register controls the access to protected sfrs. to access protected bits, the user should first write aah to the ta and immediately fo l lowed by a write of 55h to ta. after the two steps, a writing permission window is opened for three machine - cycles during which the user may write to protected sfrs. in timed access method, the bits, w hich are protected, have a timed write enable window. a write is successful only if this window is active, otherwise the write will be discarded. when the software writes aah to ta, a counter is started. this counter waits for three machine - cycles looking for a write of 55h to ta. if the second write of 55h occurs within three machine - cycles of the first write of aah, then the timed access window is opened. it remains open for three machine - cycles during which the user may write to the protected bits. after three machine - cycles, this window automatically closes. once the window closes , the procedure should be repeated to access the other protected bits. not that the ta protected sfrs are required timed access for wri t ing. however, the reading is not protecte d. the user may read ta protected sfr without giving aa h and 55 h to ta. the suggestion code for opening the timed access window is shown below. (clr ea) ;if any interrupt is enabled, disable temporarily mov ta, #0aah mov ta, #55h (instruction that writ es a ta protected register) (setb ea) ;resume interrupts enabled the writes of aah and 55h should occur within 3 machine - cycles of each other. interrupts should be di s abled during this procedure to avoid delay between the two writes. if there is no int errupt enabled,
n79e 71 5 datasheet jan. 6 , 201 6 page 126 of 189 revision 1.0 1 the clr ea and setb ea instructions can be left out. once the timed access window closes, the procedure should be repeated to access the other protected bits. examples of timed assessing are shown to i llustrate correct or incorrect writing process es . example 1, (clr ea) ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;2 machine - cycles. mov ta,#55h ;2 machine - cycles. orl chpcon,#data ;2 machine - cycles. (setb ea) ;resume interrupts enabled example 2, (clr ea) ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;2 machine - cycles. mov ta,#55h ;2 machine - cycles. nop ;1 machine - cycle. nop ;1 machine - cycle. anl isptrg,#data ;2 machine - cycles. (setb ea) ;resume interrupts enabled example 3, (c lr ea) ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;2 machine - cycles. nop ;1 machine - cycle. mov ta,#55h ;2 machine - cycles. mov wdcon0,#data1 ;2 machine - cycles. orl pmcr,#data2 ;2 machine - cycles. (setb ea) ;resume interrup ts enabled example 4, (clr ea) ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;2 machine - cycles. nop ;1 machine - cycle. nop ;1 machine - cycle. mov ta,#55h ;2 machine - cycles. anl wdcon0,#data ;2 machine - cycles. (setb ea) ;re sume interrupts enabled in the first example , the writing to the pro tected bits is done before the three machine - cycle window closes. in ex ample 2 , however, the writing to isptrg does not complete during the window opening, there will be no change of the value of isptrg . in example 3 , the wdcon0 is successful written but the pmc r access is out of the three machine - cycle window. therefore, pmc r value will not change either. in example 4 , the second write 55h to ta completes after three machine - cycles of the first write ta of aah , therefore the timed access window in not opened at all, and the write to the protected bit fails. in N79E715 , the ta protected sfrs inclu de pmcr (a3h) , chpcon (9fh), isptrg (a4h) , shbda (9ch), wdcon0 ( d8 h) , and wdcon1 ( ab h) .
n79e 71 5 datasheet jan. 6 , 201 6 page 127 of 189 revision 1.0 1 19 interru pt system the N79E715 has four priority level of interrupts structure with 14 interrupt sources. each of the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. in addition, the interrupts can be globally enabled or di sabled. 19.1 interrupt sources the external interrupts and can be either edge triggered or level triggered, depending on bits it0 and it1. the bits ie0 and ie1 in the tcon register are the flags which are checked t o generate the interrupt. in the edge triggered mode, the intx inputs are sampled in every machine - cycle. if the sample is high in one cycle and low in the next, then a high to low transition is detected and the interrupts request flag iex in tcon is set. the flag bit requests the interrupt. since the external interrupts are sampled every machine - cycle, they have to be held high or low for at least one complete machine - cycle. the iex flag is automatically cleared when the service routine is called. if the l evel triggered mode is selected, then the requesting source has to hold the pin low till the interrupt is serviced. the iex flag will not be cleared by the hardware on entering the service ro u tine. if the interrupt continues to be held low even after the s ervice routine is completed, then the processor may acknowledge another interrupt request from the same source. the timer 0 and 1 interrupts are generated by the tf0 and tf1 flags. these flags are set by the overflow in the timer 0 and timer 1. the tf0 and tf1 flags are automatically cleared by the hardware when the timer interrupt is serviced. the watchdog timer can be used as a system monitor or a simple timer. in either case, when the timeout count is reached, the watchdog timer interrupt flag wd tr f ( wd con0 .3) is set. if the interrupt is enabled by the enable bit eie.4, then an interrupt will occur. the serial block can generate interrupt on reception or transmission. there are two interrupt sources from the serial block, which are obtained by the ri and ti bits in the scon sfr. these bits are not automatically cleared by the hardware, and the user will have to clear these bits using software. i 2 c will generate an interrupt due to a new sio state present in i2sta register, if both ea and es bits (in ie re gister) are both enabled. spi asserts interrupt flag, spif, upon completion of data transfer with an external device. if spi interrupt is e n abled (espi at eie.6), a serial peripheral interrupt is generated. spif flag is software clear, by writing 0. modf and spiovf will also generate interrupt if occur. they share the same vector address as spif. int0 int1
n79e 71 5 datasheet jan. 6 , 201 6 page 128 of 189 revision 1.0 1 the adc can generate interrupt after finished adc converter. there is one interrupt source, which is obtained by the adci bit in the adccon 0 sfr. this bit is not automatically cleared by the hardware, and the user will have to clear this bit using software. pwm brake interrupt flag bkf is generated if p0.2 (brake pin) detects a high (bkps=1) or low (bkps=0) at port pin. at this moment, bkf ( pwmcon2 .0) is set by ha rdware and it should be cleared by software. pwm period interrupt flag cf is set by hardware when its 10 - bit down counter underflow and is only cleared by sof t ware. bkf is set the pwm interrupt is requested if pwm interrupt is enabled (epwm=1). keyboard interrupt is generated when any of the keypad connected to p0 pins detects a low - level or edge changed at port pin. each keypad interrupt can be individually enabled or disabled. the kbi flag (kbif[7:0]) should be cleared by software. por detect can cause pof flag, bof , to be asserted if power voltage drop below bod voltage level. interrupt will occur if ebo d (ie.5) and global interrupt enable (ea) are set. all the bits that generate interrupts can be set or reset by software, and thereby software initiated interrupts can be generated. each of the individual interrupts can be enabled or disabled by setting or clearing a bit in the ie sfr. ie also has a global enable/disable bit ea, in which can be cleared to disable all the interrupts.
n79e 71 5 datasheet jan. 6 , 201 6 page 129 of 189 revision 1.0 1 figure 19 - 1 interrupt flag block diagram 19.2 priority level structure there are four priority levels for the interrupts, highest, high, low and lowest. the interrupt sources can be ind i vidually set to eit her high or low levels. naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt. however there exists a pre - defined hierarchy amongst the interrupts themselves. this hierarchy comes into play when the interrupt controller has to resolve simultaneous requests having the same prior i ty level. this hierarchy is defined as shown in table 19 - 3 , the interrupts are numbered starting from the highest priority to the lowest. the interrupt fl ags are sampled every machine - cycle. in the same machine - cycle, the sampled interrupts are polled and their priority is resolved. if certain conditions are met then the hardware will i e 0 i e 1 b o f k b i f [ 7 : 0 ] e k b e b o d e x 1 e x 0 s i e s r i + t i e t 1 t f 1 e t 0 t f 0 e a i n t e r r u p t t o c p u w a k e u p ( i f i n p o w e r d o w n ) e p w m e s p i s p i f m o d f s p i o v f b k f e t 2 t f 2 w d t f e a d c a d c i w d t e n e c p t f c p t f 0 c p t f 1 c p t f 2 e i 2 c i 2 t o f
n79e 71 5 datasheet jan. 6 , 201 6 page 130 of 189 revision 1.0 1 execute an internally generated lcall instruction which will vector the p rocess to the appropriate interrupt vector address. the conditions for generating the lcall include: 1. an interrupt of equal or higher priority is not currently being serviced. 2. the current polling cycle is the last machine - cycle of the instruction curr ently being executed. 3. the current instruction does not involve a write to ie, eie, ip , ip h, eip or iph1 registers and is not a reti. if any of these conditions are not met, then the lcall will not be generated. the polling cycle is repeated ev e ry machin e - cycle, with the interrupts sampled in the same machine - cycle. if an interrupt flag is active in one cycle but not responded to, and is not active when the above conditions are met, the denied interrupt will not be serviced. this means that active interru pts are not remembered; every polling cycle is new. the processor responds to a valid interrupt by executing an lcall instruction to the appropriate service ro u tine. this may or may not clear the flag which caused the interrupt. in case of timer interrupts , the tf0 or tf1 flags are cleared by hardware whenever the processor vectors to the appropriate timer service routine. in case of external interrupt, int0 and int1, the flags are cleared only if they are edge triggered. in case of serial i n terrupts, the f lags are not cleared by hardware. in the case of timer 2 interrupt, the flags are not cleared by hardware. the hardware lcall behaves exactly like the software lcall instruction. this instruction saves the program counter contents onto the stack, but does not save the program status word psw. the pc is reloaded with the vector address of that interrupt which caused the lcall. these address of vector for the different sources are as follows .
n79e 71 5 datasheet jan. 6 , 201 6 page 131 of 189 revision 1.0 1 table 19 - 1 vector l ocations for interrupt sources source vector address source vector address external interrupt 0 0003h timer 0 overflow 000bh external interrupt 1 0013h timer 1 overflow 001bh serial port 0023h timer 2 overflow/match 002bh i 2 c interrupt 0033h kbi inte rrupt 003bh bod interrupt 00 43 h spi interrupt 004bh watchdog timer 0053h adc interrupt 005bh capture 00 63 h pwm brake interrupt 0073h the vector table is not evenly spaced; this is to accommodate future expansions to the device family. table 19 - 2 four - level interrupt priority priority bits interrupt priority level ipxh ipx 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority) execution continues from the vectore d address till an reti instruction is executed. on execution of the reti instruction the processor pops the stack and loads the pc with the contents at the top of the stack. the user should watch out for the status of the stack is restored to whatever afte r the hardware lcall, if the ex e cution is to return to the interrupted program. the processor does not notice anything if the stack contents are modified and will proceed with execution from the address put back into pc. note that a ret instruction would p erform exactly the same process as a reti instruction, but it would not inform the interrupt controller that the interrupt service routine is completed, and would leave the controller still thinking that the service routine is u n derway. the N79E715 use s a four - priority level interrupt structure. this allows great flexibility in controlling the handling of the N79E715 many interrupt sources. the N79E715 support s up to 14 interrupt sources. each interrupt source can be individually enabled or disabled by sett ing or clearing a bit in registers ie or eie. the ie register also contains a global disable bit, ea, which disables all interrupts at once. each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the ip , ip h, eip , and eip h registers. an interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the
n79e 71 5 datasheet jan. 6 , 201 6 page 132 of 189 revision 1.0 1 highest priority interrupt service cannot be interrupted by a ny other interrupt source. so, if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence dete rmines which request is serviced. this is called the arbitration ranking. note that the arbitration ranking is only used to resolve simultaneous requests of the same priority level. the following t able summarizes the interrupt sources, flag bits, vector ad dresses, enable bits, priority bits, arbitr a tion ranking, and whether each interrupt may wake up the cpu from power - down mode . table 19 - 3 summary of interrupt sources description interrupt flag bit(s) vector address interrupt enable bit(s) flag cleared by interrupt priority arbitration ranking power - d own wake - up external interrupt 0 ie0 0003h ex0 (ie0.0) hardware, software ip h.0, ip .0 1 (highest) yes bod detect bof 0043h ebo d (ie.5) software ip h.5, ip .5 2 ye s watchdog timer wd t f 0053h ewdi (eie.4) software eip h.4, eip .4 3 yes timer 0 interrupt tf0 000bh et0 (ie.1) hardware, software ip h.1, ip .1 4 no i 2 c interrupt si i2tof 0033h ei2 c (eie.0) software eip h.0, eip .0 5 no adc converter adci 005bh ead c (ie.6) software ip h.6, ip .6 6 yes(1) external interrupt 1 ie1 0013h ex1 (ie.2) hardware, software ip h.2, ip .2 7 yes kbi interrupt kbif[7:0] 003bh ekb (eie.1) software eip h.1, eip .1 8 yes timer 1 interrupt tf1 001bh et1 (ie.3) hardware, software ip h.3, ip .3 9 n o serial port tx and rx ti & ri 0023h es (ie.4) software ip h.4, ip .4 10 no pwm interrupt bkf 0073h epwm (eie.5) software eip h.5, eip .5 11 no spi spif + modf + spiovf 004bh espi (eie.6) software eip h.6, eip .6 12 no timer 2 overflow/match tf2 00 2b h et2 ( eie.7) software eip h.7, eip .7 13 no capture c apf 0 - 2 00 63 h ecptf (eie. 2 ) software ip h.7, ip .7 14 (lowest) no [1] the adc converter can wake up power - down mode when its clock source is from hirc .
n79e 71 5 datasheet jan. 6 , 201 6 page 133 of 189 revision 1.0 1 19.3 interrupt response time the response time for each inter rupt source depends on several factors, such as the nature of the interrupt and the instruction underway. in the case of external interrupts to ri+ti, they are sampled at c3 of every machine - cycle and then their corresponding interru pt flags iex will be set or reset. the timer 0 and 1 overflow flags are set at c3 of the machine - cycle in which overflow has occurred. these flag values are polled only in the next machine - cycle. if a request is active and all three conditions are met, the n the hardware generated lcall is executed. this lcall itself takes four machine - cycles to be completed. thus there is a minimum time of five machine - cycles between the interrupt flag being set and the interrupt service routine being execu t ed. a longer res ponse time should be anticipated if any of the three conditions are not met. if a higher or equal pr i ority is being serviced, the interrupt latency time is obviously depend ent on the nature of the service routine currently being executed. if the polling cy cle is not the last machine - cycle of the instruction being executed, an additional delay is introduced. the maximum response time (if no other interrupt is in service) occurs if the N79E715 perform s a write to ie, eie, ip , ip h, eip or eip h and then execute s a mul or div instruction. from the time an interrupt source is activated, the longest reaction time is 12 machine - cycles. this includes 1 machine - cycle to detect the interrupt, 3 machine - cycles to complete the ie, eie, ip , ip h, eip or eip h access, 5 mach ine - cycles to complete the mul or div instruction and 4 machine - cycles to complete the hardware lcall to the interrupt vector location. thus in a single - interrupt system the interrupt response time will always be more than 5 machine - cycles and not more tha n 12 machine - cycles. the maximum latency of 12 machine - cycle is 48 clock cycles. note that in the standard 8051 the maximum latency is 8 machine - cycles which equals 96 machine - cycles. this is a 50% reduction in terms of clock periods. 19.4 sfr of interrupt the sfrs associated with the se interrupts are listed below. int0
n79e 71 5 datasheet jan. 6 , 201 6 page 134 of 189 revision 1.0 1 ie C interrupt enable (bit - addressable) 7 6 5 4 3 2 1 0 ea eadc ebo d es et1 ex1 et0 ex0 r/w r/w r/w r/w r/w r/w r/w r/w address: a8h reset value: 0000 0000b bit name description 7 ea enable a ll i nterrupt this bit globally enables/disables all interrupts. it overrides the individual interrupt mask settings. 0 = disable all interrupt sources. 1 = enable each interrupt depending on its individual mask setting. individual i n terrupts will occur if enab led. 6 eadc enable adc i nterrupt 5 ebo d enable bod i nterrupt 4 es enable serial p ort (uart) interrupt 0 = disable all uart interrupts. 1 = enable interrupt generated by ti (scon.1) or ri (scon.0). 3 et1 enable timer 1 interrupt 0 = disable timer 1 inte rrupt 1 = enable interrupt generated by tf1 (tcon.7). 2 ex1 enable external interrupt 1 0 = disable external interrupt 1. 1 = enable interrupt generated by pin (p1.4 ). 1 et0 enable timer 0 interrupt 0 = disable timer 0 interrupt 1 = enable interrupt generated by tf0 (tcon.5). 0 ex0 enable external interrupt 0 0 = disable external interrupt 0. 1 = enable interrupt generated by pin (p1.3 ). e ie C extensive interrupt enable 7 6 5 4 3 2 1 0 et2 espi epwm ewdi - ecptf ekb ei2 c 1 int 0 int
n79e 71 5 datasheet jan. 6 , 201 6 page 135 of 189 revision 1.0 1 r/w r/w r/w r/w - r/w r/w r/w address: e8 h reset value: 0000 0000b bit name description 7 et2 0 = disable timer 2 interrupt. 1 = enable timer 2 interrupt. 6 espi spi interrupt enable: 0 = disable spi interrupt. 1 = enable spi interrupt. 5 epwm 0 = disable pwm interrupt when external brake pin was braked. 1 = enable pwm interrupt when external brake pin was braked. 4 e wd i 0 = disable watchdog timer interrupt. 1 = enable watchdog timer interrupt. 3 - reserved 2 ecptf 0 = disable captur e interrupts. 1 = enable capture interrupts. 1 ekb 0 = disable keypad interrupt. 1 = enable keypad interrupt. 0 ei2 c 0 = disable i 2 c interrupt. 1 = enable i 2 c interrupt. ip C interrupt priority - 0 register 7 6 5 4 3 2 1 0 pcap padc pbod ps pt1 px1 pt0 p x0 r/w r/w r/w r/w r/w r/w r/w r/w address: b8h reset value: 0000 0000b bit name description 7 pcap 1 = set interrupt high priority of capture 0/1/2 as highest priority level. 6 padc 1 = set interrupt priority of adc as higher priority level. 5 pbod 1 = set interrupt priority of bod detector as higher priority level. 4 ps 1 = set interrupt priority of serial port 0 as higher priority level.
n79e 71 5 datasheet jan. 6 , 201 6 page 136 of 189 revision 1.0 1 bit name description 3 pt1 1 = set interrupt priority of timer 1 as higher priority level. 2 px1 1 = set interrupt priority of ext ernal interrupt 1 as higher priority level. 1 pt0 1 = set interrupt priority of timer 0 as higher priority level. 0 px0 1 = set interrupt priority of external interrupt 0 as higher priority level. iph C interrupt high priority register 7 6 5 4 3 2 1 0 pcaph padch pbo d h psh pt1h px1h pt0h px0h r/w r/w r/w r/w r/w r/w r/w r/w address: b7h reset value: 0000 0000b bit name description 7 pcaph 1 = set interrupt high priority of capture 0/1/2 as highest priority level. 6 padch 1 = set interrupt high prio rity of adc as the highest priority level. 5 pbo d h 1 = set interrupt high priority of bod detector as the highest priority level. 4 psh 1 = set interrupt high priority of serial port 0 as the highest priority level. 3 pt1h 1 = ro set interrupt high prio rity of timer 1 as the highest priority level. 2 px1h 1 = set interrupt high priority of external interrupt 1 as the highest priority level. 1 pt0h 1 = set interrupt high priority of timer 0 as the highest priority level. 0 px0h 1 = set interrupt high p riority of external interrupt 0 as the highest priority level. eip C interrupt priority - 1 register 7 6 5 4 3 2 1 0 pt2 pspi ppwm pwdi - - pkb pi2 r/w r/w r/w r/w - - r/w r/w address: ffh reset value: 0000 0000b bit name description 7 pt2 1 = set inte rrupt priority of timer 2 as higher priority level. 6 pspi 1 = set interrupt priority of spi as higher priority level. 5 ppwm 1 = set interrupt priority of pwms brake as higher priority level. 4 pwdi 1 = set interrupt priority of watchdog as higher pri ority level.
n79e 71 5 datasheet jan. 6 , 201 6 page 137 of 189 revision 1.0 1 bit name description 3 :2 - reserve d 1 pkb 1 = set interrupt priority of keypad as higher priority level. 0 pi2 1 = set interrupt priority of i 2 c as higher priority level. eiph C interrupt high priority - 1 register 7 6 5 4 3 2 1 0 pt2h pspih ppwmh pwdih - - pk bh pi2h r/w r/w r/w r/w - - r/w r/w address: f7h reset value: 0000 0000b bit name description 7 pt2h 1 = s et interrupt high priority of timer 2 as the highest priority level. 6 pspih 1 = s et interrupt high priority of spi as the highest priority level . 5 ppwmh 1 = s et interrupt high priority of pwms external brake pin as the highest priority level. 4 pwdih 1 = s et interrupt high priority of watchdog as the highest priority level. 3 :2 - reserve d 1 pkbh 1 = s et interrupt high priority of keypad as t he highest priority level. 0 pi2h 1 = set interrupt high priority of i 2 c as the highest priority level. tcon C timer 0 and 1 control (bit - addressable) 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 r/w r/w r/w r/w r/w r/w r/w r/w address: 88h reset value: 0000 0000b bit name description 3 ie1 external interrupt 1 edge flag this flag is set via hardware when an edge/level of type defined by it1 is detec t ed. if it1 = 1, this bit will remain set until it is cleared via software or at the beginning of t he external interrupt 1 service routine. if it1 = 0, this flag is the inverse of the input signal's logic level. 1 int
n79e 71 5 datasheet jan. 6 , 201 6 page 138 of 189 revision 1.0 1 bit name description 2 it1 external interrupt 1 type selection this bit selects whether the pin will detect falling e dge or low level triggered interrupts. 0 = is low level triggered. 1 = is falling edge triggered. 1 ie0 external interrupt 0 edge flag this flag is set via hardware when an edge/level of type defined by it0 is detec t ed. if it0 = 1, this bit will remain set until cleared via software or at the beginning of the external interrupt 0 service routine. if it0 = 0, this flag is the inverse of the input signal's logic level. 0 it0 external inter rupt 0 type selection this bit selects whether the pin will detect falling edge or low level triggered interrupts. 0 = is low level triggered. 1 = is falling edge triggered. 1 int 0 int
n79e 71 5 datasheet jan. 6 , 201 6 page 139 of 189 revision 1.0 1 20 in system pr ogramming ( isp ) the internal program memory and on - chip data flash support both hardware programming and in system pr o gramming (isp). hardware programming mode uses gang - writers to reduce programming costs and time to market while the products enter the ma ss production state. however , if the product is just under develo p ment or the end p roduct needs firmware updating in the hand of an end user , the hardware programming mode will make repeated programming difficult and inconvenient . isp method makes it easy and possible. the N79E715 support s isp mode al lowing a device to be reprogrammed under software control. t he capability to update the application firmware makes v dd = 3.0v ~ 5.5v of applications. isp is performed without removing the microcontroller from the system. the most common method to perform isp is via uart along with the firmware in ldrom. general speaking , pc transfers the new aprom code through serial port . then ldrom firmware receives it and re - programs into aprom through isp commands. nuvoton provides isp firmware , p lease visit nuvoton 8 - bit microcontroller website below and select nuvoton isp - icp programmer. http://www.n uvoton.com/hq/products/microcontrollers/8bit - 8051 - mcus/software 20.1 isp procedure unlike rams re al - time operation, to update flash data often takes long time. furthermore, it is a quite complex timing procedure to erase, program , or read flash data. fortunat ely, the N79E715 carried out the flash operation with convenient mechanism to help the user update the flash content. after isp enabled by se t ting ispen (chpcon.0 with ta protect ed ), t he user can easily fill the 16 - bit target address in ispah and ispal , da ta in ispfd and command in ispcn. then the isp is ready to begin by setting a triggering bit ispgo (isptrg.0). note that isptrg is also ta protected. at this moment, the cpu holds the program counter and the built - in isp automation takes over to control th e internal charge - pump for high voltage and the detail signal timing. after isp action completed , the program counter continues to run the following instructions . th e ispgo bit will be automatic cleared by hardware . the user may repeat steps above for next isp action if necessary. through this progress, the user can easily erase, program , and verify the embedded flash by just watching out for the pure software . nominally, a page - erase time is 2 0 ms and a byte - program time is 4 0 s. the following registers a re relate d to isp processing.
n79e 71 5 datasheet jan. 6 , 201 6 page 140 of 189 revision 1.0 1 chpcon C chip control (ta p rotected) 7 6 5 4 3 2 1 0 swrst ispf lduen - - - bs ispen w r/w r/w - - - r/w r/w address: 9fh reset value: see table 7 C 2 N79E715 s fr description and reset value s bit name description 6 ispf isp fault f lag the hardware will set this bit when any of the following condition is met: 1. the accessing area is illegal, such as, (a) erasing or programming aprom itself when aprom code runs. (b) erasing or program ming ldrom when aprom code runs but ldue n is 0. (c) erasing , programming , or reading config bytes when aprom code runs . (d) erasing or programming ldrom itself when ldrom code runs . (e) accessing oversize. 2. the isp operating runs from internal program me mory to external one. this bit should be cleared via software . 5 ldue n updating ldrom enable 0 = ldrom is inhibited to be erased or programmed when aprom code runs. ldrom remains read - only. 1 = ldrom is allowed to be fully accessed when aprom code runs. 4: 2 - reserved 1 bs boot s elect ion there are different meanings of writing to or reading from this bit. writing it defines from which block mcu boots after all resets. 0 = the next rebooting will be from aprom. 1 = the next rebooting will be from ldrom. reading it indicates from which block mcu booted after previous reset. 0 = the previous rebooting is from aprom. 1 = the previous rebooting is from ldrom. 0 ispen isp enable
n79e 71 5 datasheet jan. 6 , 201 6 page 141 of 189 revision 1.0 1 bit name description 0 = enable isp function. 1 = disable isp function. to enable isp function will start the hirc for timing control. to clear ispen should always be the last instruction after isp operation to stop hirc for reducing power consumption. ispcn C isp control 7 6 5 4 3 2 1 0 isp a17 isp a16 foen fcen fctrl.3 fctrl.2 fctrl.1 fctrl.0 r/w r/w r/w r/w r/w r/w r/w r/w address: afh reset value: 0011 0000b bit name description 7:6 ispa[17:16] isp control this byte is for isp controlling command to decide isp destinations and a c tions . 5 foen 4 fcen 3:0 fctrl[3:0] ispah C isp address high byte 7 6 5 4 3 2 1 0 ispa [ 15 : 8 ] r/w address: a 7 h reset value: 0000 0000b bit name description 7:0 ispa[15:8] isp address high byte ispah contains address ispa[15:8] for isp operations. ispal C isp address low byte 7 6 5 4 3 2 1 0 ispa[7:0] r/w add ress: a6h reset value: 0000 0000b bit name description 7:0 ispa[7:0] isp address low byte ispal contains address ispa[7:0] for isp operations.
n79e 71 5 datasheet jan. 6 , 201 6 page 142 of 189 revision 1.0 1 ispfd C isp flash data 7 6 5 4 3 2 1 0 ispfd[7:0] r/w address: aeh reset value: 0000 0000b bit name descri ption 7:0 ispfd[7:0] isp flash data this byte contains flash data which is read from or is going to be written to the flash memory. the user should write data into ispfd for program mode before triggering isp processing and read data from ispfd for read/v erify mode after isp processing is finished. isptrg C isp trigger ( ta protected ) 7 6 5 4 3 2 1 0 - - - - - - - ispgo - - - - - - - w address: a4h reset value: 0000 0000b bit name description 0 ispgo isp begin isp begins by setting this bit as logic 1 . after this instruction, the cpu holds the program counter (pc) and the isp hardware automation takes over to co n trol the progress. after isp action completed, the program counter continues to run the following instructions. the ispgo bit will be automati cally cleared and always read as logic 0.
n79e 71 5 datasheet jan. 6 , 201 6 page 143 of 189 revision 1.0 1 20.2 isp command table isp command ispcn ispah, ispal a[15:0] ispfd d[7:0] a17, a16 foen fcen fctrl[3:0] read company id x, x [1] 0 0 1011 x [1] data out d[7:0] =dah ap rom & data flash flash p age erase 0, 0 1 0 0010 a ddress i n a[15:0] x [1] flash program 0, 0 1 0 0 001 a ddress i n a[15:0] data in d[7:0] flash read 0, 0 0 0 0000 a ddress i n a[15:0] data out d[7:0] ld rom flash page erase 0, 1 1 0 0010 a ddress i n a[15:0] x [1] flash program 0, 1 1 0 0 001 a ddress i n a[15:0] data in d[7:0] flash read 0, 1 0 0 0000 a ddress i n a[15:0] data out d[7:0] config [2] page erase 1, 1 1 0 0010 a ddress i n a[15:0]=0000h x [1] config [2] program 1, 1 1 0 0001 a ddress i n a[15:0] data in d[7:0] config [2] read 1 , 1 0 0 0000 a ddress i n a[15:0] data out d[7:0] note: [1] x means dont care . [2] the config means the mcu hardware configuration. [3] each page has 128 bytes. so, the address for page erase should be 0000, 0080h, 0100h, 0180h, 0200h, .., which is incremented by 0080h.
n79e 71 5 datasheet jan. 6 , 201 6 page 144 of 189 revision 1.0 1 20.3 access table of i sp programming destination unlock lock isp code residence isp code residence aprom ldrom aprom ldrom aprom ldrom [1] [1] data flash configs [2] [2] id (read) note: fully accessing read only accessing inhibit [1] ldue should be 1, or it will be read only. [2] new config functions after por, wdt, res et pin or software reset i. config full accessing by ldrom while lock. ii. inhibit aprom jump to ldrom or ldrom jump to aprom. iii. mcu run in aprom cannot read configs. 20.4 isp u ser guide isp facilitates the updating flash contents in a convenient way; however, the user should follow some restricted laws in order that the isp operates correct ly . without notic ing warnings will possible cause undetermined r e sults even serious damages of devices. be attention of these notices. furthermore, t his paragraph will also support u seful suggestions during isp procedures. (1) if no more isp operation need s , the user should c lear ispen (chpcon.0 ) to zer o. it will make the system void to trigger isp unaware. furthermore, isp requires hirc running. if the external clock source is chosen , disabling isp will stop hirc for sav ing power co n sumption. note that a write to ispen is ta protect ed . ( 2 ) config byte s can be isp fully accessed only when loader code executing in ldrom. new config byte s other than cbs bit activate after all resets . new cbs bit activates after resets other than software reset. ( 3 ) when the lock bit ( config0 .1 ) is activated, isp reading, writing, or erasing can still be valid .
n79e 71 5 datasheet jan. 6 , 201 6 page 145 of 189 revision 1.0 1 ( 4 ) isp works under v dd = 3.0 v ~ 5.5v. ( 5 ) aprom and ldrom can read itself through isp method. n ote : if the user would like to develop isp program, always erase and program config bytes at the last step for data security. 20.5 isp demo code common subroutine for isp enable_isp: mov ispcn,#00110000b ;select standby mode clr ea ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;chpcon is ta - protection mov ta,#55h ; orl chpcon,#00000001b ;ispen=1, enable isp function setb ea call trigger_isp ; ret disable_isp: mov ispcn,#00110000b ;select standby mode call trigger_isp ; clr ea ;if any interrupt is enabled, disable temporarily mov ta,#0aah ;chpcon is ta - protection mov ta,#55h ; anl chpcon,#11111110b ;ispen=0, disable isp function setb ea ret trigger_isp: clr ea ;if any interrupt is enabled, disable temporarily mo v ta,#0aah ;isptrg is ta - protection mov ta,#55h ; mov isptrg,#00000001b ;write 1 to bit ispgo to trigger an isp processing setb ea ret read company id call enable_isp mov ispcn,#00001011b ;select read company id mode call trigger_isp mov a,ispfd ;now, ispfd contains company id (should be dah), move to acc for ; further use call disable_isp read device id call enable_isp mov ispcn,#00001100b ;select read device id mode
n79e 71 5 datasheet jan. 6 , 201 6 page 146 of 189 revision 1.0 1 mov ispah,#00h ;fill address with 0000h for low - byte did mov ispal,#00h ; call trigger_isp mov a,ispfd ;now, ispfd contains low - byte did, move to acc for further use mov ispah,#00h ;fill address with 0001h for high - byte did mov ispal,#01h ; call trigger_isp mov a,ispfd ;now, ispfd contains high - byte did, move to acc for f urther use call disable_isp flash page erase (target address in aprom/data flash/ldrom area) call enable_isp mov ispcn,#00100010b ;select flash page erase mode, (a17,a16)=(0,0) for aprom/data ; flash/ldrom mov ispah,#??h ;fill page address mov ispa l,#??h call trigger_isp call disable_isp flash program (target address in aprom/data flash/ldrom area) call enable_isp mov ispcn,#00100001b ;select flash program mode, (a17,a16)=(0,0) for aprom/data ; flash/ldrom mov ispah,#??h ;fill byte address mo v ispal,#??h mov ispfd,#??h ;fill data to be programmed call trigger_isp call disable_isp flash read (target address in aprom/data flash/ldrom area) call enable_isp mov ispcn,#00000000b ;select flash read mode, (a17,a16)=(0,0) for aprom/data ; flash /ldrom mov ispah,#??h ;fill byte address mov ispal,#??h call trigger_isp mov a,ispfd ;now, ispfd contains the flash data, move to acc for further use call disable_isp config page erase (target address in config area) call enable_isp mov ispcn,#11100 010b ;select config page erase mode, (a17,a16)=(1,1) for config mov ispah,#00h ;fill page address #0000h, because there is only one page mov ispal,#00h call trigger_isp call disable_isp config program (target address in config area)
n79e 71 5 datasheet jan. 6 , 201 6 page 147 of 189 revision 1.0 1 call enable_isp mov ispcn,#11100001b ;select config program mode, (a17,a16)=(1,1) for config mov ispah,#00h ;fill byte address, 0000h/0001h/0002h/0003h for config0/1/2/3, ; respectively mov ispal,#??h mov ispfd,#??h ;fill data to be programmed call trigger_isp call disable_isp config read (target address in config area) call enable_isp mov ispcn,#11000000b ;select config read mode, (a17,a16)=(1,1) for config mov ispah,#00h ; fill byte address, 0000h/0001h/0002h/0003h for config0/1/2/3, ; respectively mov ispal, #??h call trigger_isp mov a,ispfd ;now, ispfd contains the config data, move to acc for further ; use call disable_isp
n79e 71 5 datasheet jan. 6 , 201 6 page 148 of 189 revision 1.0 1 21 power management the N79E715 has several features that help the user to control the power consumption of the device. the power saved features have power - down mode and i dle mode operation s . for a stable cu r rent consumption, user should watch out for the states of p0 pins. in system power saving modes, user should specifically watch out for the watchdog timer. the hardware will clear wdt counter automatically after entering or being woken - up from idle or power - down mode . it prevents unconscious system reset. pcon C power control 7 6 5 4 3 2 1 0 smod smod0 - pof gf1 gf0 pd idl r/w r/w - r/w r/w r/w r/w r/w address: 87h reset value: s ee table 7 C 2 N79E715 s fr description and reset value s bit name description 1 pd power - down m ode setting this bit puts mcu into power - down mode . under this mode, both cpu and peripheral clocks stop and program cou nter (pc) suspends. it provides the lowest power consumption. after cpu is woken up from power down, this bit will be a u tomatically cleared via hardware and the program continue executing the interrupt service routine (isr) of the very interrupt source tha t woke the system up before. after return from the isr, the device continues execution at the instruction which follows the instruction that put the system into power - down mode . note : if idl bit and pd bit are set simultaneously, the mcu will enter power - d own mode . then it does not go to idle mode after exiting power down. 0 idl idle m ode setting this bit puts mcu into idle mode. under this mode, the cpu clock stops and program counter (pc) suspends. after cpu is woken up from idle, this bit will be automa tically cleared via hardware and the program continue executing the isr of the very interrupt source that woke the system up before. after return from the isr, the device continues execution at the instruction which follows the i n struction that put the sys tem into idle mode. 21.1 idle mode idle mode suspends cpu processing by holding the program c ounter. no program code are fetched and run in idle mode. this forces the cpu state to be frozen. the program counter (pc), the stack pointer (sp), the program status word (psw), the accumulator (acc) , and the other registers hold
n79e 71 5 datasheet jan. 6 , 201 6 page 149 of 189 revision 1.0 1 their contents during idle mode . the port pins hold the logical states they had at the time idle was activated. generally it saves consi d erable power of typical ha lf of the full operating powe r. since the clock provided for peripheral function logic circuit like timer or serial port still remain in idle mode , the cpu can be released from the idle mode using any of the interrupt sources if enabled. the user can put the device into i dle mode by w riting 1 to the bit idl ( pcon.0 ) . the instruction that sets the idl bit is the last i n struction that will be executed before the device goes into idle m ode. the idle mode can be terminated in two ways. first, any interrupt if enabled will cause an exit. th is will aut o matically clear the idl bit, terminate the idle mode , and the i nterrupt s ervice r outine (isr) will be executed. after using the reti instruction to jump out of the isr, execution of the program will be the one following the instruction which pu t the cpu into idle mode. the second way to terminate the idle mode is wit h any reset ot h er than software reset. 21.2 power - d own mode power - down mode is the lowest power state that N79E715 can enter. it remain the power co n sumption as a a level. this is achieved by stopping the clock system no matter hirc clock or external crystal . both of cpu and peripheral functions like timers or uart are frozen . flash memory stop s . all activity is completely stopped and the power consumption is red uced to the lowest possible value. the device can be put into power - down mode by writing 1 to bit pd ( pcon.1 ) . the instruction that does this action will be the last instruction to be executed before the device goes into power - down mode . in power - down mode , ram maintains its content. t he port pins output the values held by their respective . there are two ways to exit N79E715 from power - down mode . the first is with all resets except software reset. bod reset will also wake up cpu from power - down mode . make s ure that bod detection is en a bled before the system enters into power - d own. however, for a principle of least power consumption, it is uncommon to enable bod detection in power - down mode , which is not a recommended application. of course , the rst pin reset and power - on reset will remove the power down status. after rst pin reset or power - on reset , t he cpu is initialized and start s executing program code from the beginning. the N79E715 can be woken up from power - down mode by forcing an external interrupt pin activated, provid ing the corresponding interrupt enabled and the global enable ea bit (ie.7) is set . if these cond i tions are met, the trigger on the external pin will asynchronously restart the clock system . then device executes the interrupt service rout ine (isr) for the corresponding external interrupt. after the isr is completed, the program execution returns to the instruction after the one that put s the device into power - down mode and continues.
n79e 71 5 datasheet jan. 6 , 201 6 page 150 of 189 revision 1.0 1 bod , w at ch dog and kbi interrupt are other source s to wak e up cpu from power down. as mentioned before the user will endure the current of bod detection circuit. using kbi interrupt to wake up cpu from power down has a restriction : the kbi pin keeps low (high) before cpu enters power down. then only rising (fal l ing) edge of kbi interrupt can wake up cpu from power down.
n79e 71 5 datasheet jan. 6 , 201 6 page 151 of 189 revision 1.0 1 22 clock system the N79E715 provide s three options of the clock system source that is configure d by f osc ( config3 .1 ~0 ) . it switches the system clock from crystal/ resonator , high speed internal rc osc illator (hirc) , or e xternal c lock from xtal1 pin. the N79E715 is embed ded with hirc selected by config setting, factory trimmed to 1 % under the condition of room temperature and v dd =5v . if the e x ternal clock source is f ro m t he c rystal , the frequency supp ort s from 4 mhz to 24 mhz. figure 22 - 1 clock system block diagram o s c i l l a t i n g c i r c u i t i n t e r n a l r c o s c i l l a t o r ( 2 2 . 1 1 8 4 m h z ) x t a l 2 x t a l 1 1 / 2 f o s c [ 1 : 0 ] ( c o n f i g 3 [ 1 : 0 ] ) o s c f s ( c o n f i g 3 . 3 ) f o s c 1 0 0 x 1 0 t u r b o 8 0 5 1 c p u t i m e r s s e r i a l p o r t ( u a r t ) i 2 c p w m i n t e r n a l r c o s c i l l a t o r ( ~ 1 0 k h z ) f l a s h f h i r c f l i r c 1 1 c l o c k d i v i d e r f s y s w a t c h d o g t i m e r a d c d i v m c l o c k f i l t e r c k f ( c o n f i g 3 . 4 ) k b i d i v 2 ( c o n f i g 4 . 0 ) f x t a l
n79e 71 5 datasheet jan. 6 , 201 6 page 152 of 189 revision 1.0 1 config3 7 6 5 4 3 2 1 0 cwdten ckfs1 ckfs0 ckf oscfs - fosc1 fosc0 r/w r/w r/w r/w r/w - r/w r/w factory de fault value: 1111 1111b bit name description 4 ckf clock filter enable 1 = enable clock filter. it increases noise immunity and emc capacity. 0 = disable clock filter. 3 oscfs hirc frequency selection 1 = select 22.1184 mhz as the clock system if hirc mo de is used. it bypasses the divided - by - 2 path of hirc to select 22.1184 mhz output as the clock system source. 0 = select 11.0592 mhz as the clock system if hirc mode is used. the hirc divided - by - 2 path is selected. the hirc is equiv a lent to 11.0592 mhz ou tput used as the clock system . 2 - reserved 1:0 fosc1 fosc0 oscillator select b it for c hip clock source s elect ion, refer to the following table. (fosc1, fosc0) chip clock source (1, 1) hirc (1, 0) reserved (0, 1 ) (0, 0) external crystal, 4 mhz ~ 24 mh z divm C clock divider register 7 6 5 4 3 2 1 0 divm[7:0] r/w address: 95h reset value: 0000 0000b bit name description 7:0 divm[7:0] clock divider the system clock frequency f sys follows the equation below according to divm value. f sys = f osc , wh ile divm = 00h. f sys = f osc, while divm = 01h ~ ffh. ) 1 + divm ( 2 1
n79e 71 5 datasheet jan. 6 , 201 6 page 153 of 189 revision 1.0 1 22.1 on - chip rc oscillator s the high speed internal rc oscillator of 22.1184 mhz ( hirc ) is enabled while fosc (config3.1~0) = [1,1] . it can be selected as the system clock. setting oscf s (config3.3) logic 1 will switch to a divided - by - 2 path. another low speed on - chip rc oscillator of 10 khz (lirc) is only use for watchdog timer clock source. 22.2 crystal/resonator the crystal/resonator is selected as the system clock while fosc[1:0] keep pro grammed as [0:1]. xtal1 and xtal2 are the input and output, respectively, of an internal inverting amplifier. a crystal or resonator can be used by connecting between xtal1 and xtal2 pins. the crystal or resonator frequency from 4 mhz to 24 mhz is allowed. ckf (config3.4) is the control bit of clock filter circuit of xtal1 input pin.
n79e 71 5 datasheet jan. 6 , 201 6 page 154 of 189 revision 1.0 1 23 power monitoring to prevent incorrect execution during power up and power drop, N79E715 provide three power monitor function s, p ower - on detect ion and bod detect ion . 23.1 power - o n de tect ion the power - on detect ion function is design ed for detect ing power up after power voltage reaches to a level where system can work . after power - on detect ed , the po f (pcon. 4) will be set 1 to indicate a cold reset, a power - on reset complete. the p of fl ag can be cleared via software. 23.2 brown - out detect ion the other power monitoring function, bod detection circuit is for monitoring the v dd level during execution. there are two programmable bod trigger levels available for wide voltage applications. th e two nominal levels are 2. 7 v and 3.8 v selected via setting cbov i n config2 . when v dd drops to the selected bod trigger level ( v bod ), the bod detection logic will either reset the cpu or request a bod interrupt. the use r may determine bod reset or interrupt enab le according to different application system s . the bod detect ion will request the interrupt while v dd drops below v bod while borst (pmc r .4) is 0. in this case, bof (p m c r .3) will set as 1. after the user clear s this flag whereas v dd remains below v bod , bof will not set again. bof just acknowledge the user a power drop occurs. the bof will set 1 after v dd goes higher than v bod to indicate a power resuming. v bod has a hysteresis of 2 0~ 20 0mv. config2 7 6 5 4 3 2 1 0 c bod en cbov - c borst - - - - r/w r/w - r/w - - - - factory default value: 1111 1111b bit name description 7 c bod en config bod detection e nable 1 = dis able bod detection . 0 = en able bod detection . boden is initialized by inverted cboden ( config2 , bit - 7) at any resets.
n79e 71 5 datasheet jan. 6 , 201 6 page 155 of 189 revision 1.0 1 bit name description 6 cbov config bod voltage selection th is bit select one of two bod voltage level. config - bits cbov sfr bov bod voltage 1 0 enable bod= 2.7v 0 1 enable bod= 3.8v 5 - reserved 4 c borst config bod reset e nable this bit decides if a bod reset is caused after a bod event. 1 = ena ble bod reset when v dd drops below v bod . 0 = disable bod reset when v dd drops below v bod . pmc r C power monitoring control ( ta protected ) 7 6 5 4 3 2 1 0 boden bov - borst bof - - bos r/w r/w - r/w r/w - - r address: a 3 h reset value: see table 7 C 2 N79E715 s fr description and reset value s bit name description 7 bod en bod - detect function control bod en is initialized by inverted c bod en ( config2 , bit - 7) at any resets. 1 = en able bod detection . 0 = dis able bod detection . 6 bo v bod voltage select b its bod are initialized at reset with the value of bits cbov in config3 - bits bod voltage select bits: config - bits cbov sfr bov bod voltage 1 0 enable bod= 2.7v 0 1 enable bod= 3.8v 5 - reserved 4 borst bod reset enable this bit decides if a bod reset is caused after a bod event. 0 = disable bod reset when v dd drops below v bod. 1 = enable bod reset when v dd drops below v bod .
n79e 71 5 datasheet jan. 6 , 201 6 page 156 of 189 revision 1.0 1 bit name description 3 bof bod flag this flag will be set as logic 1 via hardware after a v dd dropping below or rising above v bod event occurs. if both ebod (ie.5 ) and ea (ie.7) are set, a bod inte r rupt requirement will be generated. this bit should be cleared via software. 2 - it should be set to logic 0. 1 - reserved 0 bos bod status 1 = v dd voltage level is h igher than v bod . 0 = v dd voltage level is lower than v bod . note : i f bof is 1 after chip reset, it is strongly recommended to initialize the user program by clearing bof .
n79e 71 5 datasheet jan. 6 , 201 6 page 157 of 189 revision 1.0 1 24 reset conditions the N79E715 has several options to place device in reset condition. in general, most sfrs go to their reset value irrespective of the reset condition, but there are several reset source indicati on flags whose state depends on the s ource of reset. t here are 5 ways of putting the device into reset state. they are power - on r eset, rst pin reset , software reset, watchdog timer reset , and bod reset. 24.1 power - o n reset the N79E715 incorporates an internal voltage reference . during a power - on process of rising power supply voltage v dd , this voltage reference will hold the cpu in power - on reset mode when v dd is lower than t he voltage reference threshold. this design make s cpu not access program flash while the v dd is not adequate performing the flash reading. if a n undetermined operating code is read from the program flash and ex e cuted, this will put cpu and even the whole system in to an erroneous state. after a while, v dd rises above the reference threshold where the system can work , the selected oscillator will star t and then program code will be executed from 0000h. at the same t ime, a power - on flag pof (pcon.4) will be set 1 to indicate a cold reset, a power - on reset complete. note that the contents of internal ram will be undetermined after a power - on. it is recommended that user give initial value s for the ram block. p 1 . 6 , p 1 . 7 , p1 .0 and p1.1 are forced to quasi - bi - direction type when chip is in reset state. it is recommended that t he pof be cleared to 0 via software to check if a cold reset or warm reset pe r formed after the next reset occurs. if a cold reset caused by power off and on, pof will be set 1 again. if the reset is a warm reset caused by other reset sources, pof will remain 0. the user may take a different course to check other reset flag s and deal with the warm reset event . pcon C power control 7 6 5 4 3 2 1 0 smod smod 0 - pof gf1 gf0 pd idl r/w r/w - r/w r/w r/w r/w r/w address: 87h reset value: see table 7 C 2 N79E715 s fr description and reset value s bit name description 4 pof power - on reset flag this bit will be set as 1 after a power - on reset. it indicates a cold reset, a power - on reset complete. this bit remains its value after any other resets. this flag is recommended to be cleared via software.
n79e 71 5 datasheet jan. 6 , 201 6 page 158 of 189 revision 1.0 1 24.2 bod reset bod detection circuit is for monitoring the v dd level during execution. when v dd drops to the selected bod trigger level ( v bod ) or v dd rises over v bod , the bod detection logic will reset the cpu if borst (pmc r .4) se t ting 1. pmcr C power monitoring control ( ta protected ) 7 6 5 4 3 2 1 0 boden bov - borst bof - - bos r/w r/w - r/w r/w - - r address: a3h reset value: see table 7 C 2 N79E715 s fr description and reset value s bit name description 7 boden bod - detect function control boden is initialized by inverted cboden ( conf ig2 , bit - 7) at any resets. 1 = en able bod detection . 0 = dis able bod detection . 6 bov bod voltage select b its bod are initialized at reset with the value of bits cbov in config3 - bits bod voltage select bits: config - bits cbov sfr bov bod voltage 1 0 enabl e bod= 2.7v 0 1 enable bod= 3.8v 5 - reserved 4 borst bod reset enable this bit decides if a bod reset is caused after a bod event. 0 = disable bod reset when v dd drops below v bod . 1 = enable bod reset when v dd drops below v bod . 3 bof bod flag this f lag will be set as logic 1 via hardware after a v dd dropping below or rising above v bod event occurs. if both ebod (ie.5) and ea (ie.7) are set, a bod interrupt requirement will be generated. this bit should be cleared via software. 2 - it should be set t o logic 0. 1 - reserved
n79e 71 5 datasheet jan. 6 , 201 6 page 159 of 189 revision 1.0 1 bit name description 0 bos bo d s tatus 1 = v dd voltage level is higher than v bod . 0 = v dd voltage level is lower than v bod . 24.3 rst pin reset the hardware reset input is rst pin which is the input with a schmitt trigger. a hardware reset is accomplished by holding t he rst pin low for at least two machine - cycle s to ensure detection of a valid hardware reset signal . the reset circuitry then synchronously applies the internal reset signal. thus the reset is a synchr o nous operation and requires the clock to b e running to cause an external reset. once the device is in reset condition, it will remain so as long as rst pin is 1 . a fter the rst low is remov ed, the cpu will exit the reset state with in two machine - cycle s and begin code executing from address 0000h . there is no flag associated with the rst pin reset condit ion. however since the other reset sources have flags, the external reset can be considered a s the default reset if those reset flags are cleared. if a rst pin reset applie s while cpu is in power - dow n mode , the way to trigger a hardware reset is slightly different. since the power - down mode stops clock system , the reset signal will asynchronously cause the clock system resuming . after the clock system is stable, cpu will enter the reset state, then ex it and start to execute program code from address 0000h. note: after the cpu is released from all reset state, the hardware will always check the bs bit i n stead of the cbs bit to determine from aprom or ldrom that the device reboots. 24.4 watchdog timer reset t he watchdog t imer is a free running timer with programmable time - out intervals. the user can clear the watchdog timer at any time, causing it to restart the count. when the selected time - out occurs, the watchdog timer will reset the system directly. the re set condition is maintained via hardware for two machine - cycle s. after the reset is removed the device will begin execution from 0000 h . once a reset due to watchdog timer occurs the watchdog timer reset flag wdtrf ( wdcon0 . 3 ) will be set. this bit keeps unc hanged after any reset other than a power - on reset. the user may clear wdtrf via sof t ware.
n79e 71 5 datasheet jan. 6 , 201 6 page 160 of 189 revision 1.0 1 wdcon0 C watchdog timer control ( ta protected ) 7 6 5 4 3 2 1 0 wdten wdclr wdtf widpd wdtrf wps2 wps1 wps0 r/w w - r/w r/w r/w r/w r/w address: d8h reset value: s ee table 7 C 2 N79E715 s fr description and reset value s bit name description 3 wdtrf wdt reset flag when the mcu resets itself, this bit is set by hardware. the bit should be cleared by software. if ewrst=0, the int errupt flag wdtrf wont be set by hardware, and the mcu will reset itself right away. if ewrst=1, the interrupt flag wdtrf will be set by hardware and the mcu will jump into wdts interrupt service routine if wdt interrupt is enabled, and the mcu wont res et itself until 512 cpu clocks elapse. in other words, in this condition, the user also needs to clear the wdt counter (by writing 1 to wdclr bit) during this period of 512 cpu clocks, or the mcu will also reset itself when 512 cpu clocks elapse. wdcon 1 C watchdog timer control ( ta protected ) 7 6 5 4 3 2 1 0 - - - - - - - ewrst - - - - - - - r/w address: abh reset value: 0000 0000b bit name description 0 ewrst 0 = disable wdt reset function. 1 = enable wdt reset function. 24.5 software reset N79E715 a re enhanced with a software reset. this allows the program code to reset the whole system in software approach. it is quite useful in the end of an isp progress. for example , if an ldrom updating aprom isp finishes and the code in aprom is correctly update d, a software reset can be asserted to r e boot cpu from the aprom to check the result of the updated aprom program code immediately. writing 1 to swrst (chpcon.7) will trigger a software reset. note that this bit is timed access protection. see demo code be low.
n79e 71 5 datasheet jan. 6 , 201 6 page 161 of 189 revision 1.0 1 chpcon C chip control (ta p rotected) 7 6 5 4 3 2 1 0 swrst ispf lduen - - - bs ispen w r/w r/w - - - r/w r/w address: 9fh reset value: see table 7 C 2 N79E715 s fr description and reset value s bit name descri ption 7 swrst software reset setting this bit as logic 1 will cause a software reset. it will automatically be cleared via hardware after reset in finished. the software demo code is listed below. clr ea ; i f any interrupt is enabled, disable tempora rily mov ta,#0aah ;ta protection. mov ta,#55h ; anl chpcon,#0fdh ;bs = 0, reset to aprom. mov ta,#0aah mov ta,#55h orl chpcon,#80h ;software reset 24.6 boot select ion figure 24 - 1 boot selectio n diagram the N79E715 provide s user a flexible boot selection for variant application. the sfr bit bs in chpcon.1 determines cpu boot ing from ap rom or ld rom after any source of reset . if reset occurs and bs is 0 , cpu will re boot from ap prom . else, the cpu will re boot from ld rom . r s t - p i n r e s e t b r o w n o u t r e s e t s o f t w a r e r e s e t l o a d r e s e t a n d b o o t f r o m l d r o m r e s e t a n d b o o t f r o m a p r o m c o n f i g 0 . 7 c h p c o n . 1 w a t c h d o g t i m e r r e s e t b s c b s b s = 0 b s = 1 p o w e r - o n r e s e t
n79e 71 5 datasheet jan. 6 , 201 6 page 162 of 189 revision 1.0 1 config0 7 6 5 4 3 2 1 0 cbs - - - - - lock dfen r/w - - - - - r/w r/w factory default value: 1111 1111b bit name description 7 cbs config b oot s elect ion this bit defines from which block mcu boots after all resets except softwa re reset . 1 = mcu will boot from aprom after all resets except software reset . 0 = mcu will boot from ldrom after all resets except software reset . chpcon C chip control (ta p rotected) 7 6 5 4 3 2 1 0 swrst ispf ldue n - - - bs [1] ispen w r/w r/w - - - r /w r/w address: 9fh reset value: see table 7 C 2 N79E715 s fr description and reset value s bit name description 1 bs boot s elect ion there are different meanings of writing to or reading from this bit. writing : it de fines from which block mcu boots after all resets . 0 = the next re booting will be from aprom. 1 = the next re booting will be from ldrom. reading : it indicates from which block mcu booted after previous reset. 0 = the previous re booting is from aprom. 1 = the previous re booting is from ldrom. [1] note that this bit is initialized by being loaded from the inverted value of cbs bit in config0 .7 at all resets except software reset . it keeps unchanged after software reset. note: after the cpu is released f rom all reset state, the hardware will always check the bs bit i n stead of the cbs bit to determine from aprom or ldrom that the device reboots. 24.7 reset state the reset state does not affect the on - chip ram. the data in the ram will be preserved during the re set. note that the ram contents may be lost if the v dd falls below approximately 1.2 v. this is the
n79e 71 5 datasheet jan. 6 , 201 6 page 163 of 189 revision 1.0 1 minimum voltage level required for ram data retention. therefore , after the power - on reset the ram contents will be in determinate. during a power fail condit ion . if the power falls below the data retention minimum voltage , the ram contents will also los e . after a reset, most of sfrs go to their initial value s except bits which are affected by different reset events. see the note s in table 7 C 2 N79E715 s fr description and reset value s . for the initial state of all sfrs. some special function registers initial value depends on different reset sources. the program counter is forced to 0000h and held as long as the reset con dition is applied. note that the s tack p ointer is also reset to 07 h , therefore the stack contents may be effectively lost during the reset event even though the ram contents are not altered. after a r eset, i nterrupts and timers are disabled. the watchdog t imer is disabled if the reset source was a power - on reset . the i/o port sfrs have ff h written into them which puts the port pins in a high state. table 24 - 2 initial state of sfr caused by different resets power - on reset watchdog reset sof t ware/ exte r nal r eset bod reset with time a c cess protection wdcon 0 (d8h) c000 0000b b7(enwdt)= /cenwdt( config3 . 7) c0uu 1uuub c 0uu uuuub y wdcon1 (abh) 0000 0000b y isptrg (a4h) xxxx xxx0b y pmcr (a3h) c x cc 10xxb b[7:4]= config2 u x uu u0xxb u x uu 10xxb y chpcon (9fh) 0000 00c0b b1(bs)=/cbs 000x xuu0b y shbda (9ch) config1 unchanged y pcon (87h) 0001 000b 00uu 0000b 00uu 0000b ( software /external reset) 00uu 0000b n note: the write of aah and 55h should occur within 3 machine - cycles of each other. interrupts should be dis abled during this procedure to avoid delay between the two writes.
n79e 71 5 datasheet jan. 6 , 201 6 page 164 of 189 revision 1.0 1 25 config b it s ( config ) the N79E715 ha s several hardware configuration bytes , called config bits , which are used to co n figure the hardware option s such as the security bits, clock system sour ce , and so on. these hardware options can be re - configured through the programmer/writer or isp modes. N79E715 ha ve four config bits those are config0 ~ 3. several functions which are defined by certain config bits are also available to be re - configured by c ertain sfr bits. therefore, there is a need to load such config bits into respective sfr bits. such loading will occurs after reset s . (software reset will reload all config bits except cbs bit in config0 . 7 ) these sfr bits can be continuously controlled via users software. other resets will remain the values in these sfr bits unchanged. note: config bits marked as " - " should always keep unprogrammed. 25.1 config0 7 6 5 4 3 2 1 0 cbs - - - - - lock dfen r/w - - - - - r/w r/w factory default value: 1111 1111b bit name description 7 cbs config boot selection this bit defines from which block mcu boots after all resets except software r e set. 1 = mcu will boot from aprom after all resets except software reset. 0 = mcu will boot from ldrom after all resets except software reset. 6 :2 - reserved
n79e 71 5 datasheet jan. 6 , 201 6 page 165 of 189 revision 1.0 1 bit name description 1 lock chip lock e nable 1 = chip is unlocked. all of aprom, ldrom , and data flash are not locked . their contents can be read out through a parallel programmer/writer. 0 = chip is locked. aprom, ldrom, and data flash are loc ked. their contents read through parallel programmer/writer will become ffh. note that config bytes are always unlocked and can be read. hence, once the chip is locked, the config bytes cannot be erased or programmed individually. the only way to disable c hip lock is to use the whole chip erase mode. however, all data within aprom, ldrom, data flash, and other config bits will be erased when this procedure is executed. if the chip is locked, it does not alter the isp function. 0 dfen data flash enable 1 = there is no data flash space. t he aprom size is 16 k byte s . 0 = data flash exists. the data flash and aprom share 1 6 kbytes depending on shbda setting s . figure 25 - 1 config0 rese t reload ing except software reset 25.2 config1 7 6 5 4 3 2 1 0 chbda[7:0] [1] r/w factory default value: 1111 1111b bit name description 7:0 chbda[7:0] config high byte of data flash starting address this byte is valid only when dfen ( config0 .0) is 0. it is used to determine the starting address of the data flash. [1] : t here will be no aprom if setting chbda 00h. cpu will execute codes in minimum size(256b) of in ternal pr o gram memory. c h p c o n c o n f i g 0 c b s 7 - 6 4 - 5 - 3 - 2 l o c k 1 d f e n 0 s w r s t 7 i s p f 6 l d u e 5 - 4 - 3 - 2 b s 1 i s p e n 0 -
n79e 71 5 datasheet jan. 6 , 201 6 page 166 of 189 revision 1.0 1 figure 25 - 2 config1 reset reload ing 25.3 config2 7 6 5 4 3 2 1 0 c bod en cbov - c borst - - - - r/w r/w - r/w - - - - factory default value: 1111 1111b bit name description 7 c bod en config bod detection enable 1 = dis able bod detection . 0 = en able bod detection . boden is initialized by inverted cboden ( config2 , bit - 7) at any resets. 6 cbov config bod voltage selection this bit select s one of two bod voltage level. config - bits cbov sfr bov bod voltage 1 0 enable bod= 2.7v 0 1 enable bod= 3.8v 5 - reserved 4 c borst config bod reset enable this bit decides if a bod reset is caused after a bod event. 1 = enable bod reset when v dd drops below v bod . 0 = disable bod reset when v dd drops below v bod . 3:0 - reserved s h b d a c o n f i g 1 s h b d a [ 7 : 0 ] 7 6 5 4 3 2 1 0 c h b d a [ 7 : 0 ] 7 6 5 4 3 2 1 0
n79e 71 5 datasheet jan. 6 , 201 6 page 167 of 189 revision 1.0 1 figure 25 - 3 config2 reset reload ing 25.4 config3 7 6 5 4 3 2 1 0 cwdten - - ckf oscfs - fosc1 fosc0 r/w - - r/w r/w - r/w r/w factory default value: 1111 1111b bit name description 7 c wdten config watchdog timer en able 1 = dis able watchdog timer after all resets . 0 = en able watchdog timer after all resets . wdten is initialized by inverted cwdten ( config3 , bit - 7) at any other resets. 6 - reserved 5 - reserved 4 ckf clock filter enable 1 = enable clock filter. it i ncreases noise immunity and emc capacity. 0 = disable clock filter. 3 oscfs hirc frequency selection 1 = select 22.1184 mhz as the clock system if hirc mode is used. it bypasses the divided - by - 2 path of hirc to select 22.1184 mhz output as the clock syste m source. 0 = select 11.0592 mhz as the clock system if hirc mode is used. the hirc divided - by - 2 path is selected. the hirc is equiv a lent to 11.0592 mhz output used as the clock system . 2 - reserved 1 fosc1 oscillator select b it p m c r c o n f i g 2 c b o d e n 7 c b o v 6 5 c b o r s t 4 - 3 - 2 - 1 - 0 b o d e n 7 b o v 6 5 b o r s t 4 b o f 3 - 2 - 1 b o s 0 - -
n79e 71 5 datasheet jan. 6 , 201 6 page 168 of 189 revision 1.0 1 bit name description 0 fosc0 chip clock source selecti on (s ee the f ollowing t able ) (fosc1, fosc0) chip clock source (1, 1) hirc (1, 0) reserved (0, 0) (0, 1) external crystal, 4 mhz ~ 24 mhz figure 25 - 4 config3 rese t reload ing 25.5 config4 7 6 5 4 3 2 1 0 rstdbe rstdb s - - - - - div2 r/w r/w - - - - - r/w factory default value: 1111 1111b bit name description 7 rstd be reset pin de - bounce time expend if rstdbe = 0, reset pin de - bounce time depend s on rstdbs . 1 = r es et pin de - bounce time is default value (8 f sys clock ) . 0 = r eset pin de - bounce time depend s on rstdbs . 6 rstdb s reset pin de - bounce selectio n 1 = r eset pin de - bounce time is 16 f sys clock. 0 = r eset pin de - bounce time is 32 f sys clock. rstdbe rstdbs reset pin de - bounce time 1 x 8 f sys clock 0 1 16 f sys clock 0 0 32 f sys clock 5 :1 - reserved 0 div2 system clock d ivide d by 2 1 = f sys is equal to f osc 0 = f sys is equal to f osc /2 w d c o n 0 c o n f i g 3 c w d t e n 7 6 - 5 c k f 4 o s c f s 3 - 2 f o s c 1 1 0 w d t e n 7 w d c l r 6 w d t f 5 w i d p d 4 w d t r f 3 w p s 2 2 w p s 1 1 w p s 0 0 f o s c 0 -
n79e 71 5 datasheet jan. 6 , 201 6 page 169 of 189 revision 1.0 1 26 instruction set s the N79E715 execute s all the instructions of the standard 8051 family. all instructions are coded within an 8 - bit field called an opcode. this single byte should be fetched from program memory. the opcode is decoded by the cpu. it determines what action the microcontroller will take and whether m ore operation data is needed from memory. if no other data is needed, then only one byte was required. thus the instruction is called a one byte instruction. in some cases, more data is needed. these will be two or three byte instructions. table 26 C 1 lists all instructions in details. the n ote of the instruction set s and addressing modes are shown below. rn (n = 0~7) register r0~r7 of the currently selected register bank. direct 8 - bit internal data locations addre ss. this could be an internal data ram location (0~127) or a sfr (e.g. i/o port, control register, status register, etc.) (128~255). @ri (i = 0, 1) 8 - bit internal data ram location (0~255) addressed indirectly through regis - ter r0 or r1. #data 8 - bit constant included in the instruction. #data16 16 - bit constant included in the instruction. addr16 16 - bit destination address. used by lcall and ljmp. a branch can be any within the 16 kbytes program memory address space. addr11 11 - bit destination address. used by acall and ajmp. the branch will be within the same 2 kbytes page of program memory as the first byte of the following instruction. rel signed (2s complement) 8 - bit offset byte. used by sjmp and all conditional branches. the range is - 128 to +127 bytes relative to first byte of the follow - ing instruction. bit direct addressed bit in internal data ram or sfr. table 26 C 1 inst ruction set for N79E715 instruction opcode bytes clock cycles N79E715 vs. tradition 80c51 speed ratio nop 00 1 4 3.0 add a, r n 28 ~2f 1 4 3.0 add a, @ri 26 , 27 1 4 3.0 add a, direct 25 2 8 1.5 add a, #data 24 2 8 1.5 addc a, r n 38 ~3f 1 4 3.0
n79e 71 5 datasheet jan. 6 , 201 6 page 170 of 189 revision 1.0 1 table 26 C 1 inst ruction set for N79E715 instruction opcode bytes clock cycles N79E715 vs. tradition 80c51 speed ratio addc a, @ri 36 , 37 1 4 3.0 addc a, direct 35 2 8 1.5 addc a, #data 34 2 8 1.5 subb a, r n 98 ~9f 1 4 3.0 subb a, @ri 96 , 97 1 4 3.0 subb a, direct 95 2 8 1.5 subb a, #data 94 2 8 1.5 inc a 04 1 4 3.0 inc r n 08 ~0f 1 4 3.0 inc @ri 06 , 07 1 4 3.0 inc direct 05 2 8 1.5 inc dptr a3 1 8 3.0 dec a 14 1 4 3.0 dec r n 18 ~1f 1 4 3.0 dec @ri 16 , 17 1 4 3.0 dec direct 15 2 8 1.5 dec dptr a5 1 8 - mul ab a4 1 20 2.4 div ab 84 1 20 2.4 da a d4 1 4 3.0 anl a, r n 58 ~5f 1 4 3.0 anl a, @ri 56 , 57 1 4 3.0 anl a, d irect 55 2 8 1.5 anl a, #data 54 2 8 1.5 anl direct, a 52 2 8 1.5 anl direct, #data 53 3 12 2.0 orl a, r n 48 ~4f 1 4 3.0 orl a, @ri 46 , 47 1 4 3.0 orl a, direct 45 2 8 1.5 orl a, #data 44 2 8 1.5 orl direct, a 42 2 8 1.5 orl direct, #data 43 3 12 2 .0 xrl a, r n 68 ~6f 1 4 3.0 xrl a, @ri 66 , 67 1 4 3.0 xrl a, direct 65 2 8 1.5 xrl a, #data 64 2 8 1.5 xrl direct, a 62 2 8 1.5 xrl direct, #data 63 3 12 2.0 clr a e4 1 4 3.0 cpl a f4 1 4 3.0 rl a 23 1 4 3.0
n79e 71 5 datasheet jan. 6 , 201 6 page 171 of 189 revision 1.0 1 table 26 C 1 inst ruction set for N79E715 instruction opcode bytes clock cycles N79E715 vs. tradition 80c51 speed ratio rlc a 33 1 4 3.0 rr a 03 1 4 3.0 rrc a 13 1 4 3.0 swap a c4 1 4 3.0 mov a, r n e8 ~ef 1 4 3.0 mov a, @ri e6 , e7 1 4 3.0 mov a, direct e5 2 8 1.5 mov a, #data 74 2 8 1.5 mov r n , a f8 ~ff 1 4 3.0 mov r n , direct a8 ~af 2 8 3.0 mov r n , #data 78 ~7f 2 8 1.5 mov @ri, a f6 , f7 1 4 3.0 mov @ri, direct a6 , a7 2 8 3.0 mov @ri, #data 76 , 77 2 8 1.5 mov direct, a f5 2 8 1.5 mov direct, r n 88 ~8f 2 8 3.0 mov direct, @ri 86 , 87 2 8 3.0 mov direct, direct 85 3 12 2.0 mov direct, #data 75 3 12 2.0 mov dptr, #data16 90 3 12 2.0 movc a, @a+dptr 93 1 8 3.0 movc a, @a+pc 83 1 8 3.0 movx a, @ri [1] e2 , e3 1 8 3.0 movx a, @dptr [1] e0 1 8 3.0 movx @ri, a [1] f2 , f3 1 8 3.0 movx @dptr, a [1] f0 1 8 3.0 push direct c0 2 8 3.0 pop direct d0 2 8 3.0 xch a, r n c8 ~cf 1 4 3.0 xch a, @ri c6 , c7 1 4 3.0 xch a, direct c5 2 8 1.5 xchd a, @ri d6 , d7 1 4 3.0 clr c c3 1 4 3.0 clr bit c2 2 8 1.5 setb c d3 1 4 3.0 setb bit d2 2 8 1.5 cpl c b3 1 4 3.0 cpl bit b2 2 8 1.5 anl c, bit 82 2 8 3.0 anl c, /bit b0 2 8 3.0 orl c, bit 72 2 8 3.0
n79e 71 5 datasheet jan. 6 , 201 6 page 172 of 189 revision 1.0 1 table 26 C 1 inst ruction set for N79E715 instruction opcode bytes clock cycles N79E715 vs. tradition 80c51 speed ratio orl c, /bit a0 2 8 3.0 mov c, bit a2 2 8 1.5 mov bit, c 92 2 8 3.0 acall addr11 11, 31, 51, 71, 91, b1, d1, f1 [2] 2 12 2.0 lcall addr16 12 3 16 1.5 ret 22 1 8 3.0 reti 32 1 8 3.0 ajmp addr 11 01, 21, 41, 61, 81, a1, c1, e1 2 12 2.0 ljmp addr16 02 3 16 1.5 jmp @a+dptr 73 1 8 3.0 sjmp rel 80 2 12 2.0 jz rel 60 2 12 2.0 jnz rel 70 2 12 2.0 jc rel 40 2 12 2.0 jnc rel 50 2 12 2.0 jb bit, rel 20 3 16 1.5 jnb bit, rel 30 3 16 1.5 jbc bit, rel 10 3 16 1.5 cjne a, direct, rel b5 3 16 1.5 cjne a, #data, rel b4 3 16 1. 5 cjne @ri, #data, rel b6 , b7 3 16 1.5 cjne r n , #data, rel b8 ~bf 3 16 1.5 djnz r n , rel d8 ~df 2 12 2.0 djnz direct, rel d5 3 16 1.5 [1] the most three significant bits in the 11 - bit address [a10:a8] decide the acall hex code. the code will be [a10,a9,a 8,1,0,0,0,1]. [2] the most three significant bits in the 11 - bit address [a10:a8] decide the ajmp hex code. the code will be [a10,a9,a8,0,0,0,0,1].
n79e 71 5 datasheet jan. 6 , 201 6 page 173 of 189 revision 1.0 1 27 in - circuit program (icp) the icp (in - circuit - program) mode is another approach to access the flash eprom. the re are only 3 pins needed to perform the icp function. one is input /rst pin, which should be fed to gnd in the icp wor k ing period. one is clock input, shared with p1.7, which accepts serial clock from external device. another is data i/o pin, shared with p1.6, that an external icp program tool shifts in/out data via p1.6 synchronized with clock(p1.7) to access the flash eprom of N79E715 . upon ent ering icp program mode, all pin s will be set to quasi - bidirectional mode, and output to level 1. the N79E715 support s flash eprom ( 16 k bytes aprom eprom) , data flash memory ( 128 bytes per page ) and ldrom programming . user can select to program the aprom , data flash and ldrom. figure 27 C 1 icp connection with N79E715 note: 1. when u s ing icp to upgrade code, the /rst , p1.6 and p1.7 should be taken within design system board. 2. after program finished by icp, to suggest system power should power off and remove icp connector then power on. 3. it is recommended that user perform erase fu nction and programming configure bits continuously without any interruption. n 7 9 e 7 1 5 p 1 . 6 p 1 . 7 v s s a p p . d e v i c e a p p . d e v i c e a p p . d e v i c e v d d v p p d a t a v s s i c p w r i t e r t o o l v c c j u m p e r i c p c o n n e c t o r s y s t e m b o a r d i c p p o w e r s w i t c h * * * * : r e s i s t o r i s o p t i o n a l b y a p p l i c a t i o n * r s t c l o c k v d d
n79e 71 5 datasheet jan. 6 , 201 6 page 174 of 189 revision 1.0 1 user may refer to the following website for icp program tool. entry the web site, please select nuvoton isp - icp progra m mer. http://www.nuvoton.com/hq/products/microcontrollers/8bit - 8051 - mcus/software figure 27 C 2 nuvoton isp - icp pr o grammer
n79e 71 5 datasheet jan. 6 , 201 6 page 175 of 189 revision 1.0 1 28 electrical characteristics 28.1 absolu te maximum ratings table 28 C 1 absolute maximum ratings parameter rating u nit operating temperature under bias - 40 to +85 ? c storage temperature range - 55 to +150 ? c voltage on v dd pin to v ss - 0.3 to +6.5 v voltage on any ot her pin to v ss - 0.3 to (v dd +0.3) v stresses at or above those listed under absolute maximum ratings m a y cause permanent damage to the device. this is a stress rating o nly and functional operation of the device at these or any other conditions above th ose indicated in the operational sections of this specification is not implied. exposure to absolute ma x imum rating conditions may affect device reliability. 28.2 dc electrical characteristics table 28 C 2 operation voltage parameter sym min typ max condition s un it operating voltage v dd 2. 4 5.5 f xtal = 4 mhz ~ 24 mhz v 2. 4 5.5 f hirc = 22.1184 mhz isp operating voltage v dd 3.0 5.5 f xtal = 4 mhz ~ 24 mhz v table 28 C 3 dc characteristics (v dd ? v ss = 2.4 ~5.5v, ta = - 40 ? c ~ + 85 ? c, unless otherwise specified. ) s ym parameter test condition s min typ max unit s vdd v dd rise rate to ensure internal power - on reset signal see section on power - on reset for details 0.05 [ 5 ] - - v/ms
n79e 71 5 datasheet jan. 6 , 201 6 page 176 of 189 revision 1.0 1 table 28 C 3 dc characteristics (v dd ? v ss = 2.4 ~5.5v, ta = - 40 ? c ~ + 85 ? c, unless otherwise specified. ) s ym parameter test condition s min typ max unit v il input low voltage ( general purpose i/o with ttl input ) 2. 4 < v dd < 5.5v - 0.5 0.2v d d - 0.1 v v il 1 input low voltage ( general purpose i/o with schmitt trigger input ) 2. 4 < v dd < 5.5v - 0.5 0.3v dd v v il2 input low voltage ( / rst, xtal1 ) 2. 4 < v dd < 5.5v - 0.5 0.2v dd - 0.1 v v ih input high voltage ( general purpose i/o with ttl input ) 2. 4 < v dd < 5.5v 0.2v dd +0.9 v dd +0.5 v v ih 1 input high voltage ( general purpose i/o with schmitt trigger input ) 2. 4 < v dd < 5.5v 0.7v dd v dd +0.5 v v ih 2 input high voltage ( / rst, xtal1 ) 2. 4 < v dd < 5.5v 0.7v dd v dd +0.5 v v ol output low voltage ( general purpose i/o of p0,p2,p3 , all modes except input only) v dd =4.5v, i ol = 20 ma [2 ] , [3 ] 0.4 5 v v dd = 3 . 0 v, i ol = 14 ma [ 2 ] , [3 ] 0.4 5 v v dd =2.4v, i ol = 10 ma [2 ] , [3 ] 0.4 5 v v ol1 output low voltage (p10, p11, p14, p16, p17) ( all modes except input only) v dd =4.5v, i ol = 38 ma [ 2 ] , [3 ] 0.4 5 v v dd =3.0v, i ol = 27 ma [2 ] , [3 ] 0.4 5 v v dd =2.4v, i ol = 20 ma [2 ] , [3 ] 0.4 5 v v oh output high voltage ( general purpose i/o , quasi bidire c tional ) v dd =4.5v i oh = - 3 8 0 a [3 ] 2.4 v v dd = 3 . 0 v i oh = - 90 a [3 ] 2. 4 v
n79e 71 5 datasheet jan. 6 , 201 6 page 177 of 189 revision 1.0 1 table 28 C 3 dc characteristics (v dd ? v ss = 2.4 ~5.5v, ta = - 40 ? c ~ + 85 ? c, unless otherwise specified. ) s ym parameter test condition s min typ max unit v dd =2.4v i oh = - 48 a [3 ] 2.0 v v oh 1 output high voltage ( general purpose i/o , push - pull ) v dd =4.5v i oh = - 28m a [2 ] , [3 ] 2.4 v v dd = 3 . 0 v i oh = - 7m a [2 ] , [3 ] 2. 4 v v dd =2.4v i oh = - 3.5m a [2 ] , [3 ] 2.0 v i il logical 0 input current ( general purpose i/o , quasi bi - direction ) v dd =5.5v, v in = 0.4v - 40 at 5.5v - 50 a i tl logical 1 to 0 transition current ( general purpose i/o , quasi bi - direction) v dd = 5.5v, v in = 2.0v [1 ] - 550 at 5.5v - 650 a i li input le akage current ( general purpose i/o , open - drain or input only) 0 < v in < v dd <1 10 a i op op current ( active mode [4 ] ) f sys = 12 mhz, v dd = 5.0v 3.1 ma f sys = 24 mhz, v dd = 5.5v 4.3 ma f sys = 12 mhz, v dd = 3.3v 1.7 ma f sys = 24 mhz, v dd = 3.3v 3.2 ma f sys = 22.1184 mhz , v dd = 5v 2. 3 ma f sys = 22.1184 mhz , v dd = 3.3v 2. 2 ma i idle idle current f sys = 12 mhz, v dd = 5.0v 2.7 ma
n79e 71 5 datasheet jan. 6 , 201 6 page 178 of 189 revision 1.0 1 table 28 C 3 dc characteristics (v dd ? v ss = 2.4 ~5.5v, ta = - 40 ? c ~ + 85 ? c, unless otherwise specified. ) s ym parameter test condition s min typ max unit f sys = 24 mhz, v dd = 5. 5 v 3.7 ma f sys = 12 mhz, v dd = 3.3v 1.3 ma f sys = 24 mhz, v dd = 3.3 v 2.3 ma f sys = 22.1184 mhz , v dd = 5v 1.6 ma f sys = 22.1184 mhz , v dd = 3.3v 1. 6 ma i pd power - down mode <10 a power - down mode (bod enable) 100 a r rst rst - pin internal pull - h igh resistor 2. 4 v < v dd < 5.5v 100 250 k v bod 38 bod 38 detect voltage ( temp.=25 ) 3.5 3.8 4.1 v bod 38 detect voltage ( temp.= 85 ) 3.5 3.8 4.9 v bod 38 detect voltage ( temp.= - 40 ) 3.0 3.8 4.1 v v bod27 bod27 detect voltage ( temp.=25 ) 2.5 2.7 2.9 v bod27 detect voltage ( temp.= 85 ) 2.5 2.7 3.1 v bod27 detect voltage ( temp.= - 40 ) 2.4 2.7 2.9 v
n79e 71 5 datasheet jan. 6 , 201 6 page 179 of 189 revision 1.0 1 [1 ] pins of ports 0~ 3 source a transition current when they are being externall y driven from 1 to 0. the transition current reaches its ma x imum value when v in is approximately 2v. [2 ] under steady state (non - transient) conditions, i ol /i oh should be externally limited as follows: maximum i ol /i oh of p0, p2, p3 per port pin: 2 0 ma max imum i ol /i oh of p 10, p11, p14, p16, p17 : 38 ma maximum total i ol /i oh for all outputs: 100 ma (through v dd total current) maximum total i ol /i oh for all outputs: 15 0ma (through v ss total current) [3 ] if i oh exceeds the test condition, v oh will be lower than the listed specification. if i ol exceeds the test condition, v ol will be higher than the listed specification. [4 ] tested while cpu is kept in reset state. [5 ] these parameters are characterized but not tested. i. typical values are not guaranteed. the valu es listed are tested at room temperature and based on a limited number of samples. ii. g eneral purpose i/o mean the general purpose i/o, such as p0, p1, p2, p3. iii. p1.2 and p1.3 are open drain structure. they have not quasi or push pull modes.
n79e 71 5 datasheet jan. 6 , 201 6 page 180 of 189 revision 1.0 1 28.3 analog electric al characteristics 28.3.1 characteristics of 10 - bits sar - adc symbol min typ max unit operation voltage v dd 2.7 5.5 v resolution 10 bit conversion time 35t adc [1] us sampling rate 150k hz integral non - linearity error inl - 1 1 lsb differential non - linearity dnl - 1 1 lsb gain error ge - 1 1 lsb offset error ofe - 4 4 lsb clock frequency adcclk 5.25 mhz absolute error - 4 4 lsb band - gap v bg 1 1.3 1.6 v [1] t adc the period time of adc input clock
n79e 71 5 datasheet jan. 6 , 201 6 page 181 of 189 revision 1.0 1 28.3.2 characteristics of 4 ~ 24 mhz crystal parame ter condition min. typ. max. unit input clock frequency external crystal 4 24 mhz parameter symbol min. typ. max. units notes external crystal frequency 1/t clcl 4 24 mhz clock high time t chcx 20.8 - - ns clock low time t clcx 20.8 - - ns clock r ise time t clch - - 10 ns clock fall time t chcl - - 10 ns note: duty cycle is 50%. 28.3.3 characteristics of hirc parameter condition s min. typ. max. unit center frequency 22.1184 mhz f hirc +25 0 c at v dd = 5v - 1 +1 % +25 0 c at v dd = 2.4 ~5.5v - 2 +2 % - 10 0 c~+70 0 c at v dd = 2.4 ~5.5v - 3 +3 % - 40 0 c~+85 0 c at v dd = 2.4 ~5.5v - 5 +5 % t clcl t clcx t chcx t clch t chcl
n79e 71 5 datasheet jan. 6 , 201 6 page 182 of 189 revision 1.0 1 28.3.4 characteristics of lirc parameter condition min. typ. max. unit f lirc v dd = 2.4v ~ 5.5v 5 10 15 khz
n79e 71 5 datasheet jan. 6 , 201 6 page 183 of 189 revision 1.0 1 29 application circuit for e mc i mmunity the applicat ion circuit is shown below. it is recommended that user follow the circuit enclosed by gray blocks to achieve the most stable and reliable operation of mcu especially in a noisy power environment for a healthy emc immunity. if hirc is used as the clock sys tem , a 0.1f capacitor should be added to gain a precise rc frequency. crystal frequency r c1 c2 4mhz~24mhz without d epend on crystal specifications figure 29 C 1 application circuit for e ft improvement v s s / r s t v d d g n d v d d 0 . 1 f 0 . 1 f 3 3 f a s c l o s e t o t h e p o w e r s o u r c e a s p o s s i b l e a s c l o s e t o m c u a s p o s s i b l e 1 0 k 1 0 f x t a l 2 x t a l 1 c 1 c 2 r c r y s t a l a s c l o s e t o x t a l p i n a s p o s s i b l e
n79e 71 5 datasheet jan. 6 , 201 6 page 184 of 189 revision 1.0 1 30 package dimensions 30.1 28 - pin sop - 300 mil e 1 28 15 14 control demensions are in milmeters . ? e
n79e 71 5 datasheet jan. 6 , 201 6 page 185 of 189 revision 1.0 1 30.2 28 - pin tssop - 4.4x9.7 mm
n79e 71 5 datasheet jan. 6 , 201 6 page 186 of 189 revision 1.0 1 30.3 20 - pin sop - 300 mil e 1 20 11 10 control demensions are in milmeters . ? e
n79e 71 5 datasheet jan. 6 , 201 6 page 187 of 189 revision 1.0 1 30.4 20 - pin tssop - 4.4x6.5mm
n79e 71 5 datasheet jan. 6 , 201 6 page 188 of 189 revision 1.0 1 30.5 16 - pin sop - 150 mil
n79e 71 5 datasheet jan. 6 , 201 6 page 189 of 189 revision 1.0 1 31 revision history revision date descrip tion 1.0 0 2015 / 09 / 16 preliminary version 1.01 2016/1/6 chapter 5: fix pin description p 0.1 and v dd in table of tssop20 and sop16 c hapter 16: modify i2clk formula to chapter 20: add isp page erase time and byte program time nomin ally, a page - erase time is 2 0 ms and a byte - program time is 4 0 s. important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications ar e deemed , insecure usage. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a re sult of customers insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton. 1) (i2clk 4 f f sys c i 2 ? ? ?

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