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1 of 265 rev: 011606 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device ma y be simultaneousl y available throu g h various sales channels. for informat ion about device errata, click here: www.maxim - ic.com/errata. general description the ds2156 is a software-selectable t1, e1, or j1 single-chip transceiver (sct) for short-haul and long-haul applications. the backplane is user- configurable for a tdm or utopia ii bus interface. the ds2156 is composed of a line interface unit (liu), framer, hdlc controllers, and a utopia/tdm backplane interface, and is controlled by an 8-bit parallel port configured for intel or motorola bus operations. the ds2156 is pin and software compatible with the ds2155. the liu is composed of transmit and receive interfaces and a jitter attenuator. the transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. t1 waveform generation includes dsx-1 line buildouts as well as csu line buildouts of -7.5db, -15db, and -22.5db. e1 waveform generation includes g.703 waveshapes for both 75 ? coax and 120 ? twisted cables. the receive interface provides network terminati on and recovers clock and data from the network. applications inverse mux atm (ima) t1/e1/j1 line cards switches and routers add-drop multiplexers features complete t1/ds1/isdn-pri/j1 transceiver functionality complete e1 (cept) pcm-30/isdn-pri transceiver functionality user-selectable tdm or utopia ii bus interface long-haul and short-haul line interface for clock/data recovery and waveshaping cmi coder/decoder for optical i/f crystal-less jitter attenuator fully independent transmit and receive functionality dual hdlc controllers programmable bert generator and detector internal software-selectable receive and transmit-side termination resistors for 75 ? /100 ? /120 ? t1 and e1 interfaces dual two-frame elastic-store slip buffers that connect to asynchronous backplanes up to 16.384mhz 16.384mhz, 8.192mhz, 4.096mhz, or 2.048mhz clock output synthesized to recovered network clock features continued in section 1 . ordering information part temp range pin-package ds2156l 0c to +70c 100 lqfp ds2156l+ 0c to +70c 100 lqfp ds2156ln -40c to +85c 100 lqfp ds2156ln+ -40c to +85c 100 lqfp DS2156G 0c to +70c 100 csbga DS2156G+ 0c to +70c 100 csbga DS2156Gn -40c to +85c 100 csbga DS2156Gn+ -40c to +85c 100 csbga + denotes lead-free/rohs -compliant package. ds2156 t1/e1/j1 single-chip transceive r tdm/utopia ii interface www.maxim-ic.com ds2156 t1/e1/j1 tdm/utopia t1/e1/j1 networ k backplane utopia tdm downloaded from: http:///
ds2156 2 of 265 table of contents 1. main feat ures............................................................................................................ 9 2. detailed d escription............................................................................................ 12 2.1 b lock d iagram ........................................................................................................................ 14 3. pin function descript ion .................................................................................... 20 3.1 tdm b ackplane ...................................................................................................................... 20 3.1.1 transmit side .................................................................................................................. .....................20 3.1.2 receive side ................................................................................................................... .....................23 3.2 utopia b us ............................................................................................................................ 26 3.2.1 receive side ................................................................................................................... .....................26 3.2.2 transmit side .................................................................................................................. .....................27 3.3 p arallel c ontrol p ort p ins ................................................................................................ 28 3.4 e xtended s ystem i nformation b us ...................................................................................... 29 3.5 u ser o utput p ort p ins ......................................................................................................... 30 3.6 jtag t est a ccess p ort p ins ................................................................................................ 31 3.7 l ine i nterface p ins ................................................................................................................ 32 3.8 s upply p ins ............................................................................................................................. 33 3.9 l and g p ackage p inout ........................................................................................................ 34 3.10 10 mm csbga p in c onfiguration .......................................................................................... 38 4. parallel port ......................................................................................................... 39 4.1 r egister m ap .......................................................................................................................... 39 4.2 utopia b us r egisters .......................................................................................................... 45 5. special per-channel re gister oper ation ................................................... 46 6. programming model ............................................................................................. 48 6.1 p ower -u p s equence .............................................................................................................. 49 6.1.1 master mode regist er........................................................................................................... ...............49 6.2 i nterrupt h andling ............................................................................................................... 50 6.3 s tatus r egisters ................................................................................................................... 50 6.4 i nformation r egisters .......................................................................................................... 51 6.5 i nterrupt i nformation r egisters ........................................................................................ 51 7. clock ma p.................................................................................................................. 52 8. t1 framer/formatter contro l and status registe rs ........................... 53 8.1 t1 c ontrol r egisters ........................................................................................................... 53 8.2 t1 t ransmit t ransparency ................................................................................................... 58 8.3 ais-ci and rai-ci g eneration and d etection ..................................................................... 58 8.4 t1 r eceive -s ide d igital -m illiwatt c ode g eneration ......................................................... 59 9. e1 framer/formatter contro l and status registe rs........................... 62 9.1 e1 c ontrol r egisters .......................................................................................................... 62 9.2 a utomatic a larm g eneration ............................................................................................... 66 9.3 e1 i nformation r egisters .................................................................................................... 67 10. common control and st atus regis ters ...................................................... 69 10.1 t1/e1 s tatus r egisters ........................................................................................................ 70 11. i/o pin configurat ion opti ons ........................................................................... 76 12. loopback conf iguration.................................................................................... 78 12.1 p er -c hannel l oopback ......................................................................................................... 80 13. error count registe rs ....................................................................................... 82 13.1 l ine -c ode v iolation c ount r egister (lcvcr) ................................................................... 83 13.1.1 t1 oper ation ................................................................................................................... .....................83 13.1.2 e1 oper ation ................................................................................................................... .....................83 13.2 p ath c ode v iolation c ount r egister (pcvcr) .................................................................. 85 downloaded from: http:///
ds2156 3 of 265 13.2.1 t1 oper ation ................................................................................................................... .....................85 13.2.2 e1 oper ation ................................................................................................................... .....................85 13.3 f rames o ut - of -s ync c ount r egister (foscr).................................................................. 86 13.3.1 t1 oper ation ................................................................................................................... .....................86 13.3.2 e1 oper ation ................................................................................................................... .....................86 13.4 e-b it c ounter (ebcr) ........................................................................................................... 87 14. ds0 monitoring function..................................................................................... 88 15. signaling o peration ............................................................................................. 90 15.1 r eceive s ignaling .................................................................................................................. 90 15.1.1 processor-based signaling...................................................................................................... ............90 15.1.2 hardware-based re ceive signaling ............................................................................................... .....91 15.2 t ransmit s ignaling ................................................................................................................ 96 15.2.1 processor-b ased mode ........................................................................................................... ............96 15.2.2 software signaling inse rtion-enable register s, e1 cas mode ........................................................100 15.2.3 software signaling insertion-en able registers, t1 mode .................................................................102 15.2.4 hardware-b ased mode ............................................................................................................ ..........102 16. per-channel idle co de generat ion .............................................................. 103 16.1 i dle -c ode p rogramming e xamples ..................................................................................... 104 17. channel blocking registe rs .......................................................................... 108 18. elastic stores operatio n ................................................................................ 111 18.1 r eceive s ide ......................................................................................................................... 114 18.1.1 t1 mode ........................................................................................................................ .....................114 18.1.2 e1 mode........................................................................................................................ .....................114 18.2 t ransmit s ide ....................................................................................................................... 114 18.2.1 t1 mode ........................................................................................................................ .....................115 18.2.2 e1 mode........................................................................................................................ .....................115 18.3 e lastic s tores i nitialization .............................................................................................. 115 18.4 m inimum d elay m ode ............................................................................................................ 115 19. g.706 intermediate crc-4 upda ting (e1 mode only).................................. 116 20. t1 bit-oriented code (boc) cont roller ...................................................... 117 20.1 t ransmit boc ....................................................................................................................... 117 transmit a boc................................................................................................................. ...............................117 20.2 r eceive boc ......................................................................................................................... 117 receive a boc.................................................................................................................. ...............................117 21. additional (sa) and international (s i) bit operation (e1 only).......... 120 21.1 m ethod 1: h ardware s cheme ............................................................................................. 120 21.2 m ethod 2: i nternal r egister s cheme b ased on d ouble -f rame ...................................... 120 21.3 m ethod 3: i nternal r egister s cheme b ased on crc4 m ultiframe ................................ 123 22. hdlc contro llers ............................................................................................... 133 22.1 b asic o peration d etails ..................................................................................................... 133 22.2 hdlc c onfiguration ........................................................................................................... 133 22.2.1 fifo c ontrol ................................................................................................................... ...................137 22.3 hdlc m apping ...................................................................................................................... 138 22.3.1 receive ........................................................................................................................ ......................138 22.3.2 transmit ....................................................................................................................... ......................140 22.3.3 fifo info rmation ............................................................................................................... .................145 22.3.4 receive packet-bytes available ................................................................................................. .......145 22.3.5 hdlc fifos ..................................................................................................................... .................146 22.4 r eceive hdlc c ode e xample .............................................................................................. 147 22.5 l egacy fdl s upport (t1 m ode ).......................................................................................... 147 22.5.1 overview ....................................................................................................................... .....................147 22.5.2 receive section ................................................................................................................ .................147 22.5.3 transmit section ............................................................................................................... .................149 downloaded from: http:///
ds2156 4 of 265 22.6 d4/slc-96 o peration .......................................................................................................... 149 23. line interface unit (l iu) ..................................................................................... 150 23.1 liu o peration ...................................................................................................................... 150 23.2 r eceiver ............................................................................................................................... 150 23.2.1 receive level indicator and threshold interrupt ...............................................................................1 51 23.2.2 receive g.703 synchroniza tion signal (e 1 mode) ............................................................................151 23.2.3 monitor mode ................................................................................................................... ..................151 23.3 t ransmitter .......................................................................................................................... 152 23.3.1 transmit short-circui t detector/limiter........................................................................................ ......152 23.3.2 transmit open-cir cuit detector ................................................................................................. ........152 23.3.3 transmit bpv e rror inse rtion ................................................................................................... ..........152 23.3.4 transmit g.703 synchronizati on signal (e 1 mode)...........................................................................152 23.4 mclk p rescaler .................................................................................................................. 153 23.5 j itter a ttenuator ............................................................................................................... 153 23.6 cmi (c ode m ark i nversion ) o ption .................................................................................... 153 23.7 liu c ontrol r egisters ....................................................................................................... 154 23.8 r ecommended c ircuits ........................................................................................................ 161 23.9 c omponent s pecifications .................................................................................................. 163 24. utopia backplane interf ace........................................................................... 168 24.1 d escription .......................................................................................................................... 168 24.1.1 list of applic able standards ................................................................................................... ...........168 24.1.2 acronyms and definitions ....................................................................................................... ...........168 24.2 utopia c lock m odes .......................................................................................................... 169 24.3 f ull t1/e1 m ode and c lear -c hannel e1 m ode ................................................................. 169 24.4 f ractional t1/e1 mode ........................................................................................................ 170 24.5 t ransmit o peration ............................................................................................................. 171 24.5.1 utopia side transmit: muxed mo de with one tran smit clav.......................................................171 24.5.2 utopia side transmit: direct st atus mode (multitr ansmit clav) ...................................................174 24.5.3 transmit pr ocessing ............................................................................................................ ..............176 24.6 r eceive o peration ............................................................................................................... 177 24.6.1 receive processing ............................................................................................................. ..............177 24.6.2 utopia side receive: muxed mode with one re ceive cl av.........................................................179 24.6.3 utopia side receive: direct st atus mode (multi receive clav) .....................................................180 24.7 r egister d efinitions ........................................................................................................... 182 24.8 r eceive fifo o verrun ........................................................................................................ 193 24.9 utopia d iagnostic l oopback ............................................................................................ 193 25. programmable in-band loop code generation and detection ........ 194 26. bert func tion ........................................................................................................ 201 26.1 s tatus ............................................................................................................................... .... 201 26.2 m apping ............................................................................................................................... .. 201 26.3 bert r egister d escriptions ............................................................................................. 203 26.4 bert r epetitive p attern s et ............................................................................................. 207 26.5 bert b it c ounter ............................................................................................................... 208 26.6 bert e rror c ounter ......................................................................................................... 209 27. payload error-insertion function (t1 mode only)................................ 211 27.1 n umber - of -e rrors r egisters ............................................................................................ 213 27.1.1 number-of-errors left register................................................................................................. .........214 28. interleaved pcm bus operation (ibo)........................................................... 215 28.1 c hannel i nterleave ............................................................................................................. 215 28.2 f rame i nterleave ................................................................................................................. 215 29. extended system inform ation bus (esib) .................................................... 218 30. programmable backplane clock synth esizer....................................... 222 31. fractional t1/e1 suppo rt ................................................................................. 222 downloaded from: http:///
ds2156 5 of 265 31.1 tdm b ackplane m ode .......................................................................................................... 222 31.2 utopia b ackplane m ode .................................................................................................... 223 32. user-programmable output pins.................................................................. 224 33. jtag boundary scan architect ure and test access po rt ................ 225 33.1 d escription .......................................................................................................................... 225 33.2 i nstruction r egister .......................................................................................................... 228 sample/preload................................................................................................................. ........................229 bypass ......................................................................................................................... ..................................229 extest......................................................................................................................... ...................................229 clamp .......................................................................................................................... ...................................229 highz.......................................................................................................................... .....................................229 idcode......................................................................................................................... ...................................229 33.3 t est r egisters ..................................................................................................................... 230 33.4 b oundary s can r egister .................................................................................................... 230 33.5 b ypass r egister .................................................................................................................. 230 33.6 i dentification r egister ....................................................................................................... 230 34. functional timi ng diag rams ............................................................................ 234 34.1 t1 m ode ............................................................................................................................... . 234 34.2 e1 m ode ............................................................................................................................... . 239 35. operating p aramete rs ...................................................................................... 248 36. ac timing parameter s and diag rams ........................................................... 250 36.1 m ultiplexed b us ac c haracteristics ................................................................................ 250 36.2 n onmultiplexed b us ac c haracteristics ......................................................................... 253 36.3 r eceive -s ide ac c haracteristics ...................................................................................... 256 36.4 t ransmit ac c haracteristics ............................................................................................ 259 36.5 utopia t ransmit ac c haracteristics .............................................................................. 262 36.6 utopia r eceive ac c haracteristics ................................................................................ 262 37. revision hi story ................................................................................................... 263 38. package info rmation ......................................................................................... 264 38.1 100-p in lqfp (56-g5002-000).............................................................................................. 264 38.2 100-b all csbga (56-g6008-001) ........................................................................................ 265 downloaded from: http:///
ds2156 6 of 265 list of figures figure 2-1. block diagram ...................................................................................................... .................. 14 figure 2-2. receive and transmit liu (tdm backplane enabled)........................................................... 15 figure 2-3. receive and transmit liu (utopia backplane enabled) ..................................................... 16 figure 2-4. receive and transmit framer/hdlc ................................................................................... .. 17 figure 2-5. backplane interface (tdm backplane enabled) .................................................................... 18 figure 2-6. backplane interface (utopia bus enabled) ......................................................................... 19 figure 3-1. 10mm csbga pin configuration (tdm signals shown) ....................................................... 38 figure 6-1. programming sequence ............................................................................................... ......... 48 figure 7-1. clock map (tdm mode) ............................................................................................... .......... 52 figure 15-1. simplified diagram of receive signaling path ..................................................................... 9 0 figure 15-2. simplified diagram of transmit signaling path .................................................................... 9 6 figure 19-1. crc-4 recalculate method .......................................................................................... ..... 116 figure 23-1. typical monitor application ....................................................................................... ......... 151 figure 23-2. cmi coding ........................................................................................................................ 153 figure 23-3. basic interface ................................................................................................... ................ 161 figure 23-4. protected interface using internal receive termination.................................................... 162 figure 23-5. e1 transmit pulse template ........................................................................................ ...... 164 figure 23-6. t1 transmit pulse template ........................................................................................ ...... 164 figure 23-7. jitter tolerance .................................................................................................. ................ 165 figure 23-8. jitter tolerance (e1 mode)........................................................................................ ......... 165 figure 23-9. jitter attenuation (t1 mode)...................................................................................... ......... 166 figure 23-10. jitter attenuation (e1 mode) ..................................................................................... ....... 166 figure 23-11. optional crystal connections..................................................................................... ...... 167 figure 24-1. utopia clocking configurations .................................................................................... ... 169 figure 24-2. polling phase and selection phase at transmit interface ................................................. 172 figure 24-3. end and restart of cell at transmit interface ................................................................... 1 73 figure 24-4. transmission to phy paused for three cycles ................................................................. 174 figure 24-5. example of direct status indication, transmit direction .................................................... 175 figure 24-6. transmit cell flow ................................................................................................ ............. 176 figure 24-7. cell-delineation state diagram .................................................................................... ...... 177 figure 24-8. header correction state machine ................................................................................... ... 178 figure 24-9. polling phase and selection at receive interface.............................................................. 179 figure 24-10. end and restart of cell transmission at receive interface............................................. 180 figure 24-11. example of direct status indication, receive direction ................................................... 181 figure 26-1. simplified diagram of bert in network direction ............................................................. 202 figure 26-2. simplified diagram of bert in backplane direction.......................................................... 202 figure 28-1. ibo example ....................................................................................................... ............... 217 figure 29-1. esib group of four ds2156s ........................................................................................ .... 218 figure 33-1. jtag functional block diagram ..................................................................................... ... 225 figure 33-2. tap controller state diagram...................................................................................... ...... 228 figure 34-1. receive-side d4 timing ............................................................................................ ........ 234 figure 34-2. receive-side esf timing ........................................................................................... ....... 234 figure 34-3. receive-side boundary timing (with elastic store disabled) ............................................. 235 figure 34-4. receive-side 1.544mhz boundary timing (with elastic store enabled) ........................... 235 figure 34-5. receive-side 2.048mhz boundary timing (with elastic store enabled) ........................... 236 figure 34-6. transmit-side d4 timing ........................................................................................... ........ 236 figure 34-7. transmit-side esf timing .......................................................................................... ....... 237 figure 34-8. transmit-side boundary timing (with elastic store disabled)........................................... 237 figure 34-9. transmit-side 1.544mhz boundary timing (with elastic store enabled) .......................... 238 figure 34-10. transmit-side 2.048mhz boundary timing (with elastic store enabled) ........................ 238 figure 34-11. receive-side timing .............................................................................................. .......... 239 figure 34-12. receive-side boundary timing (with elastic store disabled).......................................... 239 downloaded from: http:///
ds2156 7 of 265 figure 34-13. receive-side boundary timing, rsysclk = 1.544mhz (elastic store enabled)........... 240 figure 34-14. receive-side boundary timing, rsysclk = 2.048mhz (elastic store enabled)........... 240 figure 34-15. receive ibo channel interleave mode timing ................................................................ 241 figure 34-16. receive ibo frame interleave mode timing ................................................................... 242 figure 34-17. g.802 timing, e1 mode only ....................................................................................... .... 243 figure 34-18. transmit-side timing ............................................................................................. .......... 243 figure 34-19. transmit-side boundary timing (elastic store disabled) ................................................ 244 figure 34-20. transmit-side boundary timing, tsysclk = 1.544mhz (elastic store enabled) ......... 244 figure 34-21. transmit-side boundary timing, tsysclk = 2.048mhz (elastic store enabled) .......... 245 figure 34-22. transmit ibo channel interleave mode timing ............................................................... 246 figure 34-23. transmit ibo frame interleave mode timing .................................................................. 247 figure 36-1. intel bus read timing (bts = 0/mux = 1) ........................................................................ 251 figure 36-2. intel bus write timing (bts = 0/mux = 1)......................................................................... 2 51 figure 36-3. motorola bus timing (bts = 1/mux = 1)........................................................................... 25 2 figure 36-4. intel bus read timing (bts = 0/mux = 0) ........................................................................ 254 figure 36-5. intel bus write timing (bts = 0/mux = 0)......................................................................... 2 54 figure 36-6. motorola bus read timing (bts = 1/mux = 0) ................................................................. 255 figure 36-7. motorola bus write timing (bts = 1/mux = 0) ................................................................. 255 figure 36-8. receive-side timing ............................................................................................... ........... 257 figure 36-9. receive-side timing, elastic store enabled...................................................................... 25 8 figure 36-10. receive line interface timing.................................................................................... ...... 258 figure 36-11. transmit-side timing ............................................................................................. .......... 260 figure 36-12. transmit-side timing, elastic store enabled................................................................... 261 figure 36-13. transmit line interface timing................................................................................... ...... 261 figure 36-14. utopia interface setup and hold times ........................................................................ 262 figure 36-15. utopia interface delay times ..................................................................................... ... 262 downloaded from: http:///
ds2156 8 of 265 list of tables table 3-a. pin description sorted by pin number (tdm backplane enabled) ........................................ 34 table 3-b. pin description sorted by pin number (utopia backplane enabled)................................... 36 table 4-a. register map sorted by address ...................................................................................... ...... 39 table 4-b. utopia register map ................................................................................................. ........... 45 table 8-a. t1 alarm criteria..................................................................................................................... 61 table 9-a. e1 sync/resync criteria ......................................................................................................... 63 table 9-b. e1 alarm criteria..................................................................................................................... 68 table 13-a. t1 line code violation counting options ............................................................................ .83 table 13-b. e1 line-code violation counting options ............................................................................ 83 table 13-c. t1 path code violation counting arrangements .................................................................. 85 table 13-d. t1 frames out-of-sync counting arrangements ................................................................. 86 table 15-a. time slot numbering schemes ........................................................................................ .... 97 table 16-a. idle-code array address mapping.................................................................................... .. 103 table 16-b. gric and gtic functions ............................................................................................ ...... 105 table 18-a. elastic store delay after initialization ........................................................................... ...... 115 table 22-a. hdlc controller registers .......................................................................................... ....... 134 table 23-a. transformer specifications ......................................................................................... ........ 163 table 24-a. utopia clock mode configuration .................................................................................... 170 table 27-a. transmit error-insertion setup sequence .......................................................................... 21 1 table 27-b. error insertion examples ........................................................................................... ......... 213 table 33-a. instruction codes for ieee 1149.1 architecture ................................................................. 229 table 33-b. id code structure .................................................................................................. ............. 230 table 33-c. device id codes.................................................................................................... ............. 230 table 33-d. boundary scan control bits......................................................................................... ....... 231 downloaded from: http:///
ds2156 9 of 265 1. main features the ds2156 contains all of the features of the previous generation of dallas semiconducto rs t1 and e1 scts plus many new features such as a utopia bus interface. general programmable output clocks for fractional t1, e1, h0, and h12 applications interleaving pcm bus operation 8-bit parallel control port, multiplexed or nonmultiplexed, intel or motorola ieee 1149.1 jtag-boundary scan 3.3v supply with 5v tolerant inputs and outputs pin compatible with ds2155, ds2152/ds2154, and ds21x5y sct family signaling system 7 support rai-ci, ais-ci support 100-pin lqfp package (14mm x 14mm) (ds2156) 3.3v supply with 5v tolerant inputs and outputs lqfp package that is pin compatible with ds2152/ds2154, ds21352/ds21354, ds21552/ds21554, and ds2155 evaluation kits ieee 1149.1 jtag boundary scan driver source code available from the factory line interface requires only a 2.048mhz master clock for both e1 and t1 operation with the option to use 1.544mhz for t1 operation fully software configurable short-haul and long-haul applications automatic receive sensitivity adjustments ranges include 0 to 43db or 0 to 12db for e1 applications and 0 to 13db or 0 to 36db for t1 applications receive level indication in 2.5db steps from -42.5db to -2.5db internal receive term ination option for 75 ? , 100 ? , and 120 ? lines internal transmit termination option for 75 ? , 100 ? , and 120 ? lines monitor application gain settings of 20db, 26db, and 32db g.703 receive synchronization-signal mode flexible transmit waveform generation t1 dsx-1 line buildouts t1 csu line buildouts of -7.5db, -15db, and -22.5db e1 waveforms include g.703 waveshapes for both 75 ? coax and 120 ? twisted cables ais generation independent of loopbacks alternating ones and zeros generation square-wave output open-drain output option nrz format option transmitter power-down transmitter 50ma short-circuit limiter with current-limit-exceeded indication transmit open-circuit-detected indication line interface function can be completely decoupled from the framer/formatter clock synthesizer output frequencies include 2.048mhz, 4.096mhz, 8.192mhz, and 16.384mhz derived from recovered receive clock jitter attenuator 32-bit or 128-bit crystal-less jitter attenuator requires only a 2.048mhz master clock for both e1 and t1 operation with the option to use 1.544mhz for t1 operation can be placed in either the receive or transmit path or disabled limit trip indication framer/formatter fully independent transmit and receive functionality full receive and transmit path transparency t1 framing formats include d4 (slc-96) and esf detailed alarm and status reporting with optional interrupt support large path and line error counters for: C t1: bpv, cv, crc6, and framing bit errors C e1: bpv, cv, crc4, e-bit, and frame alignment errors timed or manual update modes ds1 idle code generation on a per-channel basis in both transmit and receive paths C user-defined C digital milliwatt ansi t1.403-1998 support rai-ci detection and generation ais-ci detection and generation e1ets 300 011 rai generation g.965 v5.2 link detect ability to monitor one ds0 channel in both the transmit and receive paths in-band repeating pattern generators and detectors C three independent generators and detectors C patterns from 1 to 8 bits or 16 bits in length downloaded from: http:///
ds2156 10 of 265 rcl, rlos, rra, and rais alarms interrupt on change-of-state flexible signaling support C software or ha rdware based C interrupt generated on change of signaling data C receive signaling freeze on loss-of-sync, carrier loss, or frame slip addition of hardware pins to indicate carrier loss and signaling freeze automatic rai generation to ets 300 011 specifications access to sa and si bits option to extend carrier loss criteria to a 1ms period as per ets 300 233 japanese j1 support C ability to calculate and check crc6 according to the japanese standard C ability to generate yellow alarm according to the japanese standard tdm bus dual two-frame independe nt receive and transmit elastic stores C independent control and clocking C controlled slip capability with status C minimum delay mode supported 16.384mhz maximum backplane burst rate supports t1 to cept (e1) conversion programmable output clocks for fractional t1, e1, h0, and h12 applications interleaving pcm bus operation hardware signaling capability C receive signaling reinsertion to a backplane multiframe sync C availability of signaling in a separate pcm data stream C signaling freezing ability to pass the t1 f-bit position through the elastic stores in the 2.048mhz backplane mode access to the data streams in between the framer/formatter and the elastic stores user-selectable synthesized clock output utopia bus supports fractional t1/e1 a nd arbitrary bit rates in multiples of 64kbps (ds0/ts) up to 2.048mbps supports clear e1 compliant to the atm fo rum specifications for atm over ds1 and e1, respectively standard utopia-ii inte rface to the atm layer configurable utopia address supports diagnostic loopback optional payload scrambling in transmit direction and descrambling in receive direction as per the itu i.432 for the cell-based physical layer optional hec insertion in transmit direction with programmable coset polynomial addition option of using either idle or unassigned cells for cell-rate decoupling in transmit direction 1-byte programmable pattern for payload of cells used for cell-rate decoupling transmit fifo depth configurable to either 2, 3, 4 cell deep, which provides co ntrol over cell latency transmit fifo depth indication for 2-cell space optional single-bit hec error insertion hec-based cell delineation optional single-bit hec error correction in the receive direction optional filtering of hec errored cells received optional receive idle/unassigned cell filtering programmable loss-of-cell delineation (lcd) integration and optional interrupt interrupt for fifo overr un in receive direction saturating counts for: C number of error-free assigned cells received and transmitted C number of correctable and uncorrectable hec- errored cells received optional internally generated clock (system clock divided by 8) in diagnostic loopback mode hdlc controllers two independent hdlc controllers fast load and unload features for fifos ss7 support for fisu transmit and receive independent 128-byte rx and tx buffers with interrupt support access fdl, sa, or single/multiple ds0 channels ds0 access includes nx64 or nx56 compatible with polled or interrupt driven environments bit-oriented code (boc) support test and diagnostics programmable on-chip bi t error-rate testing pseudorandom patterns including qrss user-defined repetitive patterns daly pattern error insertion single and continuous total bit and errored bit counts payload error insertion error insertion in the payload portion of the t1 frame in the transmit path errors can be inserted over the entire frame or selected channels insertion options include continuous and absolute number with selectable insertion rates f-bit corruption for line testing downloaded from: http:///
ds2156 11 of 265 loopbacks: remote, local, analog, and per-channel loopback extended system information bus host can read interrupt and alarm status on up to 8 ports with a single bus read user-programmable output pins four user-defined output pins for controlling external logic control port 8-bit parallel control port multiplexed or nonmultiplexed buses intel or motorola formats supports polled or interrupt environments software access to device id and silicon revision software reset supported C automatic clear on power-up hardware reset pin the ds2156 is compliant with the following standards: ansi: t1.403-1995, t1.231C1993, t1.408 at&t: tr54016, tr62411 itu: g.703, g.704, g.706, g.736, g.775, g.823, g.932, i.431, o.151, q.161 itu-t: recommendation i.432C03/93 b-isdn user-network interfacephysical layer specification etsi: ets 300 011, ets 300 166, ets 300 233, ctr12, ctr4 japanese: jtg.703, jti.431, jj-20.11 (cmi coding only) atm forum: ds1 physical layer specification, af-phy-0016.000, september 1994 atm forum: e1 physical layer specification, af-phy-0064.000, september 1996 atm forum: utopia level 2 specification, version 1.0, af-phy-0039.000, june 1995 downloaded from: http:///
ds2156 12 of 265 2. detailed description the ds2156 is a software-selectable t1, e1, or j1 si ngle-chip transceiver (sct) for short-haul and long- haul applications. the backplane is user-configur able for a tdm or utopia ii bus interface. the ds2156 is composed of an liu, framer, hdlc cont rollers, and a utopia/tdm backplane interface, and is controlled by an 8-bit parallel port configured for intel or motorola bus operations. the ds2156 is pin and software compatible with the ds2155. the liu is composed of transmit and receive interfaces and a jitter attenuator. the transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. t1 waveform generation includes dsx-1 line buildouts as well as csu line buil douts of -7.5db, -15db, and -22.5db. e1 waveform generation includes g.703 waveshapes for both 75 ? coax and 120 ? twisted cables. the receive interface provides network termination and recovers clock and data from the ne twork. the receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0 to 43db or 0 to 12db for e1 a pplications and 0 to 30db or 0 to 36db for t1 applications. the jitter atte nuator removes phase jitter from the transmitted or received signal. the crystal-less jitter attenuato r requires only a 2.048mhz mclk for both e1 and t1 applications (with the option of us ing a 1.544mhz mclk in t1 applicati ons) and can be placed in either transmit or receive data paths. an additional feature of the liu is a cmi coder/decoder for interfacing to optical networks. on the transmit side, clock, data, and frame-sync si gnals are provided to th e framer by the backplane interface section. the framer inserts the appropriate synchronization fr aming patterns, alarm information, calculates and inserts th e crc codes, and provides the b8zs/ hdb3 (zero code suppression) and ami line coding. the receive-side framer decodes ami, b8zs, and hdb3 line coding, synchronizes to the data stream, reports alarm information, counts fram ing/coding/crc errors, and provides clock/data and frame-sync signals to the backplane interface section. both the transmit and receive path have two hdl c controllers. the hdlc controllers transmit and receive data through the framer block. the hdlc cont rollers can be assigned to any time slot, group of time slots, portion of a time slot or to fdl (t1) or sa bits (e1). each controller has 128-byte fifos, thus reducing the amount of processor ove rhead required to manage the flow of data. in a ddition, built-in support for reducing the processor time is required in ss7 applications. the backplane interface provides a versatile method of sending and receiving data from the host system. elastic stores provide a method for interfacing to asynchronous systems, converting from a t1/e1 network to a 2.048mhz, 4.096mhz, 8.192mhz, or n x 64khz system backplane. the elastic stores also manage slip conditions (asynchronous interface). an in terleave bus option (ibo) is provided to allow up to eight transceivers to share a high-speed backplane in tdm mode. the parallel port provides access for control and configuration of the ds2156s features. the extended system information bus (esib) function allows up to eight transceivers to be accessed by a single read for interrupt status or other user-s electable alarm status informati on. diagnostic capabilities include loopbacks, prbs pattern generation/detection, a nd 16-bit loop-up and loop-down code generation and detection. downloaded from: http:///
ds2156 13 of 265 readers note: this data sheet assumes a particular nomen clature of the t1 operating environment. in each 125 s frame there are 24 8-bit channels plus a framing b it. it is assumed that the framing bit is sent first followed by channel 1. each cha nnel is made up of eight bits that are numbered 1 to 8. bit number 1 is the msb and is transmitted first. bit number 8 is th e lsb and is transmitted last. the term locked is used to refer to two clock signals that are phase- or frequency-locked or de rived from a common clock (i.e., a 1.544mhz clock can be lock ed to a 2.048mhz clock if they share the same 8khz component). throughout this data sheet, the fo llowing abbreviations are used: b8zs bipolar with 8 zero substitution boc bit-oriented code crc cyclical redundancy check d4 superframe (12 frames per multiframe) multiframe structure esf extended superframe (24 frames per multiframe) multiframe structure fdl facility data link fps framing pattern sequence in esf fs signaling framing pattern in d4 ft terminal framing pattern in d4 hdlc high-level data link control mf multiframe slcC96 subscriber loop carrier96 channels downloaded from: http:///
ds2156 14 of 265 2.1 block diagram figure 2-1 shows a simplified bloc k diagram featuring the major co mponents of the ds2156. details are shown in subsequent figures. about 30 device pins have dual functions depending on the selection of the backplane, utopia, or tdm. some of the block diagrams depict a configuration based on the state of the backplane selection. the block diagram is divi ded into three functional blocks: liu, framer, and backplane interface. figure 2-1. block diagram tx liu clock adapter backplane interface circuit utopia or tdm host interface t1/e1/j1 network clock jtag esib rx liu jitter attenuator local loopback remote loopback framer loopback payload loopback mux mux external access to receive signals (tdm backplane only) external access to transmit signals (tdm backplane only) backplane backplane clock synth liu framer backplane interface sync hdlcs singaling alarm det framer crc gen singaling alarm gen hdlcs hdb3 / b8zs hdb3 / b8zs ds2156 downloaded from: http:///
ds2156 15 of 265 figure 2-2. receive and transmit liu (tdm backplane enabled) local loopback tring ttip jitter attenuator transmit or receive path receive line i/f rring rtip remote loopback vco / pll mclk 8xclk 32.768mhz xtald rposo rnego rnegi rposi tposi tnegi tnego tposo rclko rclki tclki tclko liuc mux mux rpos rneg rclk tpos tneg tclk jaclk rcl transmit line i/f downloaded from: http:///
ds2156 16 of 265 figure 2-3. receive and transmit liu (utopia backplane enabled) local loopback tring ttip jitter attenuator transmit or receive path receive line i/f rring rtip remote loopback vco / pll mclk 8xclk 32.768mhz xtald rpos rneg rclk tpos tneg tclk rcl jaclk transmit line i/f downloaded from: http:///
ds2156 17 of 265 figure 2-4. receive and transmit framer/hdlc receive framer transmit framer data clock sync sync clock data framer loopback xmit hdlc #1 mapper xmit hdlc #2 mapper 128 byte fifo 128 byte fifo mapper mapper rec hdlc #1 rec hdlc #2 128 byte fifo 128 byte fifo data clock sync sync clock data rpos rneg rclk tpos tneg tclk payload loopback downloaded from: http:///
ds2156 18 of 265 figure 2-5. backplane interface (tdm backplane enabled) rlink rlclk rsig rsigfr rser rclk rsync rdata rfsync rmsync elastic store signaling buffer sa bit/fdl extraction data clock sync rchblk rchclk channel timing rsysclk tser tsig tssync tsync tdata teso tchblk tchclk tlink tlclk channel timing sync clock data signaling buffer elastic store sa/fdl insert tclk mux tclk tsysclk jaclk downloaded from: http:///
ds2156 19 of 265 figure 2-6. backplane interface (utopia bus enabled) transmit framer interface control scrambling & rate decoupling cell storage fifo transmit utopia bus interface u t - e nb ut-soc ut-clk ut-addr0 to ut-addr4 ut-data0 to ut-data7 ut-clav0 5 8 receive framer interface control scrambling & rate decoupling cell storage fifo receive utopia bus interface u r - e nb ur-soc ur-clk ur-addr0 to ur-addr4 ur-data0 to ur-data7 ur-clav0 5 8 data rchclk data sync loopback tclk rclk rsync ut-2clav0 rdata ut-utdo tsync tdata tchclk data sync rclk tclk downloaded from: http:///
ds2156 20 of 265 3. pin function description the ds2156 has a user-selectable tdm or utopia b ackplane. table 3-a and table 3-b indicate which pins have alternate functions depending on the bac kplane selected. note that even when the utopia backplane is selected, the basic tdm signals such as clock, data, and frame-sync are available for both the transmit and receive directions. 3.1 tdm backplane 3.1.1 transmit side signal name: tclk signal description: transmit clock signal type: input a 1.544mhz (t1) or a 2.048mhz (e1) primary clock. used to clock data through the transmit-side formatter. tclk can be internally sourced from mclk. this is th e most flexible method and requires only a single clock signal for both t1 or e1. if internal sourcing is used, then the tclk pin should be connected low. signal name: tser signal description: transmit serial data signal type: input transmit nrz serial data. sampled on the falling edge of tc lk when the transmit-side elastic store is disabled. sampled on the falling edge of tsysclk when the transmit-side elastic store is enabled. signal name: tchclk signal description: transmit channel clock signal type: output a 192khz (t1) or 256khz (e1) clock that pulses high during the lsb of each channel. can also be programmed to output a gated transmit bit clock on a per-channel basis. sy nchronous with tclk when the transmit-side elastic store is disabled. synchronous with tsysclk when the tran smit-side elastic store is enabled. useful for parallel- to-serial conversion of channel data. signal name: tchblk signal description: transmit channel block signal type: output a user-programmable output that can be forced high or low during any of the channels. synchronous with tclk when the transmit-side elastic store is disabled. synchronous with tsysclk when the transmit-side elastic store is enabled. useful for blocking clocks to a serial uart or lapd controller in a pplications where not all channels are used such as fractional t1, fractional e1, 384kbps (h 0), 768kbps, or isdnCpri. also useful for locating individual channels in drop-and-in sert applications, for external pe r-channel loopback, and for per-channel conditioning. signal name: tsysclk signal description: transmit system clock signal type: input 1.544mhz, 2.048mhz, 4.096mhz, 8.192mhz, or 16.384mhz cl ock. only used when the transmit-side elastic store function is enabled. should be connected low in app lications that do not use the transmit-side elastic store. see section 28 for details on 4.096mhz, 8.192mhz, and 16.384mhz operation using the ibo. downloaded from: http:///
ds2156 21 of 265 signal name: tlclk signal description: transmit link clock signal type: output demand clock for the transmit link data [tlink] input. t1 mode: a 4khz or 2khz (zbtsi) clock. e1 mode: a 4khz to 20khz clock. signal name: tlink signal description: transmit link data signal type: input if enabled, this pin is sampled on the falling edge of tclk for data insertion into either the fdl stream (esf) or the fs-bit position (d4), or the z-bit position (zbts i) or any combination of the sa-bit positions (e1). signal name: tsync signal description: transmit sync signal type: input/output a pulse at this pin establishes either frame or multifra me boundaries for the transmit side. can be programmed to output either a frame or multiframe pulse. if this pin is set to output pulses at frame boundaries, it can also be set by iocr1.3 to output double-wide pulses at signaling frames in t1 mode. signal name: tssync signal description: transmit system sync signal type: input only used when the transmit-side elastic store is enabled. a pulse at this pin establishes either frame or multiframe boundaries for the transmit side. should be connected low in applications that do not use the transmit-side elastic store. signal name: tsig signal description: transmit signaling input signal type: input when enabled, this input samples signaling bits fo r insertion into outgoing pcm data stream. sampled on the falling edge of tclk when the transmit-side elastic st ore is disabled. sampled on the falling edge of tsysclk when the transmit-side elastic store is enabled. signal name: teso signal description: transmit elastic store data output signal type: output updated on the rising edge of tclk with data out of the transmit-side elastic store whether the elastic store is enabled or not. this pin is normally connected to tdata. signal name: tdata signal description: transmit data signal type: input sampled on the falling edge of tclk with data to be clocked through the transmit-side formatter. this pin is normally connected to teso. downloaded from: http:///
ds2156 22 of 265 signal name: tposo signal description: transmit positive-data output signal type: output updated on the rising edge of tclko with the bipolar data out of the transmit-side formatter. can be programmed to source nrz data by the output data format (iocr1.0) c ontrol bit. this pin is normally connected to tposi. signal name: tnego signal description: transmit negative-data output signal type: output updated on the rising edge of tclko with the bipolar data out of the transmit-side formatter. this pin is normally connected to tnegi. signal name: tclko signal description: transmit clock output signal type: output buffered clock that is used to clock data through the transm it-side formatter (i.e., either tclk or rclki). this pin is normally connected to tclki. signal name: tposi signal description: transmit positive-data input signal type: input sampled on the falling edge of tclki for data to be tran smitted out onto the t1 line. can be internally connected to tposo by connecting the liuc pin high. tposi and tn egi can be connected together in nrz applications. signal name: tnegi signal description: transmit negative-data input signal type: input sampled on the falling edge of tclki for data to be tran smitted out onto the t1 line. can be internally connected to tnego by connecting the liuc pin high. tposi and tn egi can be connected together in nrz applications. signal name: tclki signal description: transmit clock input signal type: input line interface transmit clock. can be internally connected to tclko by connecting the liuc pin high. downloaded from: http:///
ds2156 23 of 265 3.1.2 receive side signal name: rlink signal description: receive link data signal type: output t1 mode: updated with either fdl data (esf) or fs bits (d4) or z bits (zbtsi) one rclk before the start of a frame. e1 mode: updated with the full e1 data stream on the rising edge of rclk. signal name: rlclk signal description: receive link clock signal type: output t1 mode: a 4khz or 2khz (zbtsi) clock for the rlink output. e1 mode: a 4khz to 20khz clock. signal name: rclk signal description: receive clock signal type: output 1.544mhz (t1) or 2.048mhz (e1) cl ock that is used to clock data through the receive-side framer. signal name: rchclk signal description: receive channel clock signal type: output a 192khz (t1) or 256khz (e1) clock that pulses high dur ing the lsb of each channel. synchronous with rclk when the receive-side elastic store is disabled. synchronous with rsysclk wh en the receive-side elastic store is enabled. useful for parallel-to-ser ial conversion of channel data. signal name: rchblk signal description: receive channel block signal type: output a user-programmable output that can be forced high or low during any of the 24 t1 or 32 e1 channels. synchronous with rclk when the receive-side elastic st ore is disabled. synchronous with rsysclk when the receive-side elastic store is enabled. useful for blocking clocks to a serial uart or lapd controller in applications where not all channels are used such as fractional service, 384kbps service, 768kbps, or isdnCpri. also useful for locating individual channels in drop-and- insert applications, for external per-channel loopback, and for per-channel conditioning. see section 17 for details. signal name: rser signal description: receive serial data signal type: output received nrz serial data. updated on rising edges of rcl k when the receive-side elastic store is disabled. updated on the rising edges of rsysclk when the receive-side elastic store is enabled. signal name: rsync signal description: receive sync signal type: input/output an extracted pulse, one rclk wide, is output at this pin that identifies either frame (iocr1.5 = 0) or multiframe (iocr1.5 = 1) boundaries. if set to output frame boundaries, then through iocr1.6, rs ync can also be set to output double-wide pulses on signaling frames in t1 mode. if th e receive-side elastic store is enabled, then this pin can be enabled to be an input through iocr1.4, at wh ich a frame or multiframe boundary pulse is applied. signal name: rfsync signal description: receive frame sync signal type: output an extracted 8khz pulse, one rclk wide, is outpu t at this pin that identifies frame boundaries. downloaded from: http:///
ds2156 24 of 265 signal name: rmsync signal description: receive multiframe sync signal type: output an extracted pulse, one rclk wide (elastic store disabled) or one rsysclk wide (elastic store enabled), is output at this pin that identifies multiframe boundaries. signal name: rdata signal description: receive data signal type: output updated on the rising edge of rclk with the data out of the receive-side framer. signal name: rsysclk signal description: receive system clock signal type: input 1.544mhz, 2.048mhz, 4.096mhz, or 8.192mhz clock. only used when the receive-side elastic store function is enabled. should be connected low in applications that do not use the receive-side elastic store. see section 28 for details on 4.096mhz and 8.192m hz operation using the ibo. signal name: rsig signal description: receive signaling output signal type: output outputs signaling bits in a pcm format. updated on rising edges of rclk when the receive-side elastic store is disabled. updated on the rising edges of rsysclk wh en the receive-side elastic store is enabled. signal name: rlos/lotc signal description: receive loss-of-sync/loss-of-transmit clock signal type: output a dual function output that is controlled by the ccr1.0 cont rol bit. this pin can be programmed to either toggle high when the synchronizer is searching for the frame a nd multiframe or to toggle hi gh if the tclk pin has not been toggled for 5 s. signal name: rcl signal description: receive carrier loss signal type: output set high when the line interface detects a carrier loss. signal name: rsigf signal description: receive signaling freeze signal type: output set high when the signaling data is frozen by either auto matic or manual intervention. used to alert downstream equipment of the condition. signal name: bpclk signal description: backplane clock signal type: output a user-selectable synthesized clock output that is refere nced to the clock that is output at the rclk pin. downloaded from: http:///
ds2156 25 of 265 signal name: rposo signal description: receive positive-data output signal type: output updated on the rising edge of rclko with bipolar data out of the line interface. this pin is normally connected to rposi. signal name: rnego signal description: receive negative-data output signal type: output updated on the rising edge of rclko with the bipolar data out of the line interface. this pin is normally connected to rposi. signal name: rclko signal description: receive clock output signal type: output buffered recovered clock from the network. this pin is normally connected to rclki. signal name: rposi signal description: receive positive-data input signal type: input sampled on the falling edge of rclki for data to be cl ocked through the receive-side framer. rposi and rnegi can be connected together for an nrz interface. can be internally connected to rposo by connecting the liuc pin high. signal name: rnegi signal description: receive negative-data input signal type: input sampled on the falling edge of rclki for data to be cl ocked through the receive-side framer. rposi and rnegi can be connected together for an nrz interface. can be internally connected to rnego by connecting the liuc pin high. signal name: rclki signal description: receive clock input signal type: input clock used to clock data through the receive-side fram er. this pin is normally connected to rclko. can be internally connected to rclko by connecting the liuc pin high. downloaded from: http:///
ds2156 26 of 265 3.2 utopia bus 3.2.1 receive side signal name: ur-addr0 to ur-addr4 signal description: receive utopia address signal type: input 5-bit utopia address bus driven from atm layer to select the appropriate utopia port. rx_utop_addr4 is the msb; rx_utop_addr0 is the lsb. signal name: ur -en b signal description: receive utopia enable signal type: input active-low signal asserted by the atm layer to indicate th at ur-datax and ur-soc are sampled at the end of the next cycle. signal name: ur-soc signal description: receive utopia start of cell signal type: output active-high signal asserted by the ds2156 when ur-datax contains the first valid byte of a cell and is enabled only in cycles following those with ur-enb asserted and cell transfer is in progress. signal name: ur-data0 to ur-data7 signal description: receive utopia data bus signal type: output this byte-wide data bus is driven by the ds2156 in res ponse to the selection of one of the utopia ports by the atm layer for cell transfer. this bus is tri-statable and is enabled only in cycles following those with ur-enb asserted and cell transfer is in progress for a port. ur-data7 is the msb; ur-data0 is the lsb. signal name: ur-clav signal description: receive utopia cell available signal type: output the active-high ur-clav signal is asserted if a complete cell is available for transfer to the atm layer for the polled port. if ur-addrx does not match with any one of ut opia port addresses, this signal is tri-stated at the chip level using the control lines detailed below. ur-cl av0 is driven in multiplexed bus with 1clav polling mode as well as direct status mode. signal name: ur-clk signal description: receive utopia clock signal type: input receive utopia bus clock. downloaded from: http:///
ds2156 27 of 265 3.2.2 transmit side signal name: ut-addr0 to ut-addr4 signal description: transmit utopia address signal type: input this 5-bit wide bus is driven by the atm layer to poll and select the appropriate utopia port. ut-addr4 is the msb; ut-addr0 is the lsb. signal name: ut-en b signal description: transmit utopia enable signal type: input active-low enable signal asserted by atm layer during cycles when ut-datax contains valid cell data. signal name: ut-soc signal description: transmit utopia start of cell signal type: input active-high signal asserted by atm layer when ut-datax contains the first valid byte of the cell. signal name: ut-data0 to ut-data7 signal description: transmit utopia data bus signal type: input byte-wide true data driven from atm layer to one of th e selected ports. ut-data7 is the msb; ut-data0 is the lsb. signal name: ut-clav signal description: transmit utopia cell available signal type: output this active-high ut-clav signal is asserted by the ds 2156 if it has a cell space available to accommodate a complete cell from the atm layer to the polled port. signal name: ut-2clav signal description: transmit utopia 2 cells available signal type: output this active-high signal is asserted by the ds2156 to indicat e that the transmitter can accommodate two cells. ut- 2clav0 is driven in multiplexed bus with 1clav mode as well as direct status mode for port 0. the timing of this signal follows as that of ut-clav. this bus is not tri-statable. signal name: ut-utdo signal description: utopia transmit data output signal type: output access to the data prior to the transmit formatter. update d on the rising edge of tclk. this output is normally connected to tdata. signal name: ut-clk signal description: receive utopia clock signal type: input transmit utopia bus clock. downloaded from: http:///
ds2156 28 of 265 3.3 parallel control port pins signal name: in t signal description: interrupt signal type: output flags host controller during conditions and events defined in the status registers. active-low, open-drain output. signal name: tstrst signal description: tri-state control and device reset signal type: input a dual function pin. a 0-to-1 transition issues a hardware reset to the ds2156 register set. a reset clears all configuration registers. configuration register contents are set to 0. leaving tstrst high tri-states all output and i/o pins (including the parallel control port). set low for normal operation. useful in board-level testing. signal name: mux signal description: bus operation signal type: input set low to select nonmultiplexed bus operation. set high to select multiplexed bus operation. signal name: ad0 to ad7 signal description: data bus [d0 to d7] or address/data bus signal type: input/output in nonmultiplexed bus operation (mux = 0), these serve as th e data bus. in multiplexed bus operation (mux = 1), these pins serve as an 8-bit multiplexed address/data bus. signal name: a0 to a6 signal description: address bus signal type: input in nonmultiplexed bus operation (mux = 0), these ser ve as the address bus. in multiplexed bus operation (mux = 1), these pins are not used and should be connected low. signal name: bts signal description: bus type select signal type: input strap high to select motorola bus timing ; strap low to select intel bus timing. this pin controls the function of the rd ( ds ), ale (as), and wr (r/ w ) pins. if bts = 1, then these pins assume the function listed in parentheses (). signal name: rd ( ds ) signal description: read input, data strobe signal type: input rd and ds are active-low signals. ds active high when mux = 1. see bus timing diagrams . downloaded from: http:///
ds2156 29 of 265 signal name: cs signal description: chip select signal type: input must be low to read or write to the device. cs is an active-low signal. signal name: ale(as)/a7 signal description: address latch enable (address strobe) or a7 signal type: input in nonmultiplexed bus operation (mux = 0), serves as th e upper address bit. in multiplexed bus operation (mux = 1), serves to demultiplex the bus on a positive-going edge. signal name: wr (r/ w ) signal description: write input(read/write) signal type: input wr is an active-low signal. signal name: tusel signal description: tdm/utopia backplane select signal type: input low to enable tdm backplane. hi gh to enable utopia backplane. 3.4 extended system information bus signal name: esibs0 signal description: extended system information bus select 0 signal type: input/output used to group two to eight ds2156s into a bus-sharing mode for alarm and status reporting. see section 29 for more details. signal name: esibs1 signal description: extended system information bus select 1 signal type: input/output used to group two to eight ds2156s into a bus-sharing mode for alarm and status reporting. see section 29 for more details. signal name: esibrd signal description: extended system information bus read signal type: input/output used to group two to eight ds2156s into a bus-sharing mode for alarm and status reporting. see section 29 for more details. downloaded from: http:///
ds2156 30 of 265 3.5 user output port pins signal name: uop0 signal description: user output port 0 signal type: output this output port pin can be set low or high by the ccr4.0 control bit. this pin is forced low on power-up and after any device reset. signal name: uop1 signal description: user output port 1 signal type: output this output port pin can be set low or high by the ccr4.1 control bit. this pin is forced low on power-up and after any device reset. signal name: uop2 signal description: user output port 2 signal type: output this output port pin can be set low or high by the ccr4.2 control bit. this pin is forced low on power-up and after any device reset. signal name: uop3 signal description: user output port 3 signal type: output this output port pin can be set low or high by the ccr4.3 control bit. this pin is forced low on power-up and after any device reset. downloaded from: http:///
ds2156 31 of 265 3.6 jtag test access port pins signal name: jtrst signal description: ieee 1149.1 test reset signal type: input jtrst is used to asynchronously reset the test access por t controller. after power-up, jtrst must be toggled from low to high. this action sets the device into the jtag device id mode. normal device operation is restored by pulling jtrst low. jtrst is pulled high internally by a 10k ? resistor operation. signal name: jtms signal description: ieee 1149.1 test mode select signal type: input this pin is sampled on the rising edge of jtclk and is u sed to place the test access port into the various defined ieee 1149.1 states. this pin has a 10k ? pullup resistor. signal name: jtclk signal description: ieee 1149.1 test clock signal signal type: input this signal is used to shift data into jtdi on th e rising edge and out of jtdo on the falling edge. signal name: jtdi signal description: ieee 1149.1 test data input signal type: input test instructions and data are clocked into this pin on the rising edge of jtclk. this pin has a 10k ? pullup resistor. signal name: jtdo signal description: ieee 1149.1 test data output signal type: output test instructions and data are clocked out of this pin on the falling edge of jtclk. if not used, this pin should be left unconnected. downloaded from: http:///
ds2156 32 of 265 3.7 line interface pins signal name: mclk signal description: master clock input signal type: input a (50ppm) clock source is applied at this pin. this clock is used internally for both clock/data recovery and for the jitter attenuator for t1 and e1 modes. a quartz crystal of 2.048mhz can be applied across mclk and xtald instead of the clock source. the clock rate can be 16.384mhz, 8.192mhz, 4.096mhz, or 2.048mhz. when using the ds2156 in t1-only operation, a 1.544mhz (50ppm) clock source can be used. signal name: xtald signal description: quartz crystal driver signal type: output a quartz crystal of 2.048mhz (optional 1.544mhz in t1-only operation) can be applied across mclk and xtald instead of a clock source at mclk. leave open circuited if a clock source is applied at mclk. signal name: 8xclk signal description: eight times clock (8x) signal type: output an 8x clock that is locked to the recovered network clock provided from the clock/data recovery block (if the jitter attenuator is enabled on the receive side) or from the tclki pin (if the jitter attenuator is enabled on the transmit side). signal name: liuc signal description: line interface connect signal type: input connect low to separate the line interface circuitry from the framer/formatter circuitry and activate the tposi/tnegi/tclki/rposi/rnegi/rclki pins. connect hi gh to connect the line interface circuitry to the framer/formatter circuitry and deactivate the tposi/tne gi/tclki/rposi/rnegi/rclki pins. when liuc is connected high, the tposi/tnegi/tclki/rposi/r negi/rclki pins should be connected low. signal name: rtip and rring signal description: receive tip and ring signal type: input analog inputs for clock recovery circuitry. these pins connect through a 1:1 transformer to the network. see section 23 for details. signal name: ttip and tring signal description: transmit tip and ring signal type: output analog line driver outputs. these pins connect through a 1:2 step-up transformer to the network. see section 23 for details. downloaded from: http:///
ds2156 33 of 265 3.8 supply pins signal name: dvdd signal description: digital positive supply signal type: supply 3.3v 5%. should be connected to the rvdd and tvdd pins. signal name: rvdd signal description: receive analog positive supply signal type: supply 3.3v 5%. should be connected to the dvdd and tvdd pins. signal name: tvdd signal description: transmit analog positive supply signal type: supply 3.3v 5%. should be connected to the rvdd and dvdd pins. signal name: dvss signal description: digital signal ground signal type: supply should be connected to the rvss and tvss pins. signal name: rvss signal description: receive analog signal ground signal type: supply 0v. should be connected to dvss and tvss. signal name: tvss signal description: transmit analog signal ground signal type: supply 0v. should be connected to dvss and rvss. downloaded from: http:///
ds2156 34 of 265 3.9 l and g package pinout the ds2156 is available in either a 100-pin lqfp (l) or 10mm csbga, 0.8mm pitch (g) package. table 3-a. pin description sorted by pin number (tdm backplane enabled) bold entries indicate pins t hat have an alternate function when utopia bus interface is enabled. pin lqfp csbga symbol type function 1 a1 rchblk o receive channel block 2 b2 jtms i ieee 1149.1 test mode select 3 c3 bpclk o backplane clock 4 b1 jtclk i ieee 1149.1 test clock signal 5 d4 jtrst i ieee 1149.1 test reset 6 c2 rcl o receive carrier loss 7 c1 jtdi i ieee 1149.1 test data input 8 d3 uop0 o user output 0 9 d2 uop1 o user output 1 10 d1 jtdo o ieee 1149.1 test data output 11 e3 bts i bus type select 12 e2 liuc i line interface connect 13 e1 8xclk o eight times clock 14 e4 tstrst i test/reset 15 e5 uop2 o user output 2 16 f1 rtip i receive analog tip input 17 f2 rring i receive analog ring input 18 f3 rvdd receive an alog positive supply 19, 20, 24 f4, g1, j1 rvss receive analog signal ground 21 g2 mclk i master clock input 22 h1 xtald o quartz crystal driver 23 g3 uop3 o user output 3 25 h2 int o interrupt 26 k1 tusel backplane interface select 27, 28 j2, h3 n.c. reserved for factory test 29 k2 ttip o transmit analog tip output 30 g4 tvss C transmit analog signal ground 31 j3 tvdd C transmit analog positive supply 32 k3 tring o transmit analog ring output 33 h4 tchblk o transmit channel block 34 j4 tlclk o transmit link clock 35 k4 tlink i transmit link data 36 h5 esibs0 i/o extended system information bus 0 37 j5 tsync i/o transmit sync 38 k5 tposi i transmit positive-data input 39 g5 tnegi i transmit negative-data input 40 f5 tclki i transmit clock input 41 k6 tclko o transmit clock output 42 j6 tnego o transmit negative-data output 43 h6 tposo o transmit positive-data output 44, 61, 81, 83 k7, f8, b8, c7 dvdd digital positive supply 45, 60, 80, 84 g6, g10, d7, b7 dvss digital signal ground 46 j7 tclk i transmit clock 47 k8 tser i transmit serial data 48 h7 tsig i transmit signaling input downloaded from: http:///
ds2156 35 of 265 pin lqfp csbga symbol type function 49 k9 teso o transmit elastic store output 50 j8 tdata i transmit data 51 k10 tsysclk i transmit system clock 52 j9 tssync i transmit system sync 53 h8 tchclk o transmit channel clock 54 j10 esibs1 i/o extended system information bus 1 55 g7 mux i bus operation 56 h9 d0/ad0 i/o data bus bit0/address/data bus bit 0 57 h10 d1/ad1 i/o data bus bit1/address/data bus bit 1 58 g8 d2/ad2 i/o data bus bit 2/address/data bus 2 59 g9 d3/ad3 i/o data bus bit 3/address/data bus bit 3 62 f9 d4/ad4 i/o data bus bit4/address/data bus bit 4 63 f10 d5/ad5 i/o data bus bit 5/address/data bus bit 5 64 f7 d6/ad6 i/o data bus bit 6/address/data bus bit 6 65 f6 d7/ad7 i/o data bus bit 7/address/data bus bit 7 66 e10 a0 i address bus bit 0 67 e9 a1 i address bus bit 1 68 e8 a2 i address bus bit 2 69 d10 a3 i address bus bit 3 70 e7 a4 i address bus bit 4 71 d9 a5 i address bus bit 5 72 c10 a6 i address bus bit 6 73 d8 ale (as)/a7 i address latch enable/address bus bit 7 74 b10 rd ( ds ) i read input (data strobe) 75 c9 cs i chip select 76 a10 esibrd i/o extended system information bus read 77 b9 wr (r/ w ) i write input (read/write) 78 c8 rlink o receive link data 79 a9 rlclk o receive link clock 82 a8 rclk o receive clock 85 a7 rdata o receive data 86 c6 rposi i receive positive-data input 87 b6 rnegi i receive negative-data input 88 a6 rclki i receive clock input 89 d6 rclko o receive clock output 90 e6 rnego o receive negative-data output 91 a5 rposo o receive positive-data output 92 b5 rchclk o receive channel clock 93 c5 rsigf o receive signaling-freeze output 94 a4 rsig o receive signaling output 95 d5 rser o receive serial data 96 b4 rmsync o receive multiframe sync 97 a3 rfsync o receive frame sync 98 c4 rsync i/o receive sync 99 a2 rlos/lotc o receive loss-of-sync/loss-of-transmit clock 100 b3 rsysclk i receive system clock downloaded from: http:///
ds2156 36 of 265 table 3-b. pin description sorted by pin number (utopia backplane enabled) bold entries indicate pins t hat have an alternate function when the tdm bus interface is enabled. pin lqfp csbga symbol type description 1 a1 ur-soc o utopia receive start of cell 2 b2 jtms i ieee 1149.1 test mode select 3 c3 ur-enb i utopia receive enable 4 b1 jtclk i ieee 1149.1 test clock signal 5 d4 jtrst i ieee 1149.1 test reset 6 c2 rcl o receive carrier loss 7 c1 jtdi i ieee 1149.1 test data input 8 d3 ut-soc i utopia transmit start of cell 9 d2 ut-e nb i utopia transmit enable 10 d1 jtdo o ieee 1149.1 test data output 11 e3 bts i bus type select 12 e2 ut-clav o utopia transmit cell available 13 e1 8xclk o eight times clock 14 e4 tstrst i test/reset 15 e5 uop2 user output pin 2 16 f1 rtip i receive analog tip input 17 f2 rring i receive analog ring input 18 f3 rvdd receive an alog positive supply 19, 20, 24 f4, g1, j1 rvss receive analog signal ground 21 g2 mclk i master clock input 22 h1 xtald o quartz crystal driver 23 g3 ut-addr0 i utopia transmit address bus bit 0 25 h2 int o interrupt 26 k1 tusel i backplane interface select 27, 28 j2, h3 n.c. no connection. reserved for factory test 29 k2 ttip o transmit analog tip output 30 g4 tvss transmit analog signal ground 31 j3 tvdd transmit analog positive supply 32 k3 tring o transmit analog ring output 33 h4 ut-addr1 i utopia transmit address bus bit 1 34 j4 ut-addr2 i utopia transmit address bus bit 2 35 k4 ut-addr3 i utopia transmit address bus bit 3 36 h5 esibs0 i/o extended system information bus 0 37 j5 tsync i/o transmit sync 38 k5 ut-addr4 i utopia transmit address bus bit 4 39 g5 ut-data0 i utopia transmit data bus bit 0 40 f5 ut-data1 i utopia transmit data bus bit 1 41 k6 ut-data2 i utopia transmit data bus bit 2 42 j6 ut-data3 i utopia transmit data bus bit 3 43 h6 ut-data4 i utopia transmit data bus bit 4 44, 61, 81, 83 k7, f8, b8, c7 dvdd digital positive supply 45, 60, 80, 84 g6, g10, d7, b7 dvss digital signal ground 46 j7 tclk i transmit clock 47 k8 ut-data5 i utopia transmit data bus bit 5 48 h7 ut-data6 i utopia transmit data bus bit 6 downloaded from: http:///
ds2156 37 of 265 pin lqfp csbga symbol type description 49 k9 ut-utdo o utopia transmit data output 50 j8 tdata i transmit data 51 k10 ut-data7 i utopia transmit data bus bit 7 52 j9 ut-clk i utopia transmit clock 53 h8 ur-clk i utopia receive clock 54 j10 esibs1 i/o extended system information bus 1 55 g7 mux i bus operation 56 h9 d0/ad0 i/o data bus bit0/address/data bus bit 0 57 h10 d1/ad1 i/o data bus bit1/address/data bus bit 1 58 g8 d2/ad2 i/o data bus bit 2/address/data bus 2 59 g9 d3/ad3 i/o data bus bit 3/address/data bus bit 3 62 f9 d4/ad4 i/o data bus bit4/address/data bus bit 4 63 f10 d5/ad5 i/o data bus bit 5/address/data bus bit 5 64 f7 d6/ad6 i/o data bus bit 6/address/data bus bit 6 65 f6 d7/ad7 i/o data bus bit 7/address/data bus bit 7 66 e10 a0 i address bus bit 0 67 e9 a1 i address bus bit 1 68 e8 a2 i address bus bit 2 69 d10 a3 i address bus bit 3 70 e7 a4 i address bus bit 4 71 d9 a5 i address bus bit 5 72 c10 a6 i address bus bit 6 73 d8 ale (as)/a7 i address latch enable/address bus bit 7 74 b10 rd ( ds ) i read input (data strobe) 75 c9 cs i chip select 76 a10 esibrd i/o extended system information bus read 77 b9 wr (r/ w ) i write input (read/write) 78 c8 ur-data0 o utopia receive data bus bit 0 79 a9 ur-data1 o utopia receive data bus bit 1 82 a8 rclk o receive clock 85 a7 rdata o receive data 86 c6 ur-data2 o utopia receive data bus bit 2 87 b6 ur-data3 o utopia receive data bus bit 3 88 a6 ur-data4 o utopia receive data bus bit 4 89 d6 ur-data5 o utopia receive data bus bit 5 90 e6 ur-data6 o utopia receive data bus bit 6 91 a5 ur-data7 o utopia receive data bus bit 7 92 b5 ur-addr0 i utopia receive address bus bit 0 93 c5 ur-addr1 i utopia receive address bus bit 1 94 a4 ur-addr2 i utopia receive address bus bit 2 95 d5 ur-clav o utopia receive cell available 96 b4 ur-addr3 i utopia receive address bus bit 3 97 a3 ur-addr4 i utopia receive address bus bit 4 98 c4 rsync i/o receive sync 99 a2 rlos/lotc o receive loss-of-sync/loss-of-transmit clock 100 b3 ut-2clav o utopia transmit 2 cells available downloaded from: http:///
ds2156 38 of 265 3.10 10mm csbga pin configuration figure 3-1. 10mm csbga pin confi guration (tdm signals shown) 1 2 3 4 5 6 7 8 9 10 a rchblk rlos/ lotc rfsync rsig rposo rclki rdata rclk rlclk esibrd b jtclk jtms rsysclk rmsync rchclk rnegi dvss dvdd wr (r/ w ) rd ( ds ) c jtdi rcl bpclk rsync rsigf rposi dvdd rlink cs a6 d jtdo uop1 uop0 jtrst rser rclko dvss ale(as)/ a7 a5 a3 e 8xclk liuc bts tstrst uop2 rnego a4 a2 a1 a0 f rtip rring rvdd rvss tclki d7/ad7 d6/ad6 dvdd d4/ad4 d5/ad5 g rvss mclk uop3 tvss tnegi dvss mux d2/ad2 d3/ad3 dvss h xtald int n.c. tchblk esibs0 tposo tsig tchclk d0/ad0 d1/ad1 j rvss n.c. tvdd tlclk tsync tnego tclk tdata tssync esibs1 k tusel ttip tring tlink tposi tclko dvdd tser teso tsysclk top view downloaded from: http:///
ds2156 39 of 265 4. parallel port the sct is controlled by either a nonmultiplexed (mux = 0) or a multiplexed (mux = 1) bus through an external microcontroller or microprocessor. the sct can operate with either intel or motorola bus timing configurations. if the bts pin is connected low, intel ti ming is selected; if c onnected high, motorola timing is selected. all motorola bus signals are lis ted in parentheses (). s ee the timing diagrams in ac electrical characteristics in section 36 for more details. 4.1 register map table 4-a. register map sorted by address address xxh r/w register name symbol page 00 r/w master mode register mstrreg 49 01 r/w i/o configuration register 1 iocr1 76 02 r/w i/o configuration register 2 iocr2 77 03 r/w t1 receive control register 1 t1rcr1 53 04 r/w t1 receive control register 2 t1rcr2 54 05 r/w t1 transmit control register 1 t1tcr1 55 06 r/w t1 transmit control register 2 t1tcr2 56 07 r/w t1 common control register 1 t1ccr1 57 08 r/w software signaling insertion enable 1 ssie1 100 09 r/w software signaling insertion enable 2 ssie2 100 0a r/w software signaling insertion enable 3 ssie3 101 0b r/w software signaling insertion enable 4 ssie4 101 0c r/w t1 receive digital milliwatt enable register 1 t1rdmr1 59 0d r/w t1 receive digital milliwatt enable register 2 t1rdmr2 59 0e r/w t1 receive digital milliwatt enable register 3 t1rdmr3 59 0f r device identification register idr 70 10 r/w information register 1 info1 60 11 r information register 2 info2 158 12 r/w information register 3 info3 67 13 14 r interrupt information register 1 iir1 51 15 r interrupt information register 2 iir2 51 16 r/w status register 1 sr1 159 17 r/w interrupt mask register 1 imr1 160 18 r/w status register 2 sr2 70 19 r/w interrupt mask register 2 imr2 71 1a r/w status register 3 sr3 72 1b r/w interrupt mask register 3 imr3 73 1c r/w status register 4 sr4 74 1d r/w interrupt mask register 4 imr4 75 1e r/w status register 5 sr5 113 1f r/w interrupt mask register 5 imr5 113 20 r/w status register 6 sr6 142 21 r/w interrupt mask register 6 imr6 143 22 r/w status register 7 sr7 142 23 r/w interrupt mask register 7 imr7 143 24 r/w status register 8 sr8 119 downloaded from: http:///
ds2156 40 of 265 address xxh r/w register name symbol page 25 r/w interrupt mask register 8 imr8 119 26 r/w status register 9 sr9 205 27 r/w interrupt mask register 9 imr9 206 28 r/w per-channel pointer register pcpr 46 29 w per-channel data register 1 pcdr1 47 2a w per-channel data register 2 pcdr2 47 2b w per-channel data register 3 pcdr3 47 2c w per-channel data register 4 pcdr4 47 2d r/w information register 4 info4 144 2e r information register 5 info5 144 2f r information register 6 info6 144 30 r information register 7 info7 67 31 r/w hdlc #1 receive control h1rc 136 32 r/w hdlc #2 receive control h2rc 136 33 r/w e1 receive control register 1 e1rcr1 62 34 r/w e1 receive control register 2 e1rcr2 63 35 r/w e1 transmit control register 1 e1tcr1 64 36 r/w e1 transmit control register 2 e1tcr2 65 37 r/w boc control register bocc 118 38 r/w receive signaling change-of-s tate information 1 rsinfo1 95 39 r/w receive signaling change-of-s tate information 2 rsinfo2 95 3a r/w receive signaling change-o f-state information 3 rsinfo3 95 3b r/w receive signaling change-o f-state information 4 rsinfo4 95 3c r/w receive signaling change-of-state interrupt enable 1 rscse1 95 3d r/w receive signaling change-of-state interrupt enable 2 rscse2 95 3e r/w receive signaling change-of-state interrupt enable 3 rscse3 95 3f r/w receive signaling change-of-state interrupt enable 4 rscse4 95 40 r/w signaling control register sigcr 92 41 r/w error count configuration register ercnt 82 42 r line-code violation count register 1 lcvcr1 84 43 r line-code violation count register 2 lcvcr2 84 44 r path code violation count register 1 pcvcr1 85 45 r path code violation count register 2 pcvcr2 85 46 r frames out-of-sync count register 1 foscr1 86 47 r frames out-of-sync count register 2 foscr2 86 48 r e-bit count register 1 ebcr1 87 49 r e-bit count register 2 ebcr2 87 4a r/w loopback control register lbcr 78 4b r/w per-channel loopback enable register 1 pclr1 80 4c r/w per-channel loopback enable register 2 pclr2 80 4d r/w per-channel loopback enable register 3 pclr3 81 4e r/w per-channel loopback enable register 4 pclr4 81 4f r/w elastic store control register escr 112 50 r/w transmit signaling register 1 ts1 98 51 r/w transmit signaling register 2 ts2 98 52 r/w transmit signaling register 3 ts3 98 53 r/w transmit signaling register 4 ts4 98 downloaded from: http:///
ds2156 41 of 265 address xxh r/w register name symbol page 54 r/w transmit signaling register 5 ts5 98 55 r/w transmit signaling register 6 ts6 98 56 r/w transmit signaling register 7 ts7 98 57 r/w transmit signaling register 8 ts8 98 58 r/w transmit signaling register 9 ts9 98 59 r/w transmit signaling register 10 ts10 98 5a r/w transmit signaling register 11 ts11 98 5b r/w transmit signaling register 12 ts12 98 5c r/w transmit signaling register 13 ts13 98 5d r/w transmit signaling register 14 ts14 98 5e r/w transmit signaling register 15 ts15 98 5f r/w transmit signaling register 16 ts16 98 60 r receive signaling register 1 rs1 93 61 r receive signaling register 2 rs2 93 62 r receive signaling register 3 rs3 93 63 r receive signaling register 4 rs4 93 64 r receive signaling register 5 rs5 93 65 r receive signaling register 6 rs6 93 66 r receive signaling register 7 rs7 93 67 r receive signaling register 8 rs8 93 68 r receive signaling register 9 rs9 93 69 r receive signaling register 10 rs10 93 6a r receive signaling register 11 rs11 93 6b r receive signaling register 12 rs12 93 6c r receive signaling register 13 rs13 93 6d r receive signaling register 14 rs14 93 6e r receive signaling register 15 rs15 93 6f r receive signaling register 16 rs16 93 70 r/w common control register 1 ccr1 69 71 r/w common control register 2 ccr2 222 72 r/w common control register 3 ccr3 223 73 r/w common control register 4 ccr4 224 74 r/w transmit channel monitor select tds0sel 88 75 r transmit ds0 monitor register tds0m 88 76 r/w receive channel monitor select rds0sel 89 77 r receive ds0 monitor register rds0m 89 78 r/w line interface control 1 lic1 154 79 r/w line interface control 2 lic2 155 7a r/w line interface control 3 lic3 156 7b r/w line interface control 4 lic4 157 7c 7d 7e w idle array address register iaar 105 7f r/w per-channel idle code value register pcicr 105 80 r/w transmit idle code enable register 1 tcice1 106 81 r/w transmit idle code enable register 2 tcice2 106 82 r/w transmit idle code enable register 3 tcice3 106 downloaded from: http:///
ds2156 42 of 265 address xxh r/w register name symbol page 83 r/w transmit idle code enable register 4 tcice4 106 84 r/w receive idle code enable register 1 rcice1 107 85 r/w receive idle code enable register 2 rcice2 107 86 r/w receive idle code enable register 3 rcice3 107 87 r/w receive idle code enable register 4 rcice4 107 88 r/w receive channel blocking register 1 rcbr1 108 89 r/w receive channel blocking register 2 rcbr2 108 8a r/w receive channel blocking register 3 rcbr3 109 8b r/w receive channel blocking register 4 rcbr4 109 8c r/w transmit channel blocking register 1 tcbr1 110 8d r/w transmit channel blocking register 2 tcbr2 110 8e r/w transmit channel blocking register 3 tcbr3 110 8f r/w transmit channel blocking register 4 tcbr4 110 90 r/w hdlc #1 transmit control h1tc 135 91 r/w hdlc #1 fifo control h1fc 137 92 r/w hdlc #1 receive channel select 1 h1rcs1 138 93 r/w hdlc #1 receive channel select 2 h1rcs2 138 94 r/w hdlc #1 receive channel select 3 h1rcs3 138 95 r/w hdlc #1 receive channel select 4 h1rcs4 138 96 r/w hdlc #1 receive time slot bits/sa bits select h1rtsbs 139 97 r/w hdlc #1 transmit channel select1 h1tcs1 140 98 r/w hdlc #1 transmit channel select2 h1tcs2 140 99 r/w hdlc #1 transmit channel select3 h1tcs3 140 9a r/w hdlc #1 transmit channel select4 h1tcs4 140 9b r/w hdlc #1 transmit time slot bits/sa bits select h1ttsbs 141 9c r hdlc #1 receive packet bytes available h1rpba 145 9d w hdlc #1 transmit fifo h1tf 146 9e r hdlc #1 receive fifo h1rf 146 9f r hdlc #1 transmit fifo buffer available h1tfba 145 a0 r/w hdlc #2 transmit control h2tc 135 a1 r/w hdlc #2 fifo control h2fc 137 a2 r/w hdlc #2 receive channel select 1 h2rcs1 138 a3 r/w hdlc #2 receive channel select 2 h2rcs2 138 a4 r/w hdlc #2 receive channel select 3 h2rcs3 138 a5 r/w hdlc #2 receive channel select 4 h2rcs4 138 a6 r/w hdlc #2 receive time slot bits/sa bits select h2rtsbs 139 a7 r/w hdlc #2 transmit channel select1 h2tcs1 140 a8 r/w hdlc #2 transmit channel select2 h2tcs2 140 a9 r/w hdlc #2 transmit channel select3 h2tcs3 140 aa r/w hdlc #2 transmit channel select4 h2tcs4 140 ab r/w hdlc #2 transmit time slot bits/sa bits select h2ttsbs 141 ac r hdlc #2 receive packet bytes available h2rpba 145 ad w hdlc #2 transmit fifo h2tf 146 ae r hdlc #2 receive fifo h2rf 146 af r hdlc #2 transmit fifo buffer available h2tfba 145 b0 r/w extend system information bus control register 1 esibcr1 219 b1 r/w extend system information bus control register 2 esibcr2 220 downloaded from: http:///
ds2156 43 of 265 address xxh r/w register name symbol page b2 r extend system information bus register 1 esib1 221 b3 r extend system information bus register 2 esib2 221 b4 r extend system information bus register 3 esib3 221 b5 r extend system information bus register 4 esib4 221 b6 r/w in-band code control register ibcc 195 b7 r/w transmit code definition register 1 tcd1 196 b8 r/w transmit code definition register 2 tcd2 196 b9 r/w receive up code definition register 1 rupcd1 197 ba r/w receive up code definition register 2 rupcd2 197 bb r/w receive down code definition register 1 rdncd1 198 bc r/w receive down code definition register 2 rdncd2 198 bd r/w in-band receive spare control register rscc 199 be r/w receive spare code definition register 1 rscd1 200 bf r/w receive spare code definition register 2 rscd2 200 c0 r receive fdl register rfdl 148 c1 r/w transmit fdl register tfdl 149 c2 r/w receive fdl match register 1 rfdlm1 148 c3 r/w receive fdl match register 2 rfdlm2 148 c4 c5 r/w interleave bus operation control register iboc 216 c6 r receive align frame register raf 121 c7 r receive nonalign frame register rnaf 121 c8 r receive si align frame rsiaf 123 c9 r receive si nonalign frame rsinaf 124 ca r receive remote alarm bits rra 124 cb r receive sa4 bits rsa4 125 cc r receive sa5 bits rsa5 125 cd r receive sa6 bits rsa6 126 ce r receive sa7 bits rsa7 126 cf r receive sa8 bits rsa8 127 d0 r/w transmit align frame register taf 122 d1 r/w transmit nonalign frame register tnaf 122 d2 r/w transmit si align frame tsiaf 127 d3 r/w transmit si nonalign frame tsinaf 128 d4 r/w transmit remote alarm bits tra 128 d5 r/w transmit sa4 bits tsa4 129 d6 r/w transmit sa5 bits tsa5 129 d7 r/w transmit sa6 bits tsa6 130 d8 r/w transmit sa7 bits tsa7 130 d9 r/w transmit sa8 bits tsa8 131 da r/w transmit sa bit control register tsacr 132 db r/w bert alternating word count rate bawc 206 dc r/w bert repetitive pattern set register 1 brp1 207 dd r/w bert repetitive pattern set register 2 brp2 207 de r/w bert repetitive pattern set register 3 brp3 207 df r/w bert repetitive pattern set register 4 brp4 207 e0 r/w bert control register 1 bc1 203 downloaded from: http:///
ds2156 44 of 265 address xxh r/w register name symbol page e1 r/w bert control register 2 bc2 204 e2 e3 r bert bit count register 1 bbc1 208 e4 r bert bit count register 2 bbc2 208 e5 r bert bit count register 3 bbc3 208 e6 r bert bit count register 4 bbc4 208 e7 r bert error count register 1 bec1 209 e8 r bert error count register 2 bec2 209 e9 r bert error count register 3 bec3 209 ea r/w bert interface control register bic 210 eb r/w error rate control register erc 212 ec r/w number-of-errors 1 noe1 213 ed r/w number-of-errors 2 noe2 213 ee r number-of-errors left 1 noel1 214 ef r number-of-errors left 2 noel2 214 f0 * test register test f1Cf9 * test register test faCff * test register test *test1 to test16 registers are used only by the factory. downloaded from: http:///
ds2156 45 of 265 4.2 utopia bus registers when the utopia bus is enabled, register space 50hC6a is mapped to the utopia function. table 4-b. utopia register map address xxh r/w register symbol page 50 r/w transmit configuration register u_tcfr 182 51 r/w transmit pmon counter-latch enable register u_tpcle 183 52 w transmit assigned cell counter msb u_tacc1 183 53 r transmit assigned cell counter lsb u_tacc2 183 54 r transmit idle/unassigned payload byte u_tiupb 184 55 r/w transmit hec error-insertion pattern u_thepr 184 56 r/w transmit control register 1 u_tcr1 185 57 r/w transmit control register 2 u_tcr2 186 58, 59, 5aC5f reserved 60 r/w receive configuration register u_rcfr 186 61 r/w receive lcd integration period register u_rlcdip 187 62 r/w receive pmon counter-latch enable register u_rpce 187 63 w receive correctable hec latch register u_rchec 188 64 r receive uncorrectable hec msb u_ruhec1 188 65 r receive uncorrectable hec lsb u_ruhec2 188 66 r receive assigned cell counter msb u_racc1 189 67 r receive assigned cell counter lsb u_racc2 189 68 r receive status register u_rsr 190 69 r receive control register 1 u_rcr1 191 6a r/w receive control register 2 u_rcr2 192 6bC6f reserved downloaded from: http:///
ds2156 46 of 265 5. special per-channel register operation some of the features described in the data sheet that operate on a pe r-channel basis use a special method for channel selection. there are five registers invol ved: per-channel pointer register (pcpr) and per- channel data registers 1C4 (pcdr1C4). the user selects which function or functions are to be applied on a per-channel basis by setting the appropria te bit(s) in the pcpr register. the user then writes to the pcdr registers to select the channels for that function. the following is an example of mapping the transmit and receive bert function to channels 9C12, 20, and 21. write 11h to pcpr write 00h to pcdr1 write 0fh to pcdr2 write 18h to pcdr3 write 00h to pcdr4 the user may write to the pcdr1-4 with muliple func tions in the pcpr register selected, but can only read the values from the pcdr1-4 registers for a si ngle function at a time. more information about how to use these per-channel features can be found in their respective sections in the data sheet. register name: pcpr register description: per-channel pointer register register address: 28h bit # 7 6 5 4 3 2 1 0 name rsaoics rsrcs rfcs brcs thscs peics tfcs btcs default 0 0 0 0 0 0 0 0 bit 0/bert transmit channel select (btcs) bit 1/transmit fractional channel select (tfcs) bit 2/payload error insert channel select (peics) bit 3/transmit hardware signaling channel select (thscs) bit 4/bert receive channel select (brcs) bit 5/receive fractional channel select (rfcs) bit 6/receive signaling reinsertion channel select (rsrcs) bit 7/receive signaling all-ones insertion channel select (rsaoics) downloaded from: http:///
ds2156 47 of 265 register name: pcdr1 register description: per-channel data register 1 register address: 29h bit # 7 6 5 4 3 2 1 0 name default ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 register name: pcdr2 register description: per-channel data register 2 register address: 2ah bit # 7 6 5 4 3 2 1 0 name default ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 register name: pcdr3 register description: per-channel data register 3 register address: 2bh bit # 7 6 5 4 3 2 1 0 name default ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 register name: pcdr4 register description: per-channel data register 4 register address: 2ch bit # 7 6 5 4 3 2 1 0 name default ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 downloaded from: http:///
ds2156 48 of 265 6. programming model the ds2156 register map is divided into three groups : t1 specific features, e1 specific features, and common features. the typical programming sequence begi ns with issuing a rese t to the ds2156, selecting t1 or e1 operation in the master mode register, enabling t1 or e1 functions and enabling the common functions. the act of resetting th e ds2156 automatically clears all conf iguration and stat us registers. therefore, it is not necessary to load unused registers with 0s. figure 6-1. programming sequence power-on issue reset select t1 or e1 operation in master mode register program t1 specific registers program e1 specific registers program common registers ds2156 operational downloaded from: http:///
ds2156 49 of 265 6.1 power-up sequence the ds2156 contains an on-chip power-up reset function that automatically clears the writeable register space immediately after power is supplied to the ds2156. the user can issue a chip reset at any time. issuing a reset disrupts traffic flowing through the ds2156 until the de vice is reprogrammed. the reset can be issued through hardware using the tstrst pi n or through software using the sftrst function in the master mode register. the lirst (lic2.6) should be toggled from 0 to 1 to reset the line interface circuitry. (it takes the ds2156 about 40 ms to recover from the lirst bit being toggled.) finally, after the tsysclk and rsysclk inputs are stable, the receive and transmit elastic stores should be reset (this step can be skipped if the elastic stores are disabled). 6.1.1 master mode register register name: mstrreg register description: master mode register register address: 00h bit # 7 6 5 4 3 2 1 0 name urst test1 test0 t1/e1 sftrst default 0 0 0 0 0 0 0 0 bit 0/software-issued reset (sftrst). a 0-to-1 transition causes the register space in the ds2156 to be cleared. a reset clears all configuration and status registers. the b it automatically clears itself wh en the reset has completed. bit 1/ds2156 operating mode (t1/e1). used to select the operating mode of the framer/formatter (digital) portion of the 2156. the operating mode of the liu must also be programmed. 0 = t1 operation 1 = e1 operation bits 2, 3/test mode bits (test0, test1). test modes are used to force the output pins of the ds2156 into known states. this can facilitate the checkout of assemblie s during the manufacturing process and also be used to isolate devices from shared buses. test1 test0 effect on output pins 0 0 operate normally 0 1 force all output pins into tri-state (i ncluding all i/o pins and parallel port pins) 1 0 force all output pins low (including all i/o pins except parallel port pins) 1 1 force all output pins high (including all i/o pins except parallel port pins) bit 4/utopia reset (urst). a 0-to-1 transition causes the utopia interface to reset. bits 5 to 7/unused, must be set to 0 for proper operation downloaded from: http:///
ds2156 50 of 265 6.2 interrupt handling various alarms, conditions, and events in the ds2156 can cause interrupts. for simplicity, these are all referred to as events in this e xplanation. all status registers can be programmed to produce interrupts. each status register has an associat ed interrupt mask register. for exampl e, sr1 (status register 1) has an interrupt control register called imr1 (interrupt mask register 1). status regist ers are the only sources of interrupts in the ds2156. on power-up, all writeable regi sters are automatically cl eared. since bits in the imrx registers have to be set = 1 to allow a particul ar event to cause an inte rrupt, no interrupts can occur until the host selects which events ar e to product interrupts. since ther e are potentially many sources of interrupts on the ds2156, several features are availabl e to help sort out and identify which event is causing an interrupt. when an interrupt occurs, the host should first read the iir1 and iir2 registers (interrupt information registers) to identify which stat us register (or registers) is producing the interrupt. once that is determined, the individual status register or registers can be examined to determine the exact source. in multiple port configurati ons, two to eight ds2156s can be c onnected together by the 3-wire esib feature. this allows multiple ds2156s to be interrogated by a sing le cpu port read cycle. the host can determine the synchronization status , or interrupt status of up to ei ght devices with a single read. the esib feature also allows the user to select from various events to be examined through this method. for more information, see section 29. the u_rsr register in the utopia sections works sligh tly different than all other status registers. only two of the bits in this register are capable of generating interrupts, u_rsr.0 and u_rsr.1. these two bits, unlike the other status register bits, are on ly set if the corresponding mask bits u_rcr2.3 and u_rcr2.4 are set. once an interrupt has occurred, the interrupt handler routin e should set the intdis bit (ccr3.6) to stop further activity on the interrupt pin. after all interrupt s have been determined a nd processed, the interrupt hander routine should re-enable interr upts by setting the intdis bit = 0. 6.3 status registers when a particular event or condition has occurred (o r is still occurring in the case of conditions), the appropriate bit in a status register is set to a 1. all of the status registers operate in a latched fashion. this means that if an event or condition occurs a bit is set to a 1. it remains set until th e user reads that bit. an event bit is cleared when it is read and it is not set again until the even t has occurred again. condition bits such as rbl, rlos, etc., remain set if the alarm is still present. the user always proceeds a read of any of the status registers with a wr ite. the byte written to the register informs the ds2156 which bits the user wishes to read and have cleared. the user writes a byte to one of these registers, with a 1 in the bit positions the user wishes to read and a 0 in the bit positions the user does not wish to obtain the latest in formation on. when a 1 is written to a bit location, the re ad register is updated with the latest information. when a 0 is written to a bit position, the read register is not updated and the previous value is held. a write to the status registers is immediately followed by a read of the same register. this write-read scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register . this operation is key in controlling the ds2156 with higher order languages. status register bits are divided into two groups, condi tion bits and event bits. condition bits are typically network conditions such as loss-of-s ync or all-ones detect. event bits are typically markers such as the one-second timer, elastic store slip, etc. each status re gister bit is labeled as a condition or event bit. some of the status registers have bits for both th e detection of a condition and the clearance of the downloaded from: http:///
ds2156 51 of 265 condition. for example, sr2 has a bit that is set wh en the device goes into a loss-of-sync state (sr2.0, a condition bit) and a bit that is set (sr2.4, an event bi t) when the loss-of-sync condition clears (goes in sync). some of the status register bits (condition bits) do not have a se parate bit for th e condition clear event but rather the stat us bit can produce interrupts on both edge s, setting and clearing. these bits are marked as double interrupt bits. an interrupt is produced when the cond ition occurs and when it clears. 6.4 information registers information registers operate the same as status registers except they cannot cause interrupts. they are all latched except for info7 and some of the bits in info5 and info6. info7 re gister is a read-only register. it reports th e status of the e1 synchroni zer in real time. info7 and some of the bits in info6 and info5 are not latched and it is not necessary to precede a read of these bits with a write. 6.5 interrupt information registers the interrupt information registers provide an indicat ion of which status regist ers (sr1 through sr9) are generating an interrupt. when an interrupt occurs, the host can read iir1 and iir2 to quickly identify which of the nine status regi sters are causing the interrupt. register name: iir1 register description: interrupt information register 1 register address: 14h bit # 7 6 5 4 3 2 1 0 name sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 default 0 0 0 0 0 0 0 0 register name: iir2 register description: interrupt information register 2 register address: 15h bit # 7 6 5 4 3 2 1 0 name u_rsr sr9 default 0 0 0 0 0 0 0 0 downloaded from: http:///
ds2156 52 of 265 7. clock map figure 7-1 shows the clock map of the ds2156. the rou ting for the transmit and receive clocks are shown for the various loopback modes and j itter attenuator positions. although there is only one jitter attenuator, which can be placed in the receive or transmit pa th, two are shown for simplification and clarity. figure 7-1. clock map (tdm mode) the tclk mux is dependent on the state of the tcss0 and tcss1 bits in the lic1 register and the state of the tclk pin. tcss1 tcss0 transmit clock source 0 0 the tclk pin (c) is always the source of transmit clock. 0 1 switch to the recovered clock (b) when the signal at the tclk pin fails to transition after one channel time. 1 0 use the scaled signal (a) derived from mclk as the transmit clock. the tclk pin is ignored. 1 1 use the recovered clock (b) as the transmit clock. the tclk pin is ignored. transmit formatter receive framer bpclk synth remote loopback framer loopback payload loopback (see notes) ltca ltca jitter attenuator see lic1 register local loopback bpclk rclk tclk mclk rxclk txclk to liu llb = 0 llb = 1 plb = 0 plb = 1 rlb = 1 rlb = 0 flb = 1 flb = 0 jas = 0 and dja = 0 jas = 1 or dja = 1 jas = 0 or dja = 1 jas = 1 and dja = 0 rcl = 1 rcl = 0 dja = 1 dja = 0 8xclk 8 x pll pre-scaler lic4.mps0 lic4.mps1 lic2.3 2.048 to 1.544 synthesizer b a c mclks = 0 tsysclk mclks = 1 tclk mux downloaded from: http:///
ds2156 53 of 265 8. t1 framer/formatter co ntrol and status registers the t1 framer portion of the ds2156 is configured thr ough a set of nine control registers. typically, the control registers are only accessed when the syst em is first powered up. once the ds2156 has been initialized, the control registers only need to be accessed when there is a change in the system configuration. there are two receive control regi sters (t1rcr1 and t1rcr2), two transmit control registers (t1tcr1 and t1tcr2), and a common control register (t1ccr1). each of these registers is described in this section. 8.1 t1 control registers register name: t1rcr1 register description: t1 receive control register 1 register address: 03h bit # 7 6 5 4 3 2 1 0 name arc oof1 oof2 syncc synct synce resync default 0 0 0 0 0 0 0 0 bit 0/resynchronize (resync). when toggled from low to high, a resynchronization of the receive-side framer is initiated. must be cleared and set again for a subsequent resync. bit 1/sync enable (synce) 0 = auto resync enabled 1 = auto resync disabled bit 2/sync time (synct) 0 = qualify 10 bits 1 = qualify 24 bits bit 3/sync criteria (syncc) in d4 framing mode: 0 = search for ft pattern, then search for fs pattern 1 = cross couple ft and fs pattern in esf framing mode: 0 = search for fps pattern only 1 = search for fps and verify with crc6 bits 4, 5/out-of-frame select bits (oof2, oof1) oof2 oof1 out-of-frame criteria 0 0 2/4 frame bits in error 0 1 2/5 frame bits in error 1 0 2/6 frame bits in error 1 1 2/6 frame bits in error bit 6/auto resync criteria (arc) 0 = resync on oof or rcl event 1 = resync on oof only bit 7/unused, must be set to 0 for proper operation downloaded from: http:///
ds2156 54 of 265 register name: t1rcr2 register description: t1 receive control register 2 register address: 04h bit # 7 6 5 4 3 2 1 0 name rfm rb8zs rslc96 rzse rzbtsi rjc rd4ym default 0 0 0 0 0 0 0 0 bit 0/receive-side d4 yellow alarm select (rd4ym) 0 = 0s in bit 2 of all channels 1 = a 1 in the s-bit position of frame 12 (j1 yellow alarm mode) bit 1/receive japanese crc6 enable (rjc) 0 = use ansi/at&t/itu crc6 calculation (normal operation) 1 = use japanese standard jtCg704 crc6 calculation bit 2/receive-side zbtsi support enable (rzbtsi). allows zbtsi information to be output on rlink pin. 0 = zbtsi disabled 1 = zbtsi enabled bit 3/receive fdl zero-destuffer enable (rzse). set this bit to 0 if using the internal hdlc/boc controller instead of the legacy support for th e fdl. see section 22.5 for details. 0 = zero destuffer disabled 1 = zero destuffer enabled bit 4/receive slc-96 enable (rslc96). only set this bit to a 1 in d4/slc-96 framing applications. see section 22.6 for details. 0 = slc-96 disabled 1 = slc-96 enabled bit 5/receive b8zs enable (rb8zs) 0 = b8zs disabled 1 = b8zs enabled bit 6/receive frame mode select (rfm) 0 = d4 framing mode 1 = esf framing mode bit 7/unused, must be set to 0 for proper operation downloaded from: http:///
ds2156 55 of 265 register name: t1tcr1 register description: t1 transmit control register 1 register address: 05h bit # 7 6 5 4 3 2 1 0 name tjc tfpt tcpt tsse gb7s tfdls tbl tyel default 0 0 0 0 0 0 0 0 bit 0/transmit yellow alarm (tyel) 0 = do not transmit yellow alarm 1 = transmit yellow alarm bit 1/transmit blue alarm (tbl) 0 = transmit data normally 1 = transmit an unframed all-ones code at tpos and tneg bit 2/tfdl register select (tfdls) 0 = source fdl or fs-bits from the internal tfdl register (legacy fdl support mode) 1 = source fdl or fs-bits from the internal hdlc controller or the tlink pin bit 3/global bit 7 stuffing (gb7s) 0 = allow the ssiex registers to determine which cha nnels containing all 0s are to be bit 7 stuffed 1 = force bit 7 stuffing in all 0-byte channels re gardless of how the ssiex registers are programmed bit 4/transmit software signaling enable (tsse). 0 = do not source signaling data from the tsx register s regardless of the ssiex registers. the ssiex registers still define which cha nnels are to have b7 stuffing preformed. 1 = source signaling data as enabled by the ssiex registers bit 5/transmit crc pass-through (tcpt) 0 = source crc6 bits internally 1 = crc6 bits sampled at tser during f-bit time bit 6/transmit f-bit pass-through (tfpt) 0 = f bits sourced internally 1 = f bits sampled at tser bit 7/transmit japanese crc6 enable (tjc) 0 = use ansi/at&t/itu crc6 calculation (normal operation) 1 = use japanese standard jtCg704 crc6 calculation downloaded from: http:///
ds2156 56 of 265 register name: t1tcr2 register description: t1 transmit control register 2 register address: 06h bit # 7 6 5 4 3 2 1 0 name tb8zs tslc96 tzse fbct2 fbct1 td4ym tzbtsi tb7zs default 0 0 0 0 0 0 0 0 bit 0/transmit-side bit 7 zero-suppression enable (tb7zs) 0 = no stuffing occurs 1 = bit 7 forced to a 1 in channels with all 0s bit 1/transmit-side zbtsi support enable (tzbtsi). allows zbtsi information to be input on tlink pin. 0 = zbtsi disabled 1 = zbtsi enabled bit 2/transmit-side d4 yellow alarm select (td4ym) 0 = 0s in bit 2 of all channels 1 = a 1 in the s-bit position of frame 12 bit 3/f-bit corruption type 1 (fbct1). a low-to-high transition of this bit causes the next three consecutive ft (d4 framing mode) or fps (esf framing mode) bits to be co rrupted causing the remote end to experience a loss of synchronization. bit 4/f-bit corruption type 2 (fbct2). setting this bit high enables the corruption of one ft (d4 framing mode) or fps (esf framing mode) bit in every 128 ft or fps bits as long as the bit remains set. bit 5/transmit fdl zero-stuffer enable (tzse). set this bit to 0 if using the internal hdlc controller instead of the legacy support for the fdl. see section 15 for details. 0 = zero stuffer disabled 1 = zero stuffer enabled bit 6/transmit slc-96/fs-bit insertion enable (tslc96). only set this bit to a 1 in d4 framing applications. must be set to 1 to source the fs pattern from the tfdl register. see section 22.6 for details. 0 = slc-96/fs-bit insertion disabled 1 = slc-96/fs-bit insertion enabled bit 7/transmit b8zs enable (tb8zs) 0 = b8zs disabled 1 = b8zs enabled downloaded from: http:///
ds2156 57 of 265 register name: t1ccr1 register description: t1 common control register 1 register address: 07h bit # 7 6 5 4 3 2 1 0 name trai-ci tais-ci tfm pde tloop default 0 0 0 0 0 0 0 0 bit 0/transmit loop-code enable (tloop). see section 25 for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in registers tcd1 and tcd2 bit 1/pulse density enforcer enable (pde). the framer always examines the transmit and receive data streams for violations of these, which are required by ansi t1.403: no more than 15 consecutive 0s and at least n 1s in each and every time window of 8 x (n + 1) bits, where n = 1 through 23. violations for the transmit and receive data streams are reported in the info1.6 and info1.7 bits , respectively. when this bit is set to 1, the ds2156 forces the transmitted stream to meet this requirement no matter the content of the transmitted stream. when running b8zs, this bit should be set to 0 since b8zs encoded data streams cannot violate the pulse density requirements. 0 = disable transmit pulse density enforcer 1 = enable transmit pulse density enforcer bit 2/transmit frame mode select (tfm) 0 = d4 framing mode 1 = esf framing mode bit 3/transmit ais-ci enable (tais-ci). setting this bit and the tbl bit (t1tcr1.1) causes the ais-ci code to be transmitted at tposo and tnego, as defined in ansi t1.403. 0 = do not transmit the ais-ci code 1 = transmit the ais-ci code (t1tcr1.1 must also be set = 1) bit 4/transmit rai-ci enable (trai-ci). setting this bit causes the esf rai-ci code to be transmitted in the fdl bit position. 0 = do not transmit the esf rai-ci code 1 = transmit the esf rai-ci code bits 5 to 7/unused, must be set to 0 for proper operation downloaded from: http:///
ds2156 58 of 265 8.2 t1 transmit transparency the software signaling insertion-enab le registers, ssie1Cssie4, can be used to select signaling insertion from the transmit signaling registers, ts1Cts12, on a per-channel basis. setting a bit in the ssiex register allows signaling data to be sourced from the signaling registers for that channel. in transparent mode, bit 7 stuffing and/or robbed-bit signaling is prevented from overwriting the data in the channels. if a ds0 is programmed to be clear, no robbed-bit signaling is inserted nor does the channel have bit 7 stuffing performed. however, in the d4 framing mode, bit 2 is ove rwritten by a 0 when a yellow alarm is transmitted. also, the user has the opt ion to globally override the ssiex registers from determining which channels are to have bit 7 stuffing performed. if the t1tcr1.3 and t1tcr2.0 bits are set to 1, then all 24 t1 channels have bit 7 stuffi ng performed on them, regardless of how the ssiex registers are programmed. in this manner, the ssiex re gisters are only affecting the channels that are to have robbed-bit signaling inserted into them. 8.3 ais-ci and rai-ci generation and detection the ds2156 can transmit and detect the rai-ci a nd ais-ci codes in t1 mode. these codes are compatible with and do not interfere with the standa rd rai (yellow) and ais (blue) alarms. these codes are defined in ansi t1.403. the ais-ci code (alarm indicatio n signal-customer installation) is the same for both esf and d4 operation. setting the tais-ci bit in the t1ccr1 regist er and the tbl bit in th e t1tcr1 register causes the ds2156 to transmit the ais-ci code. the rais-ci status bit in the sr4 register indicates the reception of an ais-ci signal. the rai-ci (remote alarm indication-customer installa tion) code for t1 esf operation is a special form of the esf yellow alarm (an unscheduled message). setting the rais-ci bit in the t1ccr1 register causes the ds2156 to transmit the rai-ci code. the ra i-ci code causes a standard yellow alarm to be detected by the receiver. when the host processor dete cts a yellow alarm, it can then test the alarm for the rai-ci state by checking the boc detector for the rai-ci flag. that flag is a 011111 code in the 6- bit boc message. the rai-ci code for t1 d4 operation is a 10001011 flag in all 24 time slots. to transmit the rai-ci code the host sets all 24 channels to idle w ith a 10001011 idle code. since this code meets the requirements for a standard t1 d4 yellow alarm, th e host can use the receive channel monitor function to detect the 100001011 code whenever a standard yellow alarm is detected. downloaded from: http:///
ds2156 59 of 265 8.4 t1 receive-side digital-milliwatt code generation receive-side digital-milliwatt code generation invol ves using the receive di gital-milliwatt registers (t1rdmr1/2/3) to determine which of the 24 t1 channels of the t1 line going to the backplane should be overwritten with a digital-milliwatt pattern. the di gital-milliwatt code is an 8-byte repeating pattern that represents a 1khz sine wave (1e/0b/0b/1e/9 e/8b/8b/9e). each bit in the t1rdmrx registers represents a particular channel. if a bit is set to a 1, then th e receive data in that ch annel is replaced with the digital-milliwatt code. if a bit is set to 0, no replacement occurs. register name: t1rdmr1 register description: t1 receive digital-milliwatt enable register 1 register address: 0ch bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive digital-milliwatt enable for channels 1 to 8 (ch1 to ch8) 0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code register name: t1rdmr2 register description: t1 receive digital-milliwatt enable register 2 register address: 0dh bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive digital-milliwatt enable for channels 9 to 16 (ch9 to ch16) 0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code register name: t1rdmr3 register description: t1 receive digital-milliwatt enable register 3 register address: 0eh bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch 21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive digital-milliwatt enable for channels 17 to 24 (ch17 to ch24) 0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code downloaded from: http:///
ds2156 60 of 265 register name: info1 register description: information register 1 register address: 10h bit # 7 6 5 4 3 2 1 0 name rpdv tpdv cofa 8zd 16zd sefe b8zs fbe default 0 0 0 0 0 0 0 0 bit 0/frame bit-error event (fbe). set when an ft (d4) or fps (esf) framing bit is received in error. bit 1/b8zs codeword detect event (b8zs). set when a b8zs codeword is detected at rpos and rneg independent of whether the b8zs mode is selected or not by t1tcr2.7. useful for automatically setting the line coding. bit 2/severely errored framing event (sefe). set when two out of six framing bits (ft or fps) are received in error. bit 3/sixteen zero-detect event (16zd). set when a string of at least 16 consecutive 0s (regardless of the length of the string) have been received at rposi and rnegi. bit 4/eight zero-detect event (8zd). set when a string of at least eight consecutive 0s (regardless of the length of the string) have been received at rposi and rnegi. bit 5/change-of-frame alignment event (cofa). set when the last resync r esulted in a change-of-frame or multiframe alignment. bit 6/transmit pulse-density violation event (tpdv). set when the transmit data stream does not meet the ansi t1.403 requirements for pulse density. bit 7/receive pulse-density violation event (rpdv). set when the receive data stream does not meet the ansi t1.403 requirements for pulse density. downloaded from: http:///
ds2156 61 of 265 table 8-a. t1 alarm criteria alarm set criteria clear criteria blue alarm (ais) (note 1) when over a 3ms window, five or fewer 0s are received when over a 3ms window, six or more 0s are received yellow alarm (rai) d4 bit 2 mode (t1rcr2.0 = 0) when bit 2 of 256 consecutive channels is set to 0 for at least 254 occurrences when bit 2 of 256 consecutive channels is set to 0 for fewer than 254 occurrences d4 12th f-bit mode (t1rcr2.0 = 1; this mode is also referred to as the japanese yellow alarm) when the 12th framing bit is set to 1 for two consecutive occurrences when the 12th framing bit is set to 0 for two consecutive occurrences esf mode when 16 consecutive patterns of 00ff appear in the fdl when 14 or fewer patterns of 00ff hex out of 16 possible appear in the fdl red alarm (lrcl) (also referred to as loss of signal) when 192 consecutive 0s are received when 14 or more 1s out of 112 possible bit positions are received note 1: the definition of blue alarm (or ais) is an unframed all-ones signal. blue alarm detectors s hould be able to operate properly in the presence of a 10e-3 error rate and they should not falsely tri gger on a framed all-1s signal. blue alarm criteria in the ds2156 has been set to achieve this performance. it is recommended that the rbl bit be qualified with the rlos bit. note 2: ansi specifications use a different nomenclature than the ds2156 does. the following terms are equivalent: rbl = ais rcl = los rlos = lof ryel = rai downloaded from: http:///
ds2156 62 of 265 9. e1 framer/formatter control and status registers the e1 framer portion of the ds2156 is configured by a set of four control re gisters. typically, the control registers are only accessed when the syst em is first powered up. once the ds2156 has been initialized, the control registers need only to be accessed when there is a change in the system configuration. there are two receive control registers (e1rcr1 and e1rcr2) and two transmit control registers (e1tcr1 and e1tcr2). there are also four status and informati on registers. each of these eight registers is describe d in this section. 9.1 e1 control registers register name: e1rcr1 register description: e1 receive control register 1 register address: 33h bit # 7 6 5 4 3 2 1 0 name rserc rsigm rhdb3 rg802 rcrc4 frc synce resync default 0 0 0 0 0 0 0 0 bit 0/resync (resync). when toggled from low to high, a resync is initiated. must be cleared and set again for a subsequent resync. bit 1/sync enable (synce) 0 = auto resync enabled 1 = auto resync disabled bit 2/frame resync criteria (frc) 0 = resync if fas received in error three consecutive times 1 = resync if fas or bit 2 of non-fas is received in error three consecutive times bit 3/receive crc4 enable (rcrc4) 0 = crc4 disabled 1 = crc4 enabled bit 4/receive g.802 enable (rg802). see section 16 for details. 0 = do not force rchblk high during bit 1 of time slot 26 1 = force rchblk high during bit 1 of time slot 26 bit 5/receive hdb3 enable (rhdb3) 0 = hdb3 disabled 1 = hdb3 enabled bit 6/receive signaling mode select (rsigm) 0 = cas signaling mode 1 = ccs signaling mode bit 7/rser control (rserc) 0 = allow rser to output data as received under all conditions 1 = force rser to 1 under loss-of-frame alignment conditions downloaded from: http:///
ds2156 63 of 265 table 9-a. e1 sync/resync criteria frame or multiframe level sync criteria resync criteria itu spec. fas fas present in frame n and n + 2; fas not present in frame n + 1 three consecutive incorrect fas received alternate: (e1rcr1.2 = 1) the above criteria is met or three consecutive incorrect bit 2 of non-fas received g.706 4.1.1 4.1.2 crc4 two valid mf alignment words found within 8ms 915 or more crc4 codewords out of 1000 received in error g.706 4.2 and 4.3.2 cas valid mf alignment word found and previous time slot 16 contains code other than all 0s two consecutive mf alignment words received in error g.732 5.2 register name: e1rcr2 register description: e1 receive control register 2 register address: 34h bit # 7 6 5 4 3 2 1 0 name sa8s sa7s sa6s sa5s sa4s rcla default 0 0 0 0 0 0 0 0 bit 0/receive carrier-loss (rcl) alternate criteria (rcla). defines the criteria for a receive carrier-loss condition for both the framer and liu. 0 = rcl declared upon 255 consecutive 0s (125s) 1 = rcl declared upon 2048 consecutive 0s (1ms) bits 1, 2/unused, must be set to 0 for proper operation bit 3/sa4 bit select (sa4s). set to 1 to have rlclk pulse at the sa4 bit position; set to 0 to force rlclk low during sa4 bit position. see section 34 for details. bit 4/sa5 bit select (sa5s). set to 1 to have rlclk pulse at the sa5 bit position; set to 0 to force rlclk low during sa5 bit position. see section 34 for details. bit 5/sa6 bit select (sa6s). set to 1 to have rlclk pulse at the sa6 bit position; set to 0 to force rlclk low during sa6 bit position. see section 34 for details. bit 6/sa7 bit select (sa7s). set to 1 to have rlclk pulse at the sa7 bit position; set to 0 to force rlclk low during sa7 bit position. see section 34 for details. bit 7/sa8 bit select (sa8s). set to 1 to have rlclk pulse at the sa8 bit position; set to 0 to force rlclk low during sa8 bit position. see section 34 for details. downloaded from: http:///
ds2156 64 of 265 register name: e1tcr1 register description: e1 transmit control register 1 register address: 35h bit # 7 6 5 4 3 2 1 0 name tfpt t16s tua1 tsis tsa1 thdb3 tg802 tcrc4 default 0 0 0 0 0 0 0 0 bit 0/transmit crc4 enable (tcrc4) 0 = crc4 disabled 1 = crc4 enabled bit 1/transmit g.802 enable (tg802). see section 34 for details. 0 = do not force tchblk high during bit 1 of time slot 26 1 = force tchblk high during bit 1 of time slot 26 bit 2/transmit hdb3 enable (thdb3) 0 = hdb3 disabled 1 = hdb3 enabled bit 3/transmit signaling all ones (tsa1) 0 = normal operation 1 = force time slot 16 in every frame to all ones bit 4/transmit international bit select (tsis) 0 = sample si bits at tser pin 1 = source si bits from taf and tnaf registers (in this mode, e1tcr1.7 must be set to 0) bit 5/transmit unframed all ones (tua1) 0 = transmit data normally 1 = transmit an unframed all-ones code at tposo and tnego bit 6/transmit time slot 16 data select (t16s). see section 15.2 for details. 0 = time slot 16 determined by the ssiex registers and the thscs function in the pcpr register 1 = source time slot 16 from ts1 to ts16 registers bit 7/transmit time slot 0 pass-through (tfpt) 0 = fas bits/sa bits/remote alarm sourced in ternally from the taf and tnaf registers 1 = fas bits/sa bits/remote alarm sourced from tser downloaded from: http:///
ds2156 65 of 265 register name: e1tcr2 register description: e1 transmit control register 2 register address: 36h bit # 7 6 5 4 3 2 1 0 name sa8s sa7s sa6s sa5s sa4s aebe aais ara default 0 0 0 0 0 0 0 0 bit 0/automatic remote alarm generation (ara) 0 = disabled 1 = enabled bit 1/automatic ais generation (aais) 0 = disabled 1 = enabled bit 2/automatic e-bit enable (aebe) 0 = e-bits not automatically set in the transmit direction 1 = e-bits automatically set in the transmit direction bit 3/sa4 bit select (sa4s). set to 1 to source the sa4 bit from the tlink pin; set to 0 to not source the sa4 bit. see section 34 for details. bit 4/sa5 bit select (sa5s). set to 1 to source the sa5 bit from the tlink pin; set to 0 to not source the sa5 bit. see section 34 for details. bit 5/sa6 bit select (sa6s). set to 1 to source the sa6 bit from the tlink pin; set to 0 to not source the sa6 bit. see section 34 for details. bit 6/sa7 bit select (sa7s). set to 1 to source the sa7 bit from the tlink pin; set to 0 to not source the sa7 bit. see section 34 for details. bit 7/sa8 bit select (sa8s). set to 1 to source the sa8 bit from the tlink pin; set to 0 to not source the sa8 bit. see section 34 for details. downloaded from: http:///
ds2156 66 of 265 9.2 automatic alarm generation the device can be programmed to automatically tran smit ais or remote alarm. when automatic ais generation is enabled (e1tcr2.1 = 1), the device monitors the receive-sid e framer to determine if any of the following conditions are present: loss-of-rece ive frame synchronization, ais alarm (all ones) reception, or loss-of-receive carrier (o r signal). the framer forces either an ais or remote alarm if any one or more of these conditions is present. when automatic rai generation is enabled (e1tcr2.0 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss-of-r eceive-frame synchronization, ais alarm (all ones) reception, loss-of-recei ve carrier (or signal) , or if crc4 multiframe synchronization cannot be found within 128ms of fas synchronization (i f crc4 is enabled). if any one or more of these conditions is present, then the framer transmits an rai alarm. rai generation conforms to ets 300 011 specifications and a constant remote alarm is transmitted if the ds2156 cannot find crc4 multiframe synchronization within 400ms as per g.706. note: it is an invalid state to have both automatic ais generation and automatic remote alarm generation enabled at the same time. downloaded from: http:///
ds2156 67 of 265 9.3 e1 information registers register name: info3 register description: information register 3 register address: 12h bit # 7 6 5 4 3 2 1 0 name crcrc fasrc casrc default 0 0 0 0 0 0 0 0 bit 0/cas resync criteria met event (casrc). set when two consecutive cas mf alignment words are received in error. bit 1/fas resync criteria met event (fasrc). set when three consecutive fas words are received in error. bit 2/crc resync criteria met event (crcrc). set when 915/1000 codewords are received in error. register name: info7 register description: information register 7 (real-time, non-latched register) register address: 30h bit # 7 6 5 4 3 2 1 0 name csc5 csc4 csc3 csc2 csc0 fassa cassa crc4sa default 0 0 0 0 0 0 0 0 bit 0/crc4 mf sync active (crc4sa). set while the synchronizer is searching for the crc4 mf alignment word. this is a read-only, non-latched, real-time bit. it is not necessary to precede the read of this bit with a write. bit 1/cas mf sync active (cassa). set while the synchronizer is searching for the cas mf alignment word. this is a read-only, non-latched, real-time bit. it is not necessary to precede the read of this bit with a write. bit 2/fas sync active (fassa). set while the synchronizer is searching for alignment at the fas level. this is a read-only, non-latched, real-time bit. it is not n ecessary to precede the read of this bit with a write. bits 3 to 7/crc4 sync counter bits (csc0, csc2 to csc4). the crc4 sync counter increments each time the 8ms crc4 multiframe search times out. the counter is cleared when the framer has successfully obtained synchronization at the crc4 level. the counter can also be cleared by disabling the crc4 mode (e1rcr1.3 = 0). this counter is useful for determining the amount of tim e the framer has been searching for synchronization at the crc4 level. itu g.706 suggests that if synchronization at the crc4 level cannot be obtained within 400ms, then the search should be abandoned and proper action taken. th e crc4 sync counter rolls over. csc0 is the lsb of the 6-bit counter. (note: the bit next to lsb is not accessible. csc1 is omitted to allow resolution to >400ms using 5 bits.) these are read-only, non-latched, real-time b its. it is not necessary to pr ecede the read of these bits with a write. downloaded from: http:///
ds2156 68 of 265 table 9-b. e1 alarm criteria alarm set criteria clear criteria itu specification rlos an rlos condition exists on power-up prior to initial synchronization, when a resync criteria has been met, or when a manual resync has been initiated by e1rcr1.0 rcl 255 or 2048 consecutive 0s received as determined by e1rcr2.0 at least 32 1s in 255-bit times are received g.775/g.962 rra bit 3 of nonalign frame set to 1 for three consecutive occasions bit 3 of nonalign frame set to 0 for three consecutive occasions o.162 2.1.4 rua1 fewer than three 0s in two frames (512 bits) more than two 0s in two frames (512 bits) o.162 1.6.1.2 rdma bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes v52lnk two out of three sa7 bits are 0 g.965 downloaded from: http:///
ds2156 69 of 265 10. common control and status registers register name: ccr1 register description: common control register 1 register address: 70h bit # 7 6 5 4 3 2 1 0 name mclks crc4r sie odm dicai tcss1 tcss0 rlosf default 0 0 0 0 0 0 0 0 bit 0/function of the rlos/lotc output (rlosf) 0 = receive loss of sync (rlos) 1 = loss-of-transmit clock (lotc) bit 1/transmit clock source select bit 0 (tcss0) bit 2/transmit clock source select bit 0 (tcss1) tcss1 tcss0 transmit clock source 0 0 the tclk pin is always the source of transmit clock. 0 1 switch to the clock present at rclk when the signal at the tclk pin fails to transition after 1 channel time. 1 0 use the scaled signal present at mclk as the transmit clock. the tclk pin is ignored. 1 1 use the signal present at rclk as the transmit clock. the tclk pin is ignored. bit 3/disable idle code auto increment (dicai). selects/deselects the auto-increment feature for the transmit and receive idle code array address register. see section 16. 0 = addresses in iaar register automatically increment on every read/write operation to the pcicr register 1 = addresses in iaar register do not automatically increment bit 4/output data mode (odm) 0 = pulses at tposo and tnego are one full tclko period wide 1 = pulses at tposo and tnego are one-half tclko period wide bit 5/signaling integration enable (sie) 0 = signaling changes of state reporte d on any change in selected channels 1 = signaling must be stable for three multiframes in order for a change of state to be reported bit 6/crc-4 recalculate (crc4r) 0 = transmit crc-4 generation and insertion operates in normal mode 1 = transmit crc-4 generation operates according to g.706 intermediate path recalculation method bit 7/mclk source (mclks). selects the source of mclk 0 = mclk is source from the mclk pin 1 = mclk is source from the tsysclk pin downloaded from: http:///
ds2156 70 of 265 register name: idr register description: device identification register register address: 0fh bit # 7 6 5 4 3 2 1 0 name id7 id6 id5 id4 id3 id2 id1 id0 default 1 1 0 0 0 0 0 0 bits 0 to 3/chip revision bits (id0 to id3). the lower four bits of the idr are used to display the die revision of the chip. ido is the lsb of a decimal co de that represents the chip revision. bits 4 to 7/device id (id4 to id7). the upper four bits of the idr are used to display the ds2156 id. 10.1 t1/e1 status registers register name: sr2 register description: status register 2 register address: 18h bit # 7 6 5 4 3 2 1 0 name ryelc rua1c frclc rlosc ryel rua1 frcl rlos default 0 0 0 0 0 0 0 0 bit 0/receive loss-of-sync condition (rlos). set when the ds2156 is not synchronized to the received data stream. bit 1/framer receive carrier-loss condition (frcl). set when 255 (or 2048 if e1rcr2.0 = 1) e1 mode or 192 t1 mode consecutive 0s have been detected at rposi and rnegi. bit 2/receive unframed all-ones (t1 blue alarm, e1 ais) condition (rua1). set when an unframed all 1s code is received at rposi and rnegi. bit 3/receive yellow alarm condition (ryel) (t1 only). set when a yellow alarm is received at rposi and rnegi. bit 4/receive loss-of-sync clear event (rlosc). set when the framer achieves synchronization; remains set until read. bit 5/framer receive carrier-loss clear event (frclc). set when the carrier loss condition at rposi and rnegi is no longer detected. bit 6/receive unframed all-ones clear event (rua1c). set when the unframed all 1s condition is no longer detected. bit 7/receive yellow alarm clear event (ryelc) (t1 only). set when the receive yellow alarm condition is no longer detected. downloaded from: http:///
ds2156 71 of 265 register name: imr2 register description: interrupt mask register 2 register address: 19h bit # 7 6 5 4 3 2 1 0 name ryelc rua1c frclc rlosc ryel rua1 frcl rlos default 0 0 0 0 0 0 0 0 bit 0/receive loss-of-sync condition (rlos) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising edge only bit 1/framer receive carrier loss condition (frcl) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising edge only bit 2/receive unframed all-ones (blue alarm) condition (rua1) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising edge only bit 3/receive yellow alarm condition (ryel) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising edge only bit 4/receive loss-of-sync clear event (rlosc) 0 = interrupt masked 1 = interrupt enabled bit 5/framer receive carrier loss condition clear (frclc) 0 = interrupt masked 1 = interrupt enabled bit 6/receive unframed all-ones condition clear event (rua1c) 0 = interrupt masked 1 = interrupt enabled bit 7/receive yellow alarm clear event (ryelc) 0 = interrupt masked 1 = interrupt enabled downloaded from: http:///
ds2156 72 of 265 register name: sr3 register description: status register 3 register address: 1ah bit # 7 6 5 4 3 2 1 0 name lspare ldn lup lotc lorc v52lnk rdma rra default 0 0 0 0 0 0 0 0 bit 0/receive remote alarm condition (rra) (e1 only). set when a remote alarm is received at rposi and rnegi. this is a double interrupt bit. see section 6.3. bit 1/receive distant mf alarm condition (rdma) (e1 only). set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes. this alarm is not disabled in the ccs signaling mode. this is a double interrupt bit. see section 6.3. bit 2/v5.2 link detected condition (v52lnk) (e1 only). set on detection of a v5.2 link identification signal (g.965). this is a double interrupt bit. see section 6.3. bit 3/loss-of-receive clock condition (lorc). set when the rclki pin has not transitioned for one channel time. this is a double interrupt bit. see section 6.3. bit 4/loss-of-transmit clock condition (lotc). set when the tclk pin has not transitioned for one channel time. forces the lotc pin high if enabled by ccr1.0. this is a double interrupt bit. see section 6.3. bit 5/loop-up code detected condition (lup) (t1 only). set when the loop-up code as defined in the rupcd1/2 register is being received. see section 25 for details. this is a double interrupt bit. see section 6.3. bit 6/loop-down code detected condition (ldn) (t1 only). set when the loop down code as defined in the rdncd1/2 register is being received. see section 25 for details. this is a double interrupt bit. see section 6.3. bit 7/spare code detected condition (lspare) (t1 only). set when the spare code as defined in the rscd1/2 registers is being received. see section 25 for details. this is a double interrupt bit. see section 6.3. downloaded from: http:///
ds2156 73 of 265 register name: imr3 register description: interrupt mask register 3 register address: 1bh bit # 7 6 5 4 3 2 1 0 name lspare ldn lup lotc lorc v52lnk rdma rra default 0 0 0 0 0 0 0 0 bit 0/receive remote alarm condition (rra) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising and falling edges bit 1/receive distant mf alarm condition (rdma) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising and falling edges bit 2/v5.2 link detected condition (v52lnk) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising and falling edges bit 3/loss-of-receive clock condition (lorc) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising and falling edges bit 4/loss-of-transmit clock condition (lotc) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising and falling edges bit 5/loop-up code-detected condition (lup) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising and falling edges bit 6/loop-down code-detected condition (ldn) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising and falling edges bit 7/spare code detected condition (lspare) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising and falling edges downloaded from: http:///
ds2156 74 of 265 register name: sr4 register description: status register 4 register address: 1ch bit # 7 6 5 4 3 2 1 0 name rais-ci rsao rsaz tmf taf rmf rcmf raf default 0 0 0 0 0 0 0 0 bit 0/receive align frame event (raf) (e1 only). set every 250s at the beginning of align frames. used to alert the host that si and sa bits are available in the raf and rnaf registers. bit 1/receive crc4 multiframe event (rcmf) (e1 only). set on crc4 multiframe boundaries; continues to set every 2ms on an arbitrary boundary if crc4 is disabled. bit 2/receive multiframe event (rmf) e1 mode: set every 2ms (regardless if cas signaling is enabled or not) on receive multiframe boundaries. used to alert the host that signaling data is available. t1 mode: set every 1.5ms on d4 mf boundaries or every 3ms on esf mf boundaries. bit 3/transmit align frame event (taf) (e1 only). set every 250s at the beginning of align frames. used to alert the host that the taf and tnaf registers need to be updated. bit 4/transmit multiframe event (tmf) e1 mode: set every 2ms (regardless if crc4 is enab led) on transmit multiframe boundaries. used to alert the host that signaling data needs to be updated. t1 mode: set every 1.5ms on d4 mf boundaries or every 3ms on esf mf boundaries. bit 5/receive signaling all-zeros event (rsaz) (e1 only). set when over a full mf, time slot 16 contains all 0s. bit 6/receive signaling all-ones event (rsao) (e1 only). set when the contents of time slot 16 contains fewer than three 0s over 16 consecutive frames. this al arm is not disabled in the ccs signaling mode. bit 7/receive ais-ci event (rais-ci) (t1 only). set when the receiver detects the ais-ci pattern as defined in ansi t1.403. downloaded from: http:///
ds2156 75 of 265 register name: imr4 register description: interrupt mask register 4 register address: 1dh bit # 7 6 5 4 3 2 1 0 name rais-ci rsao rsaz tmf taf rmf rcmf raf default 0 0 0 0 0 0 0 0 bit 0/receive align frame event (raf) 0 = interrupt masked 1 = interrupt enabled bit 1/receive crc4 multiframe event (rcmf) 0 = interrupt masked 1 = interrupt enabled bit 2/receive multiframe event (rmf) 0 = interrupt masked 1 = interrupt enabled bit 3/transmit align frame event (taf) 0 = interrupt masked 1 = interrupt enabled bit 4/transmit multiframe event (tmf) 0 = interrupt masked 1 = interrupt enabled bit 5/receive signaling all-zeros event (rsaz) 0 = interrupt masked 1 = interrupt enabled bit 6/receive signaling all-ones event (rsao) 0 = interrupt masked 1 = interrupt enabled bit 7/receive ais-ci event (rais-ci) 0 = interrupt masked 1 = interrupt enabled downloaded from: http:///
ds2156 76 of 265 11. i/o pin configuration options register name: iocr1 register description: i/o configuration register 1 register address: 01h bit # 7 6 5 4 3 2 1 0 name rsms rsms2 rsms1 rsio tsdw tsm tsio odf default 0 0 0 0 0 0 0 0 bit 0/output data format (odf) 0 = bipolar data at tposo and tnego 1 = nrz data at tposo; tnego = 0 bit 1/tsync i/o select (tsio) 0 = tsync is an input 1 = tsync is an output bit 2/tsync mode select (tsm). selects frame or multiframe mode for the tsync pin. see the timing diagrams in section 34. 0 = frame mode 1 = multiframe mode bit 3/tsync double-wide (tsdw). (note: this bit must be set to 0 when iocr1.2 = 1 or when iocr1.1 = 0.) 0 = do not pulse double-wide in signaling frames 1 = do pulse double-wide in signaling frames bit 4/rsync i/o select (rsio). (note: this bit must be set to 0 when escr.0 = 0.) 0 = rsync is an output 1 = rsync is an input (only valid if elastic store enabled) bit 5/rsync mode select 1(rsms1). selects frame or multiframe pulse when rsync pin is in output mode. in input mode (elastic store must be enabled), multiframe mode is only useful when re ceive signaling reinsertion is enabled. see the timing diagrams in section 34. 0 = frame mode 1 = multiframe mode bit 6/rsync mode select 2 (rsms2) t1 mode: rsync pin must be programmed in the output frame mode (iocr1.5 = 0, iocr1.4 = 0). 0 = do not pulse double-wide in signaling frames 1 = do pulse double-wide in signaling frames e1 mode: rsync pin must be programmed in the output multiframe mode (iocr1.5 = 1, iocr1.4 = 0). 0 = rsync outputs cas multiframe boundaries 1 = rsync outputs crc4 multiframe boundaries bit 7/rsync multiframe skip control (rsms). useful in framing format conversions from d4 to esf. this function is not available when the recei ve-side elastic store is enabled. rs ync must be set to output multiframe pulses (iocr1.5 = 1 and iocr1.4 = 0). 0 = rsync outputs a pulse at every multiframe 1 = rsync outputs a pulse at every other multiframe downloaded from: http:///
ds2156 77 of 265 register name: iocr2 register description: i/o configuration register 2 register address: 02h bit # 7 6 5 4 3 2 1 0 name rclkinv tclkinv rsyncinv tsyncinv tssyncinv h100en tsclkm rsclkm default 0 0 0 0 0 0 0 0 bit 0/rsysclk mode select (rsclkm) 0 = if rsysclk is 1.544mhz 1 = if rsysclk is 2.048mhz or ibo enabled (see section 28 for details on ibo function.) bit 1/tsysclk mode select (tsclkm) 0 = if tsysclk is 1.544mhz 1 = if tsysclk is 2.048mhz or ibo enabled (see section 28 for details on ibo function.) bit 2/h.100 sync mode (h100en) 0 = normal operation 1 = sync shift bit 3/tssync invert (tssyncinv) 0 = no inversion 1 = invert bit 4/tsync invert (tsyncinv) 0 = no inversion 1 = invert bit 5/rsync invert (rsyncinv) 0 = no inversion 1 = invert bit 6/tclk invert (tclkinv) 0 = no inversion 1 = invert bit 7/rclk invert (rclkinv) 0 = no inversion 1 = invert downloaded from: http:///
ds2156 78 of 265 12. loopback configuration register name: lbcr register description: loopback control register register address: 4ah bit # 7 6 5 4 3 2 1 0 name liuc llb rlb plb flb default 0 0 0 0 0 0 0 0 bit 0/framer loopback (flb). this loopback is useful in testing and debugging applications. in flb, the ds2156 loops data from the transmit side back to the recei ve side. when flb is enabled, the following occurs: 1) t1 mode: an unframed all-ones code is transmitted at tposo and tnego. e1 mode: normal data is transmitted at tposo and tnego. 2) data at rposi and rnegi is ignored. 3) all receive-side signals take on timing synchronous with tclk instead of rclki. please note that it is not acceptable to have rclk conn ected to tclk during this loopback because this causes an unstable condition. 0 = loopback disabled 1 = loopback enabled bit 1/payload loopback (plb). when plb is enabled, the following occurs: 1) data is transmitted from the tposo and tnego pi ns synchronous with rclk instead of tclk. 2) all the receive side signals continue to operate normally. 3) data at the tser, tdata, and tsig pins is ignored. 4) the tlclk signal becomes synchronous with rclk instead of tclk. 0 = loopback disabled 1 = loopback enabled t1 mode. normally, this loopback is only enabled when esf framing is being performed but can also be enabled in d4 framing applications. in a plb situat ion, the ds2156 loops the 192 bits of payload data (with bpvs corrected) from the re ceive section back to the transmit section. the fps framing pattern, crc6 calculation, and the fdl bits are not loope d back; they are reinserted by the ds2156. e1 mode. in a plb situation, the ds2156 loops the 248 bits of payload data (with bpvs corrected) from the receive section back to the transmit section. the transmit section modifies the payload as if it was input at tser. the fas word; si, sa, and e bits; and crc4 are not looped back; they are reinserted by the ds2156. bit 2/remote loopback (rlb) . in this loopback, data input by the rposi and rnegi pins is transmitted back to the tposo and tnego pins. data continues to pass through the receive-side framer of the ds2156 as it would normally. data from the transmit-side formatter is ignored. see figure 2-1 for more details. 0 = loopback disabled 1 = loopback enabled downloaded from: http:///
ds2156 79 of 265 bit 3/local loopback (llb). in this loopback, data continues to be transmitted as normal through the transmit side of the sct. data being received at rtip and rring ar e replaced with the data being transmitted. data in this loopback passes through the jitter attenuator. see figure 2-2 for more details. 0 = loopback disabled 1 = loopback enabled bit 4/line interface unit mux control (liuc). this is a software version of the liuc pin. when the liuc pin is connected high, the liuc bit has control. when th e liuc pin is connected low, the framer and liu are separated and the liuc bit has no effect 0 = if liuc pin connected high, liu internally connected to framer block and deactivate the tposi/tnegi/tclki/rposi/rnegi/rclki pins 1 = if liuc pin connected high, disconnect liu from framer block and activate the tposi/tnegi/tclki/rposi/rnegi/rclki pins liuc pin liuc bit condition 0 0 liu and framer separated 0 1 liu and framer separated 1 0 liu and framer connected 1 1 liu and framer separated bits 5 to 7/unused, must be set to 0 for proper operation downloaded from: http:///
ds2156 80 of 265 12.1 per-channel loopback the per-channel loopback registers (pclrs) determin e which channels (if any) from the backplane should be replaced with the data from th e receive side or, i.e., off of the t1 or e1 line. if this loopback is enabled, then transmit and receive clocks and fr ame syncs must be synchronized. one method to accomplish this is to connect rclk to tclk and rfsync to tsync. there are no restrictions on which channels can be looped back or on how many channels can be looped back. each of the bit positions in the per-channel loopback registers (pclr1/pclr2/pclr3/pclr4) represents a ds0 channel in the outgoing frame. when these bits ar e set to a 1, data from the corresponding receive channel replaces the data on tser for that channel. register name: pclr1 register description: per-channel loopback enable register 1 register address: 4bh bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 to 7/per-channel loopback enab le for channels 1 to 8 (ch1 to ch8) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel register name: pclr2 register description: per-channel loopback enable register 2 register address: 4ch bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 to 7/per-channel loopback enab le for channels 9 to 16 (ch9 to ch16) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel downloaded from: http:///
ds2156 81 of 265 register name: pclr3 register description: per-channel loopback enable register 3 register address: 4dh bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch 21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/per-channel loopback enable for channels 17 to 24 (ch17 to ch24) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel register name: pclr4 register description: per-channel loopback enable register 4 register address: 4eh bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch 29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 to 7/per-channel loopback enable for channels 25 to 32 (ch25 to ch32) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel downloaded from: http:///
ds2156 82 of 265 13. error count registers the ds2156 contains four counters that are used to accumulate line-coding er rors, path errors, and synchronization errors. counter update options incl ude one-second boundaries, 42ms (t1 mode only), 62ms (e1 mode only), or manual. see error-counter configuration register (ercnt) . when updated automatically, the user can use the interrupt from the tim er to determine when to read these registers. all four counters saturate at their re spective maximum counts, and they do not roll over. note: only the line- code violation count regist er has the potential to overflow, but th e bit error would have to exceed 10e-2 before this would occur. register name: ercnt register description: error-counter configuration register register address: 41h bit # 7 6 5 4 3 2 1 0 name mecu ecus eams vcrfs fsbe moscrf lcvcrf default 0 0 0 0 0 0 0 0 bit 0/t1 line-code violation count register function select (lcvcrf) 0 = do not count excessive 0s 1 = count excessive 0s bit 1/multiframe out-of-sync count register function select (moscrf) 0 = count errors in the framing bit position 1 = count the number of multiframes out-of-sync bit 2/pcvcr fs-bit error-report enable (fsbe) 0 = do not report bit errors in fs-bit position; only ft-bit position 1 = report bit errors in fs-bit position as well as ft-bit position bit 3/e1 line-code violation count register function select (vcrfs) 0 = count bipolar violations (bpvs) 1 = count code violations (cvs) bit 4/error-accumulation mode select (eams) 0 = ercnt.5 determines accumulation time 1 = ercnt.6 determines accumulation time bit 5/error-counter update select (ecus) t1 mode: 0 = update error counters once a second 1 = update error counters every 42ms (333 frames) e1 mode: 0 = update error counters once a second 1 = update error counters every 62.5ms (500 frames) bit 6/manual error-counter update (mecu). when enabled by ercnt.4, the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error-counter registers with the latest counts and reset the counters. the user must wait a minimum of 1.5 rclk clock periods before reading the error count registers to allow for proper update. bit 7/unused, must be set to 0 for proper operation downloaded from: http:///
ds2156 83 of 265 13.1 line-code violation count register (lcvcr) 13.1.1 t1 operation t1 code violations are defined as bi polar violations (bpvs) or excessive 0s. if the b8zs mode is set for the receive side, then b8zs codewords are not counted. this counter is always en abled; it is not disabled during receive loss-of-synchroniza tion (rlos = 1) conditions. tabl e 13-a shows what the lcvcrs count. table 13-a. t1 line code violation counting options count excessive zeros? (ercnt.0) b8zs enabled? (t1rcr2.5) counted in the lcvcrs no no bpvs yes no bpvs + 16 consecutive 0s no yes bpvs (b8zs codewords not counted) yes yes bpvs + 8 consecutive 0s 13.1.2 e1 operation either bipolar violations or code violations can be counte d. bipolar violations are defined as consecutive marks of the same polarity. in this mode, if the hdb3 mode is set for the receive side, then hdb3 codewords are not counted as bpvs. if ercnt.3 is se t, then the lvc counts code violations as defined in itu o.161. code violations are defi ned as consecutive bipolar violations of the same polarity. in most applications, the framer should be programmed to c ount bpvs when receiving ami code and to count cvs when receiving hdb3 code. this counter increments at all times and is not disabled by loss-of-sync conditions. the counter saturates at 65,535 and does not roll over. the bit- error rate on an e1 line would have to be greater than 10 -2 before the vcr would saturate (table 13-b). table 13-b. e1 line-code violation counting options e1 code violation select (ercnt.3) counted in the lcvcrs 0 bpvs 1 cvs downloaded from: http:///
ds2156 84 of 265 register name: lcvcr1 register description: line-code violation count register 1 register address: 42h bit # 7 6 5 4 3 2 1 0 name lcvc15 lcvc14 lcvc13 lcvc 12 lcvc11 lcvc10 lcvc9 lccv8 default 0 0 0 0 0 0 0 0 bits 0 to 7/line-code violation counter bits 8 to 15 (lcvc8 to lcvc15). lcv15 is the msb of the 16-bit code violation count. register name: lcvcr2 register description: line-code violation count register 2 register address: 43h bit # 7 6 5 4 3 2 1 0 name lcvc7 lcvc6 lcvc5 lcvc4 lcvc3 lcvc2 lcvc1 lcvc0 default 0 0 0 0 0 0 0 0 bits 0 to 7/line-code violation counter bits 0 to 7 (lcvc0 to lcvc7). lcv0 is the lsb of the 16-bit code violation count. downloaded from: http:///
ds2156 85 of 265 13.2 path code violation count register (pcvcr) 13.2.1 t1 operation the path code violation count regist er records ft, fs, or crc6 errors in t1 frames. when the receive side of a framer is set to operate in the t1 esf framing mode, pcvcr reco rds errors in the crc6 codewords. when set to operate in the t1 d4 framing mode , pcvcr counts errors in the ft framing bit position. through the ercnt.2 bit, a framer can be programmed to also report errors in the fs framing bit position. the pcvcr is disabled du ring receive loss-of-synchronizatio n (rlos = 1) conditions. table 13-c shows what errors the pcvcr counts. table 13-c. t1 path code violation counting arrangements framing mode count fs errors? counted in the pcvcrs d4 no errors in the ft pattern d4 yes errors in both the ft and fs patterns esf dont care errors in the crc6 codewords 13.2.2 e1 operation the path code violation-count register records crc4 errors. since the maximum crc4 count in a one- second period is 1000, this counter cannot saturate. the counter is disabl ed during loss-of-sync at either the fas or crc4 level; it continues to count if lo ss-of-multiframe sync occurs at the cas level. path code violation-count register 1 (pcvcr1) is the most significant word and pcvcr2 is the least significant word of a 16-bit counter th at records path violations (pvs). register name: pcvcr1 register description: path code violation count register 1 register address: 44h bit # 7 6 5 4 3 2 1 0 name pcvc15 pcvc14 pcvc13 pcvc 12 pcvc11 pcvc10 pcvc9 pcvc8 default 0 0 0 0 0 0 0 0 bits 0 to 7/path code violation counter bits 8 to 15 (pcvc8 to pcvc15). pcvc15 is the msb of the 16-bit path code violation count. register name: pcvcr2 register description: path code violation count register 2 register address: 45h bit # 7 6 5 4 3 2 1 0 name pcvc7 pcvc6 pcvc5 pcvc4 pcvc3 pcvc2 pcvc1 pcvc0 default 0 0 0 0 0 0 0 0 bits 0 to 7/path code violation counter bits 0 to 7 (pcvc0 to pcvc7). pcvc0 is the lsb of the 16-bit path code violation count. downloaded from: http:///
ds2156 86 of 265 13.3 frames out-of-sync count register (foscr) 13.3.1 t1 operation the foscr is used to count the numb er of multiframes that the receive synchronizer is out of sync. this number is useful in esf applicati ons needing to measure the paramete rs loss-of-frame count (lofc) and esf error events as described in at&t publicat ion tr54016. when the foscr is operated in this mode, it is not disabled during re ceive loss-of-synchronization (rlos = 1) conditions. the foscr has an alternate operating mode whereby it counts either erro rs in the ft framing pattern (in the d4 mode) or errors in the fps framing pattern (in the esf mode). when the foscr is operated in this mode, it is disabled during receive loss-of-s ynchronization (rlos = 1) conditio ns. table 13-d shows what the foscr is capable of counting. table 13-d. t1 frames out-of-sync counting arrangements framing mode (t1rcr1.3) count mos or f-bit errors (ercnt.1) counted in the foscrs d4 mos number of multiframes out-of-sync d4 f-bit errors in the ft pattern esf mos number of multiframes out-of-sync esf f-bit errors in the fps pattern 13.3.2 e1 operation the foscr counts word errors in the fas in time slot 0. this counter is disabled when rlos is high. fas errors are not counted when the framer is s earching for fas alignment and/or synchronization at either the cas or crc4 multiframe level. since th e maximum fas word error count in a one-second period is 4000, this counter cannot saturate. the frames out-of-sync count regist er 1 (foscr1) is the most significa nt word and foscr2 is the least significant word of a 16-bit counter that records frames out-of-sync. register name: foscr1 register description: frames out-of-sync count register 1 register address: 46h bit # 7 6 5 4 3 2 1 0 name fos15 fos14 fos13 fos 12 fos11 fos10 fos9 fos8 default 0 0 0 0 0 0 0 0 bits 0 to 7/frames out-of-sync counter bits 8 to 15 (fos8 to fos15). fos15 is the msb of the 16-bit frames out-of-sync count. register name: foscr2 register description: frames out-of-sync count register 2 register address: 47h bit # 7 6 5 4 3 2 1 0 name fos7 fos6 fos5 fos4 fos3 fos2 fos1 fos0 default 0 0 0 0 0 0 0 0 bits 0 to 7/frames out-of-sync counter bits 0 to 7 (fos0 to fos7). fos0 is the lsb of the 16-bit frames out- of-sync count. downloaded from: http:///
ds2156 87 of 265 13.4 e-bit counter (ebcr) this counter is only available in e1 mode. e-bit count register 1 (e bcr1) is the most significant word and ebcr2 is the least significant wo rd of a 16-bit counter that records far-end bloc k errors (febe) as reported in the first bit of fram es 13 and 15 on e1 lines running with crc4 multiframe. these count registers increment once each time the received e-bit is set to 0. since the maximum e-bit count in a one- second period is 1000, this counter cannot saturate. the counter is disabl ed during loss-of-sync at either the fas or crc4 level; it continues to count if lo ss-of-multiframe sync occurs at the cas level. register name: ebcr1 register description: e-bit count register 1 register address: 48h bit # 7 6 5 4 3 2 1 0 name eb15 eb14 eb13 eb12 eb11 eb10 eb9 eb8 default 0 0 0 0 0 0 0 0 bits 0 to 7/e-bit counter bits 8 to 15 (eb8 to eb15). eb15 is the msb of the 16-bit e-bit count. register name: ebcr2 register description: e-bit count register 2 register address: 49h bit # 7 6 5 4 3 2 1 0 name eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 default 0 0 0 0 0 0 0 0 bits 0 to 7/e-bit counter bits 0 to 7 (eb0 to eb7). eb0 is the lsb of the 16-bit e-bit count. downloaded from: http:///
ds2156 88 of 265 14. ds0 monitoring function the ds2156 has the ability to monitor one ds0 64kbps channel in the transmit direction and one ds0 channel in the receive direction at the same time. in the transmit direction, the user determines which channel is to be monitored by proper ly setting the tcm0 to tcm4 bits in the tds0sel register. in the receive direction, the rcm0 to rcm4 bits in the rd s0sel register need to be properly set. the ds0 channel pointed to by the tcm0 to tcm4 bits a ppear in the transmit ds0 monitor (tds0m) register. the ds0 channel pointed to by the rcm0 to rcm4 bits appear in the receive ds0 (rds0m) register. the tcm4 to tcm0 and rcm4 to rcm0 bits should be programmed with the decimal decode of the appropriate t1or e1 channel. t1 channels 1 through 24 map to register values 0 through 23. e1 channels 1 through 32 map to register values 0 through 31. for example, if ds0 channel 6 in the transmit direction and ds0 channel 15 in the receive direction needed to be monito red, then the following values would be programmed into tds0sel and rds0sel: tcm4 = 0 rcm4 = 0 tcm3 = 0 rcm3 = 1 tcm2 = 1 rcm2 = 1 tcm1 = 0 rcm1 = 1 tcm0 = 1 rcm0 = 0 register name: tds0sel register description: transmit channel monitor select register address: 74h bit # 7 6 5 4 3 2 1 0 name tcm4 tcm3 tcm2 tcm1 tcm0 default 0 0 0 0 0 0 0 0 bits 0 to 4/transmit channel monitor bits (tcm0 to tcm4). tcm0 is the lsb of a 5-bit channel select that determines which transmit channel data appear in the tds0m register. bits 5 to 7/unused, must be set to 0 for proper operation register name: tds0m register description: transmit ds0 monitor register register address: 75h bit # 7 6 5 4 3 2 1 0 name b1 b2 b3 b4 b5 b6 b7 b8 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit ds0 channel bits (b1 to b8). transmit channel data that has been selected by the transmit channel monitor select register. b8 is the lsb of the ds0 channel (last bit to be transmitted). downloaded from: http:///
ds2156 89 of 265 register name: rds0sel register description: receive channel monitor select register address: 76h bit # 7 6 5 4 3 2 1 0 name rcm4 rcm3 rcm2 rcm1 rcm0 default 0 0 0 0 0 0 0 0 bits 0 to 4/receive channel monitor bits (rcm0 to rcm4). rcm0 is the lsb of a 5-bit channel select that determines which receive ds0 channel da ta appear in the rds0m register. bits 5 to 7/unused, must be set to 0 for proper operation register name: rds0m register description: receive ds0 monitor register register address: 77h bit # 7 6 5 4 3 2 1 0 name b1 b2 b3 b4 b5 b6 b7 b8 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive ds0 channel bits (b1 to b8). receive channel data that has been selected by the receive channel monitor select register. b8 is the lsb of the ds0 channel (last bit to be received). downloaded from: http:///
ds2156 90 of 265 15. signaling operation there are two methods to access r eceive signaling data and provide transmit signaling data, processor- based (software-based) or hardware-based. proce ssor-based refers to access through the transmit and receive signaling registers rs1Crs1 6 and ts1Cts16. hardware-based refe rs to the tsig and rsig pins. both methods can be used simultaneously. 15.1 receive signaling figure 15-1. simplified diagra m of receive signaling path 15.1.1 processor-based signaling the robbed-bit signaling (t1) or ts16 cas signaling (e 1) is sampled in the receive data stream and copied into the receive signaling registers, rs 1Crs16. in t1 mode, only rs1Crs12 are used. the signaling information in these registers is always updated on multiframe boundaries. this function is always enabled. 15.1.1.1 change-of-state to avoid constant monitoring of th e receive signaling registers, the ds2156 can be programmed to alert the host when any specific channel or channels undergo a change of th eir signaling state. rscse1Crscse4 for e1 and rscse1Crscse3 for t1 ar e used to select which channels can cause a change-of-state indication. the change -of-state is indicated in status register 5 (sr1.5). if signaling integration (ccr1.5) is enabled, then the new signa ling state must be constant for three multiframes before a change-of-state is indica ted. the user can enable the int pin to toggle low upon detection of a change in signaling by setting the imr1.5 bit. the signaling integration mode is global and cannot be enabled on a channel-by-channel basis. the user can identity which channels have unde rgone a signaling change-of-state by reading the rsinfo1Crsinfo4 registers. the info rmation from these registers inform the user which rsx register to read for the new signaling data. all changes are indicated in the rs info1Crsinfo4 registers regardless of the rscse1Crscse4 registers. receive signaling registers change-of-state indication registers signaling buffers a ll-ones reinsertion control rser rsync rsig t1/e1 data stream per-channel control signaling extraction downloaded from: http:///
ds2156 91 of 265 15.1.2 hardware-based receive signaling in hardware-based signaling the signaling data can be obtained from the rser pin or the rsig pin. rsig is a signaling pcm stream output on a channe l-by-channel basis from the signaling buffer. the signaling data, t1 robbed bit or e1 ts16, is still present in the original data stream at rser. the signaling buffer provides signaling data to the rsig pin and also allows signaling data to be reinserted into the original data stream in a different alignm ent that is determined by a multiframe signal from the rsync pin. in this mode, the receive elastic store can be enabled or disabled. if the receive elastic store is enabled, then the backplane clock (rsysclk) can be either 1.544mhz or 2.048mhz. in the esf framing mode, the abcd signaling bits are output on rsig in the lower nibble of each channel. the rsig data is updated once a multiframe (3ms) unless a freeze is in effect. in the d4 framing mode, the ab signaling bits are output twice on rsig in the lower ni bble of each channel. hence, bits 5 and 6 contain the same data as bits 7 and 8, respectivel y, in each channel. the rsig data is updated once a multiframe (1.5ms) unless a freeze is in effect. see th e timing diagrams in section 34 for some examples. 15.1.2.1 receive signaling reinsertion at rser in this mode, the user provides a multiframe sync at the rsync pin and the signaling data is reinserted based on this alignment. in t1 mode, this results in two copies of the signaling data in the rser data stream, the original signaling data a nd the realigned data. this is of litt le consequence in voice channels. reinsertion can be avoided in data ch annels since this feature is activat ed on a per-channel basis. in this mode, the elastic store must be enabled; however , the backplane clock can be either 1.544mhz or 2.048mhz. signaling reinsertion can be enabled on a per-channel basis by setting the rsrcs bit high in the pcpr register. the channels that will have signaling rein serted are selected by writing to the pcdr1Cpcdr3 registers for t1 mode and pcdr1Cpc dr4 registers for e1 mode. in e1 mode, the user generally selects all channels or none for reinsertion. in e1 mode, signa ling reinsertion on all channels can be enabled with a single bit, sigcr.7 (grsre). this bit allows the user to reinsert a ll signaling channels without having to program all channels through the per-channel function. 15.1.2.2 force recei ve signaling all ones in t1 mode, the user can, on a per-channel basis, fo rce the robbed-bit signaling bit positions to a 1 by using the per-channel re gister (section 5). the user sets the btcs bit in the pc pr register. the channels that will be forced to 1 are selected by writing to the pcdr 1Cpcdr3 registers. 15.1.2.3 receive signaling freeze the signaling data in the four mu ltiframe signaling buffers is frozen in a known good state upon either a loss of synchronization (oof event), carrier loss, or frame slip. this action meets the requirements of bellcore trCtsyC000170 for signaling freezing. to allo w this freeze action to occur, the rfe control bit (sigcr.4) should be set high. the user can for ce a freeze by setting the rff control bit (sigcr.3) high. the rsigf output pin provides a hardware indication that a freeze is in e ffect. the four-multiframe buffer provides a three-multiframe delay in the signali ng bits provided at the rs ig pin (and at the rser pin if receive signaling reinsertion is enabled). when freezing is enable d (rfe = 1), the signaling data is held in the last-known good state until the corrupti ng error condition subsides. when the error condition subsides, the signaling data is held in the old state for at least an additional 9ms (or 4.5ms in d4 framing mode) before updating with new signaling data. downloaded from: http:///
ds2156 92 of 265 register name: sigcr register description: signaling control register register address: 40h bit # 7 6 5 4 3 2 1 0 name grsre rfe rff rccs tccs frsao default 0 0 0 0 0 0 0 0 bit 0/force receive signaling all ones (frsao). in t1 mode, this bit forces all signaling data at the rsig and rser pin to all ones. this bit has no effect in e1 mode. 0 = normal signaling data at rsig and rser 1 = force signaling data at rsig and rser to all ones bit 1/transmit time slot control for cas signaling (tccs). controls the order that signaling is transmitted from the transmit signaling registers. this bit should be set = 0 in t1 mode. 0 = signaling data is cas format 1 = signaling data is ccs format bit 2/receive time slot control for cas signaling (rccs). controls the order that signaling is placed into the receive signaling registers. this bit should be set = 0 in t1 mode. 0 = signaling data is cas format 1 = signaling data is ccs format bit 3/receive force freeze (rff). freezes receive-side signaling at rsig (and rser if receive signaling reinsertion is enabled); overrides receive freeze en able (rfe). see section 15.1.2.3 for details. 0 = do not force a freeze event 1 = force a freeze event bit 4/receive freeze enable (rfe). see section 15.1.2.3 for details. 0 = no freezing of receive signaling data occurs 1 = allow freezing of receive signaling data at rsig (a nd rser if receive signaling reinsertion is enabled) bits 5, 6/unused, must be set to 0 for proper operation bit 7/global receive signaling reinsertion enable (grsre). this bit allows the user to reinsert all signaling channels without programming all channels through the per-channel function. 0 = do not reinsert all signaling 1 = reinsert all signaling downloaded from: http:///
ds2156 93 of 265 register name: rs1 to rs12 register description: receive signaling registers (t1 mode, esf format) register address: 60h to 6bh (msb) (lsb) ch2-a ch2-b ch2-c ch2-d ch1-a ch1-b ch1-c ch1-d rs1 ch4-a ch4-b ch4-c ch4-d ch3-a ch3-b ch3-c ch3-d rs2 ch6-a ch6-b ch6-c ch6-d ch5-a ch5-b ch5-c ch5-d rs3 ch8-a ch8-b ch8-c ch8-d ch7-a ch7-b ch7-c ch7-d rs4 ch10-a ch10-b ch10-c ch10-d ch9-a ch9-b ch9-c ch9-d rs5 ch12-a ch12-b ch12-c ch12-d ch11-a ch11-b ch11-c ch11-d rs6 ch14-a ch14-b ch14-c ch14-d ch13-a ch13-b ch13-c ch13-d rs7 ch16-a ch16-b ch16-c ch16-d ch15-a ch15-b ch15-c ch15-d rs8 ch18-a ch18-b ch18-c ch18-d ch17-a ch17-b ch17-c ch17-d rs9 ch20-a ch20-b ch20-c ch20-d ch19-a ch19-b ch19-c ch19-d rs10 ch22-a ch22-b ch22-c ch22-d ch21-a ch21-b ch21-c ch21-d rs11 ch24-a ch24-b ch24-c ch24-d ch23-a ch23-b ch23-c ch23-d rs12 register name: rs1 to rs12 register description: receive signaling registers (t1 mode, d4 format) register address: 60h to 6bh (msb) (lsb) ch2-a ch2-b ch2-a ch2-b ch1-a ch1-b ch1-a ch1-b rs1 ch4-a ch4-b ch4-a ch4-b ch3-a ch3-b ch3-a ch3-b rs2 ch6-a ch6-b ch6-a ch6-b ch5-a ch5-b ch5-a ch5-b rs3 ch8-a ch8-b ch8-a ch8-b ch7-a ch7-b ch7-a ch7-b rs4 ch10-a ch10-b ch10-a ch10-b ch9-a ch9-b ch9-a ch9-b rs5 ch12-a ch12-b ch12-a ch12-b ch11-a ch11-b ch11-a ch11-b rs6 ch14-a ch14-b ch14-a ch14-b ch13-a ch13-b ch13-a ch13-b rs7 ch16-a ch16-b ch16-a ch16-b ch15-a ch15-b ch15-a ch15-b rs8 ch18-a ch18-b ch18-a ch18-b ch17-a ch17-b ch17-a ch17-b rs9 ch20-a ch20-b ch20-a ch20-b ch19-a ch19-b ch19-a ch19-b rs10 ch22-a ch22-b ch22-a ch22-b ch21-a ch21-b ch21-a ch21-b rs11 ch24-a ch24-b ch24-a ch24-b ch23-a ch23-b ch23-a ch23-b rs12 note: in d4 format, ts1Cts12 contain signaling data for two frames. bold type indicates data for second frame. downloaded from: http:///
ds2156 94 of 265 register name: rs1 to rs16 register description: receive signaling registers (e1 mode, cas format) register address: 60h to 6fh (msb) (lsb) 0 0 0 0 x y x x rs1 ch2-a ch2-b ch2-c ch2-d ch1-a ch1-b ch1-c ch1-d rs2 ch4-a ch4-b ch4-c ch4-d ch3-a ch3-b ch3-c ch3-d rs3 ch6-a ch6-b ch6-c ch6-d ch5-a ch5-b ch5-c ch5-d rs4 ch8-a ch8-b ch8-c ch8-d ch7-a ch7-b ch7-c ch7-d rs5 ch10-a ch10-b ch10-c ch10-d ch9-a ch9-b ch9-c ch9-d rs6 ch12-a ch12-b ch12-c ch12-d ch11-a ch11-b ch11-c ch11-d rs7 ch14-a ch14-b ch14-c ch14-d ch13-a ch13-b ch13-c ch13-d rs8 ch16-a ch16-b ch16-c ch16-d ch15-a ch15-b ch15-c ch15-d rs9 ch18-a ch18-b ch18-c ch18-d ch17-a ch17-b ch17-c ch17-d rs10 ch20-a ch20-b ch20-c ch20-d ch19-a ch19-b ch19-c ch19-d rs11 ch22-a ch22-b ch22-c ch22-d ch21-a ch21-b ch21-c ch21-d rs12 ch24-a ch24-b ch24-c ch24-d ch23-a ch23-b ch23-c ch23-d rs13 ch26-a ch26-b ch26-c ch26-d ch25-a ch25-b ch25-c ch25-d rs14 ch28-a ch28-b ch28-c ch28-d ch27-a ch27-b ch27-c ch27-d rs15 ch30-a ch30-b ch30-c ch30-d ch29-a ch29-b ch29-c ch29-d rs16 register name: rs1 to rs16 register description: receive signaling registers (e1 mode, ccs format) register address: 60h to 6fh (msb) (lsb) 1 2 3 4 5 6 7 8 rs1 9 10 11 12 13 14 15 16 rs2 17 18 19 20 21 22 23 24 rs3 25 26 27 28 29 30 31 32 rs4 33 34 35 36 37 38 39 40 rs5 41 42 43 44 45 46 47 48 rs6 49 50 51 52 53 54 55 56 rs7 57 58 59 60 61 62 63 64 rs8 65 66 67 68 69 70 71 72 rs9 73 74 75 76 77 78 79 80 rs10 81 82 83 84 85 86 87 88 rs11 89 90 91 92 93 94 95 96 rs12 97 98 99 100 101 102 103 104 rs13 105 106 107 108 109 110 111 112 rs14 113 114 115 116 117 118 119 120 rs15 121 122 123 124 125 126 127 128 rs16 downloaded from: http:///
ds2156 95 of 265 register name: rscse1, rscse2, rscse3, rscse4 register description: receive signaling change-of-state interrupt enable register address: 3ch, 3dh, 3eh, 3fh (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 rscse1 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 rscse2 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 rscse3 ch30 ch29 ch28 ch27 ch26 ch25 rscse4 setting any of the ch1Cch30 bits in the rscse1Crscse4 registers causes an interrupt when that channels signaling data changes state. register name: rsinfo1, rsinfo2, rsinfo3, rsinfo4 register description: receive signaling change-of-state information register address: 38h, 39h, 3ah, 3bh (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 rsinfo1 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 rsinfo2 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 rsinfo3 ch30 ch29 ch28 ch27 ch26 ch25 rsinfo4 when a channels signaling data chang es state, the respective b it in registers rsinfo1C4 is set. an interrupt is generated if the channel was also enabled as an interrupt source by setting the appropr iate bit in rscse1C4. the bit remains set until read. downloaded from: http:///
ds2156 96 of 265 15.2 transmit signaling figure 15-2. simplified diagram of transmit signaling path 15.2.1 processor-based mode in processor-based mode, signaling da ta is loaded into the transmit si gnaling registers (t s1Cts16) by the host interface. on multif rame boundaries, the contents of these regist ers are loaded into a shift register for placement in the appropriate bit position in the outgoing data stream. the user can employ the transmit multiframe interrupt in status register 4 (sr4.4) to know when to update the signaling bits. the user need not update any transmit signaling regi ster for which there is no cha nge-of-state for that register. each transmit signaling register c ontains the robbed-bit signaling (t 1) or ts16 cas signaling (e1) for two time slots that are inserted into the outgoing stream, if enabled to do so through t1tcr1.4 (t1 mode) or e1tcr1.6 (e1 mode). in t1 mode, only ts1Cts12 are used. signaling data can be sourced from the ts regist ers on a per-channel basis by using the software signaling insertion enable registers, ssie1Cssie4. 15.2.1.1 t1 mode in t1 esf framing mode, there are four signaling b its per channel (a, b, c, and d). ts1Cts12 contain a full multiframe of signaling data. in t1 d4 framing mode, there are only two signaling bits per channel (a and b). in t1 d4 framing mode, the framer uses the c and d bit positions as the a and b bit positions for the next multiframe. in d4 mode , two multiframes of signaling data can be loaded into ts1Cts12. the framer loads the contents of ts1Cts12 into the outgoing shift register every other d4 multiframe. in d4 mode, the host should load new contents into ts1Cts12 on every other multiframe boundary and no later than 120s after the boundary. transmit signaling registers signaling buffers per-channel control tser tsig t1/e1 data stream per-channel control ssie1 - ssie4 b7 t1tcr1.4 1 0 01 0 1 pcpr.3 only applies to t1 mode downloaded from: http:///
ds2156 97 of 265 15.2.1.2 e1 mode in e1 mode, ts16 carries the signaling information. this information can be in either ccs (common channel signaling) or cas (channel a ssociated signaling) format. the 32 time slots are referenced by two different channel number schemes in e1. in cha nnel numbering, ts0Cts31 are labeled channels 1 through 32. in phone channel numbering, ts1Cts 15 are labeled channel 1 through channel 15 and ts17Cts31 are labeled channel 15 through channel 30. table 15-a. time slot numbering schemes ts 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 phone channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 downloaded from: http:///
ds2156 98 of 265 register name: ts1 to ts16 register description: transmit signaling registers (e1 mode, cas format) register address: 50h to 5fh (msb) (lsb) 0 0 0 0 x y x x ts1 ch2-a ch2-b ch2-c ch2-d ch1-a ch1-b ch1-c ch1-d ts2 ch4-a ch4-b ch4-c ch4-d ch3-a ch3-b ch3-c ch3-d ts3 ch6-a ch6-b ch6-c ch6-d ch5-a ch5-b ch5-c ch5-d ts4 ch8-a ch8-b ch8-c ch8-d ch7-a ch7-b ch7-c ch7-d ts5 ch10-a ch10-b ch10-c ch10-d ch9-a ch9-b ch9-c ch9-d ts6 ch12-a ch12-b ch12-c ch12-d ch11-a ch11-b ch11-c ch11-d ts7 ch14-a ch14-b ch14-c ch14-d ch13-a ch13-b ch13-c ch13-d ts8 ch16-a ch16-b ch16-c ch16-d ch15-a ch15-b ch15-c ch15-d ts9 ch18-a ch18-b ch18-c ch18-d ch17-a ch17-b ch17-c ch17-d ts10 ch20-a ch20-b ch20-c ch20-d ch19-a ch19-b ch19-c ch19-d ts11 ch22-a ch22-b ch22-c ch22-d ch21-a ch21-b ch21-c ch21-d ts12 ch24-a ch24-b ch24-c ch24-d ch23-a ch23-b ch23-c ch23-d ts13 ch26-a ch26-b ch26-c ch26-d ch25-a ch25-b ch25-c ch25-d ts14 ch28-a ch28-b ch28-c ch28-d ch27-a ch27-b ch27-c ch27-d ts15 ch30-a ch30-b ch30-c ch30-d ch29-a ch29-b ch29-c ch29-d ts16 register name: ts1 to ts16 register description: transmit signaling registers (e1 mode, ccs format) register address: 50h to 5fh (msb) (lsb) 1 2 3 4 5 6 7 8 ts1 9 10 11 12 13 14 15 16 ts2 17 18 19 20 21 22 23 24 ts3 25 26 27 28 29 30 31 32 ts4 33 34 35 36 37 38 39 40 ts5 41 42 43 44 45 46 47 48 ts6 49 50 51 52 53 54 55 56 ts7 57 58 59 60 61 62 63 64 ts8 65 66 67 68 69 70 71 72 ts9 73 74 75 76 77 78 79 80 ts10 81 82 83 84 85 86 87 88 ts11 89 90 91 92 93 94 95 96 ts12 97 98 99 100 101 102 103 104 ts13 105 106 107 108 109 110 111 112 ts14 113 114 115 116 117 118 119 120 ts15 121 122 123 124 125 126 127 128 ts16 downloaded from: http:///
ds2156 99 of 265 register name: ts1 to ts12 register description: transmit signaling registers (t1 mode, esf format) register address: 50h to 5bh (msb) (lsb) ch2-a ch2-b ch2-c ch2-d ch1-a ch1-b ch1-c ch1-d ts1 ch4-a ch4-b ch4-c ch4-d ch3-a ch3-b ch3-c ch3-d ts2 ch6-a ch6-b ch6-c ch6-d ch5-a ch5-b ch5-c ch5-d ts3 ch8-a ch8-b ch8-c ch8-d ch7-a ch7-b ch7-c ch7-d ts4 ch10-a ch10-b ch10-c ch10-d ch9-a ch9-b ch9-c ch9-d ts5 ch12-a ch12-b ch12-c ch12-d ch11-a ch11-b ch11-c ch11-d ts6 ch14-a ch14-b ch14-c ch14-d ch13-a ch13-b ch13-c ch13-d ts7 ch16-a ch16-b ch16-c ch16-d ch15-a ch15-b ch15-c ch15-d ts8 ch18-a ch18-b ch18-c ch18-d ch17-a ch17-b ch17-c ch17-d ts9 ch20-a ch20-b ch20-c ch20-d ch19-a ch19-b ch19-c ch19-d ts10 ch22-a ch22-b ch22-c ch22-d ch21-a ch21-b ch21-c ch21-d ts11 ch24-a ch24-b ch24-c ch24-d ch23-a ch23-b ch23-c ch23-d ts12 register name: ts1 to ts12 register description: transmit signaling registers (t1 mode, d4 format) register address: 50h to 5bh (msb) (lsb) ch2-a ch2-b ch2-a ch2-b ch1-a ch1-b ch1-a ch1-b ts1 ch4-a ch4-b ch4-a ch4-b ch3-a ch3-b ch3-a ch3-b ts2 ch6-a ch6-b ch6-a ch6-b ch5-a ch5-b ch5-a ch5-b ts3 ch8-a ch8-b ch8-a ch8-b ch7-a ch7-b ch7-a ch7-b ts4 ch10-a ch10-b ch10-a ch10-b ch9-a ch9-b ch9-a ch9-b ts5 ch12-a ch12-b ch12-a ch12-b ch11-a ch11-b ch11-a ch11-b ts6 ch14-a ch14-b ch14-a ch14-b ch13-a ch13-b ch13-a ch13-b ts7 ch16-a ch16-b ch16-a ch16-b ch15-a ch15-b ch15-a ch15-b ts8 ch18-a ch18-b ch18-a ch18-b ch17-a ch17-b ch17-a ch17-b ts9 ch20-a ch20-b ch20-a ch20-b ch19-a ch19-b ch19-a ch19-b ts10 ch22-a ch22-b ch22-a ch22-b ch21-a ch21-b ch21-a ch21-b ts11 ch24-a ch24-b ch24-a ch24-b ch23-a ch23-b ch23-a ch23-b ts12 note: in d4 format, ts1Cts12 contain signaling data for tw o frames. bold type indicates data for second frame. downloaded from: http:///
ds2156 100 of 265 15.2.2 software signaling insertion-en able registers, e1 cas mode in e1 cas mode, the cas signalin g alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data. register name: ssie1 register description: software signaling insertion enable 1 register address: 08h bit # 7 6 5 4 3 2 1 0 name ch7 ch6 ch5 ch4 ch3 ch2 ch1 ucaw default 0 0 0 0 0 0 0 0 bit 0/upper cas align/alarm word (ucaw). selects the upper cas align/alarm pattern (0000) to be sourced from the upper 4 bits of the ts1 register. 0 = do not source the upper cas align/alarm pattern from the ts1 register 1 = source the upper cas align/alarm pattern from the ts1 register bits 1 to 7/software signaling-insertion enab le for channels 1 to 7 (ch1 to ch7). these bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tsx registers for this channel 1 = source signaling data from the tsx registers for this channel register name: ssie2 register description: software signaling insertion enable 2 register address: 09h bit # 7 6 5 4 3 2 1 0 name ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 default 0 0 0 0 0 0 0 0 bits 0 to 7/software signaling insertion enab le for channels 8 to 15 (ch8 to ch15). these bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tsx registers for this channel 1 = source signaling data from the tsx registers for this channel downloaded from: http:///
ds2156 101 of 265 register name: ssie3 register description: software signaling insertion enable 3 register address: 0ah bit # 7 6 5 4 3 2 1 0 name ch22 ch21 ch20 ch19 ch18 ch17 ch16 lcaw default 0 0 0 0 0 0 0 0 bit 0/lower cas align/alarm word (lcaw). selects the lower cas align/alarm bits (xyxx) to be sourced from the lower 4 bits of the ts1 register. 0 = do not source the lower cas align/alarm bits from the ts1 register 1 = source the lower cas alarm align/bits from the ts1 register bits 1 to 7/software signaling insertion enable fo r lcaw and channels 16 to 22 (ch16 to ch22). these bits determine which channels ar e to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tsx registers for this channel 1 = source signaling data from the tsx registers for this channel register name: ssie4 register description: software signaling insertion enable 4 register address: 0bh bit # 7 6 5 4 3 2 1 0 name ch30 ch29 ch28 ch 27 ch26 ch25 ch24 ch23 default 0 0 0 0 0 0 0 0 bits 0 to 7/software signaling insertion enable for channels 22 to 30 (ch23 to ch30). these bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tsx registers for this channel 1 = source signaling data from the tsx registers for this channel downloaded from: http:///
ds2156 102 of 265 15.2.3 software signaling insertion- enable registers, t1 mode in t1 mode, only registers ssie1Cssie3 are used since there are only 24 channels in a t1 frame. register name: ssie1 register description: software signaling insertion enable 1 register address: 08h bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 to 7/software signaling insertion enable for channels 1 to 8 (ch1 to ch8). these bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tsx registers for this channel 1 = source signaling data from the tsx registers for this channel register name: ssie2 register description: software signaling-insertion enable 2 register address: 09h bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 to 7/software signaling insertion enab le for channels 9 to 16 (ch9 to ch16). these bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tsx registers for this channel 1 = source signaling data from the tsx registers for this channel register name: ssie3 register description: software signaling-insertion enable 3 register address: 0ah bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch 21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/software signaling insertion enable for channels 17 to 24 (ch17 to ch24). these bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the tsx registers for this channel 1 = source signaling data from the tsx registers for this channel 15.2.4 hardware-based mode in hardware-based mode, signaling data is input through the tsig pi n. this signaling pcm stream is buffered and inserted to the data stream being input at the tser pin. signaling data can be inserted on a per-channel basis by the transmit hardware-signaling channel-select (thscs) function. the user has the abil ity to control which channels are to have signaling data from the tsig pin inserted into them on a per-channel basis. see section 5 for details on using this per-channel (thscs) feature. the signaling insertion capabilities of the framer are available whether the transmit- side elastic store is enabled or disabled. if the el astic store is enabled, the backplane clock (tsysclk) can be either 1.544mhz or 2.048mhz. also, if the el astic is enabled in conjunction with transmit hardware signaling, ccr3.7 must be set = 0. downloaded from: http:///
ds2156 103 of 265 16. per-channel idle code generation channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. when operated in the t1 mode, only the first 24 channels are used by the ds2156, the remaining channels, ch25Cch32, are not used. the ds2156 contains a 64-byte idle code array accessed by th e idle array address re gister (iaar) and the per-channel idle code register (pcicr). the contents of the array contain the idle codes to be substituted into the appropriate transmit or receive channels. this substitution can be enable d and disabled on a per- channel basis by the transmit-channe l idle code-enable registers (tci ce1C4) and receiv e-channel idle code-enable registers (rcice1C4). to program idle codes, first select a channel by writing to the iaar register. then write the idle code to the pcicr register. for successive writes there is no need to load the iaar w ith the next consecutive address. the iaar register automatically incremen ts after a write to the pcicr register. the auto increment feature can be used for read operations as we ll. bits 6 and 7 of the i aar register can be used to block write a common idle code to all transmit or receive positions in the array with a single write to the pcicr register. bits 6 and 7 of the iaar regist er should not be used for read operations. tcice1C4 and rcice1C4 are used to enable idle c ode replacement on a per-channel basis. table 16-a. idle-code array address mapping bits 0 to 5 of iaar register maps to channel 0 transmit channel 1 1 transmit channel 2 2 transmit channel 3 30 transmit channel 31 31 transmit channel 32 32 receive channel 1 33 receive channel 2 34 receive channel 3 62 receive channel 31 63 receive channel 32 downloaded from: http:///
ds2156 104 of 265 16.1 idle-code programming examples example 1 sets transmit channel 3 idle code to 7eh. write iaar = 02h ;select channel 3 in the array write pcicr = 7eh ;set idle code to 7eh example 2 sets transmit channels 3, 4, 5, and 6 idle code to 7eh and enables transmi ssion of idle codes for those channels. write iaar = 02h ;select channel 3 in the array write pcicr = 7eh ;set channel 3 idle code to 7eh write pcicr = 7eh ;set channel 4 idle code to 7eh write pcicr = 7eh ;set channel 5 idle code to 7eh write pcicr = 7eh ;set channel 6 idle code to 7eh write tcice1 = 3ch ;enable transmission of idle codes for channels 3,4,5, and 6 example 3 sets transmit channels 3, 4, 5, and 6 idle code to 7eh, eeh, ffh, and 7eh, respectively. write iaar = 02h write pcicr = 7eh write pcicr = eeh write pcicr = ffh write pcicr = 7eh example 4 sets all transmit idle codes to 7eh. write iaar = 4xh write pcicr = 7eh example 5 sets all receive and transmit idle cod es to 7eh and enables idle code subs titution in all e1 transmit and receive channels. write iaar = cxh ;enable block write to all transmit and receive positions in the array write pcicr = 7eh ;7eh is idle code write tcice1 = feh ;enable idle code substitution for transmit channels 2 through 8 ;although an idle code was programmed for channel 1 by the block write ;function above, enabling it for channel 1 would step on the frame ;alignment, alarms, and sa bits write tcice2 = ffh ;enable idle code substitution for transmit channels 9 through 16 write tcice3 = feh ;enable idle code substitution for transmit channels 18 through 24 ;although an idle code was programmed for channel 17 by the block write ;function above, enabling it for channel 17 would step on the cas frame ;alignment, and signaling information write tcice4 = ffh ;enable idle code substitution for transmit channels 25 through 32 write rcice1 = feh ;enable idle code substitution for receive channels 2 through 8 write rcice2 = ffh ;enable idle code substitution for receive channels 9 through 16 write rcice3 = feh ;enable idle code substitution for receive channels 18 through 24 write rcice4 = ffh ;enable idle code substitution for receive channels 25 through 32 downloaded from: http:///
ds2156 105 of 265 register name: iaar register description: idle array address register register address: 7eh bit # 7 6 5 4 3 2 1 0 name gric gtic iaa5 iaa4 iaa3 iaa2 iaa1 iaa0 default 0 0 0 0 0 0 0 0 bits 0 to 5/channel pointer a ddress bits (iaa0 to iaa5). these bits select the channel to be programmed with the idle code defined in the pcicr register. iaa0 is the lsb of the 5-bit channel code. channel 1 is 01h. bit 6/global transmit-idle code (gtic). setting this bit causes all transmit channels to be set to the idle code written to the pcicr register. this bit must be set = 0 fo r read operations. the value in bits iaa0Ciaa5 must be a valid transmit channel (01h to 20h for e1 mode; 01h to 18h for t1 mode). bit 7/global receive-idle code (gric). setting this bit causes all receive channels to be set to the idle code written to the pcicr register. this bit must be set = 0 fo r read operations. the value in bits iaa0Ciaa5 must be a valid transmit channel (01h to 20h for e1 mode; 01h to 18h for t1 mode). table 16-b. gric and gtic functions gric gtic function 0 0 updates a single transmit or receive channel 0 1 updates all transmit channels 1 0 updates all receive channels 1 1 updates all transmit and receive channels register name: pcicr register description: per-channel idle code register register address: 7fh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0 to 7/per-channel idle-code bits (c0 to c7). this register defines the idle code to be programmed in the channel selected by the iaar register. c0 is the lsb of the idle code (this bit is transmitted last). downloaded from: http:///
ds2156 106 of 265 the transmit-channel idle-code enable registers (tcice1/2/3/ 4) are used to determine which of the 24 t1 or 32 e1 channels from the backplane to the t1 or e1 line should be overwritten w ith the code placed in the per-channel code array. register name: tcice1 register description: transmit-channel idle-code enable register 1 register address: 80h bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 1 to 8 code insertion control bits (ch1 to ch8) 0 = do not insert data from the idle-code array into the transmit data stream 1 = insert data from the idle-code a rray into the transmit data stream register name: tcice2 register description: transmit-channel idle-code enable register 2 register address: 81h bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 9 to 16 code insertion control bits (ch9 to ch16) 0 = do not insert data from the idle-code array into the transmit data stream 1 = insert data from the idle code-a rray into the transmit data stream register name: tcice3 register description: transmit-channel idle-code enable register 3 register address: 82h bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch 21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 17 to 24 code insertion control bits (ch17 to ch24) 0 = do not insert data from the idle-code array into the transmit data stream 1 = insert data from the idle code-a rray into the transmit data stream register name: tcice4 register description: transmit-channel idle-code enable register 4 register address: 83h bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch 29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 25 to 32 code insertion control bits (ch25 to ch32) 0 = do not insert data from the idle-code array into the transmit data stream 1 = insert data from the idle-code array into the transmit data stream downloaded from: http:///
ds2156 107 of 265 the receive-channel idle-code enable registers (rcice1/2/3/ 4) are used to determine which of the 24 t1 or 32 e1 channels from the backplane to the t1 or e1 line should be overwritten w ith the code placed in the per-channel code array. register name: rcice1 register description: receive-channel idle-code enable register 1 register address: 84h bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 1 to 8 code insertion control bits (ch1 to ch8) 0 = do not insert data from the idle-code array into the receive data stream 1 = insert data from the idle-code array into the receive data stream register name: rcice2 register description: receive-channel idle-code enable register 2 register address: 85h bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 9 to 16 code insertion control bits (ch9 to ch16) 0 = do not insert data from the idle-code array into the receive data stream 1 = insert data from the idle-code array into the receive data stream register name: rcice3 register description: receive-channel idle-code enable register 3 register address: 86h bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch 21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 17 to 24 code insertion control bits (ch17 to ch24) 0 = do not insert data from the idle-code array into the receive data stream 1 = insert data from the idle-code array into the receive data stream register name: rcice4 register description: receive-channel idle-code enable register 4 register address: 87h bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch 29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 25 to 32 code insertion control bits (ch25 to ch32) 0 = do not insert data from the idle-code array into the receive data stream 1 = insert data from the idle-code array into the receive data stream downloaded from: http:///
ds2156 108 of 265 17. channel blocking registers the receive channel blocking registers (rcbr1/ rcbr2/rcbr3/rcbr4) and the transmit channel blocking registers (tcbr1/tcbr2/tcbr3/tcbr4) cont rol rchblk and tchblk pins, respectively. the rchblk and tchblk pins are us er-programmable outputs that can be forced either high or low during individual channels. these out puts can be used to block clocks to a usart or lapd controller in isdn-pri applications. when the appropriate bits are set to a 1, the rchbl k and tchblk pins are held high during the entire corres ponding channel time. channels 25 through 32 are ignored when the ds2156 is operated in the t1 mode. register name: rcbr1 register description: receive channel blocking register 1 register address: 88h bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 1 to 8 channel blocking control bits (ch1 to ch8) 0 = force the rchblk pin to remain low during this channel time 1 = force the rchblk pin high during this channel time register name: rcbr2 register description: receive channel blocking register 2 register address: 89h bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 9 to 16 channel blocking control bits (ch9 to ch16) 0 = force the rchblk pin to remain low during this channel time 1 = force the rchblk pin high during this channel time downloaded from: http:///
ds2156 109 of 265 register name: rcbr3 register description: receive channel blocking register 3 register address: 8ah bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch 21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 17 to 24 channel blocking control bits (ch17 to ch24) 0 = force the rchblk pin to remain low during this channel time 1 = force the rchblk pin high during this channel time register name: rcbr4 register description: receive channel blocking register 4 register address: 8bh bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch 29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 25 to 32 channel blocking control bits (ch25 to ch32) 0 = force the rchblk pin to remain low during this channel time 1 = force the rchblk pin high during this channel time downloaded from: http:///
ds2156 110 of 265 register name: tcbr1 register description: transmit channel blocking register 1 register address: 8ch bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 1 to 8 channel blocking control bits (ch1 to ch8) 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time register name: tcbr2 register description: transmit channel blocking register 2 register address: 8dh bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 9 to 16 channel blocking control bits (ch9 to ch16) 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time register name: tcbr3 register description: transmit channel blocking register 3 register address: 8eh bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch 21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 17 to 24 channel blocking control bits (ch17 to ch24) 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time register name: tcbr4 register description: transmit channel blocking register 4 register address: 8fh bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch 29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 25 to 32 channel blocking control bits (ch25 to ch32) 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time downloaded from: http:///
ds2156 111 of 265 18. elastic stores operation the elastic store function is unavailable when utopia backplane is enabled. the ds2156 contains dual two-frame elastic stores, one for the receive direction and one for the transmit direction. both elastic stores are fully independent. the transmit and receive-side elastic stores can be enabled/disabled independently of each other. also, each elastic store can interf ace to either a 1.544mhz or 2.048mhz/4.096mhz/8.192mhz/16.384mhz backplane without regard to the backplane rate the other elastic store is interfacing to. the elastic stores have two main purposes. firstly, they can be us ed for rate conversion. when the ds2156 is in the t1 mode, the elastic stores can rate-convert the t1 data stream to a 2.048mhz backplane. in e1 mode, the elasti c store can rate-convert the e1 data stream to a 1.544mhz backplane. secondly, they can be used to absorb the differences in frequency and phase betw een the t1 or e1 data stream and an asynchronous (i.e., not locked) bac kplane clock, which can be 1.544mhz or 2.048mhz. in this mode, the elastic stores manage the rate differe nce and perform controlled slips, deleting or repeating frames of data in order to manage the differe nce between the network and the backplane. the elastic stores can also be used to multiplex t1 or e1 data streams into higher backplane rates, which is the ibo discussed in section 28. downloaded from: http:///
ds2156 112 of 265 register name: escr register description: elastic store control register register address: 4fh bit # 7 6 5 4 3 2 1 0 name tesalgn tesr tesmdm tese resalgn resr resmdm rese default 0 0 0 0 0 0 0 0 bit 0/receive elastic store enable (rese) 0 = elastic store is bypassed 1 = elastic store is enabled bit 1/receive elastic store minimum-delay mode (resmdm). see section 18.4 for details. 0 = elastic stores operate at full two-frame depth 1 = elastic stores operate at 32-bit depth bit 2/receive elastic store reset (resr). setting this bit from a 0 to a 1 forc es the read and write pointers into opposite frames, maximizing the delay through the receive elastic store. it should be toggled after rsysclk has been applied and is stable. see section 18.3 fo r details. do not leave this bit set high. bit 3/receive elastic store align (resalgn). setting this bit from a 0 to a 1 forces the receive elastic stores write/read pointers to a minimum separation of half a frame. no action is taken if the pointer separation is already greater or equal to half a frame. if pointer separation is less than half a frame, the command is executed and the data is disrupted. it should be toggled after rsysclk has been applied and is stable. must be cleared and set again for a subsequent align. see section 18.3 for details. bit 4/transmit elastic store enable (tese) 0 = elastic store is bypassed 1 = elastic store is enabled bit 5/transmit elastic store minimum-delay mode (tesmdm). see section 18.4 for details. 0 = elastic stores operate at full two-frame depth 1 = elastic stores operate at 32-bit depth bit 6/transmit elastic store reset (tesr). setting this bit from a 0 to a 1 forces the read and write pointers into opposite frames, maximizing the delay through the transmit elas tic store. transmit data is lost during the reset. it should be toggled after tsysclk has been applied and is st able. see section 18.3 for details. do not leave this bit set high. bit 7/transmit elastic store align (tesalgn). setting this bit from a 0 to a 1 forces the transmit elastic stores write/read pointers to a minimum separation of half a frame. no action is taken if the pointer separation is already greater or equal to half a frame. if pointer separation is less than half a frame, the command is executed and the data is disrupted. it should be toggled after tsysclk has been applied and is stable. it must be cleared and set again for a subsequent align. see section 18.3 for details. downloaded from: http:///
ds2156 113 of 265 register name: sr5 register description: status register 5 register address: 1eh bit # 7 6 5 4 3 2 1 0 name tesf tesem tslip resf resem rslip default 0 0 0 0 0 0 0 0 bit 0/receive elastic store slip-occurrence event (rslip). set when the receive elastic store has either repeated or deleted a frame. bit 1/receive elastic store empty event (resem). set when the receive elastic store buffer empties and a frame is repeated. bit 2/receive elastic store full event (resf). set when the receive elastic store buffer fills and a frame is deleted. bit 3/transmit elastic store slip-occurrence event (tslip). set when the transmit elastic store has either repeated or deleted a frame. bit 4/transmit elastic store empty event (tesem). set when the transmit elastic store buffer empties and a frame is repeated. bit 5/transmit elastic store full event (tesf). set when the transmit elastic store buffer fills and a frame is deleted. register name: imr5 register description: interrupt mask register 5 register address: 1fh bit # 7 6 5 4 3 2 1 0 name tesf tesem tslip resf resem rslip default 0 0 0 0 0 0 0 0 bit 0/receive elastic store slip-occurrence event (rslip) 0 = interrupt masked 1 = interrupt enabled bit 1/receive elastic store empty event (resem) 0 = interrupt masked 1 = interrupt enabled bit 2/receive elastic store full event (resf) 0 = interrupt masked 1 = interrupt enabled bit 3/transmit elastic store slip-occurrence event (tslip) 0 = interrupt masked 1 = interrupt enabled bit 4/transmit elastic store empty event (tesem) 0 = interrupt masked 1 = interrupt enabled bit 5/transmit elastic store full event (tesf) 0 = interrupt masked 1 = interrupt enabled downloaded from: http:///
ds2156 114 of 265 18.1 receive side see the iocr1 and iocr2 registers for inform ation about clock and i/o configurations. if the receive-side elastic store is enabled, then the user must provide either a 1.544mhz or 2.048mhz clock at the rsysclk pin. for higher rate system clock applications, see the interleaved pcm bus operation in section 28. the user has the option of e ither providing a frame/multiframe sync at the rsync pin or having the rsync pin provide a pul se on frame/multiframe boundaries. if signaling reinsertion is enabled, signaling data in ts16 is realigned to the multiframe sync input on rsync. otherwise, a multiframe sync input on rsync is treated as a simple frame boundary by the elastic store. the framer always indicates frame boundaries on the network side of the elastic store by the rfsync output, whether the elastic store is enabled or not. multiframe boundari es are always indicated by the rmsync output. if the elastic store is enable d, then rmsync outputs the multiframe boundary on the backplane side of the elastic store. 18.1.1 t1 mode if the user selects to apply a 2.048mhz clock to the rsysclk pin, th en the data output at rser is forced to all 1s every fourth channel and the f-bit is passed into the msb of ts0. hence, channels 1 (bits 1C7), 5, 9, 13, 17, 21, 25, and 29 [time slots 0 (bits 1C7), 4, 8, 12, 16, 2 0, 24, and 28] are forced to a 1. also, in 2.048mhz applications, th e rchblk output is forced high dur ing the same channels as the rser pin. this is useful in t1-to- e1 conversion applications. if the tw o-frame elastic buffer either fills or empties, a controlled slip occurs. if the buffer emp ties, then a full frame of data is repeated at rser, and the sr5.0 and sr5.1 bits are set to a 1. if the buffer fills, then a full frame of data is deleted, and the sr5.0 and sr5.2 bits are set to a 1. 18.1.2 e1 mode if the elastic store is enabled, then either cas or crc4 multiframe boundaries are indicated through the rmsync output. if the user select s to apply a 1.544mhz clock to th e rsysclk pin, then every fourth channel of the received e1 data is deleted and an f- bit position, which is forced to 1, is inserted. hence, channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) are deleted from the received e1 data stream. also, in 1.544mhz applica tions, the rchblk output is not active in channels 25 through 32 (i.e., rcbr4 is not activ e). if the two-frame elastic buffe r either fills or empties, a controlled slip occurs. if the buffer empties, then a full frame of data is repeated at rser, and the sr5.0 and sr5.1 bits are set to a 1. if the buffer fills, then a full frame of data is deleted, and the sr5.0 and sr5.2 bits are set to a 1. 18.2 transmit side see the iocr1 and iocr2 registers for inform ation about clock and i/o configurations. the operation of the transmit elastic store is very sim ilar to the receive side. if the transmit-side elastic store is enabled, a 1.544mhz or 2.048mhz clock can be applied to the tsys clk input. for higher rate system clock applications, see interleaved pcm bus operation in section 28. controlled slips in the transmit elastic store are reported in the sr5.3 bit, and the direction of the slip is reported in the sr5.4 and sr5.5 bits. if hardware signaling inser tion is not enabled, ccr 3.7 should be set = 1. downloaded from: http:///
ds2156 115 of 265 18.2.1 t1 mode if the user selects to apply a 2.04 8mhz clock to the tsysclk pin, then the data input at tser is ignored every fourth channel. therefore channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) are ignored. the user can supply frame or multiframe sync pulse to the tssync input. also, in 2.048mhz applications, th e tchblk output is forced high du ring the channels ignored by the framer. 18.2.2 e1 mode a 1.544mhz or 2.048mhz clock can be applied to the tsysclk input. the user must supply a frame sync pulse or a multiframe sync pulse to the tssync input. 18.3 elastic stores initialization there are two elastic store initializa tions that can be used to improve performance in certain applications, elastic store reset and elastic store align. both of these involve the mani pulation of the elas tic stores read and write pointers and are useful primarily in synchronous applications (rsysclk/tsysclk are locked to rclk/tclk, resp ectively) (table 18-a). table 18-a. elastic store delay after initialization initialization register bit delay receive elastic store reset transmit elastic store reset escr.2 escr.6 8 clocks < delay < 1 frame 1 frame < delay < 2 frames receive elastic store align transmit elastic store align escr.3 escr.7 ? frame < delay < 1 ? frames ? frame < delay < 1 ? frames 18.4 minimum delay mode elastic store minimum delay mode can be used when the elastic store s system clock is locked to its network clock (i.e., rclk locked to rsysclk for th e receive side and tclk locked to tsysclk for the transmit side). escr.5 and escr.1 enable the transmit and receive elastic store minimum delay modes. when enabled, the elastic stores are forced to a maximum depth of 32 bits instead of the normal two-frame depth. this feature is us eful primarily in app lications that interf ace to a 2.048mhz bus. certain restrictions apply when minimum delay mode is used. in addition to the restriction mentioned above, rsync must be configured as an output when the receive elastic stor e is in minimum delay mode; tsync must be configured as an output when transmit mini mum delay mode is enabled. in a typical application, rsysclk a nd tsysclk are locked to rclk, and rsync (frame output mode) is connected to tssync (frame input mode ). all of the slip contention logic in the framer is disabled (since slips cannot occur). on power-up, after the rsysclk and tsysclk si gnals have locked to their respective network clock signals, the elastic store reset bits (escr.2 and es cr.6) should be toggled from a 0 to a 1 to ensure proper operation. downloaded from: http:///
ds2156 116 of 265 19. g.706 intermediate crc-4 updating (e1 mode only) the ds2156 can implement the g.706 crc-4 recalculation at intermediate path po ints. when this mode is enabled, the data stream presented at tser already has the fas/nfas, crc multiframe alignment word, and crc-4 checksum in time slot 0. the user can modify the sa bit positions. this change in data content is used to modify the crc-4 checksum. this modification, however, doe s not corrupt any error information the original crc-4 checksum may contai n. in this mode of operation, tsync must be configured to multiframe mode. the data at tser must be aligned to the tsync signal. if tsync is an input, then the user must assert tsync aligned at the beginning of the multiframe relative to tser. if tsync is an output, the user must multif rame-align the data presented to tser. figure 19-1. crc-4 recalculate method tser xor crc-4 calculator extract old crc-4 code insert new crc-4 code modify sa bit positions new sa bit data + tposo/tnego downloaded from: http:///
ds2156 117 of 265 20. t1 bit-oriented co de (boc) controller the ds2156 contains a boc generator on the transmit side and a boc detector on the receive side. the boc function is available only in t1 mode. 20.1 transmit boc bits 0 to 5 in the tfdl register contain the boc message to be transmitted. setting bocc.0 = 1 causes the transmit boc controller to imme diately begin inserting the boc sequence into the fdl bit position. the transmit boc controller automatically provides the abort sequence. boc messages are transmitted as long as bocc.0 is set. transmit a boc 1) write 6-bit code into the tfdl register. 2) set the sboc bit in bocc = 1. 20.2 receive boc the receive boc function is enab led by setting bocc.4 = 1. the rfdl register now operates as the receive boc message and information register. the lower six bits of the rfdl register (boc message bits) are preset to all 1s. when the boc bits change state, the bo c change-of-state indicator, sr8.0, alerts the host. the host then reads the rfdl regist er to get the boc status and message. a change-of- state occurs when either a new boc code has been present for a time determined by the receive boc filter bits rbf0 and rbf1 in the bocc regi ster, or a nonvalid code is being received. receive a boc 1) set integration time through bocc.1 and bocc.2. 2) enable the receive boc function (bocc.4 = 1). 3) enable interrupt (imr8.0 = 1). 4) wait for interrupt to occur. 5) read the rfdl register. 6) if sr2.7 = 1, then a valid boc message was received. C the lower six bits of the rfdl register comprise the message. downloaded from: http:///
ds2156 118 of 265 register name: bocc register description: boc control register register address: 37h bit # 7 6 5 4 3 2 1 0 name rboce rbr rbf1 rbf0 sboc default 0 0 0 0 0 0 0 0 bit 0/send boc (sboc). set = 1 to transmit the boc code placed in bits 0 to 5 of the tfdl register. bits 1 and 2/receive boc filter bits (rbf0, rbf1). the boc filter sets the number of consecutive patterns that must be received without error prior to an indication of a valid message. rbf1 rbf0 consecutive boc codes for valid sequence identification 0 0 none 0 1 3 1 0 5 1 1 7 bit 3/receive boc reset (rbr). a 0-to-1 transition resets the boc circuitry. must be cleared and set again for a subsequent reset. bit 4/receive boc enable (rboce). enables the receive boc function. the rfdl register reports the received boc code and two information bits when this bit is set. 0 = receive boc function disabled 1 = receive boc function enabled; the rfdl register reports boc messages and information bits 5 to 7/unused, must be set to 0 for proper operation register name: rfdl register description: receive fdl register register address: c0h bit # 7 6 5 4 3 2 1 0 name rboc5 rboc4 rboc3 rboc2 rboc1 rboc0 default 0 0 0 0 0 0 0 0 rfdl register bit definitions when bocc.4 = 1: bit 0 / boc bit 0 (rboc0) bit 1/boc bit 1 (rboc1) bit 2 / boc bit 2 (rboc2) bit 3/boc bit 3 (rboc3) bit 4/boc bit 4 (rboc4) bit 5/boc bit 5 (rboc5) bits 6, 7/this bit position is unused when bocc.4 = 1. downloaded from: http:///
ds2156 119 of 265 register name: sr8 register description: status register 8 register address: 24h bit # 7 6 5 4 3 2 1 0 name bocc rfdlad rfdlf tfdle rmtch rboc default 0 0 0 0 0 0 0 0 bit 0/receive boc detector change-of-state event (rboc). set whenever the boc detector sees a change of state to a valid boc. the setting of this bit prompts the user to read the rfdl register. bit 1/receive fdl match event (rmtch). set whenever the contents of the rfdl register matches rfdlm1 or rfdlm2. bit 2/tfdl register empty event (tfdle). set when the transmit fdl buffer (tfdl) empties. bit 3/rfdl register full event (rfdlf). set when the receive fdl buffer (rfdl) fills to capacity. bit 4/rfdl abort detect event (rfdlad). set when eight consecutive 1s are received on the fdl. bit 5/boc clear event (bocc). set when 30 fdl bits occur without an abort sequence. register name: imr8 register description: interrupt mask register 8 register address: 25h bit # 7 6 5 4 3 2 1 0 name bocc rfdlad rfdlf tfdle rmtch rboc default 0 0 0 0 0 0 0 0 bit 0/receive boc detector change-of-state event (rboc) 0 = interrupt masked 1 = interrupt enabled bit 1/receive fdl match event (rmtch) 0 = interrupt masked 1 = interrupt enabled bit 2/tfdl register empty event (tfdle) 0 = interrupt masked 1 = interrupt enabled bit 3/rfdl register full event (rfdlf) 0 = interrupt masked 1 = interrupt enabled bit 4/rfdl abort detect event (rfdlad) 0 = interrupt masked 1 = interrupt enabled bit 5/boc clear event (bocc) 0 = interrupt masked 1 = interrupt enabled downloaded from: http:///
ds2156 120 of 265 21. additional (sa) and international (si) bit operation (e1 only) when operated in the e1 mode, the ds2156 provides three methods for accessing the sa and the si bits. the first method involves a hardware scheme th at uses the rlink/rlcl k and tlink/tlclk pins (section 21.1). the second method involves using the internal raf/rnaf a nd taf/tnaf registers (section 21.2). the third method, which is covered in section 21.3, involves an expanded version of the second method. 21.1 method 1: hardware scheme on the receive side, all of the received data is repo rted at the rlink pin. usi ng the e1rcr2 register, the user can control the rlclk pin to pulse during any combin ation of sa bits. this allows the user to create a clock that can be used to capture the needed sa bits. if rsync is programmed to output a frame boundary, it identifies the si bits. on the transmit side, the individual sa bits can be eith er sourced from the intern al tnaf register (section 21.2) or externally from the tlink pin. using the e1 tcr2 register, the framer can be programmed to source any combination of the sa bits from the tli nk pin. si bits can be sampled through the tser pin if by setting e1tcr1.4 = 0. 21.2 method 2: internal register scheme based on double-frame on the receive side, the raf and rnaf registers always report the data as it received in the sa and si bit locations. the raf and rnaf registers are updated on align-frame boundaries. the setting of the receive align frame bit in status register 4 (sr4.0) indicates that the contents of the raf and rnaf have been updated. the host can use the sr4.0 bit to know when to read the raf and rnaf registers. the host has 250s to retrieve the data before it is lost. on the transmit side, data is sampled from the taf and tnaf registers with the setting of the transmit align frame bit in status register 4 (sr4.3). the host can use the sr4.3 bit to know when to update the taf and tnaf registers. it has 250s to update the data or else the old data is retransmitted . if the taf and tnaf registers are only being used to source the align frame and nonalign frame-sync patterns, then the host need only write once to these registers . data in the si bit position is overwritten if either the framer is (1) programmed to source the si bits from the tser pin, (2) in the crc4 mode, or (3) has automatic e-bit insertion enabled. data in the sa bit position is overwritten if any of the e1tcr2.3 to e1tcr2.7 bits are set to 1. downloaded from: http:///
ds2156 121 of 265 register name: raf register description: receive align frame register register address: c6h bit # 7 6 5 4 3 2 1 0 name si 0 0 1 1 0 1 1 default 0 0 0 0 0 0 0 0 bit 0/frame alignment signal bit (1) bit 1/frame alignment signal bit (1) bit 2/frame alignment signal bit (0) bit 3/frame alignment signal bit (1) bit 4/frame alignment signal bit (1) bit 5/frame alignment signal bit (0) bit 6/frame alignment signal bit (0) bit 7/international bit (si) register name: rnaf register description: receive nonalign frame register register address: c7h bit # 7 6 5 4 3 2 1 0 name si 1 a sa4 sa5 sa6 sa7 sa8 default 0 0 0 0 0 0 0 0 bit 0/additional bit 8 (sa8) bit 1/additional bit 7 (sa7) bit 2/additional bit 6 (sa6) bit 3/additional bit 5 (sa5) bit 4/additional bit 4 (sa4) bit 5/remote alarm (a) bit 6/frame nonalignment signal bit (1) bit 7/international bit (si) downloaded from: http:///
ds2156 122 of 265 register name: taf register description: transmit align frame register register address: d0h bit # 7 6 5 4 3 2 1 0 name si 0 0 1 1 0 1 1 default 0 0 0 1 1 0 1 1 bit 0/frame alignment signal bit (1) bit 1/frame alignment signal bit (1) bit 2/frame alignment signal bit (0) bit 3/frame alignment signal bit (1) bit 4/frame alignment signal bit (1) bit 5/frame alignment signal bit (0) bit 6/frame alignment signal bit (0) bit 7/international bit (si) register name: tnaf register description: transmit nonalign frame register register address: d1h bit # 7 6 5 4 3 2 1 0 name si 1 a sa4 sa5 sa6 sa7 sa8 default 0 1 0 0 0 0 0 0 bit 0/additional bit 8 (sa8) bit 1/additional bit 7 (sa7) bit 2/additional bit 6 (sa6) bit 3/additional bit 5 (sa5) bit 4/additional bit 4 (sa4) bit 5/remote alarm [used to transmit the alarm (a)] bit 6/frame nonalignment signal bit (1) bit 7/international bit (si) downloaded from: http:///
ds2156 123 of 265 21.3 method 3: internal register sc heme based on crc4 multiframe the receive side contains a set of eight registers (rsiaf, rsinaf, rra, and rs a4Crsa8) that report the si and sa bits as they are rece ived. these registers are updated wi th the setting of the receive crc4 multiframe bit in status register 2 (sr4.1). the host can use the sr4.1 bit to know when to read these registers. the user has 2ms to retrieve the data before it is lost. the msb of each register is the first received. see the following register descriptions for more details. the transmit side also contains a set of eight re gisters (tsiaf, tsinaf, tr a, and tsa4Ctsa8) that, through the transmit sa bit control regi ster (tsacr), can be programmed to insert si and sa data. data is sampled from these registers with th e setting of the transmit multiframe bit in status register 2 (sr4.4). the host can use the sr4.4 bit to know when to update these registers. it has 2ms to update the data or else the old data is retransmitted. the msb of each re gister is the first bit transmitted. see the following register descriptions for more details. register name: rsiaf register description: received si bits of the align frame register address: c8h bit # 7 6 5 4 3 2 1 0 name sif14 sif12 sif10 sif8 sif6 sif4 sif2 sif0 default 0 0 0 0 0 0 0 0 bit 0/si bit of frame 0 (sif0) bit 1/si bit of frame 2 (sif2) bit 2/si bit of frame 4 (sif4) bit 3/si bit of frame 6 (sif6) bit 4/si bit of frame 8 (sif8) bit 5/si bit of frame 10 (sif10) bit 6/si bit of frame 12 (sif12) bit 7/si bit of frame 14 (sif14) downloaded from: http:///
ds2156 124 of 265 register name: rsinaf register description: received si bits of the nonalign frame register address: c9h bit # 7 6 5 4 3 2 1 0 name sif15 sif13 sif11 sif9 sif7 sif5 sif3 sif1 default 0 0 0 0 0 0 0 0 bit 0/si bit of frame 1 (sif1) bit 1/si bit of frame 3 (sif3) bit 2/si bit of frame 5 (sif5) bit 3/si bit of frame 7 (sif7) bit 4/si bit of frame 9 (sif9) bit 5/si bit of frame 11 (sif11) bit 6/si bit of frame 13 (sif13) bit 7/si bit of frame 15 (sif15) register name: rra register description: received remote alarm register address: cah bit # 7 6 5 4 3 2 1 0 name rraf15 rraf13 rraf11 rraf9 rraf7 rraf5 rraf3 rraf1 default 0 0 0 0 0 0 0 0 bit 0/remote alarm bit of frame 1 (rraf1) bit 1/remote alarm bit of frame 3 (rraf3) bit 2/remote alarm bit of frame 5 (rraf5) bit 3/remote alarm bit of frame 7 (rraf7) bit 4/remote alarm bit of frame 9 (rraf9) bit 5/remote alarm bit of frame 11 (rraf11) bit 6/remote alarm bit of frame 13 (rraf13) bit 7/remote alarm bit of frame 15 (rraf15) downloaded from: http:///
ds2156 125 of 265 register name: rsa4 register description: received sa4 bits register address: cbh bit # 7 6 5 4 3 2 1 0 name rsa4f15 rsa4f13 rsa4f11 rsa4f9 rsa4f7 rsa4f5 rsa4f3 rsa4f1 default 0 0 0 0 0 0 0 0 bit 0/sa4 bit of frame 1 (rsa4f1) bit 1/sa4 bit of frame 3 (rsa4f3) bit 2/sa4 bit of frame 5 (rsa4f5) bit 3/sa4 bit of frame 7 (rsa4f7) bit 4/sa4 bit of frame 9 (rsa4f9) bit 5/sa4 bit of frame 11 (rsa4f11) bit 6/sa4 bit of frame 13 (rsa4f13) bit 7/sa4 bit of frame 15 (rsa4f15) register name: rsa5 register description: received sa5 bits register address: cch bit # 7 6 5 4 3 2 1 0 name rsa5f15 rsa5f13 rsa5f11 rsa5f9 rsa5f7 rsa5f5 rsa5f3 rsa5f1 default 0 0 0 0 0 0 0 0 bit 0/sa5 bit of frame 1 (rsa5f1) bit 1/sa5 bit of frame 3 (rsa5f3) bit 2/sa5 bit of frame 5 (rsa5f5) bit 3/sa5 bit of frame 7 (rsa5f7) bit 4/sa5 bit of frame 9 (rsa5f9) bit 5/sa5 bit of frame 11 (rsa5f11) bit 6/sa5 bit of frame 13 (rsa5f13) bit 7/sa5 bit of frame 15 (rsa5f15) downloaded from: http:///
ds2156 126 of 265 register name: rsa6 register description: received sa6 bits register address: cdh bit # 7 6 5 4 3 2 1 0 name rsa6f15 rsa6f13 rsa6f11 rsa6f9 rsa6f7 rsa6f5 rsa6f3 rsa6f1 default 0 0 0 0 0 0 0 0 bit 0/sa6 bit of frame 1 (rsa6f1) bit 1/sa6 bit of frame 3 (rsa6f3) bit 2/sa6 bit of frame 5 (rsa6f5) bit 3/sa6 bit of frame 7 (rsa6f7) bit 4/sa6 bit of frame 9 (rsa6f9) bit 5/sa6 bit of frame 11 (rsa6f11) bit 6/sa6 bit of frame 13 (rsa6f13) bit 7/sa6 bit of frame 15 (rsa6f15) register name: rsa7 register description: received sa7 bits register address: ceh bit # 7 6 5 4 3 2 1 0 name rsa7f15 rsa7f13 rsa7f11 rsa7f9 rsa7f7 rsa7f5 rsa7f3 rsa7f1 default 0 0 0 0 0 0 0 0 bit 0/sa7 bit of frame 1 (rsa7f1) bit 1/sa7 bit of frame 3 (rsa7f3) bit 2/sa7 bit of frame 5 (rsa7f5) bit 3/sa7 bit of frame 7 (rsa7f7) bit 4/sa7 bit of frame 9 (rsa7f9) bit 5/sa7 bit of frame 11 (rsa7f11) bit 6/sa7 bit of frame 13 (rsa7f13) bit 7/sa7 bit of frame 15 (rsa4f15) downloaded from: http:///
ds2156 127 of 265 register name: rsa8 register description: received sa8 bits register address: cfh bit # 7 6 5 4 3 2 1 0 name rsa8f15 rsa8f13 rsa8f11 rsa8f9 rsa8f7 rsa8f5 rsa8f3 rsa8f1 default 0 0 0 0 0 0 0 0 bit 0/sa8 bit of frame 1 (rsa8f1) bit 1/sa8 bit of frame 3 (rsa8f3) bit 2/sa8 bit of frame 5 (rsa8f5) bit 3/sa8 bit of frame 7 (rsa8f7) bit 4/sa8 bit of frame 9 (rsa8f9) bit 5/sa8 bit of frame 11 (rsa8f11) bit 6/sa8 bit of frame 13 (rsa8f13) bit 7/sa8 bit of frame 15 (rsa8f15) register name: tsiaf register description: transmit si bits of the align frame register address: d2h bit # 7 6 5 4 3 2 1 0 name tsif14 tsif12 tsif10 tsif8 tsif6 tsif4 tsif2 tsif0 default 0 0 0 0 0 0 0 0 bit 0/si bit of frame 0 (tsif0) bit 1/si bit of frame 2 (tsif2) bit 2/si bit of frame 4 (tsif4) bit 3/si bit of frame 6 (tsif6) bit 4/si bit of frame 8 (tsif8) bit 5/si bit of frame 10 (tsif10) bit 6/si bit of frame 12 (tsif12) bit 7/si bit of frame 14 (tsif14) downloaded from: http:///
ds2156 128 of 265 register name: tsinaf register description: transmit si bits of the nonalign frame register address: d3h bit # 7 6 5 4 3 2 1 0 name tsif15 tsif13 tsif11 tsif9 tsif7 tsif5 tsif3 tsif1 default 0 0 0 0 0 0 0 0 bit 0/si bit of frame 1 (tsif1) bit 1/si bit of frame 3 (tsif3) bit 2/si bit of frame 5 (tsif5) bit 3/si bit of frame 7 (tsif7) bit 4/si bit of frame 9 (tsif9) bit 5/si bit of frame 11 (tsif11) bit 6/si bit of frame 13 (tsif13) bit 7/si bit of frame 15 (tsif15) register name: tra register description: transmit remote alarm register address: d4h bit # 7 6 5 4 3 2 1 0 name traf15 traf13 traf11 traf9 traf7 traf5 traf3 traf1 default 0 0 0 0 0 0 0 0 bit 0/remote alarm bit of frame 1 (traf1) bit 1/remote alarm bit of frame 3 (traf3) bit 2/remote alarm bit of frame 5 (traf5) bit 3/remote alarm bit of frame 7 (traf7) bit 4/remote alarm bit of frame 9 (traf9) bit 5/remote alarm bit of frame 11 (traf11) bit 6/remote alarm bit of frame 13 (traf13) bit 7/remote alarm bit of frame 15 (traf15) downloaded from: http:///
ds2156 129 of 265 register name: tsa4 register description: transmit sa4 bits register address: d5h bit # 7 6 5 4 3 2 1 0 name tsa4f15 tsa4f13 tsa4f11 tsa4f 9 tsa4f7 tsa4f5 tsa4f3 tsa4f1 default 0 0 0 0 0 0 0 0 bit 0/sa4 bit of frame 1 (tsa4f1) bit 1/sa4 bit of frame 3 (tsa4f3) bit 2/sa4 bit of frame 5 (tsa4f5) bit 3/sa4 bit of frame 7 (tsa4f7) bit 4/sa4 bit of frame 9 (tsa4f9) bit 5/sa4 bit of frame 11 (tsa4f11) bit 6/sa4 bit of frame 13 (tsa4f13) bit 7/sa4 bit of frame 15 (tsa4f15) register name: tsa5 register description: transmitted sa5 bits register address: d6h bit # 7 6 5 4 3 2 1 0 name tsa5f15 tsa5f13 tsa5f11 tsa5f 9 tsa5f7 tsa5f5 tsa5f3 tsa5f1 default 0 0 0 0 0 0 0 0 bit 0/sa5 bit of frame 1 (tsa5f1) bit 1/sa5 bit of frame 3 (tsa5f3) bit 2/sa5 bit of frame 5 (tsa5f5) bit 3/sa5 bit of frame 7 (tsa5f7) bit 4/sa5 bit of frame 9 (tsa5f9) bit 5/sa5 bit of frame 11 (tsa5f11) bit 6/sa5 bit of frame 13 (tsa5f13) bit 7/sa5 bit of frame 15 (tsa5f15) downloaded from: http:///
ds2156 130 of 265 register name: tsa6 register description: transmit sa6 bits register address: d7h bit # 7 6 5 4 3 2 1 0 name tsa6f15 tsa6f13 tsa6f11 tsa6f 9 tsa6f7 tsa6f5 tsa6f3 tsa6f1 default 0 0 0 0 0 0 0 0 bit 0/sa6 bit of frame 1 (tsa6f1) bit 1/sa6 bit of frame 3 (tsa6f3) bit 2/sa6 bit of frame 5 (tsa6f5) bit 3/sa6 bit of frame 7 (tsa6f7) bit 4/sa6 bit of frame 9 (tsa6f9) bit 5/sa6 bit of frame 11 (tsa6f11) bit 6/sa6 bit of frame 13 (tsa6f13) bit 7/sa6 bit of frame 15 (tsa6f15) register name: tsa7 register description: transmit sa7 bits register address: d8h bit # 7 6 5 4 3 2 1 0 name tsa7f15 tsa7f13 tsa7f11 tsa7f 9 tsa7f7 tsa7f5 tsa7f3 tsa7f1 default 0 0 0 0 0 0 0 0 bit 0/sa7 bit of frame 1 (tsa7f1) bit 1/sa7 bit of frame 3 (tsa7f3) bit 2/sa7 bit of frame 5 (tsa7f5) bit 3/sa7 bit of frame 7 (tsa7f7) bit 4/sa7 bit of frame 9 (tsa7f9) bit 5/sa7 bit of frame 11 (tsa7f11) bit 6/sa7 bit of frame 13 (tsa7f13) bit 7/sa7 bit of frame 15 (tsa4f15) downloaded from: http:///
ds2156 131 of 265 register name: tsa8 register description: transmit sa8 bits register address: d9h bit # 7 6 5 4 3 2 1 0 name tsa8f15 tsa8f13 tsa8f11 tsa8f 9 tsa8f7 tsa8f5 tsa8f3 tsa8f1 default 0 0 0 0 0 0 0 0 bit 0/sa8 bit of frame 1 (tsa8f1) bit 1/sa8 bit of frame 3 (tsa8f3) bit 2/sa8 bit of frame 5 (tsa8f5) bit 3/sa8 bit of frame 7 (tsa8f7) bit 4/sa8 bit of frame 9 (tsa8f9) bit 5/sa8 bit of frame 11 (tsa8f11) bit 6/sa8 bit of frame 13 (tsa8f13) bit 7/sa8 bit of frame 15 (tsa8f15) downloaded from: http:///
ds2156 132 of 265 register name: tsacr register description: transmit sa bit control register register address: dah bit # 7 6 5 4 3 2 1 0 name siaf sinaf ra sa4 sa5 sa6 sa7 sa8 default 0 0 0 0 0 0 0 0 bit 0/additional bit 8 insertion control bit (sa8) 0 = do not insert data from the tsa8 register into the transmit data stream 1 = insert data from the tsa8 register into the transmit data stream bit 1/additional bit 7 insertion control bit (sa7) 0 = do not insert data from the tsa7 register into the transmit data stream 1 = insert data from the tsa7 register into the transmit data stream bit 2/additional bit 6 insertion control bit (sa6) 0 = do not insert data from the tsa6 register into the transmit data stream 1 = insert data from the tsa6 register into the transmit data stream bit 3/additional bit 5 insertion control bit (sa5) 0 = do not insert data from the tsa5 register into the transmit data stream 1 = insert data from the tsa5 register into the transmit data stream bit 4/additional bit 4 insertion control bit (sa4) 0 = do not insert data from the tsa4 register into the transmit data stream 1 = insert data from the tsa4 register into the transmit data stream bit 5/remote alarm insertion control bit (ra) 0 = do not insert data from the tra register into the transmit data stream 1 = insert data from the tra register into the transmit data stream bit 6/international bit in nonalign frame insertion control bit (sinaf) 0 = do not insert data from the tsinaf register into the transmit data stream 1 = insert data from the tsinaf register into the transmit data stream bit 7/international bit in align frame insertion control bit (siaf) 0 = do not insert data from the tsiaf register into the transmit data stream 1 = insert data from the tsiaf register into the transmit data stream downloaded from: http:///
ds2156 133 of 265 22. hdlc controllers this device has two enhanced hdlc controlle rs, hdlc #1 and hdlc #2. each controller is configurable for use with time slots, sa4 to sa8 bits (e1 mode), or the fdl (t1 mode). each hdlc controller has 128-byte buffers in the transmit and receive paths. when used with time slots, the user can select any time slot or multiple time slots, conti guous or noncontiguous, as well as any specific bits within the time slot(s) to assign to the hdlc controllers. the user must not map both transmit hdlc controllers to the same sa bits, time slots or, in t1 mode, map both controllers to the fdl. hdlc #1 and hdlc #2 are identical in operation and therefore the following operational description refe rs only to a singular controller. the hdlc controller performs the entire necessary overhead for generating and receiving performance report messages (prms) as described in ansi t1.403 and the messages as described in at&t tr54016. the hdlc controller automatically generates and detects flags, ge nerates and checks the crc check sum, generates and detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream. the 128-byte buffers in the hdlc cont roller are large enough to allow a full pr m to be received or transmitted without host intervention. 22.1 basic operation details the hdlc registers are divided into four groups: control/configura tion, status/information, mapping, and fifos. table 22-a lists these registers by group. 22.2 hdlc configuration the hxtc and hxrc registers perform the basic c onfiguration of the hdlc controllers. operating features such as crc generation, zero stuffer, transmit and rece ive hdlc mapping options, and idle flags are selected here. these regist ers also reset the hdlc controllers. downloaded from: http:///
ds2156 134 of 265 table 22-a. hdlc controller registers register function control and configuration h1tc , hdlc #1 transmit control register h2tc , hdlc #2 transmit control register general control over the transmit hdlc controllers h1rc , hdlc #1 receive control register h2rc , hdlc #2 receive control register general control over the receive hdlc controllers h1fc , hdlc #1 fifo control register h2fc , hdlc #2 fifo control register sets high watermark for receiver and low watermark for transmitter status and information sr6 , hdlc #1 status register sr7 , hdlc #2 status register key status information for both transmit and receive directions imr6 , hdlc #1 interrupt mask register imr7 , hdlc #2 interrupt mask register selects which bits in the status registers (sr7 and sr8) cause interrupts info4 , hdlc #1 and #2 information register info5 , hdlc #1 information register info6 , hdlc #2 information register information about hdlc controller h1rpba , hdlc #1 receive packet bytes available register h2rpba , hdlc #2 receive packet bytes available register indicates the number of bytes that can be read from the receive fifo h1tfba , hdlc #1 transmit fifo buffer available register h2tfba , hdlc #2 transmit fifo buffer available register indicates the number of bytes that can be written to the transmit fifo mapping h1rcs1, h1rcs2, h1rcs3, h1rcs4, hdlc #1 receive channel select registers h2rcs1, h2rcs2, h2rcs3, h2rcs4, hdlc #2 receive channel select registers selects which channels are mapped to the receive hdlc controller h1rtsbs, hdlc #1 receive ts/sa bit select register h2rtsbs, hdlc #2 receive ts/sa bit select register selects which bits in a channel are used or which sa bits are used by the receive hdlc controller h1tcs1, h1tcs2, h1tcs3, h1tcs4, hdlc #1 transmit channel select registers h2tcs1, h2tcs2, h2tcs3, h2tcs4, hdlc #2 transmit channel select registers selects which channels are mapped to the transmit hdlc controller h1ttsbs, hdlc # 1 transmit ts/sa bit select register h2ttsbs, hdlc # 2 transmit ts/sa bit select register selects which bits in a channel are used or which sa bits are used by the transmit hdlc controller fifos h1rf , hdlc #1 receive fifo register h2rf , hdlc #1 receive fifo register access to 128-byte receive fifo h1tf , hdlc #1 transmit fifo register h2tf , hdlc #2 transmit fifo register access to 128-byte transmit fifo downloaded from: http:///
ds2156 135 of 265 register name: h1tc, h2tc register description: hdlc #1 transmit control hdlc #2 transmit control register address: 90h, a0h bit # 7 6 5 4 3 2 1 0 name nofs teoml thr thms tfs teom tzsd tcrcd default 0 0 0 0 0 0 0 0 bit 0/transmit crc defeat (tcrcd). a 2-byte crc code is automatically appended to the outbound message. this bit can be used to disable the crc function. 0 = enable crc generation (normal operation) 1 = disable crc generation bit 1/transmit zero-stuffer defeat (tzsd). the zero-stuffer function automatically inserts a 0 in the message field (between the flags) after five consecutive 1s to prev ent the emulation of a flag or abort sequence by the data pattern. the receiver automatically removes (destuffs ) any 0 after five 1s in the message field. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer bit 2/transmit end of message (teom). should be set to a 1 just before the last data byte of an hdlc packet is written into the transmit fifo at hxtf. if not disabled through tcrcd, the transmitter automatically appends a 2- byte crc code to the end of the message. bit 3/transmit flag/idle select (tfs). this bit selects the intermessage fill char acter after the closing and before the opening flags (7eh). 0 = 7eh 1 = ffh bit 4/transmit hdlc mapping select (thms) 0 = transmit hdlc assigned to channels 1 = transmit hdlc assigned to fdl (t1 mode), sa bits (e1 mode) bit 5/transmit hdlc reset (thr). resets the transmit hdlc controller and flushes the transmit fifo. an abort followed by 7eh or ffh flags/idle is transmitted un til a new packet is initiated by writing new data into the fifo. must be cleared and set again for a subsequent reset. 0 = normal operation 1 = reset transmit hdlc controller and flush the transmit fifo bit 6/transmit end of message and loop (teoml). to loop on a message, this bit should be set to a 1 just before the last data byte of an hdlc packet is written into the transmit fifo. the me ssage repeats until the user clears this bit or a new message is written to the tran smit fifo. if the host clears the bit, the looping message completes, then flags are transmitted until a new message is written to the fifo. if the host terminates the loop by writing a new message to the fifo, the loop terminates, one or two flags are transmitted, and the new message starts. if not disabled through tcrcd, the transmitter automa tically appends a 2-byte crc code to the end of all messages. this is useful for transmitting consecutive ss7 fisus without host intervention. bit 7/number of flags select (nofs) 0 = send one flag between consecutive messages 1 = send two flags between consecutive messages downloaded from: http:///
ds2156 136 of 265 register name: h1rc, h2rc register description: hdlc #1 receive control hdlc #2 receive control register address: 31h, 32h bit # 7 6 5 4 3 2 1 0 name rhr rhms rsfd default 0 0 0 0 0 0 0 0 bit 0/receive ss7 fill-in signal unit delete (rsfd) 0 = normal operation; all fisus are stored in the receive fifo and reported to the host. 1 = when a consecutive fisu having the same bsn the previous fisu is detected, it is deleted without host intervention. bits 1 to 5/unused, must be set to 0 or proper operation bit 6/receive hdlc mapping select (rhms) 0 = receive hdlc assigned to channels 1 = receive hdlc assigned to fdl (t1 mode), sa bits (e1 mode) bit 7/receive hdlc reset (rhr). resets the receive hdlc controller and flushes the receive fifo. must be cleared and set again for a subsequent reset. 0 = normal operation 1 = reset receive hdlc controller and flush the receive fifo downloaded from: http:///
ds2156 137 of 265 22.2.1 fifo control the fifo control register (hxfc) controls and sets the watermarks for the transmit and receive fifos. bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. when the transmit fifo empties below the low watermark, the tlwm bit in the appropriate hdlc status register sr6 or sr7 is set. tlwm is a real- time bit and remains set as long as the transmit fifos read pointer is below the watermark. if enabled, th is condition can also caus e an interrupt through the int pin. when the receive fifo fills above the high waterm ark, the rhwm bit in the appropriate hdlc status register is set. rhwm is a real- time bit and remains set as long as th e receive fifos write pointer is above the watermark. if enabled, this conditi on can also cause an interrupt through the int pin. register name: h1fc, h2fc register description: hdlc # 1 fifo control hdlc # 2 fifo control register address: 91h, a1h bit # 7 6 5 4 3 2 1 0 name tflwm2 tflwm1 tflwm0 rfhwm2 rfhwm1 rfhwm0 default 0 0 0 0 0 0 0 0 bits 0 to 2/receive fifo high-watermark select (rfhwm0 to rfhwm2) rfhwm2 rfhwm1 rfhwm0 receive fifo watermark (bytes) 0 0 0 4 0 0 1 16 0 1 0 32 0 1 1 48 1 0 0 64 1 0 1 80 1 1 0 96 1 1 1 112 bits 3 to 5/transmit fifo low-watermark select (tflwm0 to tflwm2) tflwm2 tflwm1 tflwm0 transmit fifo watermark (bytes) 0 0 0 4 0 0 1 16 0 1 0 32 0 1 1 48 1 0 0 64 1 0 1 80 1 1 0 96 1 1 1 112 bits 6, 7/unused, must be set to 0 for proper operation downloaded from: http:///
ds2156 138 of 265 22.3 hdlc mapping 22.3.1 receive the hdlc controllers must be assigned a space in the t1/e1 bandwidth in which they transmit and receive data. the controllers can be mapped to either the fdl (t1), sa bits (e1), or to channels. if mapped to channels, then any channel or combination of channels, contiguous or not, can be assigned to an hdlc controller. when assigned to a channel(s), a ny combination of bits within the channel(s) can be avoided. the hxrcs1Chxrcs4 registers are used to assign the receive cont rollers to channels 1C24 (t1) or 1C32 (e1) according to the following table: register channels hxrcs1 1C8 hxrcs2 9C16 hxrcs3 17C24 hxrcs4 25C32 register name: h1rcs1, h1rcs2, h1rcs3, h1rcs4 h2rcs1, h2rcs2, h2rcs3, h2rcs4 register description: hdlc # 1 receive channel select x hdlc # 2 receive channel select x register address: 92h, 93h, 94h, 95h a2h, a3h, a4h, a5h bit # 7 6 5 4 3 2 1 0 name rhcs7 rhcs6 rhcs5 rhcs4 rhcs3 rhcs2 rhcs1 rhcs0 default 0 0 0 0 0 0 0 0 bit 0/receive hdlc channel select bit 0 (rhcs0). select channel 1, 9, 17, or 25. bit 1/receive hdlc channel select bit 1 (rhcs1). select channel 2, 10, 18, or 26. bit 2/receive hdlc channel select bit 2 (rhcs2). select channel 3, 11, 19, or 27. bit 3/receive hdlc channel select bit 3 (rhcs3). select channel 4, 12, 20, or 28. bit 4/receive hdlc channel select bit 4 (rhcs4). select channel 5, 13, 21, or 29. bit 5/receive hdlc channel select bit 5 (rhcs5). select channel 6, 14, 22, or 30. bit 6/receive hdlc channel select bit 6 (rhcs6). select channel 7, 15, 23, or 31. bit 7/receive hdlc channel select bit 7 (rhcs7). select channel 8, 16, 24, or 32. downloaded from: http:///
ds2156 139 of 265 register name: h1rtsbs, h2rtsbs register description: hdlc # 1 receive time slot bits/sa bits select hdlc # 2 receive time slot bits/sa bits select register address: 96h, a6h bit # 7 6 5 4 3 2 1 0 name rcb8se rcb7se rcb6se rcb5se rcb4se rcb3se rcb2se rcb1se default 0 0 0 0 0 0 0 0 bit 0/receive channel bit 1 suppress enable/sa8 bit enable (rcb1se ). lsb of the channel. set to 1 to stop this bit from being used. bit 1/receive channel bit 2 suppress enable/sa7 bit enable (rcb2se). set to 1 to stop this bit from being used. bit 2/receive channel bit 3 suppress enable/sa6 bit enable (rcb3se). set to 1 to stop this bit from being used. bit 3/receive channel bit 4 suppress enable/sa5 bit enable (rcb4se). set to 1 to stop this bit from being used. bit 4/receive channel bit 5 suppress enable/sa4 bit enable (rcb5se). set to 1 to stop this bit from being used. bit 5/receive channel bit 6 suppress enable (rcb6se). set to 1 to stop this bit from being used. bit 6/receive channel bit 7 suppress enable (rcb7se). set to 1 to stop this bit from being used. bit 7/receive channel bit 8 suppress enable (rcb8se). msb of the channel. set to 1 to stop this bit from being used. downloaded from: http:///
ds2156 140 of 265 22.3.2 transmit the hxtcs1Chxtcs4 registers are us ed to assign the transmit controllers to channels 1C24 (t1) or 1C32 (e1) according to the following table. register channels hxtcs1 1C8 hxtcs2 9C16 hxtcs3 17C24 hxtcs4 25C32 register name: h1tcs1, h1tcs2, h1tcs3, h1tcs4 h2tcs1, h2tcs2, h2tcs3, h2tcs4 register description: hdlc # 1 transmit channel select hdlc # 2 transmit channel select register address: 97h, 98h, 99h, 9ah a7h, a8h, a9h, aah bit # 7 6 5 4 3 2 1 0 name thcs7 thcs6 thcs5 thcs4 thcs3 thcs2 thcs1 thcs0 default 0 0 0 0 0 0 0 0 bit 0/transmit hdlc channel select bit 0 (thcs0). select channel 1, 9, 17, or 25. bit 1/transmit hdlc channel select bit 1 (thcs1). select channel 2, 10, 18, or 26. bit 2/transmit hdlc channel select bit 2 (thcs2). select channel 3, 11, 19, or 27. bit 3/transmit hdlc channel select bit 3 (thcs3). select channel 4, 12, 20, or 28. bit 4/transmit hdlc channel select bit 4 (thcs4). select channel 5, 13, 21, or 29. bit 5/transmit hdlc channel select bit 5 (thcs5). select channel 6, 14, 22, or 30. bit 6/transmit hdlc channel select bit 6 (thcs6). select channel 7, 15, 23, or 31. bit 7/transmit hdlc channel select bit 7 (thcs7). select channel 8, 16, 24, or 32. downloaded from: http:///
ds2156 141 of 265 register name: h1ttsbs, h2ttsbs register description: hdlc # 1 transmit time slot bits/sa bits select hdlc # 2 transmit time slot bits/sa bits select register address: 9bh, abh bit # 7 6 5 4 3 2 1 0 name tcb8se tcb7se tcb6se tcb5 se tcb4se tcb3se tcb2se tcb1se default 0 0 0 0 0 0 0 0 bit 0/transmit channel bit 1 suppress enable/sa8 bit enable (tcb1se). lsb of the channel. set to 1 to stop this bit from being used. bit 1/transmit channel bit 2 suppress enable/sa7 bit enable (tcb1se). set to 1 to stop this bit from being used. bit 2/transmit channel bit 3 suppress enable/sa6 bit enable (tcb1se). set to 1 to stop this bit from being used. bit 3/transmit channel bit 4 suppress enable/sa5 bit enable (tcb1se). set to 1 to stop this bit from being used. bit 4/transmit channel bit 5 suppress enable/sa4 bit enable (tcb1se). set to 1 to stop this bit from being used. bit 5/transmit channel bit 6 suppress enable (tcb1se). set to 1 to stop this bit from being used. bit 6/transmit channel bit 7 suppress enable (tcb1se). set to 1 to stop this bit from being used. bit 7/transmit channel bit 8 suppress enable (tcb1se). msb of the channel. set to 1 to stop this bit from being used. downloaded from: http:///
ds2156 142 of 265 register name: sr6, sr7 register description: hdlc #1 status register 6 hdlc #2 status register 7 register address: 20h, 22h bit # 7 6 5 4 3 2 1 0 name tmend rpe rps rhwm rne tlwm tnf default 0 0 0 0 0 0 0 0 bit 0/transmit fifo not full condition (tnf). set when the transmit 128-byte fifo has at least 1 byte available. bit 1/transmit fifo below low-watermark condition (tlwm). set when the transmit 128-byte fifo empties beyond the low watermark as defined by the transmit low-watermark register (tlwmr). bit 2/receive fifo not empty condition (rne). set when the receive 128-byte fifo has at least 1 byte available for a read. bit 3/receive fifo above high-watermark condition (rhwm). set when the receive 128-byte fifo fills beyond the high watermark as defined by the r eceive high-watermark register (rhwmr). bit 4/receive packet-start event (rps) . set when the hdlc controller detects an opening byte. this is a latched bit and is cleared when read. bit 5/receive packet-end event (rpe). set when the hdlc controller detects either the finish of a valid message (i.e., crc check complete) or when the cont roller has experienced a me ssage fault such as a crc checking error, or an overrun condition, or an abort has b een seen. this is a latched bit and is cleared when read. bit 6/transmit message-end event (tmend). set when the transmit hdlc controller has finished sending a message. this is a latched bit and is cleared when read. downloaded from: http:///
ds2156 143 of 265 register name: imr6, imr7 register description: hdlc # 1 interrupt mask register 6 hdlc # 2 interrupt mask register 7 register address: 21h, 23h bit # 7 6 5 4 3 2 1 0 name tmend rpe rps rhwm rne tlwm tnf default 0 0 0 0 0 0 0 0 bit 0/transmit fifo not full condition (tnf) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising edge only bit 1/transmit fifo below low-watermark condition (tlwm) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising edge only bit 2/receive fifo not empty condition (rne) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising edge only bit 3/receive fifo above high-watermark condition (rhwm) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising edge only bit 4/receive packet-start event (rps) 0 = interrupt masked 1 = interrupt enabled bit 5/receive packet-end event (rpe) 0 = interrupt masked 1 = interrupt enabled bit 6/transmit message-end event (tmend) 0 = interrupt masked 1 = interrupt enabled downloaded from: http:///
ds2156 144 of 265 register name: info5, info6 register description: hdlc #1 information register hdlc #2 information register register address: 2eh, 2fh bit # 7 6 5 4 3 2 1 0 name tempty tfull rempty ps2 ps1 ps0 default 0 0 0 0 0 0 0 0 bits 0 to 2/receive packet status (ps0 to ps2) . these are real-time bits indicating the status as of the last read of the receive fifo. ps2 ps1 ps0 packet status 0 0 0 in progress 0 0 1 packet ok: packet ended with correct crc codeword 0 1 0 crc error: a closing flag was detected, preceded by a corrupt crc codeword 0 1 1 abort: packet ended because an abort signal was detected (seven or more 1s in a row). 1 0 0 overrun: hdlc controller terminated reception of packet because receive fifo is full. bit 3/receive fifo empty (rempty). a real-time bit that is set high when the receive fifo is empty. bit 4/transmit fifo full (tfull). a real-time bit that is set high when the fifo is full. bit 5/transmit fifo empty (tempty). a real-time bit that is set high when the fifo is empty. register name: info4 register description: hdlc event information register #4 register address: 2dh bit # 7 6 5 4 3 2 1 0 name h2udr h2obt h1udr h1obt default 0 0 0 0 0 0 0 0 bit 0/hdlc #1 opening byte event (h1obt). set when the next byte available in the receive fifo is the first byte of a message. bit 1/hdlc #1 transmit fi fo underrun event (h1udr). set when the transmit fifo empties out without having seen the tmend bit set. an abort is automatically sent. this bit is latched and is cleared when read. bit 2/hdlc #2 opening byte event (h2obt). set when the next byte available in the receive fifo is the first byte of a message. bit 3/hdlc #2 transmit fi fo underrun event (h2udr). set when the transmit fifo empties out without having seen the tmend bit set. an abort is automatically sent. this bit is latched and is cleared when read . downloaded from: http:///
ds2156 145 of 265 22.3.3 fifo information the transmit fifo buffer-available re gister indicates the number of byt es that can be written into the transmit fifo. the count form this register informs th e host as to how many bytes can be written into the transmit fifo without overflowing the buffer. register name: h1tfba, h2tfba register description: hdlc # 1 transmit fifo buffer available hdlc # 2 transmit fifo buffer available register address: 9fh, afh bit # 7 6 5 4 3 2 1 0 name tfba7 tfba6 tfba5 tfba4 tfba3 tfba2 tfba1 tfba0 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit fifo bytes available (tfbao to tfba7). tfba0 is the lsb. 22.3.4 receive packet-bytes available the lower 7 bits of the receive p acket-bytes available register indi cates the number of bytes (0 through 127) that can be read from the receive fifo. the va lue indicated by this regi ster (lower seven bits) informs the host as to how many bytes can be read from the receive fifo without going past the end of a message. this value refers to one of four possibilities: the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet. after reading th e number of bytes indicated by this register, the host then checks the hdlc inform ation register for detailed message status. if the value in the hxrpba register refers to th e beginning portion of a message or continuation of a message, then the msb of the hxrpba register retu rns a value of 1. this i ndicates that the host can safely read the number of bytes returned by the lowe r seven bits of the hxrpba register, but there is no need to check the information register since the packet has not yet terminated (s uccessfully or otherwise). register name: h1rpba, h2rpba register description: hdlc # 1 receive packet bytes available hdlc # 2 receive packet bytes available register address: 9ch, ach bit # 7 6 5 4 3 2 1 0 name ms rpba6 rpba5 rpba4 rpba3 rpba2 rpba1 rpba0 default 0 0 0 0 0 0 0 0 bits 0 to 6/receive fifo packet bytes available count (rpba0 to rpba6). rpba0 is the lsb. bit 7/message status (ms) 0 = bytes indicated by rpba0 through rpba6 are the end of a message. host must check the info5 or info6 register for details. 1 = bytes indicated by rpba0 through rpba6 are the beginning or continuation of a message. the host does not need to check the info5 or info6 register. downloaded from: http:///
ds2156 146 of 265 22.3.5 hdlc fifos register name: h1tf, h2tf register description: hdlc # 1 transmit fifo hdlc # 2 transmit fifo register address: 9dh, adh bit # 7 6 5 4 3 2 1 0 name thd7 thd6 thd5 thd4 thd3 thd2 thd1 thd0 default 0 0 0 0 0 0 0 0 bit 0/transmit hdlc data bit 0 (thd0). lsb of an hdlc packet data byte. bit 1/transmit hdlc data bit 1 (thd1) bit 2/transmit hdlc data bit 2 (thd2) bit 3/transmit hdlc data bit 3 (thd3) bit 4/transmit hdlc data bit 4 (thd4) bit 5/transmit hdlc data bit 5 (thd5) bit 6/transmit hdlc data bit 6 (thd6) bit 7/transmit hdlc data bit 7 (thd7). msb of an hdlc packet data byte. register name: h1rf, h2rf register description: hdlc # 1 receive fifo hdlc # 2 receive fifo register address: 9eh, aeh bit # 7 6 5 4 3 2 1 0 name rhd7 rhd6 rhd5 rhd4 rhd3 rhd2 rhd1 rhd0 default 0 0 0 0 0 0 0 0 bit 0/receive hdlc data bit 0 (rhd0). lsb of an hdlc packet data byte. bit 1/receive hdlc data bit 1 (rhd1) bit 2/receive hdlc data bit 2 (rhd2) bit 3/receive hdlc data bit 3 (rhd3) bit 4/receive hdlc data bit 4 (rhd4) bit 5/receive hdlc data bit 5 (rhd5) bit 6/receive hdlc data bit 6 (rhd6) bit 7/receive hdlc data bit 7 (rhd7). msb of an hdlc packet data byte. downloaded from: http:///
ds2156 147 of 265 22.4 receive hdlc code example the following is an example of a receive hdlc routine: 1) reset receive hdlc controller. 2) set hdlc mode, mapping, and high watermark. 3) start new message buffer. 4) enable rpe and rhwm interrupts. 5) wait for interrupt. 6) disable rpe and rhwm interrupts. 7) read hxrpba register. n = hxrpba (lower 7 bits are byte count, msb is status). 8) read (n and 7fh) bytes from receive fifo and store in message buffer. 9) read info5 register. 10) if ps2, ps1, ps0 = 000, then go to step 4. 11) if ps2, ps1, ps0 = 001, then packet terminated ok, save present message buffer. 12) if ps2, ps1, ps0 = 010, then packet terminated with crc error. 13) if ps2, ps1, ps0 = 011, then packet aborted. 14) if ps2, ps1, ps0 = 100, then fifo overflowed. 15) go to step 3. 22.5 legacy fdl support (t1 mode) 22.5.1 overview to provide backward compatibility to the older ds21x52 t1 device, the ds2156 maintains the circuitry that existed in the previous generation of the t1 fr amer. in new applications, it is recommended that the hdlc controllers and boc controller desc ribed in section 20 and 22 are used. 22.5.2 receive section in the receive section, the recovere d fdl bits or fs bits are shifte d bit-by-bit into the receive fdl register (rfdl). because the rfdl is 8 bits in length, it fills up every 2ms (8 x 250s). the framer signals an external microcontroller that the buffer has filled through the sr8.3 bit. if enabled through imr8.3, the int pin toggles low, indicating that the buffer has filled and needs to be read. the user has 2ms to read this data before it is lost. if the byte in the rfdl matches either of the bytes programmed into the rfdlm1 or rfdlm2 registers, then the sr8.1 bit is set to a 1 and the int pin toggles low if enabled through imr8.1. this feature al lows an external microcontroller to ignore the fdl or fs pattern until an important event occurs. the framer also contains a zero destuffer, which is controlled th rough the t1rcr2.3 bit. in both ansi t1.403 and tr54016, communications on the fdl follows a subset of an lapd protocol. the lapd protocol states that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abor t signal (11111111). if enab led through t1rcr2.3, the ds2156 automatically looks for five 1s in a row, followed by a 0. if it finds such a pattern, it automatically removes the zero. if the zero destuffer s ees six or more 1s in a ro w followed by a 0, the 0 is not removed. the t1rcr2.3 bit should always be se t to a 1 when the ds2156 is extracting the fdl. refer to application note 335: ds2141a , ds2151 controlling the fdl for information about using the ds2156 in fdl applications in this legacy support mode. downloaded from: http:///
ds2156 148 of 265 register name: rfdl register description: receive fdl register register address: c0h bit # 7 6 5 4 3 2 1 0 name rfdl7 rfdl6 rfdl5 rfdl4 rfdl3 rfdl2 rfdl1 rfdl0 default 0 0 0 0 0 0 0 0 the receive fdl register (rfdl) reports the incoming fd l or the incoming fs bits. the lsb is received first. bit 0/receive fdl bit 0 (rfdl0). lsb of the received fdl code. bit 1/receive fdl bit 1 (rfdl1) bit 2/receive fdl bit 2 (rfdl2) bit 3/receive fdl bit 3 (rfdl3) bit 4/receive fdl bit 4 (rfdl4) bit 5/receive fdl bit 5 (rfdl5) bit 6/receive fdl bit 6 (rfdl6) bit 7/receive fdl bit 7 (rfdl7). msb of the received fdl code. register name: rfdlm1, rfdlm2 register description: receive fdl match register 1 receive fdl match register 2 register address: c2h, c3h bit # 7 6 5 4 3 2 1 0 name rfdlm7 rfdlm6 rfdlm5 rfdlm4 rfdlm3 rfdlm2 rfdlm1 rfdlm0 default 0 0 0 0 0 0 0 0 bit 0/receive fdl match bit 0 (rfdlm0). lsb of the fdl match code. bit 1/receive fdl match bit 1 (rfdlm1) bit 2/receive fdl match bit 2 (rfdlm2) bit 3/receive fdl match bit 3 (rfdlm3) bit 4/receive fdl match bit 4 (rfdlm4) bit 5/receive fdl match bit 5 (rfdlm5) bit 6/receive fdl match bit 6 (rfdlm6) bit 7/receive fdl match bit 7 (rfdlm7). msb of the fdl match code. downloaded from: http:///
ds2156 149 of 265 22.5.3 transmit section the transmit section shifts out into the t1 data stream either the fdl (in the esf framing mode) or the fs bits (in the d4 framing mode) contained in the transmit fdl regist er (tfdl). when a new value is written to the tfdl, it is multiplexed serially (lsb first) into the prope r position in the outgoing t1 data stream. after the full 8 bits have been shifted out, the framer signals the host microcontroller by setting the sr8.2 bit to a 1 that the buffer is empty and that more data is needed. the int also toggles low if enabled through imr8.2. the user has 2ms to update th e tfdl with a new value. if the tfdl is not updated, the old value in the tfdl is transmitted once again. the framer al so contains a zero stuffer that is controlled through the t1t cr2.5 bit. in both ansi t1.403 a nd tr54016, communications on the fdl follows a subset of an lapd protocol. the lapd prot ocol states that no more than five 1s should be transmitted in a row so that the da ta does not resemble an opening or closing flag (01111110) or an abort signal (11111111). if enabled th rough t1tcr2.5, the framer automatically looks for five 1s in a row. if it finds such a pattern, it automatica lly inserts a 0 after the five 1s. th e t1tcr2.5 bit should always be set to a 1 when the framer is inserting the fdl. register name: tfdl register description: transmit fdl register register address: c1h bit # 7 6 5 4 3 2 1 0 name tfdl7 tfdl6 tfdl5 tfdl4 tfdl3 tfdl2 tfdl1 tfdl0 default 0 0 0 0 0 0 0 0 note: also used to insert fs framing pattern in d4 framing mode. the transmit fdl register (tfdl) contains the fdl information that is to be inserted on a byte basis into the outgoing t1 data stream. the lsb is transmitted first. bit 0/transmit fdl bit 0 (tfdl0). lsb of the transmit fdl code. bit 1/transmit fdl bit 1 (tfdl1) bit 2/transmit fdl bit 2 (tfdl2) bit 3/transmit fdl bit 3 (tfdl3) bit 4/transmit fdl bit 4 (tfdl4) bit 5/transmit fdl bit 5 (tfdl5) bit 6/transmit fdl bit 6 (tfdl6) bit 7/transmit fdl bit 7 (tfdl7). msb of the transmit fdl code. 22.6 d4/slc-96 operation in the d4 framing mode, the framer uses the tfdl regi ster to insert the fs framing pattern. to allow the device to properly insert the fs fram ing pattern, the tfdl register at address c1h must be programmed to 1ch and the following bits must be programmed as shown: t1tcr1.2 = 0 (source fs data from the tfdl register) t1tcr2.6 = 1 (allow the tfdl register to load on multiframe boundaries) since the slc-96 message fields share the fs-bit po sition, the user can access these message fields through the tfdl and rfdl registers. refer to application note 345: ds2141a, ds2151, ds2152 slc- 96 for a detailed description about implementing an slc-96 function. downloaded from: http:///
ds2156 150 of 265 23. line interface unit (liu) the liu contains three sections: the receiver that ha ndles clock and data recovery, the transmitter that waveshapes and drives the t1 line, a nd the jitter attenuator. these three sections are controlled by the line interface control registers (lic1Clic4), which are de scribed in the following sections. the liu has its own t1/e1 mode-select bit and can operate independently of the framer function. the ds2156 can switch between t1 or e1 networks without changing any extern al components on either the transmit or receive side. figure 23-3 shows a ne twork connection using mini mal components. in this configuration, the ds2156 can connect to t1, j1, or e1 (75 ? or 120 ? ) without any component change. the receiver can adjust the 120 ? termination to 100 ? or 75 ? . the transmitter can adjust its output impedance to provide high return-loss characteristics for 120 ? , 100 ? , and 75 ? lines. other components can be added to this configurati on to meet safety and network pr otection requirements (section 23.8). 23.1 liu operation the analog ami/hdb3 waveform off the e1 line or the ami/b8zs waveform off of the t1 line is transformer-coupled into the rtip and rring pins of the ds2156. the user has the option to use internal termination, software selectable for 75 ? /100 ? /120 ? applications, or external termination. the liu recovers clock and data from the analog signal and passes it through the jitter-attenuation mux outputting the received line clock at rclko and bipolar or nrz da ta at rposo and rnego. the ds2156 contains an active filter that reconstructs th e analog-received signal for the nonlinear losses that occur in transmission. the receive circuitry also is configurable for various monitor applications. the device has a usable receive sensitiv ity of 0db to -43db for e1 and 0db to -36db for t1, which allow the device to operate on 0.6 3mm (22awg) cables up to 2.5km (e1) and 6k feet (t1) in le ngth. data input at tposi and tnegi is sent through th e jitter-attenuation mux to the wave shaping circuitry and line driver. the ds2156 drives the e1 or t1 line from the tti p and tring pins through a coupling transformer. the line driver can handle both cept 30/isdn-pri lin es for e1 and long-haul (csu) or short-haul (dsx-1) lines for t1. 23.2 receiver the ds2156 contains a digi tal clock recovery system. the ds2156 couples to the receive e1 or t1 twisted pair (or coaxial cable in 75 ? e1 applications) through a 1:1 transformer. see table 23-a for transformer details. the ds2156 has the option of using software-selec table termination requiring only a single fixed pair of te rmination resistors. the ds2156s liu is designed to be fully software selectable for e1 and t1, requiring no change to any external resistors for the receive side. the receive side allows the user to configure the ds2156 for 75 ? , 100 ? , or 120 ? receive termination by setti ng the rt1 (lic4.1) and rt0 (l ic4.0) bits. when using the internal termination feature, the resist ors labeled r in fi gure 23-3 should be 60 ? each. if external termination is used, rt1 and rt0 should be set to 0 and the resistors labeled r in figure 23-3 should be 37.5 ? , 50 ? , or 60 ? each, depending on the line impedance. there are two ranges of user-selectable receive sensit ivity for t1 and e1. the egl bit of lic1 (lic1.4) selects the full or limited sensitivity. the resultant e1 or t1 clock derived from mclk is multiplied by 16 through an internal pll and fed to the clock recovery system. the clock recovery system uses the clock from the pll circuit to form a 16-times over-sam pler that is used to r ecover the clock and data. this over-sampling technique offers outstanding perf ormance to meet jitter tolerance specifications shown in figure 23-7. downloaded from: http:///
ds2156 151 of 265 normally, the clock that is output at the rclk pin is the recovered cl ock from the e1 ami/hdb3 or t1 ami/b8zs waveform presented at th e rtip and rring inputs. if the jit ter attenuator is placed in the receive path (as is the case in most applications ), the jitter attenuator restores the rclk to an approximate 50% duty cycle. if the jitt er attenuator is either placed in the transmit path or is disabled, the rclk output can exhibit slig htly shorter high cycles of the cloc k. this is because of the highly over- sampled digital-clock recovery circuitry. see the receive ac timing characteristics in section 36.3 for more details. when no signal is present at rt ip and rring, a receive car rier loss (rcl) condition occurs and the rclk is derived from the jaclk source. 23.2.1 receive level indicator and threshold interrupt the ds2156 reports the signal stre ngth at rtip and rring in 2.5db increments through rl3Crl0 located in information register 2 (info2). this feature is helpful when trouble-shooting line- performance problems. the ds2156 can initiate an in terrupt whenever the input falls below a certain level through the input-level under-threshold indicat or (sr1.7). using the rlt0Crlt4 bits of the ccr4 register, the user can set a threshold in 2.5db increments. the sr1.7 bit is set whenever the input level at rtip and rring falls below the threshold set by the value in rlt0Crlt4. the level must remain below the programmed threshold for approxima tely 50ms for this bit to be set. 23.2.2 receive g.703 synchroni zation signal (e1 mode) the ds2156 is capable of receiving a 2.048mhz squa re-wave synchronization clock as specified in section 13 of itu g.703, october 1998. in order to use the ds2156 in this mode, set the receive synchronization clock enable (lic3.2) = 1. 23.2.3 monitor mode monitor applications in both e1 and t1 require various flat gain settings for the receive-side circuitry. the ds2156 can be programmed to support these appli cations through the monitor mode control bits mm1 and mm0 in the lic3 register (figure 23-1). figure 23-1. typical monitor application primary t1/e1 terminating device monitor port jack t1/e1 line xf m r ds2156 rt rm rm secondary t1/e1 terminating device downloaded from: http:///
ds2156 152 of 265 23.3 transmitter the ds2156 uses a phase-lock loop along with a precis ion digital-to-analog conv erter (dac) to create the waveforms that are transmitted onto the e1 or t1 line. the waveforms created by the ds2156 meet the latest etsi, itu, ansi, and at&t specifications . the user selects which waveform is generated by setting the ets bit (lic2.7) for e1 or t1 operation, then programming the l2/l1/l0 bits in register lic1 for the appropriate application. a 2.048mhz or 1.544mhz clock is required at tclk i for transmitting data presented at tposi and tnegi. normally these pins are connected to tc lko, tposo, and tnego. however, the liu can operate in an independent fashion. itu specificati on g.703 requires an accuracy of 50ppm for both t1 and e1. tr62411 and ansi specifications require an accu racy of 32ppm for t1 interfaces. the clock can be sourced internally from rclk or jaclk. see lic2.3, lic4.4, and lic4.5 for details. because of the nature of the transmitters design, very little jitter (less than 0.005ui p-p broadband from 10hz to 100khz) is added to the jitter pres ent on tclk. also, the waveforms cr eated are independent of the duty cycle of tclk. the transmitter in the ds2156 couples to the e1 or t1 transmit twisted pair (or coaxial cable in some e1 applications) th rough a 1:2 step-up transformer. for the device to create the proper waveforms, the transformer used must meet the sp ecifications listed in tabl e 23-a. the ds2156 has the option of using software-selectable transmit termination. 23.3.1 transmit short-circuit detector/limiter the ds2156 has an automatic short-circuit limiter that limits the source current to 50ma (rms) into a 1 ? load. this feature can be disabled by setting th e scld bit (lic2.1) = 1. tcle (info2.5) provides a real-time indication of when the cu rrent limiter is activated. if the current limiter is disabled, tcle indicates that a short-circuit cond ition exists. status register sr1.2 provides a latched version of the information, which can be used to activate an interrupt when enabled by the imr1 register. the tpd bit (lic1.0) powers down the transmit line driver and tri-states the ttip and tring pins. 23.3.2 transmit open-circuit detector the ds2156 can also detect when the ttip or tr ing outputs are open ci rcuited. tocd (info2.4) provides a real-time indication of when an open circuit is detected. sr 1 provides a latched version of the information (sr1.1), which can be used to activate an interrupt when enabled by the imr1 register. 23.3.3 transmit bpv error insertion when ibpv (lic2.5) is transitioned from a 0 to a 1, the device waits for the next occurrence of three consecutive 1s to insert a bpv. ibpv must be cleared and set agai n for another bpv error insertion. 23.3.4 transmit g.703 synchr onization signal (e1 mode) the ds2156 can transmit the 2.048mhz square-wave sync hronization clock as specified in section 13 of itu g.703, october 1998. in order to transmit the 2.048m hz clock, when in e1 mode, set the transmit synchronization clock enable (lic3.1) = 1. downloaded from: http:///
ds2156 153 of 265 23.4 mclk prescaler a 16.384mhz, 8.192mhz, 4.096mhz, 2.048mhz, or 1.544mhz clock must be applied at mclk. itu specification g.703 requires an accuracy of 50ppm for both t1 and e1. tr62411 and ansi specifications require an accuracy of 32ppm for t1 interfaces. a pr escaler divides the 16mhz, 8mhz, or 4mhz clock down to 2.048mhz. ther e is an on-board pll for the jitte r attenuator, which converts the 2.048mhz clock to a 1.544mhz rate for t1 applicati ons. setting jamux (lic2.3) to a logic 0 bypasses this pll. 23.5 jitter attenuator the ds2156 contains an on-board jitte r attenuator that can be set to a depth of either 32 or 128 bits through the jabds bit (lic1.2). the 128-bit mode is us ed in applications where large excursions of wander are expected. the 32-bit mode is used in dela y-sensitive applications. the characteristics of the attenuation are shown in figure 23-9. the jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or cleari ng the jas bit (lic1.3). setting the dja bit (lic1.1) disables (in effect, removes) the ji tter attenuator. on-board circuitry adjusts either the recovered clock from the clock/data recovery bloc k or the clock applied at the tclk pin to cr eate a smooth jitter-free clock that is used to clock data out of the jitter attenuator fifo . it is acceptable to provide a gapped/bursty clock at the tclk pin if the jitter attenuator is placed on the transmit si de. if the incoming jitter exceeds either 120ui p-p (buffer depth is 128 bits) or 28ui p-p (buffer depth is 32 bits), then the ds2156 divides the internal nominal 32.768mhz (e1) or 24.704mhz (t1) clock by either 15 or 17 instead of the normal 16 to keep th e buffer from overflowing. when the de vice divides by ei ther 15 or 17, it also sets the jitter attenua tor limit trip (jalt) bit in status register 1 (sr1.4). 23.6 cmi (code mark inversion) option the ds2156 provides a cmi interface for connection to optical transports. this interface is a unipolar 1t2b signal type. ones are encoded as either a logical 1 or 0 level for the full duration of the clock period. zeros are encoded as a 0-to-1 transition at the middle of the clock period. figure 23-2. cmi coding transmit and receive cmi are enabled through lic4.7. when this register bit is set, the ttip pin outputs cmi-coded data at normal levels. this signal can be used to directly drive an opt ical interface. when cmi is enabled, the user can also use hdb3/b8zs codi ng. when this register bit is set, the rtip pin becomes a unipolar cmi input. the cmi signal is processed to extract an d align the clock with data. 0 1 11 001 clock data cmi downloaded from: http:///
ds2156 154 of 265 23.7 liu control registers register name: lic1 register description: line interface control 1 register address: 78h bit # 7 6 5 4 3 2 1 0 name l2 l1 l0 egl jas jabds dja tpd default 0 0 0 0 0 0 0 0 bit 0/transmit power-down (tpd) 0 = powers down the transmitter and tri-states the ttip and tring pins 1 = normal transmitter operation bit 1/disable jitter attenuator (dja) 0 = jitter attenuator enabled 1 = jitter attenuator disabled bit 2/jitter attenuator buffer depth select (jabds) 0 = 128 bits 1 = 32 bits (use for delay-sensitive applications) bit 3/jitter attenuator select (jas) 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side bit 4/receive equalizer gain limit (egl). this bit controls the sensitivity of the receive equalizer. t1 mode 0 = -36db (long haul) 1 = 15db (limited long haul) e1 mode 0 = -10db (short haul) 1 = -43db (long haul) bits 5 to 7/line buildout select (l0 to l2). when using the internal terminati on, the user needs only to select 000 for 75 ? operation or 001 for 120 ? operation below. this selects the proper voltage levels for 75 ? or 120 ? operation. using tt0 and tt1 of the licr4 register, th e user can then select the proper internal source termination. line buildouts 100 and 101 are for b ackwards compatibility with older products only. e1 mode l2 l1 l0 application n (1) return loss rt (1) ( ? ) 0 0 0 75 ? normal 1:2 nm 0 0 0 1 120 ? normal 1:2 nm 0 1 0 0 75 ? with high return loss * 1:2 21db 6.2 1 0 1 120 ? with high return loss * 1:2 21db 11.6 *tt0 and tt1 of lic4 register must be set to 0 in this configuration. downloaded from: http:///
ds2156 155 of 265 t1 mode l2 l1 l0 application n (1) return loss rt (1) ( ? ) 0 0 0 dsx-1 (0ft to 133ft) / 0db csu 1:2 nm 0 0 0 1 dsx-1 (133ft to 266ft) 1:2 nm 0 0 1 0 dsx-1 (266ft to 399ft) 1:2 nm 0 0 1 1 dsx-1 (399ft to 533ft) 1:2 nm 0 1 0 0 dsx-1 (533ft to 655ft) 1:2 nm 0 1 0 1 -7.5db csu 1:2 nm 0 1 1 0 -15db csu 1:2 nm 0 1 1 1 -22.5db csu 1:2 nm 0 register name: lic2 register description: line interface control 2 register address: 79h bit # 7 6 5 4 3 2 1 0 name ets lirst ibpv tua1 jamux scld clds default 0 0 0 0 0 0 0 0 bit 0/custom line driver select (clds). setting this bit to a 1 redefines the operation of the transmit line driver. when this bit is set to a 1 and lic1.5 = lic1.6 = lic1.7 = 0, the device generates a square wave at the ttip and tring outputs instead of a normal waveform. when th is bit is set to a 1 and lic1.5 = lic1.6 = lic1.7 0, the device forces ttip and tring outputs to beco me open-drain drivers instead of their normal push-pull operation. this bit should be set to 0 for normal operation of the device. bit 1/short-circuit limit disable (ets = 1) (scld). controls the 50ma (rms) current limiter. 0 = enable 50ma current limiter 1 = disable 50ma current limiter bit 2/unused, must be set to 0 for proper operation bit 3/jitter attenuator mux (jamux). controls the source for jaclk. 0 = jaclk sourced from mclk (2.048mhz or 1.544mhz at mclk) 1 = jaclk sourced from internal pll (2.048mhz at mclk) bit 4/transmit unframed all ones (tua1). the polarity of this bit is set such that the device transmits an all- ones pattern on power-up or device reset. this bit must be set to a 1 to allow the device to transmit data. the transmission of this data pattern is always timed off of the jaclk. 0 = transmit all ones at ttip and tring 1 = transmit data normally bit 5/insert bpv (ibpv). a 0-to-1 transition on this bit causes a single bpv to be inserted into the transmit data stream. once this bit has been toggled from a 0 to a 1, the device waits for the next occurrence of three consecutive 1s to insert the bpv. this bit must be cleared a nd set again for a subsequent error to be inserted. bit 6/line interface reset (lirst). setting this bit from a 0 to a 1 initiates an internal reset that resets the clock recovery state machine and recenters the jitter attenuator. norm ally this bit is only toggled on power-up. must be cleared and set again for a subsequent reset. bit 7/e1/t1 select (ets) 0 = t1 mode selected 1 = e1 mode selected downloaded from: http:///
ds2156 156 of 265 register name: lic3 register description: line interface control 3 register address: 7ah bit # 7 6 5 4 3 2 1 0 name tces rces mm1 mm0 rsclke tsclke taoz default 0 0 0 0 0 0 0 0 bit 0/transmit alternate ones and zeros (taoz). transmit a 101010 pattern (customer disconnect indication signal) at ttip and tring. the transmission of this data pattern is always timed off of tclk. 0 = disabled 1 = enabled bit 1/transmit synchronization g.703 clock enable (tsclke) 0 = disable 1.544mhz (t1)/2.048mhz (e1) transmit synchronization clock 1 = enable 1.544mhz (t1)/2.048mhz (e1) transmit synchronization clock bit 2/receive synchronization g.703 clock enable (rsclke) 0 = disable 1.544mhz (t1)/2.048mhz (e1) synchronization receive mode 1 = enable 1.544mhz (t1)/2.048mhz (e1) synchronization receive mode bits 3 to 4/monitor mode (mm0 to mm1) mm1 mm0 internal linear gain boost (db) 0 0 normal operation (no boost) 0 1 20 1 0 26 1 1 32 bit 5/receive-clock edge select (rces). selects which rclko edge to update rposo and rnego. 0 = update rposo and rnego on rising edge of rclko 1 = update rposo and rnego on falling edge of rclko bit 6/transmit-clock edge select (tces). selects which tclki edge to sample tposi and tnegi. 0 = sample tposi and tneg i on falling edge of tclki 1 = sample tposi and tnegi on rising edge of tclki bit 7/unused, must be set to 0 for proper operation downloaded from: http:///
ds2156 157 of 265 register name: lic4 register description: line interface control 4 register address: 7bh bit # 7 6 5 4 3 2 1 0 name cmie cmii mps1 mps0 tt1 tt0 rt1 rt0 default 0 0 0 0 0 0 0 0 bits 0, 1/receive termination select (rt0, rt1) rt1 rt0 internal receive-termination configuration 0 0 internal receive-side termination disabled 0 1 internal receive-side 75 ? enabled 1 0 internal receive-side 100 ? enabled 1 1 internal receive-side 120 ? enabled bits 2, 3/transmit termination select (tt0, tt1) tt1 tt0 internal transmit-termination configuration 0 0 internal transmit-side termination disabled 0 1 internal transmit -side 75 ? enabled 1 0 internal transmit -side 100 ? enabled 1 1 internal transmit -side 120 ? enabled bits 4, 5/mclk prescaler for t1 mode mclk (mhz) mps1 mps0 jamux (lic2.3) 1.544 0 0 0 3.088 0 1 0 6.176 1 0 0 12.352 1 1 0 2.048 0 0 1 4.096 0 1 1 8.192 1 0 1 16.384 1 1 1 bits 4, 5/mclk prescaler for e1 mode mclk (mhz) mps1 mps0 jamux (lic2.3) 2.048 0 0 0 4.096 0 1 0 8.192 1 0 0 16.384 1 1 0 bit 6/cmi invert (cmii) 0 = cmi normal at ttip and rtip 1 = invert cmi signal at ttip and rtip bit 7/cmi enable (cmie) 0 = disable cmi mode 1 = enable cmi mode downloaded from: http:///
ds2156 158 of 265 register name: info2 register description: information register 2 register address: 11h bit # 7 6 5 4 3 2 1 0 name bsync bd tcle tocd rl3 rl2 rl1 rl0 default 0 0 0 0 0 0 0 0 bits 0 to 3/receive level bits (rl0 to rl3). real-time bits rl3 rl2 rl1 rl0 receive level (db) 0 0 0 0 greater than -2.5 0 0 0 1 -2.5 to -5.0 0 0 1 0 -5.0 to -7.5 0 0 1 1 -7.5 to -10.0 0 1 0 0 -10.0 to -12.5 0 1 0 1 -12.5 to -15.0 0 1 1 0 -15.0 to -17.5 0 1 1 1 -17.5 to -20.0 1 0 0 0 -20.0 to -22.5 1 0 0 1 -22.5 to -25.0 1 0 1 0 -25.0 to -27.5 1 0 1 1 -27.5 to -30.0 1 1 0 0 -30.0 to -32.5 1 1 0 1 -32.5 to -35.0 1 1 1 0 -35.0 to -37.5 1 1 1 1 less than -37.5 bit 4/transmit open-circuit detect (tocd). a real-time bit that is set when the device detects that the ttip and tring outputs are open-circuited. bit 5/transmit current-limit exceeded (tcle). a real-time bit that is set when the 50ma (rms) current limiter is activated, whether the current limiter is enabled or not. bit 6/boc detected (bd). a real-time bit that is set high when the boc detector is presently seeing a valid sequence and set low when no boc is currently being detected. bit 7/bert real-time synchronization status (bsync). real-time status of the synchronizer (this bit is not latched). this bit is set when the incoming pattern matc hes for 32 consecutive bit positions . it is cleared when six or more bits out of 64 are received in error. refer to bsync in the bert status register, sr9, for an interrupt- generating version of this signal. downloaded from: http:///
ds2156 159 of 265 register name: sr1 register description: status register 1 register address: 16h bit # 7 6 5 4 3 2 1 0 name ilut timer rscos jalt lrcl tcle tocd lolitc default 0 0 0 0 0 0 0 0 bit 0/loss of line-interface transmit-clock condition (lolitc) . set when tclki has not transitioned for one channel time. this is a dou ble interrupt bit (section 6.2). bit 1/transmit open-circuit detect condition (tocd). set when the device detects that the ttip and tring outputs are open-circuited. this is a double interrupt bit (section 6.2). bit 2/transmit current-limit exceeded condition (tcle). set when the 50ma (rms) current limiter is activated, whether the current limiter is enabled or not. this is a double interrupt bit (section 6.2). bit 3/line interface receive carrier-loss condition (lrcl). set when the carrier signal is lost. this is a double interrupt bit (section 6.2). bit 4/jitter attenuator limit trip event (jalt). set when the jitter attenuator fifo reaches to within 4 bits of its useful limit. this bit is cleared when read. useful for debugging jitter attenuation operation. bit 5/receive signaling change-of-state event (rscos). set when any channel selected by the receive signaling change-of-state interrupt-enable register s (rscse1 through rscse4) changes signaling state. bit 6/timer event (timer). follows the error-counter update interval as determined by the ecus bit in the error-counter configuration register (ercnt). t1: set on increments of 1 second or 42ms based on rclk e1: set on increments of 1 second or 62.5ms based on rclk bit 7/input level under threshold (ilut). this bit is set whenever the input level at rtip and rring falls below the threshold set by the valu e in ccr4.4 through ccr4.7. the level must remain below the programmed threshold for approximately 50ms for this bit to be set. this is a double interrupt bit (section 6.2). downloaded from: http:///
ds2156 160 of 265 register name: imr1 register description: interrupt mask register 1 register address: 17h bit # 7 6 5 4 3 2 1 0 name ilut timer rscos jalt lrcl tcle tocd lolitc default 0 0 0 0 0 0 0 0 bit 0/loss-of-transmit clock condition (lolitc) 0 = interrupt masked 1 = interrupt enabledgenerates interrupts on rising and falling edges bit 1/transmit open-circuit detect condition (tocd) 0 = interrupt masked 1 = interrupt enabledgenerates interrupts on rising and falling edges bit 2/transmit current-limit exceeded condition (tcle) 0 = interrupt masked 1 = interrupt enabledgenerates interrupts on rising and falling edges bit 3/line interface receive carrier-loss condition (lrcl) 0 = interrupt masked 1 = interrupt enabledgenerates interrupts on rising and falling edges bit 4/jitter attenuator limit trip event (jalt) 0 = interrupt masked 1 = interrupt enabled bit 5/receive signaling change-of-state event (rscos) 0 = interrupt masked 1 = interrupt enabled bit 6/timer event (timer) 0 = interrupt masked 1 = interrupt enabled bit 7/input level under threshold (ilut) 0 = interrupt masked 1 = interrupt enabled downloaded from: http:///
ds2156 161 of 265 23.8 recommended circuits figure 23-3. basic interface note 1: all resistor values are 1%. note 2: resistors r should be set to 60 ? each if the internal receive-side termination feature is enabled. when this feature is disabled, r = 37.5 ? for 75 ? coaxial e1 lines, 60 ? for 120 ? twisted-pair e1 lines, or 50 ? for 100 ? twisted-pair t1 lines. note 3: c = 1f ceramic. ttiptring rtip rring dvdd tvdd rvdd vdd dvss tvss rvss ds2156 r r 2:1 1:1 c 0.1f 0.1f 0.1f 0.01f transmit line receive line 0.1f 10f 10f + + downloaded from: http:///
ds2156 162 of 265 figure 23-4. protected interface using internal receive termination note 1: all resistor values are 1%. note 2: x1 and x2 are very low dcr transformers. note 3: c1 = 1f ceramic. note 4: s1 and s2 are 6v transient suppressers. note 5: d1Cd8 are schottky diodes. note 6: the optional fuses, f1Cf4, prevent ac power line crosses from compromising the transformers. note 7: the 68 f is used to keep the local power-plane potential within tolerance during a surge. ttip tring rtip rring dvdd tvdd rvdd vdd vdd dvss tvss rvss ds2156 68f 2:1 1:1 d1 d2 d3 d4 c1 f1 f2 f3 f4 s1 0.1f 0.1f 0.1f 0.01f x1 x2 transmit line receive line 0.1f 10f 10f + + + 0.1f s2 60 60 vdd d5 d6 d7 d8 0.1f downloaded from: http:///
ds2156 163 of 265 23.9 component specifications table 23-a. transformer specifications specification recommended value turns ratio 3.3v applications 1:1 (receive) and 1:2 (transmit) 2% primary inductance 600 h (min) leakage inductance 1.0 h (max) intertwining capacitance 40pf (max) transmit transformer dc resistance primary (device side) secondary 1.0 ? (max) 2.0 ? (max) receive transformer dc resistance primary (device side) secondary 1.2 ? (max) 1.2 ? (max) downloaded from: http:///
ds2156 164 of 265 figure 23-5. e1 transmit pulse template figure 23-6. t1 transmit pulse template 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 time (ns) scaled amplitude 50 100 150 200 250 -50 -100 -150 -200 -250 269ns 194ns 219ns (in 75 ? systems, 1.0 on the scale = 2.37vpeak in 120 ? systems, 1.0 on the scale = 3.00vpeak) g.703 template 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -500 -300 -100 0 300 500 700 -400 -200 200 400 600 100 time (ns) normalized amplitude t1.102/87, t1.403, cb 119 ( oct. 79 ) , and i.431 template -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.050.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 ui time amp. maximum curve ui time amp. minimum curve downloaded from: http:///
ds2156 165 of 265 figure 23-7. jitter tolerance figure 23-8. jitter tolerance (e1 mode) frequency (hz) unit intervals (ui p-p ) 1k 100 10 1 0.1 10 100 1k 10k 100k ds2155 tolerance 1 minimum tolerance level as per itu g.823 40 1.5 0.2 20 2.4k 18k frequency (hz) unit intervals (ui p-p ) 1k 100 10 1 0.1 10 100 1k 10k 100k ds2156 tolerance 1 tr 62411 (dec. 90) itu-t g.823 downloaded from: http:///
ds2156 166 of 265 figure 23-9. jitter attenuation (t1 mode) figure 23-10. jitter attenuation (e1 mode) frequency (hz) 0db -20db-40db -60db 1 10 100 1k 10k jitter attenuation (db) 100k itu g.7xx prohibited area tbr12 prohibited area ds2156 e1 mode frequency (hz) 0db -20db-40db -60db 1 10 100 1k 10k jitter attenuation (db) 100k tr 62411 (dec. 90) prohibited area c u r v e b curve a ds2156 t1 mode downloaded from: http:///
ds2156 167 of 265 figure 23-11. optional crystal connections note 1: c1 and c2 should be 5pf lower than two time s the nominal loading capacitance of the crystal to adjust for the input capacitance of the ds2156. xtald ds2156 c1 c2 1.544mhz/2.048mhz mclk downloaded from: http:///
ds2156 168 of 265 24. utopia backp lane interface 24.1 description the ds2156s utopia interface maps the atm cells in a t1/e1 frame in the transmit direction as per atm forum specifications af-phy-0016.000 [1] and af-phy-0064.000 [2] and recovers them in the receive direction from a similar mapping. in the rece ive direction, the cell deli neation mechanism used for finding atm cell boundaries within a t1/e1 frame is performed as per itu-t i.432 [4]. the terms physical layer (phy) and line sid e are used synonymously in this do cument and refer to the device interface with the line side of the ds2156. the terms atm layer and system side are used synonymously and refer to the ut opia-ii interface of the ds2156. the transmit section receives cells from the atm layer through the utopia-ii in terface. it writes the cells into a 4-cell-deep transmit fifo that is used for rate decoupling. the fifos depth is programmable to two, three, or four atm cells. the cells are ma pped into the t1/e1 frame as per [1] and [2]. the ds2156 can be configured to perform valid hec insertion and payload scrambling. the receive section delineates the cells from the data received from the phy layer as per [4]. once cells are delineated, they are written into a 4-cell-deep receive fifo used for rate decoupling. the receive section interfaces with the atm layer through the ut opia-ii interface. it can also be configured to perform payload descrambling and id le/unassigned cell filtering. single-bi t hec error correction is also supported. 24.1.1 list of applicable standards 1) atm forum ds1 physical layer sp ecification, af-phy-0016.000, september 1994 2) atm forum e1 physical layer specification, af-phy-0064.000, september 1996 3) atm forum utopia level 2 specifi cation, version 1.0, af-phy-0039.000, june 1995 4) b-isdn user-network interfacephysical layer specificationitu-t recommendation i.432C 03/93 24.1.2 acronyms and definitions acronym definition atm asynchronous transfer mode crc cyclic redundancy check hec header error check lcd loss-of-cell delineation oam operations administration and maintenance ocd out-of-loss delineation pmon performance monitoring utopia universal test and operations phy interface for atm downloaded from: http:///
ds2156 169 of 265 24.2 utopia clock modes when the utopia backplane is enabled, the user can select from several cl ocking modes: full t1/e1, clear-channel e1, or fractional t1 /e1. because atm bytes are byte-ali gned in the frame, clear-channel mode is only available in e1 ope ration. see table 24-a for the variou s register confi gurations. figure 24-1 shows a simplified diagram of the clock, data, and sync connections betw een the framer and the utopia block. figure 24-1. utopia clocking configurations 24.3 full t1/e1 mode and clear-channel e1 mode in full t1/e1 mode, the framer is programmed to pr ovide a constant clock (rclk for the receiver and tclk for the transmitter) to th e utopia block by setting ccr3.4 and ccr3.5 = 1. the framer also provides frame-sync pulses to the utopia block. th e utopia block is programmed to use the clock and sync signals by setting u_t cr2.1 and u_rcr2.1 = 0. in this mode the utopia block uses the sync signal to byte align the transmit data stream and lo cate the f-bit position in t1 operation and ts0 and ts16 in e1 operation. in t1 mode, the receive and transmit utopia blocks always use the frame-sync pulse to gap out the f- bit position. in e1 mode, the transmit utopia block can be programmed to gap out ts0 and ts16 by setting u_tcr1.3 = 0, or use the full 256 bits of the frame by setting u_tcr1.3 = 1. using the full 256 bits of the frame is referred to as clear-c hannel mode and is only available in e1 mode. in full e1 mode, the receive utopia block always uses the frame-sync pulse to gap out ts0 and ts16. in order for the receive utopia block to operate in clear-channel mode, set u_rcr2.1 = 1 while in full clock mode or use the fractional mode of operation described in section 24.4 with all channels selected. receive framer receive utopia block rclk gapped clock frame sync clock sync transmit framer transmit utopia block tclk gapped clock frame sync clock sync tclk data data data data ccr3.4 ccr3.5 00 11 network utopia backplane downloaded from: http:///
ds2156 170 of 265 24.4 fractional t1/e1 mode in fractional t1/e1 mode, the framer is programme d to provide a gapped clock by setting ccr3.4 and ccr3.5 = 0. the gapped clocks are synchronous with rclk and tclk. the utopia block is programmed to use the clock and ignore the sync signals by setting u_tcr2.1 and u_rcr2.1 = 1. in this mode, the user can program the clock to be ac tive during any time slot or group of time slots by using the transmit and receive fractional channel-select func tion in the per-channel point er register (pcpr). see section 5 for details on using this feature. in t1 mode, the f-bit is automatically gappe d. in e1 mode, the user must program the clock to be ga pped during ts0 and/or ts16 if desired. table 24-a. utopia clock mode configuration mode u_tcfr.0 u_rcfr.0 ccr3.4 ccr3.5 u_tcr2.3 u_t cr2.1 u_rcr2.1 comments full t1 mode, f-bit position gapped 0 1 1 x 0 0 clear-channel operation is not available in t1 mode full e1 mode, ts0 and ts16 gapped 1 1 1 0 0 0 full e1 mode, clear- channel (transmit) 1 1 1 0 0 transmit framer must be set to ts0 pass-through mode e1tcr1.7 = 1 and transmit-signaling insertion disabled full e1 mode, clear- channel (receive) method #1 1 1 x 1 full e1 mode, clear- channel (receive) method #2 1 0 x 1 use pcpr and pcdr1Cpcdr4 registers to make all receive channels active fractional t1 mode 0 0 0 x 1 1 use pcpr and pcdr1Cpcdr4 registers to select active transmit and receive channels fractional e1 mode 1 0 0 x 1 1 use pcpr and pcdr1Cpcdr4 registers to select active transmit and receive channels downloaded from: http:///
ds2156 171 of 265 24.5 transmit operation the ds2156 interface to the atm la yer is fully compliant to th e atm forums utopia level 2 specification [3]. either direct status or multiplexe d with 1clav mode is s upported. the ds2156 can be configured to use any address, 0 to 3, as its utopia port address, and uses a 4-cell buffer for cell-rate decoupling. the depth of the transmit fifo is configurable to 2, 3, or 4 cells. when a port is polled and has cell space available, the ds2156 generates a cell available signal for that port. additionally, the ds2156 generates a 2-cell space availability indication fo r each port. note that this 2clav indication follows the timing and polling cycles of ut-clav. figure 24-2 shows the polling and cell transfer cycles for ds2156s used in a multiport configuration. note that ut-soc must be aligned with the first byte transfer. the ds2156 uses ut-soc to detect the first byte of a cell. if a spuri ous ut-soc comes during a cell transf er, then the ds2156 aligns with the latest ut-soc and ignores the bytes (partial cell) received thus far. 24.5.1 utopia side transmit: muxed mode with one transmit clav in the following functional description, a phy is a single ds2156 and phys are multiple ds2156s. in level 2 utopia, only one phy at a time is select ed for a cell transfer. however, another phy can be polled for its ut-clav status while the selected phy transfers data. the atm layer polls the ut- clav status of a phy by placing it s address on the transmit utopia bus. the phy drives ut-clav during each cycle following one with its address on the ut-addrx lines. the atm layer selects a phy for transfer by placing the port address of the phy onto ut-addrx, when ut-enb is deasserted during the current clock cycle, and assert ed during the next clock cycle. al l phys only examine the value on ut-addrx for selection purposes when ut-enb is deasserted. the phy is selected starting from the cycle after its address is on the ut-addrx lines and ut-enb is deasserted. and ending in the cycle, another phy is addressed for selection and ut-enb is deasserted. once a phy is selected, the cell transfer is accomplished as described by the cell-le vel handshake of utopia level 1. to operate a phy in a single phy environment, the address pins shoul d be set to the value programmed by the management interface. figure 24-2 shows an example where phys are polled until the end of a cell tran smission cycle. the ut- clav signal shows that phys n - 3 and n + 3 can accept cells and phy n + 3 is selected. the phy is selected with the rising clock edge #16. immediat ely after the beginning of cell transmission to phy n + 3, the atm layer starts polling again. usi ng the 2-clock polling cycles shown, up to 26 phys can be polled. this maximum value can only be reached if all responses occur in minimum delays, e.g., as shown, where, with clock edge #15, the response of the last phy is obtained, immediately followed by the ut-enb pulse to the phys. if an atm implementation needs additional clock cycles to select the phy, fewer than 26 phy can be polled during one cell cycle. note that if the atm would decide to select phy n again for the next cell transmission, it could leave the ut-enb line asserted and start transmitting the next cell with clock edge #15. this results in a back-to-back cell transmission. downloaded from: http:///
ds2156 172 of 265 figure 24-2. polling phase and se lection phase at transmit interface note that the active phy (phy n) is polled in octet p48. at this time, according to the utopia level 1 specification, the ut-clav signal of the phy indicates the possibility of a subs equent cell transfer. polling of phy n before octet p44 would be possible but it does not indicate availab ility of the next cell. n+2 1f n-3 1f n-2 1f n-1 1f n+3 n+1 1f n 1f n+3 1f n+1 1f n-1 1f n+2 n-3 n-2 n-1 n+3 n+1 n n+3 n+1 p35 p36 p37 p38 p39 p40 p41 p42 p43 p45 p46 p47 p48 h1 h2 h3 h4 p44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ut-clk ut-addrx ut-clav u t- e nb ut-datax ut-soc cell xmit to: phy n phy n+3 polling polling selection downloaded from: http:///
ds2156 173 of 265 the example in figure 24-3 shows where the transm ission of cells though the transmit interface is stopped by the atm, as no phy is ready to accept cells. polling continues. several clock cycles later one phy gets ready to accept a cell. du ring the transmission pause, the ut-datax and ut-soc can go into high-impedance state as shown. ut-enb is held in deasserted state. wh en a phy is found that is ready to accept a cell (phy_n + 3 in this case), the address of this phy must be a pplied again to select it. this is necessary because of the 2-clock polling cycle, where the phy is detected at the clock edge #15. at this time, the address of phy n + 3 is no longer on the bus and therefore must be ap plied again in the next clock cycle. phy n + 3 is se lected with clock edge #16. figure 24-3. end and restart of cell at transmit interface n+1 1f n 1f n+3 1f n+2 1f n-1 n 1f n+3 1f n+3 1f n-2 1f n-3 1f n p45 p46 p47 p48 h1 h2 h3 h4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ut-clk ut-addrx ut-clav u t - e nb ut-datax ut-soc cell xmit to: phy n phy n+3 polling polling selection n+1 n n+3 n+2 n-1 n+3 n+3 n-2 detection downloaded from: http:///
ds2156 174 of 265 figure 24-4 shows an example where the atm must pa use the data transmission, since it has no data available (in this case, for three clock cycles). this is done by deasserting ut-enb and (optionally) setting ut-datax and ut-soc into a high-impedance state. polling can conti nue. in the last clock cycle before restarting the transmission, the address m of the previously selected phy is put on the ut-addrx bus to reselect phy m again. figure 24-4. transmission to phy paused for three cycles 24.5.2 utopia side transmit: direct status mode (multitransmit clav) the ds2156 supports direct status mode per [3] for a maximum of four phy ports connected to one atm layer. for each phy port, the status signals ur-clav and ut-clav are permanently available according to utopia level 1 specification. phy devices with up to four phy ports on-chip have up to four ur-clav and up to four ut -clav status signals, one pair of ur-clav and ut-clav for each phy port. status signals and cell transfers are independent of each other. no address information is needed to obtain status information. address informa tion must be valid only for selecting a phy port prior to one or multiple cell transfers. with respect to the stat us signals ur-clav and ut-clav, this mode of operation corresponds to that of four individual p hy devices according to utopia level 1. with respect to the cell transfer, this mode of operation corresponds to that as described in other parts of this document. the atm layer selects a phy port for cell transfer by placing the desired port on the address lines (ur-addrx, ut-addrx), while the enable signal ( ur-enb , ut-enb ) is deasserted. all phy ports examine only the value on the address lines fo r possible selection when the enable signal is deasserted. in case the atm suspends transmission for a specific phy port during a cell transfer, no cells to/from other phy ports can be transferred during this time. n 1f n+1 1f n-4 1f m 1f n+2 n+3 1f 1f n n+1 n-4 m n+2 n+3 p31 p32 p33 p34 p35 p36 p38 p39 p37 1 2 3 4 5 6 7 8 9 10 11 12 13 ut-clk ut-addrx ut-clav u t - e nb ut-datax ut-soc cell xmit to: phy m polling phy m pause xmit polling selection downloaded from: http:///
ds2156 175 of 265 figure 24-5 shows an example of direct status for the transmit di rection. signals ut-clav[3:0] are associated to phy port addresses #4, #3, #2, and #1. ther e is no need for a unique null device, thus x = dont care represents any address between 0 and 31 on the address lines ut-addrx or any data on the data bus. the polling of phy ports starts while no cel l transfer takes place. the atm layer has pending cells for all four phy ports (one individual queue for each phy port) but all four phy ports cannot accept a cell. with rising clock edge #2, phy port #1 indicates that it can ac cept a complete cell (ut-clav0 asserted). the atm layer detects this at clock edge #3. it select s that phy port by placing address #1 on the address lines with rising clock edge #3. phy port #1 detects this at clock edge #4. at clock edge #5, phy port #1 detects ut-enb asserted, therefore cell transfer for phy port #1 starts with rising clock edge #5 (byte h1). figure 24-5. example of direct status indication, transmit direction at clock edge #5, the atm layer de tects a cell available at phy port #3 (ut-clav2 asserted). with rising clock edge #52, phy port #1 i ndicates that it cannot accept an additional cell by deasserting ut- clav0. thus, at clock edge #57, th e atm layer detects only ut-clav2 asserted (ut-clav1 and ut- clav3 remain deasserted). the atm layer dese lects phy port #1 and selects phy port #3 for cell transfer with rising clock edge #57 by placing a ddress #3 on the address lines and deasserting ut-enb . phy port #1 and phy port #3 detect this at clock edge #58. at clock edge #59, phy port #3 detects ut-enb asserted, therefore cell transfer for phy port #3 starts with rising cloc k edge #59 (byte h1). for additional examples, refer to [3]. n-4 1 2 3 4 5 6 53 54 55 56 57 58 ut-clk ut-addrx ut-clav(1) u t - e nb ut-soc 59 h1 p45 p46 p48 x p47 ut-datax x 1 x x = don't care 3 x ut-clav(2) ut-clav(3) ut-clav(4) port #1 port #2 port #3 port #4 h2 x p44 h1 port #1 transfer port #3 52 downloaded from: http:///
ds2156 176 of 265 24.5.3 transmit processing the ds2156 can optionally insert a valid hec byte in the cell header, or it can be programmed to transparently transmit the hec byte from atm layer. when inserting a valid hec byte, coset (0x55) addition can be optionally disabled. the generator polynomial used is 1 + x + x 2 + x 8 . for idle/unassigned cell in sertion (used for cell-rate decoupling), th e ds2156 inserts a valid hec byte with or without coset addition, depending on the t crds bit (u_tcr1.3). the ds2156 can optionally scramble payload bytes, depending on the tpse bit (u_tcr1.4) regist er bit. the polynomial used for scrambling is x 43 + 1. for debugging purposes, the ds2156 can be configured to introduce a single-bit hec error in the cell header of cells transmitted in a controlled manner. if configured in hec error- insertion mode, it inserts hec errors in hec on pe riod number of cells and turns off hec error insertion for hec off period number of cells se t in the transmit hec error-pattern register (u_thepr). this process repeats periodically, until hec error insert ion is disabled through u_tcr1.1. figure 24-6. transmit cell flow utopia ii data input transmit fifo hec insertion on/off hec insertion on payload scrambling on/off hec error insertion on/off idle cell unassigned cell tx_crd_sel tx_coset_enb hec_insert_enb tx_coset_enb scrambling_enb hec_err_insert_enb hec_on_period hec_off_period cell data to framer (phy) downloaded from: http:///
ds2156 177 of 265 24.6 receive operation the receive interface of the ds2156 is fully co mpliant with the atm forums utopia level 2 specifications [3]. the ds2156 can be configured to us e any address in the range 0 to 31 as its utopia port addresses. if the receive fifo is not empty, the cell-available signal is asserted. after cell transfer from a port, the external cell-available signal updates based on the receive fifo fill level only after one- clock cycle from cell-transfer completion. during this one-clock cycle, cell ava ilable indication for this port is kept in the deasserted stat e. one-clock minimum latency between two cell transfers from the same utopia port is needed by the ds2156 to update its intern al cell pointers. 24.6.1 receive processing the received bits, after ignoring framing overhead bits, are checked for possible hec pattern. the polynomial used for hec check is g(x) = 1 + x + x 2 + x 8 , as recommended in [4]. the coset subtraction (0x55) can be optionally disabl ed by clearing the regi ster bit u_rcr1.0. the cell boundaries in the incoming bit stream are identified based on hec. figure 24-7 shows the cell- delineation state machine. the cell-delineation state mach ine is initially in hunt state. in hunt state, it performs bit-by-bit hunting for correct hec. if correct hec is found, it transitions to the presync state where it cell-by-cell checks for correct hec patterns. if delta consecutive co rrect patterns are received in presync, the cell-delineation st ate machine transits to sync st ate. otherwise, it goes to hunt state itself and starts bit-by-bit hun ting. in sync state, if alpha c onsecutive incorrect hec patterns are received, cell delineation is lost and it goes to hunt state. in pr esync and sync states, only cell-by- cell checking for proper hec pattern is performed. alpha and delta are 7 and 6, respectively. figure 24-7. cell-delineation state diagram hunt sync presync a lph a consecutive incorrect hec incorrect hec correct hec bit by bit delt a consecutive correct hec cell by cell cell by cell downloaded from: http:///
ds2156 178 of 265 the persistence of an out-of-cell delineation (ocd) event is integrat ed into loss-of-cell delineation (lcd), based on programmable integration time period (receive lcd integration-pe riod register). if ocd persists for the programmed time, lcd is declared. lcd is deasserted only when cell delineation persists in sync for the same programmed time. whenever ther e is a change in lcd st atus, namely into lcd or out of lcd, an external in terrupt is optionally generated by the microprocessor interface based on the corresponding mask bit u_rcr2.4. the persistence is checked every system clock period divided by 16,383. the default value of receive lcd integration period register provides an integration time of 102ms in e1 mode and 135ms in t1 mode. if a single-bit header-error correction is enabled, the receiver mode of operation state machine follows the state machine given in figure 24-8. single-bit correction is done only if correction is enabled and the state machine is in correction mode of operation at the st art-of-cell transfer. recei ver mode of operation is valid only when cell delineation is in sync state. 8- bit correctable and 12-bit uncorrectable hec-errored cell counters are maintained as saturating counters. figure 24-8. header correction state machine no error detected (no action) correction mode detection mode single bit error detected (correction) error detected (cell discarded) no error detected (no action) multi-bit error detected (cell discarded) . hec error correction is accomplished based on the re ceiver mode of operation. in correction mode, only single-bit errors can be corrected an d the receiver switches to detectio n mode. in detectio n mode, all cells with detected header errors are discarded, provided the u_rcr1.3 bit is set = 0. when a header is examined and found not to be in error, the receiver switches to correction mode . the term no action in figure 24-8 means no correction is pe rformed and no cell is discarded. the payload bytes of the cell ar e optionally descrambled using th e self-synchronizing descrambler polynomial x 43 + 1, as given in [4]. the descrambli ng can be enabled through the u_rcr1.2 bit. descrambling is activated if cell delineation is in presync or sync state. the cell header is not affected by descrambling. after descrambling and single-bit head er-error correction, the cel ls are written into the receive fifo as long as cell delineation is in sync a nd the receive fifo is not full. id le and/or unassigned cells can be optionally filtered by properly progra mming the receive control register bits. uncorrectable hec-errored cells are normally filtered and are not written into the receive fifo unless u_rcr1.3 is set. note that if downloaded from: http:///
ds2156 179 of 265 hec error correction is disabled, all hec-errored cells are termed as uncorrect able hec-errored cells. a 16-bit count of the number of cells that can be writte n into receive fifo is maintained, which saturates at ffffh. note that, whether or not atm layer dequeue s cells from the receive fifo, this counter increments if valid cells are recei ved. this counter is cleared by the microprocessor interface once it is latched. a 2k x 8 receive fifo that holds 4-cell buffe r space per port is maintained for rate decoupling. 24.6.2 utopia side receive: muxed mode with one receive clav the ds2156 drives the internal cell-available signals onto the external clav lines based on the configured polling mode. in direct status mode, only four ports are su pported. if a port is conducting a cell transfer, its clav is kept assert ed until the last byte is transfe rred to the atm layer. this supports interfacing with the octet-level atm layer also. cell-av ailable status for any fresh cell corresponding to a port has to be polled by the atm laye r only after the current cell transfer to the port is completed. the multiplexed bus with 1clav polling mode cycle is depicted in figure 24-9 in which n, n + 2, n - 3, n - 2, n - 1, n + 3, and n + 1 are considered part of ds2156 utopia ports. during reception of a cell from phy n, the other phys are polled. it turns out that phy n - 3 and phy n + 3 have cells available, and phy n + 3 is ultimately selected. (remember that th e phy number values are for example only). just like the transmit interface, the 2-cloc k polling cycles allow up to 26 phys to be polled in the 8-bit mode. figure 24-9. polling phase and selection at receive interface n+2 1f n-3 1f n-2 1f n-1 1f n+3 n+1 1f n-1 1f n+3 1f n+1 1f n-1 1f n+2 n-3 n-2 n-1 n+3 n+1 n+3 n+1 p35 p36 p37 p38 p39 p40 p41 p42 p43 p45 p46 p47 p48 h1 h2 h3 p44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ur-clk ur-addrx ur-clav u r_enb ur-datax ur-soc cell rcv from: phy n phy n+3 polling polling selection n-1 downloaded from: http:///
ds2156 180 of 265 figure 24-10 shows a case when, after the end of tr ansmission of a cell from phy n, no other phy has a cell available. therefore, ur-enb remains asserted as the atm assu mes a cell-available from phy n. with clock edge #9, it turns out that phy n also has no cell available, as ur-soc remains low. the atm then deasserts ur-enb while the polling of the phys continues. with clock edge #15, phy n - 3 is found to have a cell for transmission. t hus, address n - 3 is applied and the phy n - 3 is selected with clock edge #16. additional receive interface examples are available in [3]. figure 24-10. end and restart of ce ll transmission at receive interface 24.6.3 utopia side receive: direct status mode (multireceive clav) up to a maximum of four phy ports can be connected to one atm layer. for each phy port, the status signals ur-clav and ut-clav are permanently availa ble according to utopia level 1 specification. status signals and cell transfers are independent of each other. no address information is needed to obtain status information. address informa tion must be valid only for selecting a phy port prior to one or multiple cell transfers. with respect to the stat us signals ur-clav and ut-clav, this mode of operation corresponds to that of four individual p hy devices according to utopia level 1. with respect to the cell transfer, this mode of operation corresponds to that as described in this document and [3]. the atm layer selects a phy port for cell transfer by placing the desired port on the address lines (ur-addrx, ut-addrx), while the enable signal ( ur-enb , ut-enb ) is deasserted. all phy ports only examine the value on the address lines for possible selection when the enable signal is deasserted. in case the atm suspends transmission for a specific phy port during a cell transfer , no cells to /from other phy ports can be transferred during this time. n-3 1f n+1 1f n-1 1f n 1f n+3 n-1 1f n-3 1f n-3 1f n+1 1f n+2 1f n-1 h1 h2 h3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ur-clk ur-addrx ur-clav u r - e nb ur-datax ur-soc cell rcv from: phy n phy n-3 polling polling selection n-3 n+1 n-1 n n+3 n-3 n-3 n+1 detection p45 p46 p47 p48 p42 p43 p44 xx downloaded from: http:///
ds2156 181 of 265 an example for the receive direction is shown in figure 24-11. the status signals ur-clavx are associated to phy port addresses #4, #3, #2, and #1. th ere is no need for a unique null device so x = dont care on the address lines ur-addrx. in figure 24-11, the polling of phy ports starts wh ile no cell transfer takes place. the atm layer monitors all four status signals ur-clavx. at clock edge #3 it detect s a cell available at phy port #1, ur-clav(1) asserted. it selects that phy port by placing address #1 on the address lines with rising clock edge #3. phy port #1 detects this at clock edge #4. at cl ock edge #5, phy port #1 detects ur-enb asserted, thus cell transfer for phy port #1 starts with rising clock edge #5. at clock edge #5 the atm layer detects a cell av ailable at phy port #3, ur -clav(3) asserted. not knowing whether phy port #1 may have another cell av ailable or not, the atm layer deselects phy port #1 and selects phy port #3 for cell transfer with rising clock edge #57 by placing address #3 on the address lines and deasserting ur-enb . phy port #1 and phy port #3 dete ct this at clock edge #58. at clock edge #59, phy port #3 detects ur-enb asserted, thus cell transfer starts with rising clock edge #59. at clock edge #111, no cell is available at phy ports #1, #2, and #4. the atm layer keeps ur-enb asserted and detects at clock edge #113 the fi rst byte of another cell available from phy port #3, ur-clav(3) asserted. thus, cell transfer takes place starting with rising clock e dge #112. at clock edge #164, again, no cell is available at phy ports #1, #2, and #4. the atm layer keeps the ur-enb asserted and also detects at clock edge #166 no cell available from phy port #3, ur-clav(3) deasserted. thus, the atm layer de selects phy port #3 by deasserting ur-enb with rising clock edge #166. figure 24-11. example of direct status indication, receive direction 1 2 3 4 5 6 58 59 60 112 113 ur-clk ur-addrx ur-clav(1) u r - e nb ur-soc 114 h1 h1 p48 h1 ur-datax x 1 x ur-clav(2) ur-clav(3) ur-clav(4) port #1 port #2 port #3 port #4 p48 h2 57 165 166 167 111 164 3 x x x p48 x cell transfer (port #1) cell transfer (port #3) cell transfer (port #3) downloaded from: http:///
ds2156 182 of 265 24.7 register definitions the ccr2 register is used to c onfigure the utopia port address. the upper five bits of the ccr2 register contain the port address 0C31. the lower three bits are used for the backplane clock function. see programmable backplane clock synthesizer in section 30. register name: ccr2 register description: common control register 2 register address: 71h bit # 7 6 5 4 3 2 1 0 name trpa4 trpa3 trpa2 trpa 1 trpa0 bpcs1 bpcs0 bpen default 0 0 0 0 0 0 0 0 bit 0/bpen. see section 30 for more information. bit 1/bpcs0. see section 30 for more information. bit 2/bpcs1. see section 30 for more information. bits 3 to 7/transmit and receive port address 0 to 4 (trpa0 to trpa4). the 5-bit value in this register is used to assign the utopia interface 1 of 32 port addresses. register name: u_tcfr register description: utopia transmit configuration register register address: 50h bit # 7 6 5 4 3 2 1 0 name tpm tpc default 0 0 0 1 0 0 0 0 bit 0/transmit port configuration (tpc) 0 = t1 mode 1 = e1 mode bit 1/transmit poll mode (tpm). transmit utopia polling mode configuration 0 = multiplexed with 1clav mode 1 = direct status bits 2 to 7/unassigned, must be set to 0 for proper operation downloaded from: http:///
ds2156 183 of 265 register name: u_tpcl register description: utopia transmit pmon counter latch register register address: 51h bit # 7 6 5 4 3 2 1 0 name default 0 0 0 0 0 0 0 0 bits 0 to 7/the host should always write 0x00 to this register when latc hing the pmon counter. this register is provided for latching in the 16-bit tr ansmit assigned cell-count value of a port into the common transmit assigned cell-counter latch regi ster. for reading the transmit assigne d cell-count value, software writes into this register and then reads from transmit-assigned cell-counter msb and lsb registers. a write into this register clears the transmit-assigned cell-count value. register name: u_tacc1 register description: utopia transmit-assigned cell-count register 1 register address: 52h bit # 7 6 5 4 3 2 1 0 name tacc15 tacc14 tacc13 tacc 12 tacc11 tacc10 tacc9 tacc8 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit-assigned cell count (tacc9 to tacc15) register name: u_tacc2 register description: utopia transmit-assigned cell-count register 2 register address: 53h bit # 7 6 5 4 3 2 1 0 name tacc7 tacc6 tacc5 tacc4 tacc3 tacc2 tacc1 tacc0 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit-assigned cell count (tacc0 to tacc7) transmit-assigned cell-count value reflects the number of atm layer cells transmitted since last latching. for reading the 16-bit transmit-assigned cell count for a port, software has to write into the transmit pmon-counter latch-enable register for the port before reading these re gisters. reading from these registers without writing into the latch-enable register returns the old value that was latched and not the current msb value. downloaded from: http:///
ds2156 184 of 265 register name: u_tiupb register description: utopia transmit idle/unassigned payload byte register register address: 54h bit # 7 6 5 4 3 2 1 0 name tiup7 tiup6 tiup5 tiup4 tiup3 tiup2 tiup1 tiup0 default 0 1 1 0 1 0 1 0 bits 0 to 7/transmit idle/unassigned payload (tiup0 to tiup7). holds the payload byte to be carried in octets of idle/unassigned cells, transmitted to wards line for cell rate decoupling. register name: u_thepr register description: utopia transmit hec error-insertion pattern register register address: 55h bit # 7 6 5 4 3 2 1 0 name hoffp4 hoffp3 hoffp2 hoffp1 hoffp0 honp2 honp1 honp0 default 0 0 1 0 1 0 0 1 bits 0 to 2/hec on period (honp0 to honp2). holds the number of cells in which incorrect hec is sent if hec error insertion is enabled. bits 3 to 7/hec off period (hoffp0 to hoffp4). holds the number of cells in which correct hec is sent if hec error insertion is enabled. if hec error insertion in the transmit control register is enabled for a port, then for the hec off period cells are transmitted to the port with correct hec. for the hec on period, cells are sent with incorrect hec. this cycle repeats until hec error insertion is disabled. note that hec error is introduced in all transmitted cells based on the transmit hec error-insertion pattern register, if the hec error-insertion bit in the transmit control register is enabled irrespective of whether the hec insertion bit in the transmit control register is enabled or disabled. downloaded from: http:///
ds2156 185 of 265 register name: u_tcr1 register description: utopia transmit control register 1 register address: 56h bit # 7 6 5 4 3 2 1 0 name tpse tcrds tcae theie thie default 0 0 0 0 0 1 0 1 bit 0/transmit hec-insertion enable (thie) 0 = hec byte as received from atm layer is transparently passed 1 = proper hec value is computed and inserted in the hec byte of the cell bit 1/transmit hec error-insertion enable (theie) 0 = hec error insertion disabled 1 = hec errors introduced in the transmitted cells as specified by transmit hec error-insertion pattern register bit 2/transmit coset-addition enable (tcae) 0 = no coset addition 1 = coset (0x55) addition to the calculated hec note that if hec insertion is disabled, then the he c byte is transmitted transparently (this bit does not impact atm layer cells). however, the hec byte of idle/unassigned cells used for cell-rate decoupling includes coset addition as long as the tcae bit is enabled. bit 3/transmit cell-rate decoupling selection (tcrds) 0 = idle cell 1 = unassigned cell bit 4/transmit payload-scrambling enable (tpse) 0 = disabling scrambling 1 = enabling scrambling bits 5 to 7/unassigned, must be set to 0 for proper operation downloaded from: http:///
ds2156 186 of 265 register name: u_tcr2 register description: utopia transmit control register 2 register address: 57h bit # 7 6 5 4 3 2 1 0 name fdc1 fdc0 tces tplim default 0 0 0 0 0 0 0 0 bits 0, 2, 6, 7/unassigned, must be set to 0 for proper operation bit 1/transmit physical-layer interface mode (tplim) 0 = clock + data + frame-pulse indication combination 1 = gapped clock + data combination bit 3/transmit clear e1 selection (tces). when this bit is set = 0, ts16 and ts0 are automatically gapped out. this is only meaningful when u_tcr2.1 is set = 0. e1tcr1.7 must be set = 1 if tces = 1. 0 = ts16 and ts0 gapped out 1 = ts16 and ts0 not gapped out bits 4, 5/transmit fifo depth configuration bits (fdc1, fdc0) fdc1 fdc0 cell depth 0 0 4 0 1 3 1 0 2 1 1 reserved register name: u_rcfr register description: utopia receive configuration register register address: 60h bit # 7 6 5 4 3 2 1 0 name rupm rpc default 0 0 0 0 0 0 0 0 bit 0/receive port configuration (rpc) 0 = t1 mode 1 = e1 mode bit 1/receive utopia polling mode (rupm) 0 = multiplexed with 1clav mode 1 = direct status bits 2 to 7/unassigned, should be set to 0 for proper operation downloaded from: http:///
ds2156 187 of 265 register name: u_rlcdip register description: utopia receive lcd integration period register register address: 61h bit # 7 6 5 4 3 2 1 0 name rlip7 rlip6 rlip5 rlip4 rlip3 rlip2 rlip1 rlip0 default 0 1 1 0 0 1 1 0 bits 0 to 7/receive lcd integration period (rlip0 to rlip7) this 8-bit register holds the lcd integration period value for which the out-of-cell delineation condition must persist for declaring loss-of-cell delineation (lcd). for deasserting lcd, cell delineation should persist in the sync state for the same amount of time programmed in this register. lcd state change condition can be programmed to generate an external interrupt through u_rcr2.4. a value of 0 programmed into this register declares lcd for every ocd condition at the resolution of the internal system clock period. the internal system clock is 8x the line clock [16.383mhz (e1 mode) and 12.352mhz (t1 mode)]. it = integration time in ms for e1 mode, register value = it / 1ms for t1 mode, register value = it / 1.326ms for example, in e1 mode a register value of 64h (100) ge nerates a 100ms integration time. in t1 mode, a register value of 4bh (75) generates a 100ms integration time. register name: u_rpce register description: utopia receive pmon-counter enable register register address: 62h bit # 7 6 5 4 3 2 1 0 name default 0 0 0 0 0 0 0 0 bits 0 to 7/the host should always write 0x00 to this register when latching the receive pmon counter. this register is provided for latching all receive pmon-counter values, namely the 16-bit receive assigned cell- count value, 12-bit receive uncorrectable hec-count value, and 8-bit receive correctable hec-count value of a port into the common receive assigned cell-counter latch register, receive uncorrectable hec-counter latch register, and receive correctable hec-count latch register, respectively. a write into this register clears the receive pmon counters for that port. downloaded from: http:///
ds2156 188 of 265 register name: u_rchec register description: utopia receive correctable hec counter register register address: 63h bit # 7 6 5 4 3 2 1 0 name rchc7 rchc6 rchc5 rchc4 rchc3 rchc2 rchc1 rchc0 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive correctabl e hec counter (rchc0 to rchc7) note that write access to the receive pmon-counter latch-enable register latches all receive pmon-counter values into temporary latch registers and clear s the internal count values. this regi ster holds the number of correctable hec-errored cells received since last latching. note th at this count corresponds to cells received when cell delineation is in sync. a correctable hec-errored cell is a cell with a single-bit error, provided single-bit hec- error correction is enabled through u_rcr1.1 and the receiver mode of operation is in correction mode. correctable hec count value is unaffected if hec-error correction is disabled. register name: u_ruhec1 register description: utopia receive uncorrectable hec counter register 1 register address: 64h bit # 7 6 5 4 3 2 1 0 name ruhc11 ruhc10 ruhc9 ruhc8 default 0 0 0 0 0 0 0 0 bits 0 to 3/receive uncorrectable hec counter (ruhc8 to ruhc11) bits 4 to 7/unused register name: u_ruhec2 register description: utopia receive uncorrectable hec counter register 2 register address: 65h bit # 7 6 5 4 3 2 1 0 name ruhc7 ruhc6 ruhc5 ruhc4 ruhc3 ruhc2 ruhc1 ruhc0 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive uncorrectab le hec counter (ruhc0 to ruhc7) the u_ruhec1 and u_ruhec2 registers count the number of uncorrectable hec-e rrored cells received since last latching. note that this count corresponds to cells received when cell delineation is in sync. for every sync- to-hunt transition of the cell delineation state machine, the correctable + uncorrectable error-count value increases by 6 instead of 7. for every sync-to-hunt transition, if hec corr ection is enabled, the correctable hec count increases by 1 and the uncorrectable hec c ount increases by 5. if hec correction is disabled, correctable hec count is not affected and uncorrectable hec count increases by 6. note that cell delineation goes to hunt state upon the reception of the 7th consecutiv e hec pattern. receive pmon counters are not updated when cell delineation is out of sync state. note that write access to the receive pmon-counter latch-enable register latches internal receive pmon-counter values and clears them once they are latched. downloaded from: http:///
ds2156 189 of 265 register name: u_racc1 register description: utopia receive-assigned cell count register 1 register address: 66h bit # 7 6 5 4 3 2 1 0 name racc15 racc14 racc13 racc12 racc11 racc10 racc9 racc8 default 0 0 0 0 0 0 0 0 bits0 to 7/receive-assigned cell count 8 to 15 (racc8 to racc15) register name: u_racc2 register description: utopia receive-assigned cell count register 2 register address: 67h bit # 7 6 5 4 3 2 1 0 name racc7 racc6 racc5 racc4 racc3 racc2 racc1 racc0 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive-assigned cell count 0 to 7 (racc0 to racc7) the u_racc1 and u_racc2 registers are common register s for all ports. for software convenience, any of the eight addresses can be used to access these registers. for reading the 16-bit receive assigned cell count for a port, software has to write into the receive pmon-counter latc h-enable register for the por t before reading from these registers. reading from these registers without writing into th e latch-enable register returns the old value that was latched and not the current value of the receive-assigned cell count of a port. the assigned cell count value reflects the number of cells written into receive fifo that can be read by the atm layer since last latching. note that whether or not the atm layer dequeues cells from the receive fifo, the assigned cell counter of a port is incremented upon the reception of a valid atm layer cell when cell delineation is in sync state. downloaded from: http:///
ds2156 190 of 265 register name: u_rsr register description: utopia receive status register register address: 68h bit # 7 6 5 4 3 2 1 0 name cds1 cds0 rms lcds lcdcsis fois default 0 0 0 0 0 1 0 0 bit 0/receive fifo overrun interrupt status (fois). set if the receive fifo overruns provided rxfifo overrun interrupt mask bit (u_rcr2.3) is set. this bit is reset when read. bit 1/lcd change-of-state interrupt status (lcdcsis). set by hardware if lcd status changes, provided that the lcd interrupt-mask bit (u_rcr2.4) is set. the lcds bit indicates the current status of lcd. this bit is reset when read. bit 2/lcd status (lcds) 0 = in-cell delineation 1 = loss-of-cell delineation bit 3/receiver mode status (rms). this bit shows valid status only when hec correction is enabled. 0 = correction mode 1 = detection mode bits 4, 5/cell delineation status 0 to 1 (cds0 to cds1). bit 5 indicates instantaneous ocd status. cds1 cds0 cell delineation status 0 0 hunt state 0 1 presync state 1 x sync state bits 6, 7/unused once a read cycle to this register is de tected, the interrupt status bits are clear ed. if any of the lower two bits is set, the external interrupt signal is asserted. if both the bits ar e 0 for all the ports, the external interrupt signal is de- asserted. downloaded from: http:///
ds2156 191 of 265 register name: u_rcr1 register description: utopia receive control register 1 register address: 69h bit # 7 6 5 4 3 2 1 0 name rucfe ricfe rphec rde rhece rcse default 0 0 0 0 0 0 0 1 bit 0/receive coset subtraction enable (rcse) 0 = ds2156 does not do coset subtraction from the hec byte for checking hec 1 = ds2156 subtracts coset polynomial (0 x 55) from the hec byte for checking hec bit 1/receive hec-error correction enable (rhece) 0 = single-bit hec-error correction is disabled 1 = ds2156 corrects single-bit hec errors based on the cu rrent state of receiver mode of operation. single- bit error correction is done only if this bit is set and receiver mode of operation is in correction state. bit 2/receive descrambling enable (rde) 0 = payload descrambling is disabled 1 = payload descrambling is enabled. payload of cells received in presync and sync state of cell delineation are descrambled based on the self-synchronizing polynomial x 43 + 1. cell header is unaffected by descrambling. bit 3/receive pass hec-errored cells (rphec) 0 = ds2156 passes only error-free and error-corrected cells to atm layer 1 = ds2156 passes all cells including hec-errored cells , received when cell delineation is sync to atm layer bit 4/receive idle cell-filter enable (ricfe) 0 = ds2156 does not filter idle cells 1 = ds2156 filters all idle cells received from being writte n into receive fifo. the cell header of idle cell (first five bytes) is 0x00, 0x00, 0x00, 0x01 and proper hec byte. cell payload is not considered for idle cell filtering. bit 5/receive unassigned cell-filter enable (rucfe) 0 = ds2156 will not filter unassigned cells. 1 = ds2156 filters all unassigned cells received from bei ng written into receive fifo. the cell header of unassigned cell (first five bytes) is 0x00, 0x00, 0x00, 0x00, and proper hec byte. cell payload is not considered for unassigned cell filtering bits 6, 7/unassigned, must be set to 0 for proper operation downloaded from: http:///
ds2156 192 of 265 register name: u_rcr2 register description: utopia receive control register 2 register address: 6ah bit # 7 6 5 4 3 2 1 0 name lcdim rfoim rplim dlbe default 0 0 0 0 0 0 0 0 bit 0/diagnostic loopback enable (dlbe) 0 = normal operation 1 = diagnostic loopback is enabled. in this loopback , the transmit data and clock is looped back onto the receive side. receiver uses transmit data and clock in stead of receive data and clock from physical layer (typically framer). bit 1/receive physical layer interface mode (rplim) 0 = clock + data + frame pulse combination 1 = gapped clock + data combination bit 2/bit must be set = 1 after reset for proper utopia bus mode operation bit 3/receive fifo overrun interrupt mask (rfoim) 0 = ds2156 does not generate external interrupt for receive fifo overrun events 1 = ds2156 generates external interrupt if receive fifo overrun condition has occurred bit 4/lcd interrupt mask (lcdim) 0 = ds2156 does not generate external interrupt for lcd state changes 1 = ds2156 generates external interrupt if lcd state has changed bits 5 to 7/unassigned, must be set to 0 for proper operation downloaded from: http:///
ds2156 193 of 265 24.8 receive fifo overrun receive fifo overrun condition indicates that receive fi fo has been written with four cells before atm layer reads the cells. the four cells that cause receiv e fifo overrun conditions are intact in receive fifo, and subsequent cells are not written into receive fifo until atm layer reads a cell from receive fifo for the port through utopia-ii interface. receive fifo overrun condition can optionally be made to raise external interrupt by sett ing receive fifo overrun interrupt mask bit u_rcr2.3. 24.9 utopia diagnostic loopback diagnostic loopback toward the atm layer side (uto pia side) can be enable d through receive control register 2, u_rcr2.0. in diagnostic loopback, data, clock, and frame- pulse indication generated by the transmit section of the ds2156 are used instead of the corresponding signals from the physical layer device. receive physical interface mode should be conf igured with the same value as transmit physical interface mode. receive active- edge selection bit should be configured as the opposite edge of that used by the transmit section of the ds2156. it is possible to use the internal ly generated system clock divided by 8 in place of tclk for this mode when enabled with u_tcr2.6. downloaded from: http:///
ds2156 194 of 265 25. programmable in-band lo op code generation and detection the ds2156 has the ability to generate and detect a repe ating bit pattern from one to eight bits or 16 bits in length. this function is available only in t1 mode. to transmit a pattern, the user loads the pattern into the transmit code-definition registers (tcd1 and tcd2) and selects the proper length of the pattern by setting the tc0 and tc1 bits in the in-band code control (ibcc) regi ster. when generating a 1-, 2-, 4-, 8-, or 16-bit pattern, both transmit code-definition registers must be filled with the proper code. generation of a 3-, 5-, 6-, and 7-bit pattern only require s tcd1 to be filled. once this is accomplished, the pattern is transm itted as long as the tloop c ontrol bit (t1ccr1.0) is enab led. normally (unless the transmit formatter is programmed to not insert the f-bit position) the framer overwrites the repeating pattern once every 193 bits to send the f-bit position. for example, to transmit the standard loop-up code for csus, which is a repeating pattern of ...10000100001... , set tcd1 = 80h, ibcc = 0, and t1ccr1.0 = 1. the framer has three programmable pa ttern detectors. typically two of the detectors are used for loop- up and loop-down code detectio n. the user programs the codes to be detected in the receive up-code definition (rupcd1 and rupcd2) registers and the receive down-code definition (rdncd1 and rdncd2) registers, and the length of each pattern is selected through the ibcc register. there is a third detector (spare) that is defined and controlled through the rscd1/rscd2 and rscc registers. when detecting a 16-bit pattern, both rece ive code-definition regi sters are used together to form a 16-bit register. for 8-bit patterns, both rece ive code-definition registers are filled with the same value. detection of a 1-, 2-, 3-, 4-, 5-, 6-, and 7-b it pattern only requires the first rece ive code-definition register to be filled. the framer detects repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10e-2. the det ectors are capable of handling both f-bit inserted a nd f-bit overwrite patterns. writing the least significant byte of the recei ve code-definition register resets the integration period for that detector. the code detector has a nominal integration period of 36ms. hence, after about 36ms of receiving a valid code, the proper status bit (lup at sr3.5, ldn at sr3.6, and lspare at sr3.7) is set to a 1. normally codes are sent for a period of five seconds. it is recommended that the software poll the framer every 50ms to 1000ms until five seconds has elapsed to ensure the code is continuously present. downloaded from: http:///
ds2156 195 of 265 register name: ibcc register description: in-band code control register register address: b6h bit # 7 6 5 4 3 2 1 0 name tc1 tc0 rup2 rup1 rup0 rdn2 rdn1 rdn0 default 0 0 0 0 0 0 0 0 bits 0 to 2/receive down-code length definition bits (rdn0 to rdn2) rdn2 rdn1 rdn0 length selected (bits) 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8/16 bits 3 to 5/receive up-code length definition bits (rup0 to rup2) rup2 rup1 rup0 length selected (bits) 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8/16 bits 6, 7/transmit code length definition bits (tc0 to tc1) tc1 tc0 length selected (bits) 0 0 5 0 1 6/3 1 0 7 1 1 16/8/4/2/1 downloaded from: http:///
ds2156 196 of 265 register name: tcd1 register description: transmit code-definition register 1 register address: b7h bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bit 0/transmit code-definition bit 0 (c0). a dont care if a 5-, 6-, or 7-bit length is selected. bit 1/transmit code-definition bit 1 (c1). a dont care if a 5-bit or 6-bit length is selected. bit 2/transmit code-definition bit 2 (c2). a dont care if a 5-bit length is selected. bits 3C6/transmit code-definition bits 3C6 (c3Cc6) bit 7/transmit code-definition bit 7 (c7). first bit of the repeating pattern. register name: tcd2 register description: transmit code definition register 2 register address: b8h bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 least significant byte of 16 bit codes. bits 0C7/transmit code-definition bits 0C7 (c0Cc7). a dont care if a 5-, 6-, or 7-bit length is selected. downloaded from: http:///
ds2156 197 of 265 register name: rupcd1 register description: receive up-code definition register 1 register address: b9h bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 note: writing this register resets the detectors integration period. bit 0/receive up-code definition bits 0 (c0). a dont care if a 1-bit to 7-bit length is selected. bit 1/receive up-code definition bit 1 (c1). a dont care if a 1-bit to 6-bit length is selected. bit 2/receive up-code definition bit 2 (c2). a dont care if a 1-bit to 5-bit length is selected. bit 3/receive up-code definition bit 3 (c3). a dont care if a 1-bit to 4-bit length is selected. bit 4/receive up-code definition bit 4 (c4). a dont care if a 1-bit to 3-bit length is selected. bit 5/receive up-code definition bit 5 (c5). a dont care if a 1-bit or 2-bit length is selected. bit 6/receive up-code definition bit 6 (c6). a dont care if a 1-bit length is selected. bit 7/receive up-code definition bit 7 (c7). first bit of the repeating pattern. register name: rupcd2 register description: receive up-code definition register 2 register address: bah bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0C7/receive up-code definition bits 0C7 (c0Cc7). a dont care if a 1-bit to 7-bit length is selected. downloaded from: http:///
ds2156 198 of 265 register name: rdncd1 register description: receive down-code definition register 1 register address: bbh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 note: writing this register resets the detectors integration period. bit 0/receive down-code definition bit 0 (c0). a dont care if a 1-bit to 7-bit length is selected. bit 1/receive down-code definition bit 1 (c1). a dont care if a 1-bit to 6-bit length is selected. bit 2/receive down-code definition bit 2 (c2). a dont care if a 1-bit to 5-bit length is selected. bit 3/receive down-code definition bit 3 (c3). a dont care if a 1-bit to 4-bit length is selected. bit 4/receive down-code definition bit 4 (c4). a dont care if a 1-bit to 3-bit length is selected. bit 5/receive down-code definition bit 5 (c5). a dont care if a 1-bit or 2-bit length is selected. bit 6/receive down-code definition bit 6 (c6). a dont care if a 1-bit length is selected. bit 7/receive down-code definition bit 7 (c7). first bit of the repeating pattern. register name: rdncd2 register description: receive down-code definition register 2 register address: bch bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0C7/receive down-code definition bits 0C7 (c0Cc7). a dont care if a 1-bit to 7-bit length is selected. downloaded from: http:///
ds2156 199 of 265 register name: rscc register description: in-band receive spare control register register address: bdh bit # 7 6 5 4 3 2 1 0 name rsc2 rsc1 rsc0 default 0 0 0 0 0 0 0 0 bits 0 to 2/receive spare code length definition bits (rsc0 to rsc2) rsc2 rsc1 rsc0 length selected (bits) 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8/16 bits 3 to 7/unused, must be set to 0 for proper operation downloaded from: http:///
ds2156 200 of 265 register name: rscd1 register description: receive spare-code definition register 1 register address: beh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 note: writing this register resets the detectors integration period. bit 0/receive spare-code definition bit 0 (c0). a dont care if a 1-bit to 7-bit length is selected. bit 1/receive spare-code definition bit 1 (c1). a dont care if a 1-bit to 6-bit length is selected. bit 2/receive spare-code definition bit 2 (c2). a dont care if a 1-bit to 5-bit length is selected. bit 3/receive spare-code definition bit 3 (c3). a dont care if a 1-bit to 4-bit length is selected. bit 4/receive spare-code definition bit 4 (c4). a dont care if a 1-bit to 3-bit length is selected. bit 5/receive spare-code definition bit 5 (c5). a dont care if a 1-bit or 2-bit length is selected. bit 6/receive spare-code definition bit 6 (c6). a dont care if a 1-bit length is selected. bit 7/receive spare-code definition bit 7 (c7). first bit of the repeating pattern. register name: rscd2 register description: receive spare code definition register 2 register address: bfh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0C7/receive spare-code definition bits 0C7 (c0Cc7). a dont care if a 1-bit to 7-bit length is selected. downloaded from: http:///
ds2156 201 of 265 26. bert function the bert block can generate and detect pseudorandom an d repeating bit patterns. it is used to test and stress data communication links, an d it is capable of generating and detecting the following patterns: the pseudorandom patterns 2e7, 2e11, 2e15, and qrss a repetitive pattern from 1 to 32 bits in length alternating (16-bit) words that flip every 1 to 256 words daly pattern the bert receiver has a 32-bit bit counter and a 24-b it error counter. the bert receiver reports three events: a change in receive synchronizer status, a bit error being detected, and if either the bit counter or the error counter overflows. each of these events can be masked w ithin the bert function through the bert control register 1 (bc1). if the software dete cts that the bert has reported an event, then the software must read the bert information register (bir) to determine which event(s) has occurred. to activate the bert block, the hos t must configure the bert mux through the bic register. 26.1 status sr9 contains the status informati on on the bert function. the host can be alerted through this register when there is a bert change-of-state. a major cha nge-of-state is defined as either a change in the receive synchronization (i.e., the bert has gone into or out of receive synchronization), a bit error has been detected, or an overflow has occurred in either the bit counter or the erro r counter. the host must read status register 9 (sr9) to determine the change-of-state. 26.2 mapping the bert function can be assigned to the network direction or backpl ane direction through the direction control bit in the bic register (bic.1). see figure 26-1 and figure 26-2. the be rt also can be assigned on a per-channel basis. the bert transmit control se lector (btcs) and bert receive control selector (brcs) bits of the per-channel pointer register (pcpr) are used to map the bert function into time slots of the transmit and receive data stre ams. in t1 mode, the user can enable mapping into the f-bit position for the transmit and receive directions through the rfus and tfus bits in the bert interface control (bic) register. downloaded from: http:///
ds2156 202 of 265 figure 26-1. simplified diagram of bert in network direction figure 26-2. simplified diagram of bert in backplane direction bert transmitter bert receiver per-channel and f-bit (t1 mode) mapping 1 0 from receive framer to receive system backplane interface from transmit system backplane interface to transmit framer per-channel and f-bit (t1 mode) mapping bert transmitter bert receiver 1 0 from receive framer to receive system backplane interface from transmit system backplane interface to transmit framer downloaded from: http:///
ds2156 203 of 265 26.3 bert register descriptions register name: bc1 register description: bert control register 1 register address: e0h bit # 7 6 5 4 3 2 1 0 name tc tinv rinv ps2 ps1 ps0 lc resync default 0 0 0 0 0 0 0 0 bit 0/force resynchronization (resync). a low-to-high transition forces the receive bert synchronizer to resynchronize to the incoming data stream. this bit shoul d be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern. must be cl eared and set again for a subsequent resynchronization. bit 1/load bit and error counters (lc). a low-to-high transition latches the current bit and error counts into registers bbc1/bbc2/bbc3/bbc4 and bec1/bec2/bec3 and clears the internal count. this bit should be toggled from low to high whenever the host wishes to begin a new acquisition period. must be cleared and set again for subsequent loads. bits 2 to 4/pattern select bits (ps0 to ps2) ps2 ps1 ps0 pattern definition 0 0 0 pseudorandom 2e7 - 1 0 0 1 pseudorandom 2e11 - 1 0 1 0 pseudorandom 2e15 - 1 0 1 1 pseudorandom pattern qrss. a 2 20 - 1 pattern with 14 consecutive zero restrictions. 1 0 0 repetitive pattern 1 0 1 alternating word pattern 1 1 0 modified 55 octet (daly) pattern. the daly pattern is a repeating 55 octet pattern that is byte-aligned into the active ds0 time slots. the pattern is defined in an atis (alliance for telecommunications industry solutions) committee t1 technical report number 25 (november 1993). 1 1 1 pseudorandom 2e9 - 1 bit 5/receive invert-data enable (rinv) 0 = do not invert the incoming data stream 1 = invert the incoming data stream bit 6/transmit invert-data enable (tinv) 0 = do not invert the outgoing data stream 1 = invert the outgoing data stream bit 7/transmit pattern load (tc). a low-to-high transition loads the pattern generator with the pattern that is to be generated. this bit should be toggled from low to hi gh whenever the host wishes to load a new pattern. must be cleared and set again for subsequent loads. downloaded from: http:///
ds2156 204 of 265 register name: bc2 register description: bert control register 2 register address: e1h bit # 7 6 5 4 3 2 1 0 name eib2 eib1 eib0 sbe rpl3 rpl2 rpl1 rpl0 default 0 0 0 0 0 0 0 0 bits 0 to 3/repetitive pattern length bit 3 (rpl0 to rpl3). rpl0 is the lsb and rpl3 is the msb of a nibble that describes how long the repetitive pattern is. the valid range is 17 (0000) to 32 ( 1111). these bits are ignored if the receive bert is programmed for a pseudorandom patter n. to create repetitive patterns fewer than 17 bits in length, the user must set the length to an integer number of the desired length that is l ess than or equal to 32. for example, to create a 6-bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30 (1101). length (bits) rpl3 rpl2 rpl1 rpl0 17 0 0 0 0 18 0 0 0 1 19 0 0 1 0 20 0 0 1 1 21 0 1 0 0 22 0 1 0 1 23 0 1 1 0 24 0 1 1 1 25 1 0 0 0 26 1 0 0 1 27 1 0 1 0 28 1 0 1 1 29 1 1 0 0 30 1 1 0 1 31 1 1 1 0 32 1 1 1 1 bit 4/single bit-error insert (sbe). a low-to-high transition creates a single-bit error. must be cleared and set again for a subsequent bit error to be inserted. bits 5 to 7/error insert bits 0 to 2 (eib0 to eib2). automatically inserts bit errors at the prescribed rate into the generated data pattern. can be used fo r verifying error-detection features. eib2 eib1 eib0 error rate inserted 0 0 0 no errors automatically inserted 0 0 1 10e-1 0 1 0 10e-2 0 1 1 10e-3 1 0 0 10e-4 1 0 1 10e-5 1 1 0 10e-6 1 1 1 10e-7 downloaded from: http:///
ds2156 205 of 265 register name: sr9 register description: status register 9 register address: 26h bit # 7 6 5 4 3 2 1 0 name bbed bbco bec0 bra1 bra0 brlos bsync default 0 0 0 0 0 0 0 0 bit 0/bert in synchronization condition (bsync). set when the incoming pattern matches for 32 consecutive bit positions. refer to bsync in the info2 register for a real -time version of this bit. this is a double interrupt bit (section 6.2). bit 1/bert receive loss-of-synchronization condition (brlos). a latched bit that is set whenever the receive bert begins searching for a pattern. once synchroniza tion is achieved, this bit remains set until read. this is a double interrupt bit (section 6.2). bit 2/bert receive all-zeros condition (bra0). a latched bit that is set when 32 consecutive 0s are received. allowed to be cleared once a 1 is received. this is a double interrupt bit (section 6.2). bit 3/bert receive all-ones condition (bra1). a latched bit that is set when 32 consecutive 1s are received. allowed to be cleared once a 0 is received. this is a double interrupt bit (section 6.2). bit 4/bert error-counter overf low (beco) event (beco). a latched bit that is set when the 24-bit bert error counter (bec) overflows. cleared when read a nd is not set again until another overflow occurs. bit 5/bert bit-counter overflow event (bbco). a latched bit that is set when the 32-bit bert bit counter (bbc) overflows. cleared when read and is not set again until another overflow occurs. bit 6/bert bit-error detected (bed) event (bbed). a latched bit that is set when a bit error is detected. the receive bert must be in synchronization for it to detect bit errors. cleared when read. downloaded from: http:///
ds2156 206 of 265 register name: imr9 register description: interrupt mask register 9 register address: 27h bit # 7 6 5 4 3 2 1 0 name bbed bbco bec0 bra1 bra0 brlos bsync default 0 0 0 0 0 0 0 0 bit 0/bert in synchronization condition (bsync) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising and falling edges bit 1/receive loss-of-synchronization condition (brlos) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising and falling edges bit 2/receive all-zeros condition (bra0) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising and falling edges bit 3/receive all-ones condition (bra1) 0 = interrupt masked 1 = interrupt enabledinterrupts on rising and falling edges bit 4/bert error-counter overflow event (beco) 0 = interrupt masked 1 = interrupt enabled bit 5/bert bit-counter overflow event (bbco) 0 = interrupt masked 1 = interrupt enabled bit 6/bit-error detected event (bbed) 0 = interrupt masked 1 = interrupt enabled bert alternating word-count rate. when the bert is programmed in the alternating word mode, the words repeat for the count loaded into this register then flip to the other word and again repeat for the number of times loaded into this register. register name: bawc register description: bert alternating word-count rate register address: dbh bit # 7 6 5 4 3 2 1 0 name acnt7 acnt6 acnt5 acnt4 acnt3 acnt2 acnt1 acnt0 default 0 0 0 0 0 0 0 0 bits 0 to 7/alternating word-count rate bits 0 to 7 (acnt0 to acnt7). acnt0 is the lsb of the 8-bit alternating word-count rate counter. downloaded from: http:///
ds2156 207 of 265 26.4 bert repetitive pattern set these registers must be properly loaded for the bert to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating wo rd pattern, or a daly pattern. for a repetitive pattern that is fewer than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern. for example, if the pattern was the re peating 5-bit pattern 01101 (where th e rightmost bit is the one sent first and received first), then brp1 should be loaded with adh, brp 2 with b5h, brp3 with d6h, and brp4 with 5ah. for a pseudorandom patte rn, all four registers should be lo aded with all 1s (i.e., ffh). for an alternating word pattern, one word should be placed into brp1 and brp2 and the other word should be placed into brp3 and brp4. for example, if the dds stress pattern 7e is to be described, the user would place 00h in brp1, 00h in brp2, 7e h in brp3, and 7eh in brp4 and the alternating word counter would be set to 50 (decimal) to allo w 100 bytes of 00h followed by 100 bytes of 7eh to be sent and received. register name: brp1 register description: bert repetitive pattern set register 1 register address: dch bit # 7 6 5 4 3 2 1 0 name rpat7 rpat6 rpat5 rpat4 rpat3 rpat2 rpat1 rpat0 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert repetitive pattern set bits 0 to 7 (rpat0 to rpat7). rpat0 is the lsb of the 32-bit repetitive pattern set. register name: brp2 register description: bert repetitive pattern set register 2 register address: ddh bit # 7 6 5 4 3 2 1 0 name rpat15 rpat14 rpat13 rpat12 rpat11 rpat10 rpat9 rpat8 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert repetitive pattern set bits 8 to 15 (rpat8 to rpat15) register name: brp3 register description: bert repetitive pattern set register 3 register address: deh bit # 7 6 5 4 3 2 1 0 name rpat23 rpat22 rpat21 rpat20 rpat19 rpat18 rpat17 rpat16 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert repetitive pattern set bits 16 to 23 (rpat16 to rpat23) register name: brp4 register description: bert repetitive pattern set register 4 register address: dfh bit # 7 6 5 4 3 2 1 0 name rpat31 rpat30 rpat29 rpat28 rpat27 rpat26 rpat25 rpat24 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert repetitive pattern set bits 24 to 31 (rpat24 to rpat31). rpat31 is the lsb of the 32-bit repetitive pattern set. downloaded from: http:///
ds2156 208 of 265 26.5 bert bit counter once bert has achieved synchronization, this 32-bit coun ter increments for each data bit (i.e., clock) received. toggling the lc c ontrol bit in bc1 can clear this counter. this counter saturates when full and sets the bbco status bit. register name: bbc1 register description: bert bit count register 1 register address: e3h bit # 7 6 5 4 3 2 1 0 name bbc7 bbc6 bbc5 bbc4 bbc3 bbc2 bbc1 bbc0 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert bit counter bits 0 to 7 (bbc0 to bbc7). bbc0 is the lsb of the 32-bit counter. register name: bbc2 register description: bert bit count register 2 register address: e4h bit # 7 6 5 4 3 2 1 0 name bbc15 bbc14 bbc13 bbc12 bbc11 bbc10 bbc9 bbc8 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert bit counter bits 8 to 15 (bbc8 to bbc15) register name: bbc3 register description: bert bit count register 3 register address: e5h bit # 7 6 5 4 3 2 1 0 name bbc23 bbc22 bbc21 bbc20 bbc19 bbc18 bbc17 bbc16 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert bit counter bits 16 to 23 (bbc16 to bbc23) register name: bbc4 register description: bert bit count register 4 register address: e6h bit # 7 6 5 4 3 2 1 0 name bbc31 bbc30 bbc29 bbc28 bbc27 bbc26 bbc25 bbc24 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert bit counter bits 24 to 31 (bbc24 to bbc31). bbc31 is the msb of the 32-bit counter. downloaded from: http:///
ds2156 209 of 265 26.6 bert error counter once bert has achieved synchronization, this 24-bit c ounter increments for each data bit received in error. toggling the lc control bit in bc1 can clear this counter. this counter saturates when full and sets the beco status bit. register name: bec1 register description: bert error-count register 1 register address: e7h bit # 7 6 5 4 3 2 1 0 name ec7 ec6 ec5 ec4 ec3 ec2 ec1 ec0 default 0 0 0 0 0 0 0 0 bits 0 to 7/error counter bits 0 to 7 (ec0 to ec7). ec0 is the lsb of the 24-bit counter. register name: bec2 register description: bert error-count register 2 register address: e8h bit # 7 6 5 4 3 2 1 0 name ec15 ec14 ec13 ec12 ec11 ec10 ec9 ec8 default 0 0 0 0 0 0 0 0 bits 0 to 7/error counter bits 8 to 15 (ec8 to ec15) register name: bec3 register description: bert error-count register 3 register address: e9h bit # 7 6 5 4 3 2 1 0 name ec23 ec22 ec21 ec20 ec19 ec18 ec17 ec16 default 0 0 0 0 0 0 0 0 bits 0 to 7/error counter bits 16 to 23 (ec16 to ec23). ec0 is the msb of the 24-bit counter. downloaded from: http:///
ds2156 210 of 265 register name: bic register description: bert interface control register register address: eah bit # 7 6 5 4 3 2 1 0 name rfus tbat tfus bertdir berten default 0 0 0 0 0 0 0 0 bit 0/bert enable (berten) 0 = bert disabled 1 = bert enabled bit 1/bert direction (bertdir) 0 = network bert transmits toward the network (ttip and tring) and receives from the network (rtip and rring). the bert pattern can be looped back to the receiver internally by using the framer loopback function. 1 = system bert transmits toward the system backplane (rser ) and receives from the system backplane (tser). bits 2, 5, 7/unused, must be set to 0 for proper operation bit 3/transmit framed/unframed select (tfus) 0 = bert does not source data into the f-bit position (framed) 1 = bert does source data into the f-bit position (unframed) bit 4/transmit byte-align toggle (tbat). a 0-to-1 transition forces the bert to byte align its pattern with the transmit formatter. this bit must be transiti oned in order to byte align the daly pattern. bit 6/receive framed/unframed select (rfus) 0 = bert is not sent data from the f-bit position (framed) 1 = bert is sent data from the f-bit position (unframed) downloaded from: http:///
ds2156 211 of 265 27. payload error-insertion function (t1 mode only) an error-insertion function is avai lable in the ds2156 and is used to create errors in the payload portion of the t1 frame in the transmit path. this function is only available in t1 mode . errors can be inserted over the entire frame or the user can select which channels are to be corrupted. errors are created by inverting the last bit in the count sequence. for example, if th e error rate 1 in 16 is selected, the 16th bit is inverted. f-bits are excluded from the count and ar e never corrupted. error rate changes occur on frame boundaries. error-insertion options include continuous and absolute number with both options supporting selectable insertion rates. table 27-a. transmit erro r-insertion setup sequence step action 1 enter desired error rate in the erc regist er. note: if er3 through er0 = 0, no errors are generated even if the constant error-insertion feature is enabled. 2a or 2b for constant error insertion, set ce = 1 (erc.4). for a defined number of errors: C set ce = 0 (erc.4) C load noe1 and noe2 with the number of errors to be inserted C toggle wnoe (erc.7) from 0 to 1 to begin error insertion downloaded from: http:///
ds2156 212 of 265 register name: erc register description: error-rate control register register address: ebh bit # 7 6 5 4 3 2 1 0 name wnoe ce er3 er2 er1 er0 default 0 0 0 0 0 0 0 0 bits 0 to 3/error-insertion rate select bits (er0 to er3) er3 er2 er1 er0 error rate 0 0 0 0 no errors inserted 0 0 0 1 1 in 16 0 0 1 0 1 in 32 0 0 1 1 1 in 64 0 1 0 0 1 in 128 0 1 0 1 1 in 256 0 1 1 0 1 in 512 0 1 1 1 1 in 1024 1 0 0 0 1 in 2048 1 0 0 1 1 in 4096 1 0 1 0 1 in 8192 1 0 1 1 1 in 16,384 1 1 0 0 1 in 32,768 1 1 0 1 1 in 65,536 1 1 1 0 1 in 131,072 1 1 1 1 1 in 262,144 bit 4/constant errors (ce). when this bit is set high (and the er0 to er3 bits are not set to 0000), the error- insertion logic ignores the number-of-error registers (noe1, noe2) and generates errors constantly at the selected insertion rate. when ce is set to 0, the noex regist ers determine how many errors are to be inserted. bits 5, 6/unused, must be set to 0 for proper operation bit 7/write noe registers (wnoe). if the host wishes to update to the noex registers, this bit must be toggled from a 0 to a 1 after the host has already loaded the prescr ibed error count into the noex registers. the toggling of this bit causes the error count loaded into the noex registers to be loaded into the error-insertion circuitry on the next clock cycle. subsequent updates require that the wnoe bit be set to 0 and then 1 once again. downloaded from: http:///
ds2156 213 of 265 27.1 number-of-errors registers the number-of-error registers determine how many e rrors are generated. up to 1023 errors can be generated. the host loads the number of errors to be generated into the noe1 and noe2 registers. the host can also update the number of erro rs to be created by first loading the prescribed value into the noe registers and then toggling the wnoe bit in the error-rate control registers. table 27-b. error insertion examples value write read 000h do not create any errors no errors left to be inserted 001h create a single error one error left to be inserted 002h create two errors two errors left to be inserted 3ffh create 1023 errors 1023 errors left to be inserted register name: noe1 register description: number-of-errors 1 register address: ech bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0 to 7/number-of-errors counter bits 0 to 7 (c0 to c7). bit c0 is the lsb of the 10-bit counter. register name: noe2 register description: number-of-errors 2 register address: edh bit # 7 6 5 4 3 2 1 0 name c9 c8 default 0 0 0 0 0 0 0 0 bits 0, 1/number-of-errors count er bits 8 to 9 (c8 to c9). bit c9 is the msb of the 10-bit counter. downloaded from: http:///
ds2156 214 of 265 27.1.1 number-of-errors left register the host can read the noelx registers at any time to de termine how many errors are left to be inserted. register name: noel1 register description: number-of-errors left 1 register address: eeh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0 to 7/number-of-errors left counter bits 0 to 7 (c0 to c7). bit c0 is the lsb of the 10-bit counter. register name: noel2 register description: number-of-errors left 2 register address: efh bit # 7 6 5 4 3 2 1 0 name c9 c8 default 0 0 0 0 0 0 0 0 bits 0, 1/number-of-errors left co unter bits 8 to 9 (c8 to c9). bit c9 is the msb of the 10-bit counter. downloaded from: http:///
ds2156 215 of 265 28. interleaved pcm bus operation (ibo) note: the interleaved pcm bus operation is not avai lable when utopia backplane is enabled. in many architectures, the pcm outputs of individual framers are combined into higher speed pcm buses to simplify transport across the system backplane. the ds2156 can be configured to allow pcm data to be multiplexed into higher speed buses eliminating external hardware, saving board space and cost. the ds2156 can be configured for channel or frame interleave. the interleaved pcm bus operation (ibo) supports three bus speeds. the 4.096mhz bus speed allows two pcm data streams to share a common bus. the 8.192mhz bus speed allows four pcm data streams to share a common bus. the 16.384mhz bus speed allows eight pcm data stream s to share a common bus. see figure 28-1 for an example of four tran sceivers sharing a common 8.192mhz pcm bus. the receive elastic stores of each tr ansceiver must be enabled. through the ibo register, the user can configure each transceiver for a specific bus position. for all ibo bus configurations, each transceiver is assigned an exclusive position in th e high-speed pcm bus. the 8khz frame sync can be generated from the system backplane or from the first device on th e bus. all other devices on the bus must have their frame syncs configured as inputs. relative to this common frame sync, the devi ces await their turn to drive or sample the bus according to the settings of the da0, da1, a nd da2 bits of the iboc register. 28.1 channel interleave in channel interleave mode, data is output to the pcm data-out bus one channel at a time from each of the connected ds2156s until all channels of frame n from each ds2156 have been placed on the bus. this mode can be used even when the ds2156s are opera ting asynchronous to each other. the elastic stores manage slip conditions (figure 34-22). 28.2 frame interleave in frame interleave mode, data is output to the pcm data-out bus one frame at a time from each of the ds2156s. this mode is used only when all connect ed ds2156s are operating in a synchronous fashion (all inbound t1 or e1 lines are synchronous) and ar e synchronous with the system clock (system clock derived from t1 or e1 line). slip conditions are not allowed in this mode (figure 34-23). downloaded from: http:///
ds2156 216 of 265 register name: iboc register description: interleave bus operation control register register address: c5h bit # 7 6 5 4 3 2 1 0 name ibs1 ibs0 ibosel iboen da2 da1 da0 default 0 0 0 0 0 0 0 0 bits 0 to 2/device assignment bits (da0 to da2) da2 da1 da0 device position on bus 0 0 0 1st 0 0 1 2nd 0 1 0 3rd 0 1 1 4th 1 0 0 5th 1 0 1 6th 1 1 0 7th 1 1 1 8th bit 3/interleave bus operation enable (iboen) 0 = ibo disabled 1 = ibo enabled bit 4/interleave bus operation select (ibosel). this bit selects channel or frame interleave mode. 0 = channel interleave 1 = frame interleave bits 5, 6/ibo bus size bit 1 (ibs0 to ibs1). indicates how many devices are on the bus. ibs1 ibs0 bus size 0 0 two devices on bus 0 1 four devices on bus 1 0 eight devices on bus 1 1 reserved for future use bit 7/unused, must be set to 0 for proper operation downloaded from: http:///
ds2156 217 of 265 figure 28-1. ibo example rsysclk tsysclk rsync tssync rsig tsig tser rser rsysclk tsysclk rsig tsig tser rser rsysclk tsysclk rsigtsig tserrser rsysclk tsysclk rsigtsig tserrser 8.192mhz system clock in system 8khz frame sync in pcm data out pcm data in pcm signaling out pcm signaling in rsync tssync rsync tssync rsync tssync ds2156 #1 ds2156 #2 ds2156 #4 ds2156 #3 downloaded from: http:///
ds2156 218 of 265 29. extended system in formation bus (esib) the extended system information bus (esib) allows up to eight ds2156s to share an 8-bit cpu bus for reporting alarms and interrupt stat us as a group. with a single bus read, the host can be updated with alarm or interrupt status from all members of the group. there are two control registers (esibcr1 and esibcr2) and four information registers (esib1, esib2, esib3, and esib4). for example, eight ds2156s can be grouped into an esib group. a single read of the esib1 register of any member of the group yields the interrupt status of all eight ds2156s . therefore, the host can determine which device or devices are causing an interrupt wi thout polling all eight devices. through esib2, the host can gather synchronization status on all members of the gr oup. esib3 and esib4 can be programmed to report various alarms on a device-by-device basis. there are three device pins invol ved in forming an esib group: esibs0, esibs1, and esibrd. a 10k ? pullup resistor must be provided on esibs0, esibs1, and esibrd. figure 29-1. esib group of four ds2156s esib0 esib1 esibrd cpu i/f ds2156 # 1 esib0 esib1 esibrd cpu i/f ds2156 # 2 esib0 esib1 esibrd cpu i/f ds2156 # 3 esib0 esib1 esibrd cpu i/f ds2156 # 4 v dd 10k ? (3) downloaded from: http:///
ds2156 219 of 265 register name: esibcr1 register description: extended system information bus control register 1 register address: b0h bit # 7 6 5 4 3 2 1 0 name esibsel2 esibsel1 esibsel0 esien default 0 0 0 0 0 0 0 0 bit 0/extended system information bus enable (esien) 0 = disabled 1 = enabled bits 1 to 3/output data bus line select (esibsel0 to esibsel2). these bits tell the ds2156 what data bus bit to output the esib data on when one of the esib in formation registers is accessed. each member of the esib group must have a unique bit selected. esibsel2 esibsel1 esibsel0 bus bit driven 0 0 0 ad0 0 0 1 ad1 0 1 0 ad2 0 1 1 ad3 1 0 0 ad4 1 0 1 ad5 1 1 0 ad6 1 1 1 ad7 bits 4 to 7/unused, must be set to 0 for proper operation downloaded from: http:///
ds2156 220 of 265 register name: esibcr2 register description: extended system information bus control register 2 register address: b1h bit # 7 6 5 4 3 2 1 0 name esi4sel2 esi4sel1 esi4sel0 esi3sel2 esi3sel1 esi3sel0 default 0 0 0 0 0 0 0 0 bits 0 to 2/address esi3 data output select (esi3sel0 to esi3sel2). these bits select what status is to be output when the ds2156 decodes an esi3 address during a bus read operation. esi3sel2 esi3sel1 esi3sel0 status output (t1 mode) status output (e1 mode) 0 0 0 rbl rua1 0 0 1 ryel rra 0 1 0 lup rdma 0 1 1 ldn v52lnk 1 0 0 sigchg sigchg 1 0 1 esslip esslip 1 1 0 1 1 1 bit 3 / unused, must be set to 0 for proper operation bits 4 to 6/address esi4 data-output select (esi4sel0 to esi4sel2). these bits select what status is to be output when the ds2156 decodes an esi4 address during a bus read operation. esi4sel2 esi4sel1 esi4sel0 status output (t1 mode) status output (e1 mode) 0 0 0 rbl rua1 0 0 1 ryel rra 0 1 0 lup rdma 0 1 1 ldn v52lnk 1 0 0 sigchg sigchg 1 0 1 esslip esslip 1 1 0 1 1 1 bit 7/unused, must be set to 0 for proper operation downloaded from: http:///
ds2156 221 of 265 register name: esib1 register description: extended system information bus register 1 register address: b2h bit # 7 6 5 4 3 2 1 0 name disn disn disn disn disn disn disn disn default 0 0 0 0 0 0 0 0 bits 0 to 7/device interrupt status (disn). causes all devices participating in the esib group to output their interrupt status on the appropriate data bus line selected by the esibsel0 to esibsel2 bits of the esibcr1 register. register name: esib2 register description: extended system information bus register 2 register address: b3h bit # 7 6 5 4 3 2 1 0 name drlosn drlosn drlosn drlosn drlosn drlosn drlosn drlosn default 0 0 0 0 0 0 0 0 bits 0 to 7/device receive loss-of-sync (drlosn). causes all devices participating in the esib group to output their frame synchronization status on th e appropriate data bus line selected by the esibsel0 to esibsel2 bits of the esibcr1 register. register name: esib3 register description: extended system information bus register 3 register address: b4h bit # 7 6 5 4 3 2 1 0 name ust1n ust1n ust1n ust 1n ust1n ust1n ust1n ust1n default 0 0 0 0 0 0 0 0 bits 0 to 7/user-selected status 1 (ust1n). causes all devices participating in the esib group to output status or alarms as selected by the esi3sel0 to esi3sel2 bits in the esibcr2 configuration register on the appropriate data bus line selected by the esibsel0 to esibsel2 bits of the esibcr2 register register name: esib4 register description: extended system information bus register 4 register address: b5h bit # 7 6 5 4 3 2 1 0 name ust2n ust2n ust2n ust 2n ust2n ust2n ust2n ust2n default 0 0 0 0 0 0 0 0 bits 0 to 7/user-selected status 2 (ust2n). causes all devices participating in the esib group to output status or alarms as selected by the esi4sel0 to esi4sel2 bits in the esibcr2 configuration register on the appropriate data bus line selected by the esibsel0 to esibsel2 bits of the esibcr2 register downloaded from: http:///
ds2156 222 of 265 30. programmable backpl ane clock synthesizer the ds2156 contains an on-chip clock synthesizer th at generates a user-selec table clock output on the bpclk pin, referenced to the recovered receive cloc k (rclk). the synthesizer uses a phase-locked loop to generate low-jitter clocks. co mmon applications include generati on of port and backplane system clocks. the ccr2 register is used to enable (ccr2.0) and select (ccr 2.1 and ccr2.2) the clock frequency of the bpclk pin. register name: ccr2 register description: common control register 2 register address: 71h bit # 7 6 5 4 3 2 1 0 name trpa4 trpa3 trpa2 trpa 1 trpa0 bpcs1 bpcs0 bpen default 0 0 0 0 0 0 0 0 bit 0/backplane clock enable (bpen) 0 = disable bpclk pin (pin held at logic 0) 1 = enable bpclk pin bits 1, 2/backplane clock selects (bpcs0, bpcs1) bpcs1 bpcs0 bpclk frequency (mhz) 0 0 16.384 0 1 8.192 1 0 4.096 1 1 2.048 bits 3 to 7/utopia port address (trpa0 to trpa4). see register definitions in section 24.7. 31. fractional t1/e1 support 31.1 tdm backplane mode the ds2156 can be programmed to output gapped cloc ks for selected channels in the receive and transmit paths to simplify connections into a usar t or lapd controller in fractional t1/e1 or isdn- pri applications. the receive and transmit paths ha ve independent enables. channel formats supported include 56kbps and 64kbps. this is accomplished by a ssigning an alternate func tion to the rchclk and tchclk pins. setting ccr3.0 = 1 cau ses the rchclk pin to output a gapped clock as defined by the receive fractional t1/e1 function of the pcpr regi ster. setting ccr3.2 = 1 cau ses the tchclk pin to output a gapped clock as defined by the transmit fractional t1/e1 func tion of the pcpr register. ccr3.1 and ccr3.3 can be used to select between 64kbps a nd 56kbps operation. see section 5 for details about programming the per-channel function. in t1 mode no clock is generated at the f-bit position. when 56kbps mode is selected, the ls b clock in the channel is omitted. only the seven most significant bits of the channel have clocks. downloaded from: http:///
ds2156 223 of 265 31.2 utopia backplane mode atm traffic can be assigned on a fractional basis. see section 24 for utopia operation. register name: ccr3 register description: common control register 3 register address: 72h bit # 7 6 5 4 3 2 1 0 name tmss intdis cttui crrui tdatfmt tgpcken rdatfmt rgpcken default 0 0 0 0 0 0 0 0 bit 0/receive gapped-clock enable (rgpcken) 0 = rchclk functions normally 1 = enable gapped bit-clock output on rchclk bit 1/receive channel-data format (rdatfmt) 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in seven out of the 8 bits) bit 2/transmit gapped-clock enable (tgpcken) 0 = tchclk functions normally 1 = enable gapped bit-clock output on tchclk bit 3/transmit channel-data format (tdatfmt) 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in seven out of the 8 bits) bit 4/connect rclk to receive utopia interface (crrui). this bit selects either a constant clock (rclk) or a gapped clock from the framer (progra mmed by the user) as its data clock. 0 = gated clock is connected to receive utopia interface 1 = rclk is connected to receive utopia interface bit 5/connect tclk to transmit utopia interface (cttui). this bit selects either a constant clock (tclk) or a gapped clock from the framer (progra mmed by the user) as its data clock. 0 = gated clock is connected to transmit utopia interface 1 = tclk is connected to transmit utopia interface bit 6/interrupt disable (intdis). this bit is convenient for disabling in terrupts without altering the various interrupt mask register settings. 0 = interrupts are enabled according to the various mask register settings 1 = interrupts are disabled regardless of the mask register settings bit 7/transmit multiframe sync source (tmss). should be set = 0 only when transmit hardware signaling is enabled. 0 = elastic store is source of multiframe sync 1 = framer or tsync pin is source of multiframe sync downloaded from: http:///
ds2156 224 of 265 32. user-programmable output pins the ds2156 provides four user-progr ammable output pins. the pins are automatically cleared to 0 at power-up or as a result of a hard ware- or software-issued reset. register name: ccr4 register description: common control register 4 register address: 73h bit # 7 6 5 4 3 2 1 0 name rlt3 rlt2 rlt1 rlt0 uop3 uop2 uop1 uop0 default 0 0 0 0 0 0 0 0 bit 0/user-defined output 0 (uop0) 0 = logic 0 level at pin 1 = logic 1 level at pin bit 1/user-defined output 1 (uop1) 0 = logic 0 level at pin 1 = logic 1 level at pin bit 2/user-defined output 2 (uop2) 0 = logic 0 level at pin 1 = logic 1 level at pin bit 3/user-defined output 3 (uop3) 0 = logic 0 level at pin 1 = logic 1 level at pin bits 4 to 7/receive level threshold bits (rlt0 to rlt3) rlt3 rlt2 rlt1 rlt0 receive level (db) 0 0 0 0 greater than -2.5 0 0 0 1 -2.5 0 0 1 0 -5.0 0 0 1 1 -7.5 0 1 0 0 -10.0 0 1 0 1 -12.5 0 1 1 0 -15.0 0 1 1 1 -17.5 1 0 0 0 -20.0 1 0 0 1 -22.5 1 0 1 0 -25.0 1 0 1 1 -27.5 1 1 0 0 -30.0 1 1 0 1 -32.5 1 1 1 0 -35.0 1 1 1 1 less than -37.5 downloaded from: http:///
ds2156 225 of 265 33. jtag boundary scan archi tecture and test access port 33.1 description the ds2156 ieee 1149.1 design supports the sta ndard instruction codes sample/preload, bypass, and extest. optional public instructi ons included are high-z, clamp, and idcode (figure 33-1.). the ds2156 contains the following features as required by ieee 1149.1 standard test access port (tap) and boundary scan architecture. test access port tap controller instruction register bypass register boundary scan register device identification register the ds2156 is pin-compatible with the ds 2152, ds21x52 (t1) and ds2154, ds21x54 (e1) sct families. the jtag feature uses pins that had no function in the ds2152 and ds2154. details about boundary scan architecture and the tap are in ieee 1149.1-1990, ieee 1149.1a-1993, and ieee 1149.1b-1994. the tap contains the necessary interface pins jt rst, jtclk, jtms, jtdi, and jtdo. see the pin descriptions in secti on 3 for details. figure 33-1. jtag functional block diagram +v boundary scan register identification register bypass register instruction register jtdi jtms jtclk jtrst jtdo +v +v test access port controller mux 10k ? 10k ? 10k ? select output enable downloaded from: http:///
ds2156 226 of 265 tap controller state machine the tap controller is a finite stat e machine that responds to the logic level at jtms on the rising edge of jtclk (figure 33-2). test-logic-reset upon power-up, the tap controlle r is in the test-logic-reset state. th e instruction register contains the idcode instruction. all system logi c of the device operates normally. run-test-idle the run-test-idle is used between scan operations or during specific tests. the instruction register and test registers remain idle. select-dr-scan all test registers retain their previous state. with jtms low, a rising edge of jtclk moves the controller into the capture-dr state and initiates a scan sequence. jtms high during a rising edge on jtclk moves the controller to the select-ir-scan state. capture-dr data can be parallel-loaded into the test data register s selected by the current instruction. if the instruction does not call for a parallel load or the selected regist er does not allow parallel loads, the test register remains at its current value. on the rising edge of jtclk, the controller goes to the shift-dr state if jtms is low or it goes to the exit1-dr state if jtms is high. shift-dr the test data register selected by the current instru ction is connected between jtdi and jtdo and shifts data one stage toward its serial output on each rising edge of jtclk. if a test register selected by the current instruction is not placed in the seri al path, it maintains its previous state. exit1-dr while in this state, a rising edge on jtclk puts the controller in the update-dr state, which terminates the scanning process, if jtms is high. a rising edge on jtclk with jtms low puts the controller in the pause-dr state. pause-dr shifting of the test registers is halted while in th is state. all test regist ers selected by the current instruction retain their previous state. the controlle r remains in this state while jtms is low. a rising edge on jtclk with jtms high puts the controller in the exit2-dr state. exit2-dr a rising edge on jtclk with jtms high while in this state puts the controller in the update-dr state and terminates the scanning process. a rising edge on jtclk with jtms low enters the shift-dr state. update-dr a falling edge on jtclk while in the update-dr state latches the data from the shift register path of the test registers into the data output latches. this prev ents changes at the parallel output because of changes in the shift register. downloaded from: http:///
ds2156 227 of 265 select-ir-scan all test registers retain their previo us state. the instruction register re mains unchanged duri ng this state. with jtms low, a rising edge on jtclk moves the c ontroller into the capture-ir state and initiates a scan sequence for the instruction register. jtms hi gh during a rising edge on jtclk puts the controller back into the test-logic-reset state. capture-ir the capture-ir state is used to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of jtclk. if jtms is high on the rising edge of jtclk, the controller enters the exit1-ir state. if jtms is low on the rising edge of jtclk, the controller enters the shift-ir state. shift-ir in this state, the shift register in the instruction register is connected between jtdi and jtdo and shifts data one stage for every rising edge of jtclk toward the serial output. the parallel register and all test registers remain at their previous states. a rising edge on jtclk w ith jtms high moves the controller to the exit1-ir state. a rising edge on jtclk with jtms low keeps the controller in the shift-ir state while moving data one stage through the instruction shift register. exit1-ir a rising edge on jtclk with jtms low puts the controll er in the pause-ir state. if jtms is high on the rising edge of jtclk, the controller enters the update-ir state and terminates the scanning process. pause-ir shifting of the instruction shift register is halted temporarily. with jtms high, a rising edge on jtclk puts the controller in the exit2-ir state. the controll er remains in the pause-ir state if jtms is low during a rising edge on jtclk. exit2-ir a rising edge on jtclk with jtms low puts the contro ller in the update-ir stat e. the controller loops back to shift-ir if jtms is high during a rising edge of jtclk in this state. update-ir the instruction code shifted into the instruction shif t register is latched into the parallel output on the falling edge of jtclk as the contro ller enters this state. once latched, this instruction becomes the current instruction. a rising edge on jtclk with jt ms low puts the controller in the run-test-idle state. with jtms high, the controller enters the select-dr-scan state. downloaded from: http:///
ds2156 228 of 265 figure 33-2. tap controller state diagram 33.2 instruction register the instruction register contains a shif t register as well as a latched parall el output and is 3 bits in length. when the tap controller enters the shift-ir state, the instruction shift register is connected between jtdi and jtdo. while in the shift-ir state, a rising edge on jtclk with jtms low shifts the data one stage toward the serial output at jtdo. a rising edge on jt clk in the exit1-ir state or the exit2-ir state with jtms high moves the controller to the update-ir st ate. the falling edge of that same jtclk latches the data in the instruction shift re gister to the instruction parallel output. instructions supported by the ds2156 and its respective operational bina ry codes are shown in table 16-a. 10 0 1 11 1 11 1 1 11 1 1 00 0 00 1 0 0 0 0 1 1 0 0 0 0 select dr-scan capture dr shift dr exit dr pause dr exit2 dr update dr select ir-scan capture ir shift ir exit ir pause ir exit2 ir update ir test logic reset run test/ idle 0 downloaded from: http:///
ds2156 229 of 265 table 33-a. instruction codes for ieee 1149.1 architecture instruction selected register instruction codes sample/preload boundary scan 010 bypass bypass 111 extest boundary scan 000 clamp bypass 011 highz bypass 100 idcode device identification 001 sample/preload this is a mandatory instruction for the ieee 1149.1 spec ification that supports two functions. the digital i/os of the device can be sampled at the boundary s can register without interfering with the normal operation of the device by using th e capture-dr state. sample/prel oad also allows the device to shift data into the boundary scan register through jtdi using the shift-dr state. bypass when the bypass instruction is latched into the pa rallel instruction regist er, jtdi connects to jtdo through the 1-bit bypass test register. this allows data to pass from jtdi to jtdo without affecting the devices normal operation. extest this allows testing of all interconne ctions to the device. when the ex test instruction is latched in the instruction register, the following ac tions occur: once enabled through th e update-ir state, the parallel outputs of all digital output pins are driven. the bounda ry scan register is c onnected between jtdi and jtdo. the capture-dr samples all digital inputs into the boundary scan register. clamp all digital outputs of the device output data from the boundary scan parallel output while connecting the bypass register between jtdi and jtdo. the output s do not change during the clamp instruction. highz all digital outputs of the device are placed in a high- impedance state. the bypass register is connected between jtdi and jtdo. idcode when the idcode instruction is latched into the pa rallel instruction register, the identification test register is selected. the device identification code is loaded into the identification register on the rising edge of jtclk following entry into the capture-dr state. shift-dr can be used to shift the identification code out serially through jtdo. during test-logic-reset, the identification code is forced into the instruction registers parallel output. the id code always has a 1 in the lsb position. the next 11 bits identify the manufacturers jedec number and number of continuati on bytes followed by 16 bits for the device and 4 bits for the version (t able 33-b). table 33-c lists the devi ce id codes for the sct devices. downloaded from: http:///
ds2156 230 of 265 table 33-b. id code structure msb lsb version contact factory device id jedec 1 4 bits 16 bits 00010100001 1 table 33-c. device id codes part 16-bit id ds2156 0019h ds2155 0010h ds21354 0005h ds21564 0003h ds21352 0004h ds21562 0002h 33.3 test registers ieee 1149.1 requires a minimum of two te st registers, the boundary scan register and the bypass register. an optional test register, the iden tification register, has been included with the ds2156 design. it is used with the idcode instruction and the test-l ogic-reset state of the tap controller. 33.4 boundary scan register this register contains both a shift re gister path and a latched parallel ou tput for all control cells and digital i/o cells. it is n bits in length. see table 33-d for ce ll bit locations and definitions. 33.5 bypass register this is a single one-bit shift register used with the bypass, clamp, and high-z instructions that provides a short path between jtdi and jtdo. 33.6 identification register the identification register contains a 32-bit shift register and a 32-bit la tched parallel output. this register is selected during the idcode instruction and when th e tap controller is in th e test-logic-reset state. see table 33-b and table 33-c for more information on bit usage. downloaded from: http:///
ds2156 231 of 265 table 33-d. boundary scan control bits ( ) = alternate function when in utopia backplane mode. bit pin name type control bit function 3 1 rchblk (ur_soc) o 2 jtms i 2 bpclk.cntl 0 = bpclk is an input (ur_enb) 1 = bpclk is an output 1 3 bpclk (ur_enb) i/o 4 jtclk i 5 jtrst i 0 6 rcl o 7 jtdi i 98 uop0.cntl 0 = uop0 is an input ut_soc 1 = uop0 is an output 97 8 uop0 (ut_soc) i/o 96 uop1.cntl 0 = uop1 is an input ut_enb 1 = uop1 is an output 95 9 uop1 (ut_enb) i/o 10 jtdo o 94 11 bts i 93 liuc.cntl 0 = liuc is an input 1 = liuc is an output (ut_clav) 92 12 liuc (ut_clav) i/o 91 13 8xclk o 90 14 tstrst i 89 15 uop2 o 16 rtip i 17 rring i 18 rvdd 19, 20, 24 rvss 21 mclk i 22 xtald o 88 uop3.cntl 0 = uop3 is an input (ut_addr0) 1 = uop3 is an output 87 23 uop3 (ut_addr0) i/o 86 25 int o 85 26 tusel i 27, 28 n.c. 29 ttip o 30 tvss 31 tvdd 32 tring o 84 tchblk.cntl 0 = tchblk is an input (ut_addr1) 1 = tchblk is an output 83 33 tchblk (ut_addr1) i/o 82 tlclk.cntl 0 = tlclk is an input (ut_addr2) 1 = tlclk is an output 81 34 tlclk (ut_addr2) i/o 80 35 tlink (ut_addr3) i 79 esibs0.cntl 0 = esibs0 is an input 1 = esibs0 is an output 78 36 esibs0 i/o 77 tsync.cntl 0 = tsync is an input downloaded from: http:///
ds2156 232 of 265 bit pin name type control bit function 1 = tsync is an output 76 37 tsync i/o 75 38 tposi (ut_addr4) i 74 39 tnegi (ut_data0) i 73 40 tclki (ut_data1) i 72 tclko.cntl 0 = tclko is an input (ut_data2) 1 = tclko is an output 71 41 tclko (ut_data2) i/o 70 tnego.cntl 0 = tnego is an input (ut_data3) 1 = tnego is an output (ut_data4) 69 42 tnego (ut_data3) i/o 68 tposo.cntl 0 = tposo is an input (ut_data4) 1 = tposo is an output 67 43 tposo (ut_data4) i/o 44 dvdd 45 dvss 66 46 tclk i 65 47 tser (ut_data5) i 64 48 tsig (ut_data6) i 63 49 teso (ut_utdo) o 62 50 tdata i 61 51 tsysclk (ut_data7) i 60 52 tssync (ut_clk) i 59 tchclk.cntl 0 = tchclk is an input (ur_clk) 1 = tchclk is an output 58 53 tchclk (ur_clk) i/o 57 esibs1.cntl 0 = esibs1 is an input 1 = esibs1 is an output 56 54 esibs1 i/o 55 55 mux i 54 bus.cntl 0 = d0Cd7/ad0Cad7 are inputs 1 = d0Cd7/ad0Cad7 are inputs 53 56 d0/ad0 i/o 52 57 d1/ad1 i/o 51 58 d2/ad2 i/o 50 59 d3/ad3 i/o 60, 80, 84 dvss 61, 81, 83 dvdd 49 62 d4/ad4 i/o 48 63 d5/ad5 i/o 47 64 d6/ad6 i/o 46 65 d7/ad7 i/o 45 66 a0 i 44 67 a1 i 43 68 a2 i 42 69 a3 i 41 70 a4 i 40 71 a5 i 39 72 a6 i 38 73 ale(as)/a7 i 37 74 rd ( ds ) i 36 75 cs i 35 esibrd.cntl 0 = esibrd is an input 1 = esibrd is an output downloaded from: http:///
ds2156 233 of 265 bit pin name type control bit function 34 76 esibrd i/o 33 77 wr (r/ w ) i 32 78 rlink (ur_data0) o 31 79 rlclk (ur_data1) o 30 82 rclk o 29 85 rdata o 28 rposi.cntl 0 = rposi is an input 1 = rposi is an output (ur_data2) 27 86 rposi (ur_data2) i/o 26 rnegi.cntl 0 = rnegi is an input 1 = rnegi is an output (ur_data3) 25 87 rnegi (ur_data3) i/o 24 rclki.cntl 0 = rclki is an input 1 = rclki is an output (ur_data4) 23 88 rclki (ur_data4) i/o 22 89 rclko (ur_data5) o 21 90 rnego (ur_data6) o 20 91 rposo (ur_data7) o 19 rchclk.cntl i/o 0 = rchclk is an input (ur_addr0) 1 = rchclk is an output 18 92 rchclk (ur_addr0) i/o 17 rsigf.cntl 0 = rsigf is an input (ur_addr1) 1 = rsigf is an output 16 93 rsigf (ur_addr1) i/o 15 rsig.cntl 0 = rsig is an input (ur_addr2) 1 = rsig is an output 14 94 rsig (ur_addr2) i/o 13 95 rser (ur_clav) o 12 rmsync.cntl 0 = rmsync is an input (ur_addr3) 11 96 rmsync (ur_addr3) i/o 10 rfsync.cntl 0 = rfsync is an input (ur_addr4) 1 = rfsync is an output 9 97 rfsync (ur_addr4) i/o 8 rsync.cntl 0 = rsync is an input 1 = rsync is an output 7 98 rsync i/o 6 99 rlos/lotc o 5 rsysclk.cntl 0 = rsysclk is an input 1 = rsysclk in an output (ut_2clav) 4 100 rsysclk (ut_2clav) i/o downloaded from: http:///
ds2156 234 of 265 34. functional timing diagrams 34.1 t1 mode figure 34-1. receive-side d4 timing note 1: rsync in the frame mode (iocr1.5 = 0) and double-wide frame sync is not enabled (iocr1.6 = 0). note 2: rsync in the frame mode (iocr1.5 = 0) and doubl e-wide frame sync is enabled (iocr1.6 = 1). note 3: rsync in the multiframe mode (iocr1.5 = 1). note 4: rlink data (fs bits) is updated one bit prio r to even frames and held for two frames. figure 34-2. receive-side esf timing note 1: rsync in frame mode (iocr1.4 = 0) and double-wide frame sync is not enabled (iocr1.6 = 0). note 2: rsync in frame mode (iocr1.4 = 0) and double-wide frame sync is enabled (iocr1.6 = 1). note 3: rsync in multiframe mode (iocr1.4 = 1). note 4: zbtsi mode disabled (t1rcr2.2 = 0). note 5: rlink data (fdl bits) is updated one bit time before odd frames and held for two frames. note 6: zbtsi mode is enabled (t1rcr2.2 = 1). note 7: rlink data (z bits) is updated one bit time before odd frames and held for four frames. frame# 1 234567891 01 11 212345 4 rlink rlclk 3 rsync 1 rsync rfsync 2 rsync 123456789101112 1 23 6 rfsync frame# tlclk rsync rsync rsync tlink 13141516171819202122232412345 4 rlclk rlink 5 7 downloaded from: http:///
ds2156 235 of 265 figure 34-3. receive-side boundary timing (with elastic store disabled) note 1: rchblk is programmed to block channel 24. note 2: shown is rlink/rlclk in the esf framing mode. figure 34-4. receive-side 1.544mhz boundary timing (with elastic store enabled) note 1: rsync is in the output mode (iocr1.4 = 0). note 2: rsync is in the input mode (iocr1.4 = 1). note 3: rchblk is programmed to block channel 24. channel 23 channel 24 channel 1 channel 23 channel 24 channel 1 rclk rser rsync rfsync rsig rchclk rchblk 1 rlclk rlink 2 b a c/a d/b a c/a d/b lsb f msb msb lsb ab rser channel 23 channel 24 channel 1 rchclk rchblk rsysclk rsync 2 3 rsync 1 rmsync rsig lsb f msb msb lsb channel 23 channel 24 channel 1 b a c/a d/b a c/a d/b ab downloaded from: http:///
ds2156 236 of 265 figure 34-5. receive-side 2.048mhz boundary timing (with elastic store enabled) note 1: rser data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to 1. note 2: rsync is in the output mode (iocr1.4 = 0). note 3: rsync is in the input mode (iocr1.4 = 1). note 4: rchblk is forced to 1 in the same channels as rser (see note 1). note 5: the f-bit position is passed thr ough the receive-side elastic store. figure 34-6. transmit-side d4 timing note 1: tsync in the frame mode (iocr1.2 = 0) and double-wide frame sync is not enabled (iocr1.1 = 0). note 2: tsync in the frame mode (iocr1.2 = 0) and doubl e-wide frame sync is enabled (iocr1.1 = 1). note 3: tsync in the multiframe mode (iocr1.2 = 1). note 4: tlink data (fs bits) is sampled during th e f-bit position of even frames for insert ion into the outgoing t1 stream when enable d through t1tcr1.2. rser channel 1 rchclk rchblk rsysclk rsync channel 31 channel 32 1 3 4 rsync 2 rmsync rsig channel 31 channel 32 b a c/a d/b c/a d/b ab channel 1 lsb msb lsb 1234567891 01 11 212345 1 23 4 tssync frame# tlclk tsync tsync tsync tlink downloaded from: http:///
ds2156 237 of 265 figure 34-7. transmit-side esf timing note 1: tsync in frame mode (iocr1.2 = 0) and double-wide frame sync is not enabled (iocr1.3 = 0). note 2: tsync in frame mode (iocr1.2 = 0) and double-wide frame sync is enabled (iocr1.3 = 1). note 3: tsync in multiframe mode (iocr1.2 = 1). note 4: tlink data (fdl bits) sampled during the f-bit time of odd frame and inserted into the outgoing t1 stream if enabled through t cr1.2. note 5: zbtsi mode is enabled (t1tcr2.1 = 1). note 6: tlink data (z bits) sampled during the f-bit time of frames 1, 5, 9, 13, 17, and 21 and inserted into the outgoing stream if en abled through t1tcr1.2. figure 34-8. transmit-side boundary timing (with elastic store disabled) note 1: tsync is in the output mode (iocr1.1 = 1). note 2: tsync is in the input mode (iocr1.1 = 0). note 3: tchblk is programmed to block channel 2. note 4: shown is tlink/tlclk in the esf framing mode. 123456789101112 1 23 6 tssync frame# tlclk tsync tsync tsync tlink 13141516171819202122232412345 4 tlclk tlink 5 lsb f msb lsb msb lsb msb channel 1 channel 2 channel 1 channel 2 abc/ad/b abc/ad/b tclk tser tsync tsync tsig tchclk tchblk tlclk tlink d/b 12 3 4 don't care downloaded from: http:///
ds2156 238 of 265 figure 34-9. transmit-side 1.544mhz boundary timing (with elastic store enabled) note 1: tchblk is programmed to block channel 24 (if the tpcsi bit is set, then the signaling data at tsig is ignored during channel 2 4). figure 34-10. transmit-side 2.048mhz boundary timing (with elastic store enabled) note 1: tser data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored. note 2: tchblk is programmed to block channel 31 (if the tpcsi bit is set, then the signaling data at tsig will be ignored). note 3: tchblk is forced to 1 in the same c hannels as tser is ignored (see note 1). note 4: the f-bit position for the t1 frame is sampled and passed thr ough the transmit-side elastic stor e into the msb bit position of channel 1. (normally, the transmit-side formatter overwrites the f-bit pos ition unless the formatter is programmed to pass through the f-b it position.) lsb f msb lsb msb channel 1 channel 24 abc/ad/b abc/ad/b tsysclk tser tssync tsig tchclk tchblk channel 23 a channel 23 channel 24 channel 1 1 lsb f lsb msb channel 1 channel 32 abc/ad/b abc/ad/b tsysclk tser tssync tsig tchclk tchblk channel 31 a channel 31 channel 32 channel 1 1 4 2,3 downloaded from: http:///
ds2156 239 of 265 34.2 e1 mode figure 34-11. receive-side timing note 1: rsync in frame mode (iocr1.5 = 0). note 2: rsync in multiframe mode (iocr1.5 = 1). note 3: rlclk is programmed to output just the sa bits. note 4: rlink always outputs all five sa bits as well as the rest of the receive data stream. note 5: this diagram assumes the cas mf begins in the raf frame. figure 34-12. receive-side boundary ti ming (with elastic store disabled) note 1: rchblk is programmed to block channel 1. note 2: rlclk is programmed to mark the sa4 bit in rlink. note 3: shown is a rnaf frame boundary. note 4: rsig normally contains the cas multif rame alignment nibble (0000) in channel 1. channel 32 channel 1 channel 2 channel 32 channel 1 channel 2 rclk rser rsync rfsync rsig rchclk rchblk 1 rlclk rlink 2 cd a lsb msb ab si 1 a sa4 sa5 sa6 sa7 sa8 sa4 sa5 sa6 sa7 sa8 b note 4 frame# 1 234567891 01 11 21 31 41 51 61 4 rlink rlclk 3 rsync 1 rsync rfsync 2 downloaded from: http:///
ds2156 240 of 265 figure 34-13. receive-side boundary ti ming, rsysclk = 1.544mhz (elastic store enabled) note 1: data from the e1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the e1 link is mapped to channel 1 of the t1 link, etc.) and the f-bit position is added (forced to on 1). note 2: rsync in the output mode (iocr1.4 = 0). note 3: rsync in the input mode (iocr1.4 = 1). note 4: rchblk is programmed to block channel 24. figure 34-14. receive-side boundary ti ming, rsysclk = 2.048mhz (elastic store enabled) note 1: rsync is in the output mode (iocr1.4 = 0). note 2 : rsync is in the input mode (iocr1.4 = 1). note 3: rchblk is programmed to block channel 1. note 4: rsig normally contains the cas multif rame alignment nibble (0000) in channel 1. rser channel 23/31 channel 24/32 channel 1/2 rchclk rchblk rsysclk rsync 2 3 rsync 1 rmsync lsb f msb msb lsb 4 rser channel 1 rchclk rchblk rsysclk rsync channel 31 channel 32 1 3 rsync 2 rmsync rsig channel 31 channel 32 c d ab channel 1 lsb msb lsb msb c d b a note 4 downloaded from: http:///
ds2156 241 of 265 figure 34-15. receive ibo channel interleave mode timing note 1: 4.096mhz bus configuration. note 2: 8.192mhz bus configuration. note 3: 16.384mhz bus configuration. note 4: rsync is in the input mode (iocr1.4 = 0). rser lsb rsysclk rsync framer2, channel 32 msb lsb framer 1, channel 1 rsig framer2, channel 32 framer 1, channel 1 msb lsb framer2, channel 1 framer2, channel 1 4 rser rsync rsig rser rsig f3 32 f4 32 f1 c1 f2 c1 f3 c1 f4 c1 f1 c2 f2 c2 f3 c2 f4 c2 1 1 22 bit level detail (4.096mhz bus configurtation) f2 c32 f1 c1 f2 c1 f1 c2 f2 c2 f2 c32 f1 c1 f2 c1 f1 c2 f2 c2 f3 c32 f4 c32 f1 c1 f2 c1 f3 c1 f4 c1 f1 c2 f2 c2 f3 c2 f4 c2 abcd abcd abcd rser rsig 33 f1 c1 f2 c1 f3 c1 f4 c1 f5 c1 f6 c1 f7 c1 f8 c1 f1 c2 f2 c2 f3 c2 f4 c2 f5 c2 f6c2 f7 c2 f8 c2 f5 c32 f6 c32 f7 c32 f8 c32 f1 c1 f2 c1 f3 c1 f4 c1 f5 c1 f6 c1 f7 c1 f8 c1 f1 c2 f2 c2 f3 c2 f4 c2 f5 c2 f6c2 f7 c2 f8 c2 f5 c32 f6 c32 f7 c32 f8 c32 framer #1, channel #1 downloaded from: http:///
ds2156 242 of 265 figure 34-16. receive ibo frame interleave mode timing note 1: 4.096mhz bus configuration. note 2: 8.192mhz bus configuration. note 3: 16.384mhz bus configuration. note 4: rsync is in the input mode (iocr1.4 = 0). rser lsb rsysclk rsync framer2, channel 32 msb lsb framer 1, channel 1 rsig framer2, channel 32 framer 1, channel 1 msb lsb framer1, channel 2 framer1, channel 2 4 rser rsync rsig rser rsig f3 f4 f1 f2 f3 f4 f1 f2 f3 f4 1 1 22 bit level detail (4.096mhz bus configurtation) f2 f1 f2 f1 f2 f2 f1 f2 f1 f2 f3 f4 f1 f2 f3 f4 f1 f2 f3 f4 abcd abcd abcd rser rsig 33 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f5 f6 f7 f8 framer #1, channels 1 through 32 downloaded from: http:///
ds2156 243 of 265 figure 34-17. g.802 timing, e1 mode only note 1: rchblk or tchblk programmed to pulse high during time sl ots 1 through 15, 17 through 25, and bit 1 of time slot 26. figure 34-18. transmit-side timing note 1: tsync in frame mode (iocr1.2 = 0). note 2: tsync in multiframe mode (iocr1.2 = 1). note 3: tlink is programmed to source just the sa4 bit. note 4: this diagram assumes both the cas mf and the crc4 mf begin with the taf frame. note 5: tlink and tlclk are not synchronous with tssync. 12345678910111213141516171819202122232425262728293031 0 31 32 ts # rsync tsync rchclk tchclk rchblk tchblk channel 26 channel 25 lsb msb rclk / rsysclk tclk / tsysclk rser / tser rchclk / tchclk rchblk / tchblk 12 0 12345 678910 11 12 1 3 tssync frame# tsync tsync 13 14 15 16 12345 tlclk tlink 14 15 16 678910 3 2 downloaded from: http:///
ds2156 244 of 265 figure 34-19. transmit-side boundary timing (elastic store disabled) note 1: tsync is in the output mode (iocr1.1 = 1). note 2: tsync is in the input mode (iocr1.1 = 0). note 3: tchblk is programmed to block channel 2. note 4: tlink is programmed to source the sa4 bit. note 5: the signaling data at tsig during channel 1 is normally overwri tten in the transmit formatter with the cas mf alignment nibble (0000). note 6: shown is a tnaf frame boundary. figure 34-20. transmit-side bounda ry timing, tsysclk = 1.544mhz (elastic store enabled) note 1: the f-bit position in the tser data is ignored. note 2: tchblk is programmed to block channel 24. lsb msb lsb msb channel 1 channel 2 channel 1 channel 2 abcd tclk tser tsync tsync tsig tchclk tchblk tlclk tlink 12 3 4 don't care si 1 a sa4 sa5 sa6 sa7 sa8 d don't care 4 lsb f msb lsb msb channel 1 channel 24 tsysclk tser tssync tchclk tchblk channel 23 1 2 downloaded from: http:///
ds2156 245 of 265 figure 34-21. transmit-side boundary timing, tsysclk = 2.048mhz (elastic store enabled) note 1: tchblk is programmed to block channel 31. lsb f lsb msb channel 1 channel 32 abcd ab tsysclk tser tssync tsig tchclk tchblk channel 31 a channel 31 channel 32 channel 1 1 4 2,3 cd downloaded from: http:///
ds2156 246 of 265 figure 34-22. transmit ibo channel interleave mode timing note 1: 4.096mhz bus configuration. note 2: 8.192mhz bus configuration. note 3: 16.384mhz bus configuration. note 4: tsync is in input mode. tser lsb tsysclk tsync framer2, channel 32 msb lsb framer 1, channel 1 tsig framer2, channel 32 framer 1, channel 1 msb lsb framer2, channel 1 framer2, channel 1 4 tser tssync trsig tser tsig f3 32 f4 32 f1 c1 f2 c1 f3 c1 f4 c1 f1 c2 f2 c2 f3 c2 f4 c2 11 2 2 bit level detail (4.096mhz bus configurtation) f2 c32 f1 c1 f2 c1 f1 c2 f2 c2 f2 c32 f1 c1 f2 c1 f1 c2 f2 c2 f3 c32 f4 c32 f1 c1 f2 c1 f3 c1 f4 c1 f1 c2 f2 c2 f3 c2 f4 c2 abcd abcd abcd tser tsig 3 3 f1 c1 f2 c1 f3 c1 f4 c1 f5 c1 f6 c1 f7 c1 f8 c1 f1 c2 f2 c2 f3 c2 f4 c2 f5 c2 f6c2 f7 c2 f8 c2 f5 c32 f6 c32 f7 c32 f8 c32 f1 c1 f2 c1 f3 c1 f4 c1 f5 c1 f6 c1 f7 c1 f8 c1 f1 c2 f2 c2 f3 c2 f4 c2 f5 c2 f6c2 f7 c2 f8 c2 f5 c32 f6 c32 f7 c32 f8 c32 framer #1, channel #1 downloaded from: http:///
ds2156 247 of 265 figure 34-23. transmit ibo frame interleave mode timing note 1: 4.096mhz bus configuration. note 2: 8.192mhz bus configuration. note 3: 16.384mhz bus configuration. note 4: tsync is in input mode. tser lsb tsysclk tsync framer2, channel 32 msb lsb framer 1, channel 1 tsig framer2, channel 32 framer 1, channel 1 msb lsb framer1, channel 2 framer1, channel 2 4 tser tssync tsig tser tsig f3 f4 f1 f2 f3 f4 f1 f2 f3 f4 11 2 2 bit level detail (4.096mhz bus configurtation) f2 f1 f2 f1 f2 f2 f1 f2 f1 f2 f3 f4 f1 f2 f3 f4 f1 f2 f3 f4 abcd abcd abcd tser tsig 3 3 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f5 f6 f7 f8 framer #1, channels 1 through 32 downloaded from: http:///
ds2156 248 of 265 35. operating parameters absolute maxi mum ratings voltage range on any pin relative to ground -1.0v to +6.0v operating temperature range for ds2156l 0 c to +70 c operating temperature range for ds2156ln -40 c to +85 c storage temperature range -55 c to +125 c soldering temperature see ipc/jedec j-std-020a this is a stress rating only and functional operation of the device at these or any other conditi ons above those indicated in t he operation sections of this specification is not implied. exposure to absolute maximum rating co nditions for extended periods of time may affect reliability. thermal char acteristics parameter symbol conditions min typ max units ambient temperature (note 1) -40c +85 c junction temperature +125 c theta-ja ( ja ) in still air for 100-pin lqfp (note 2) +32 c/w theta-ja ( ja ) vs. airflow forced air (meters per second) theta-ja ( ja ) 100-pin lqfp 0 +32 c/w 1 +27 c/w 2.5 +24 c/w recommended dc oper ating conditions (t a = 0 c to +70 c for ds2156l; t a = -40 c to +85 c for ds2156ln.) parameter symbol conditions min typ max units logic 1 v ih 2.0 5.5 v logic 0 v il -0.3 +0.8 v supply v dd (note 3) 3.135 3.3 3.465 v capacitance (t a = +25c) parameter symbol conditions min typ max units input capacitance c in 5 pf output capacitance c out 7 pf downloaded from: http:///
ds2156 249 of 265 dc characteristics ( v dd = 3.3v 5%, t a = 0 c to +70 c for ds2156l; v dd = 3.3v 5%, t a = -40 c to +85 c for ds2156ln.) parameter symbol conditions min typ max units supply current i dd (note 4) 75 ma input leakage i il (note 5) -1.0 +1.0 a output leakage i lo (note 6) 1.0 a output current (2.4v) i oh -1.0 ma output current (0.4v) i ol +4.0 ma note 1: the package is mounted on a four-layer jedec standard test board. note 2: theta-ja ( ja ) is the junction to ambient thermal resistance, when the package is mounted on a four-layer jedec standard test board. note 3: applies to rv dd , tv dd , and dv dd . note 4: tclk = tclki = rclki = tsysclk = rsysclk = mclk = 1.544mhz; outputs open-circuited. note 5: 0.0v < v in < v dd note 6: applied to int when tri-stated. downloaded from: http:///
ds2156 250 of 265 36. ac timing parameters and diagrams capacitive test loads are 40pf for bus signals, 20pf for all others. 36.1 multiplexed bus ac characteristics ac characteristics: multiplexe d parallel port (mux = 1) (figure 36-1, figure 36-2, and figure 36-3) (v dd = 3.3v 5%, t a = 0 c to +70 c for ds2156l; v dd = 3.3v 5%, t a = -40 c to +85 c for ds2156ln.) parameter symbol conditions min typ max units cycle time t cyc 200 ns pulse width, ds low or rd high pw el 100 ns pulse width, ds high or rd low pw eh 100 ns input rise/fall times t r , t f 20 ns r/ w hold time t rwh 10 ns r/ w setup time before ds high t rws 50 ns cs setup time before ds, wr , or rd active t cs 20 ns cs hold time t ch 0 ns read data hold time t dhr 10 50 ns write data hold time t dhw 0 ns muxed address valid to as or ale fall t asl 15 ns muxed address hold time t ahl 10 ns delay time ds, wr , or rd to as or ale rise t asd 20 ns pulse width as or ale high pw ash 30 ns delay time, as or ale to ds, wr or rd t ased 10 ns output data delay time from ds or rd t ddr 20 80 ns data setup time t dsw 50 ns downloaded from: http:///
ds2156 251 of 265 figure 36-1. intel bus read timing (bts = 0/mux = 1) figure 36-2. intel bus write timing (bts = 0/mux = 1) pw t cyc t asd t asd pw pw eh el t t t t t t ahl ch cs asl ased c s ad0Cad7 dhr t ddr ale r d w r pw t cyc t asd t asd pw pw eh el t t t t t t t ahl dsw dhw ch cs asl ased c s ad0C a d7 r d w r ale downloaded from: http:///
ds2156 252 of 265 figure 36-3. motorola bus timing (bts = 1/mux = 1) t a sd a sh pw t t a sl a hl t cs t a sl t t t dsw dhw t ch t t t ddr dhr rwh t a sed pw eh t rws a hl pw el t cyc a s ds a d0Cad7 (write) a d0Cad7 (read) r/ w c s downloaded from: http:///
ds2156 253 of 265 36.2 nonmultiplexed bus ac characteristics ac characteristics: nonmultiplex ed parallel po rt (mux = 0) (figure 36-4, figure 36-5, figure 36-6, and figure 36-7) (v dd = 3.3v 5%, t a = 0 c to +70 c for ds2156l; v dd = 3.3v 5%, t a = -40 c to +85 c; for ds2156ln.) parameter symbol conditions min typ max units setup time for a0 to a7, valid to cs active t1 0 ns setup time for cs active to either rd , wr , or ds active t2 0 ns delay time from either rd or ds active to data valid t3 75 ns hold time from either rd , wr , or ds inactive to cs inactive t4 0 ns hold time from cs inactive to data bus tri-state t5 5 20 ns wait time from either wr or ds active to latch data t6 75 ns data setup time to either wr or ds inactive t7 10 ns data hold time from either wr or ds inactive t8 10 ns address hold from either wr or ds inactive t9 10 ns downloaded from: http:///
ds2156 254 of 265 figure 36-4. intel bus read timing (bts = 0/mux = 0) figure 36-5. intel bus write timing (bts = 0/mux = 0) a ddress valid data valid a0 to a7 d0 to d7 w r c s r d 0ns (min) 0ns (min) 75ns (max) 0ns (min) 5ns (min) / 20ns (max) t1 t2 t3 t4 t5 a ddress valid a0 to a7 d0 to d7 r d c s w r 0ns (min) 0ns (min) 75ns (min) 0ns (min) 10ns (min) 10ns (min) t1 t2 t6 t4 t7 t8 downloaded from: http:///
ds2156 255 of 265 figure 36-6. motorola bus read timing (bts = 1/mux = 0) figure 36-7. motorola bus write timing (bts = 1/mux = 0) a ddress valid a0 to a7 d0 to d7 r/ w c s d s 0ns (min) 0ns (min) 75ns (min) 0ns (min) 10ns (min) 10ns (min) t1 t2 t6 t4 t7 t8 a ddress valid data valid a0 to a7 d0 to d7 r/ w c s d s 0ns (min) 0ns (min) 75ns (max) 0ns (min) 5ns (min) / 20ns (max) t1 t2 t3 t4 t5 downloaded from: http:///
ds2156 256 of 265 36.3 receive-side ac characteristics ac characteristics: receive side (figure 36-8, figure 36-9, and figure 36-10) (v dd = 3.3v 5%, t a = 0c to +70c for ds2156l; v dd = 3.3v 5%, t a = -40c to +85c for ds2156ln.) parameter symbol conditions min typ max units 488 (e1) rclko period t lp 648 (t1) ns t lh (note 1) 200 0.5 t lp rclko pulse width t ll (note 1) 200 0.5 t lp ns t lh (note 2) 150 0.5 t lp rclko pulse width t ll (note 2) 150 0.5 t lp ns 488 (e1) rclki period t cp 648 (t1) ns t ch 20 0.5 t cp rclki pulse width t cl 20 0.5 t cp ns (note 3) 648 (note 4) 488 ns (note 5) 244 ns (note 6) 122 rsysclk period t sp (note 7) 61 t sh 20 0.5 t sp ns rsysclk pulse width t sl 20 0.5 t sp ns rsync setup to rsysclk falling t su 20 ns rsync pulse width t pw 50 ns rposi/rnegi setup to rclki falling t su 20 ns rposi/rnegi hold from rclki falling t hd 20 ns rsysclk, rclki rise and fall times t r , t f 22 ns delay rclko to rposo, rnego valid t dd 50 ns delay rclk to rser, rdata, rsig, rlink valid t d1 50 ns delay rclk to rchclk, rsync, rchblk, rfsync, rlclk t d2 50 ns delay rsysclk to rser, rsig valid t d3 22 ns delay rsysclk to rchclk, rchblk, rmsync, rsync t d4 22 ns note 1: jitter attenuator enabled in the receive path. note 2: jitter attenuator disabled or enabled in the transmit path. note 3: rsysclk = 1.544mhz note 4: rsysclk = 2.048mhz note 5: rsysclk = 4.096mhz note 6: rsysclk = 8.192mhz note 7: rsysclk = 16.384mhz downloaded from: http:///
ds2156 257 of 265 figure 36-8. receive-side timing note 1: rsync is in the output mode. note 2: shown is rlink/rlclk in the esf framing mode. note 3: no relationship between rchclk and rchblk and other signals is implied. note 4: rlclk only pulses high during sa bit loca tions as defined in the e1rcr2 register. t d1 1 t d2 rser / rdata / rsig rchclk rchblk rsync rlclk rlink (t1mode) t d1 rclk rfsync / rmsync 2 t d2 t d2 t d2 t d2 rlink (e1 mode) sa4 to sa8 bit position 4 1st frame bit downloaded from: http:///
ds2156 258 of 265 figure 36-9. receive-side timi ng, elastic store enabled note 1: rsync is in the output mode. note 2: rsync is in the input mode. note 3: f-bit when mstrreg.1 = 0, msb of ts0 when mstreg.1 = 1. figure 36-10. receive line interface timing f t t r t d3 t d4 t d4 t d4 t t su hd rser / rsig rchclk rchblk 1 rsync 2 rsync rsysclk sl t t sp sh t t d4 rmsync see note 3 t f t r rposi, rnegi rclki cl t t cp ch t t su t hd t dd rposo, rnego rclko ll t t lp lh t downloaded from: http:///
ds2156 259 of 265 36.4 transmit ac characteristics ac characteristics: transmit side (figure 36-11, figure 36-12, and figure 36-13) (v dd = 3.3v 5%, t a = -40c to +85c for ds2156l; v dd = 3.3v 5%, t a = 0c to +70c for ds2156ln) parameter symbol conditions min typ (e1) max units 488 (e1) tclk period t cp 648 (t1) ns t ch 20 0.5 t cp tclk pulse width t cl 20 0.5 t cp ns 488 (e1) tclki period t lp 648 (t1) ns t lh 20 0.5 t lp tclki pulse width t ll 20 0.5 t lp ns (note 8) 648 (note 9) 448 (note 10) 244 (note 11) 122 tsysclk period t sp (note 12) 61 ns 20 0.5 t sp tsysclk pulse width t sp 20 0.5 t sp ns tsync or tssync setup to tclk or tsysclk falling t su 20 ns tsync or tssync pulse width t pw 50 ns tser, tsig, tdata, tlink, tposi, tnegi setup to tclk, tsysclk, tclki falling t su 20 ns tser, tsig, tdata, tlink hold from tclk or tsysclk falling t hd 20 ns tposi, tnegi hold from tclki falling t hd 20 ns tclk, tclki or tsysclk rise and fall times t r , t f 25 ns delay tclko to tposo, tnego valid t dd 50 ns delay tclk to teso, ut-utdo valid t d1 50 ns delay tclk to tchblk, tchclk, tsync, tlclk t d2 50 ns delay tsysclk to tchclk, tchblk t d3 22 ns note 8: tsysclk = 1.544mhz note 9: tsysclk = 2.048mhz note 10: tsysclk = 4.096mhz note 11: tsysclk = 8.192mhz note 12: tsysclk = 16.384mhz downloaded from: http:///
ds2156 260 of 265 figure 36-11. transmit-side timing note 1: tsync is in the output mode (iocr1.1 = 1). note 2: tsync is in the input mode (iocr1.1 = 0). note 3: tser is sampled on the falling edge of tclk when the transmit-side elastic store is disabled. note 4: tchclk and tchblk are synchronous with tclk w hen the transmit-side elasti c store is disabled. note 5: in e1 mode, tlink is only sampled during sa bit locations as defined in e1tcr2; no relationship between tlclk/tlink and tsync is implied. t f t r 1 tclk tser / tsig / tdata tchclk t t cl t ch cp tsync tsync tlink tlclk tchblk t d2 t d2 t d2 t t t t t t hd su d2 su hd d1 t hd 2 5 teso t su downloaded from: http:///
ds2156 261 of 265 figure 36-12. transmit-side timing, elastic store enabled note 1: tser is only sampled on the falling edge of tsysclk when the transmit-side elastic store is enabled. note 2: tchclk and tchblk are synchronous with tsyscl k when the transmit-side elastic store is enabled. figure 36-13. transmit line interface timing tclko tposo, tnego t dd t f t r tclki tposi, tnegi t t ll t lh lp t hd t su t f t r tsysclk tser tchclk t t sl t sh sp tssync tchblk t d3 t d3 t t t su hd su t hd downloaded from: http:///
ds2156 262 of 265 36.5 utopia transmit ac characteristics parameter symbol conditions min typ max units setup time ut-enb , ut-soc, ut-addrx, ut-datax to ut-clk tt5 10 ns hold time ut-enb, ut-soc, ut-addrx, ut-datax from ut-clk tt6 1 ns output delay ut-clav, ut-2clav from ut-clk td 20 ns ut-clav high-z from ut-clk 25 ns 36.6 utopia receive ac characteristics parameter symbol conditions min typ max units setup time ur-enb , ur-addrx to ur- clk tt5 10 ns hold time ur-enb, ur-addrx from ur- clk tt6 1 ns output delay ur-clav, ur-datax, ur- soc from ur-clk td 20 ns ur-clav, ur-data, ur-soc high-z from ur-clk 25 ns figure 36-14. utopia interface setup and hold times figure 36-15. utopia interface delay times clock signal tt5 tt6 input setup to clock input hold from clock clock signal td and tz downloaded from: http:///
ds2156 263 of 265 37. revision history revision description 011606 added lead-free packages to ordering information. added csbga package drawing to section 38: package information . 110502 original data sheet release. downloaded from: http:///
ds2156 264 of 265 38. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. the package number provided for each package is a link to the latest package outline information.) 38.1 100-pin lqfp ( 56-g5002-000 ) downloaded from: http:///
ds2156 265 of 265 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products ? printed usa the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor. 38.2 100-ball csbga ( 56-g6008-001 ) downloaded from: http:///

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