SQS484ENW www.vishay.com vishay siliconix s16-2192-rev. a, 24-oct-16 1 document number: 62896 for technical questions, contact: automostechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 automotive n-channel 40 v (d-s) 175 c mosfet features ? trenchfet ? power mosfet ? aec-q101 qualified ? 100 % r g and uis tested ? material categorization: ? for definitions of compliance please see www.vishay.com/doc?99912 notes a. package limited. b. pulse test; pulse width ? 300 s, duty cycle ? 2 %. c. when mounted on 1" square pcb (fr4 material). d. parametric verification ongoing. e. see solder profile ( www.vishay.com/doc?73257 ). the powerpak 1212-8w is a leadless package. the end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. a solder fillet at the exposed copper tip cannot b e guaranteed and is not required to ensure adequate bottom side solder interconnection. f. rework conditions: manual soldering with a solderin g iron is not recommended for leadless components. product summary v ds (v) 40 r ds(on) ( ? ) at v gs = 10 v 0.0080 r ds(on) ( ? ) at v gs = 4.5 v 0.0105 i d (a) 16 configuration single package powerpak 1212-8w powerpak ? 1212-8w s ingle top view 1 3.3 mm 3.3 mm 3.3 mm 3 mm bottom view 1 s 2 s 3 s 4 g d 8 d 7 d 6 d 5 1 s s s s fet g d s absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 40 v gate-source voltage v gs 20 continuous drain current a t c = 25 c i d 16 a t c = 125 c 16 continuous source curren t (diode conduction) a i s 16 pulsed drain current b i dm 64 single pulse avalanche current l = 0.1 mh i as 25 single pulse avalanche energy e as 31.2 mj maximum power dissipation b t c = 25 c p d 62.5 w t c = 125 c 20 operating junction and storage temperature range t j , t stg -55 to +175 c soldering recommendations (peak temperature) e, f 260 thermal resistance ratings parameter symbol limit unit junction-to-ambient pcb mount c r thja 81 c/w junction-to-case (drain) r thjc 2.4
SQS484ENW www.vishay.com vishay siliconix s16-2192-rev. a, 24-oct-16 2 document number: 62896 for technical questions, contact: automostechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not subj ect to production testing. c. independent of operating temperature. ? ? ? ? ? stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. ? specifications (t c = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0, i d = 250 a 40 - - v gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.5 2.0 2.5 gate-source leakage i gss v ds = 0 v, v gs = 20 v - - 100 na zero gate voltage drain current i dss v gs = 0 v v ds = 40 v - - 1 a v gs = 0 v v ds = 40 v, t j = 125 c - - 50 v gs = 0 v v ds = 40 v, t j = 175 c - - 150 on-state drain current a i d(on) v gs = 10 v v ds ? 5 v 20 - - a drain-source on-state resistance a r ds(on) v gs = 10 v i d = 10 a - 0.0065 0.0080 ? v gs = 10 v i d = 10 a, t j = 125 c - - 0.0113 v gs = 10 v i d = 10 a, t j = 175 c - - 0.0133 v gs = 4.5 v i d = 10 a - 0.0085 0.0105 forward transconductance b g fs v ds = 15 v, i d = 10 a - 52 - s dynamic b input capacitance c iss v gs = 0 v v ds = 25 v, f = 1 mhz - 1380 1800 pf output capacitance c oss - 850 1110 reverse transfer capacitance c rss -4060 total gate charge c q g v gs = 10 v v ds = 20 v, i d = 4 a -2235 nc gate-source charge c q gs -4- gate-drain charge c q gd -3- gate resistance r g f = 1 mhz 0.48 0.97 1.50 ? turn-on delay time c t d(on) v dd = 20 v, r l = 5 ? i d ? 4 a, v gen = 10 v, r g = 1 ? -1120 ns rise time c t r -510 turn-off delay time c t d(off) -2540 fall time c t f -1020 source-drain diode ratin g s and characteristic b pulsed current a i sm --64a forward voltage v sd i f = 10 a, v gs = 0 v - 0.82 1.1 v body diode reverse recovery time t rr i f = 5 a, di/dt = 100 a/s -4490ns body diode reverse recovery charge q rr -4290nc reverse recovery fall time t a -22- ns reverse recovery rise time t b -25- body diode peak reverse recovery current i rm(rec) --1.8-4 a
SQS484ENW www.vishay.com vishay siliconix s16-2192-rev. a, 24-oct-16 3 document number: 62896 for technical questions, contact: automostechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) output characteristics transconductance capacitance transfer characteristics on-resistance vs. drain current gate char g e 10 100 1000 10000 0 16 32 48 64 80 0246810 axis title 1st line 2nd line 2nd line i d - drain current (a) v ds - drain-to-source voltage (v) 2nd line v gs = 10 v thru 4 v v gs = 3 v 10 100 1000 10000 0 20 40 60 80 100 0 5 10 15 20 25 axis title 1st line 2nd line 2nd line g fs - transconductance (s) i d - drain current (a) 2nd line t c = 25 c t c =-55 c t c = 125 c 10 100 1000 10000 0 600 1200 1800 2400 3000 0 8 16 24 32 40 axis title 1st line 2nd line 2nd line c - capacitance (pf) v ds - drain-to-source voltage (v) 2nd line c rss c oss c iss 10 100 1000 10000 0 16 32 48 64 80 0246810 axis title 1st line 2nd line 2nd line i d - drain current (a) v gs - gate-to-source voltage (v) 2nd line t c = 25 c t c =-55 c t c = 125 c 10 100 1000 10000 0.000 0.005 0.010 0.015 0.020 0.025 0 1224364860 axis title 1st line 2nd line 2nd line r ds(on) - on-resistance () i d - drain current (a) 2nd line v gs = 4.5 v v gs = 10 v 10 100 1000 10000 0 2 4 6 8 10 0 5 10 15 20 25 axis title 1st line 2nd line 2nd line v gs - gate-to-source voltage (v) q g - total gate charge (nc) 2nd line i d = 4 a v ds = 20 v
SQS484ENW www.vishay.com vishay siliconix s16-2192-rev. a, 24-oct-16 4 document number: 62896 for technical questions, contact: automostechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) on-resistance vs. junction temperature on-resistance vs. gate-to-source volta g e source drain diode forward volta g e threshold volta g e drain source breakdown vs . junction temperature 10 100 1000 10000 0.5 0.8 1.1 1.4 1.7 2.0 -50-25 0 255075100125150175 axis title 1st line 2nd line 2nd line r ds(on) - on-resistance (normalized) t j - junction temperature (c) 2nd line i d = 6 a v gs = 10 v v gs = 4.5 v 10 100 1000 10000 0.00 0.01 0.02 0.03 0.04 0.05 0246810 axis title 1st line 2nd line 2nd line r ds(on) - on-resistance () v gs - gate-to-source voltage (v) 2nd line t j = 25 c t j = 150 c 10 100 1000 10000 0.001 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1.0 1.2 axis title 1st line 2nd line 2nd line i s - source current (a) v sd - source-to-drain voltage (v) 2nd line t j = 150 c t j = 25 c 10 100 1000 10000 -1.0 -0.7 -0.4 -0.1 0.2 0.5 -50 -25 0 25 50 75 100 125 150 175 axis title 1st line 2nd line 2nd line v gs(th) - variance (v) t j - temperature (c) 2nd line i d = 5 ma i d = 250 a 10 100 1000 10000 40 43 46 49 52 55 -50-25 0 255075100125150175 axis title 1st line 2nd line 2nd line v ds - drain-to-source voltage (v) t j - junction temperature (c) 2nd line i d = 1 ma
SQS484ENW www.vishay.com vishay siliconix s16-2192-rev. a, 24-oct-16 5 document number: 62896 for technical questions, contact: automostechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 thermal ratings (t a = 25 c, unless otherwise noted) safe operatin g area normalized thermal transient impedance, junction-to-ambient 10 100 1000 10000 0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000 axis title 1st line 2nd line 2nd line i d - drain current (a) v ds - drain-to-source voltage (v) (1) v gs > minimum v gs at which r ds(on) is specified i dm limited limited by r ds(on) (1) t c = 25 c single pulse bvdss limited 100 ms, 1 s, 10 s, dc 10 ms 1 ms 100 s i d limited 0.2 0.1 t 1 t 2 notes: p dm 1. duty cycle, d = 2. per unit base = r thja = 81 c/w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. surface mounted duty cycle = 0.5 single pulse 0.02 0.05 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 square wave pulse duration (s) normalized effective transient thermal impedance 1 0.1 0.01
SQS484ENW www.vishay.com vishay siliconix s16-2192-rev. a, 24-oct-16 6 document number: 62896 for technical questions, contact: automostechsuppo rt@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 thermal ratings (t a = 25 c, unless otherwise noted) normalized thermal transient impedance, junction-to-case note ? the characteristics shown in the two graphs ? - normalized transient thermal impedance junction-to-ambient (25 c) ? - normalized transient thermal impedance junction-to-case (25 c) ? are given for general guidelines only to enable the user to ge t a ball park indication of part capabilities. the data are ext racted from single pulse transient thermal impedance characteristics which are developed from empirical measurements. the latter is valid for the part mounted on printed circuit board - fr4, size 1" x 1" x 0.062" , double sided with 2 oz. copper, 100 % on both sides. the part ca pabilities can widely vary depending on actual application parameters and operating conditions. vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package / ta pe drawings, part marking, and reliability data, see www.vishay.com/ppg?62896 . 10 -3 10 -2 1 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 s qu are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance
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