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CYIFS731 low emi spread spectrum clock cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-73426 rev. *d revised december 16, 2014 low emi spectrum spread clock features reduces systemic emi. modulates external clocks including crystals, crystal oscillators and ceramic resonators. 1x and 2x modulated frequency outputs. modulation programmable with simple external loop filter (lf). 4 to 68 mhz operating frequency range. digitally controlled modulation. ttl/cmos compatible outputs. center spread modulation. low short term jitter. bi-directional buffers for reduced pin count. 3?5 volt power supply. low power dissipation; ? 3.3 vdc = 30 mw - typical ? 5.0 vdc = 100 mw - typical available in 8 pin soic package. functional description the CYIFS731 is a frequency spreading emi attenuator designed for the purpose of reducing electro magnetic interference (emi) found in today?s high speed digital systems. the CYIFS731 uses a proprietary technique to modulate the output clock, modout. by modulating the frequency of the digital clock, measured emi at the fundamental and harmonic frequencies is greatly reduced. th is reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements without degrading digital waveforms. the CYIFS731 is a very simple device to use and provides 1x and 2x frequency modulated outputs of the input reference frequency. by programming the two range select lines, rs0 and rs1, the CYIFS731 can operate over a very wide range of input frequencies. by utilizing bi-directional buffer design, the pin count of the CYIFS731 is kept to a minimum. bi-directional buffers is a method of providing an input control signal and an output driver circuit on the same pin. bi-directional buffers is discussed further on page 6. the CYIFS731 has a simple frequency selection table that allows it to operate from 4 mhz to 68 mhz in four separate ranges. the bandwidth of the frequency spread at modout is determined by the values of the loop filter components. the modulation rate is determined by the input frequency and the input frequency range selected. the bandwidth of the CYIFS731 can be programmed from as little as 0.5% up to as much as 4.0% by selecting the proper loop filter. it is for this reason that the CYIFS731 uses an external loop filter (lf), in contrast to an internal loop filter type device which would severely limit the use of a wide range of bandwidths. for a complete list of related documentation, click here . not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 2 of 20 block diagram modulation control logic rs0 rs1 phase detector vco bi-directional buffer/divider divide by n divide by r 250k 1 2 3 4 5 6 7 8 xin xout lf vdd vss fout/rs0 foutx2/rs1 bi-directional buffer/divider power on, reset logic not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 3 of 20 contents pin configurations ........................................................... 4 pin definitions .................................................................. 4 frequency range selection table .................................. 5 functional overview ........................................................ 6 bi-directional buffers ................................................... 6 loop filters ............ .......................................... ............ 6 sscg modulation profile ............................................ 9 theory of operation ....................................................... 10 emi ............................................................................ 10 sscg ........................................................................ 10 modulation rate .... .................................................... 12 application notes and schematics ............................... 13 calculating db reduction .......................................... 13 absolute maximum ratings .......................................... 14 electrical characteristics ............................................... 14 timing characteristics ................................................... 15 ordering information ...................................................... 16 ordering code definitions ..... .................................... 16 package diagram ............................................................ 17 acronyms ........................................................................ 18 document conventions ................................................. 18 units of measure ....................................................... 18 document history page ................................................. 19 sales, solutions, and legal information ...................... 20 worldwide sales and design s upport ......... .............. 20 products .................................................................... 20 psoc? solutions ...................................................... 20 cypress developer community ................................. 20 technical support ................. .................................... 20 not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 4 of 20 pin configurations figure 1. CYIFS731, soic package pin assignment pin definitions pin no. pin name i/o type description 1, 2 x in , x out i/o cmos/ttl pins form an on-chip reference os cillator when connected to terminals of an external parallel resonant crystal. x in may be connected to ttl/cmos external clock source. if x in is connected to an external clock other than a crystal, leave x out (pin 2) unconnected. 4 lf o analog single ended tri-state output of the phase detector. a two pole passive loop filter is connected to lf. see table 1 on page 7 and table 2 on page 8 for proper values. 3, 5 v ss ? ground circuit ground. 6 foutx2/rs1 i/o cmos/ttl bi-directional pin used for range selection input and foutx2 driver output. during power up, rs1 serves as an in put control line for selecting the proper frequency operating range. after rs1 is latched into an internal register, this pin becomes an output for the modulated foutx2 driver. refer to bi-directional buffers on page 6 for more information. the center frequency of foutx2 is 2 times the reference frequency at x in . foutx2/rs1 has an internal 250 k ? pull-up resistor to v dd . 7 fout/rs0 i/o cmos/ttl bi-directional pin used for range selection input and fout driver output. during power up, rs0 serves as an in put control line for selecting the proper frequency operating range. after power has reached v dd /3, rs0 is latched into a register and this pin becomes an output pin for the fout driver. fout is a modulated output clock of the reference frequency, x in , being the center frequency and the modulation bandwidth and rate determined by the applied loop filter. refer to table 1 on page 7 and table 2 on page 8 respectively. fout/rs0 has internal 250k ohm pull-up resistor to v dd . 8 v dd ?power positive circuit power supply. CYIFS731 not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 5 of 20 this device contains circuitry to protect the inputs against damage due to high static volt ages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the absolute maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range, v ss < (v in or v out ) < v dd . all digital inputs are tied high or low internally. refers to electrical specifications for operating supply range. figure 2. frequency vs. idd frequency range selection table x in range rs1 rs0 4?8 mhz 0 0 8?16 mhz 0 1 16?40 mhz 1 0 40?68 mhz 1 1 not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 6 of 20 functional overview bi-directional buffers two pins on the CYIFS731 are connected to bi-directional buffers. using bi-directional buffers is a method of sharing an input circuit and an output circ uit with the same pin on the ic assembly, thereby reducing the pin count. each bi-directional i/o acts as an input during power up and as an output after power has reached a certain voltage. for the CYIFS731, that voltage is approximately v dd /3. at v dd /3, the CYIFS731 latches the logic state of the respective line in an internal register for as long as power is applied to the CYIFS731. after v dd /3 has been reached and the power on reset has occurred, the respective pin is switched from an input gate to an output driver. this pin remains an output driver for as long as power is applied. loop filters the CYIFS731 requires an external loop filter to provide the proper operation and bandwidth for a given input frequency. since the CYIFS731 operates ov er a wide range of frequencies, the loop filter will change depending on the frequency of operation. the following loop filter values are recommended for best performance and modulation profile at 5.0 volts and 3.3 volts v dd , measured across pin 8 (v dd ) and 5 (v ss ). figure 3. external loop filter the table 1 on page 7 and table 2 on page 8 contain the loop filter values for the a power su pply voltage of 5.0 and 3.3 vdc, +/?10%. the values in both table 1 on page 7 and table 2 on page 8 were bench tested for accuracy and optimal performance. the loop filter va lues were determined by taking 4 mhz segments of the overall operating range and testing for the optimal performance at the center frequency of each 4 mhz band. this means that in the first band in the table below, 4?8 mhz, the loop filter values shown in the table produce the most optimized performance for 6 mhz. it is possible to deviate slightly from these values for optimal performance at some other center frequency. also note that the values listed in these tables are all commonly manufactured components. not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 7 of 20 table 1. recommended loop filter values (v dd = 5.0 vdc, +/? 10%) [1, 2] input (mhz) rs1 rs0 bw = 1% (+/?0.5%) bw = 2% (+/?1%) bw = 3% (+/?1.5%) bw = 4% (+/?2%) 4?8 0 0 r1 = 2.2k c1 = 270 pf c2 = 22 pf r1 = 2.2k c1 = 120 pf c2 = 22 pf r1 = 2.2k c1 = 82 pf c2 = 22 pf r1 = 2.2k c1 = 56 pf c2 = 22 pf 8?12 0 1 r1 = 2.2k c1 = 470 pf c2 = 22 pf r1 = 2.2k c1 = 220 pf c2 = 22 pf r1 = 2.2k c1 = 150 pf c2 = 22 pf r1 = 2.2k c1 = 100 pf c2 = 22 pf 12?16 0 1 r1 = 2.2k c1 = 180 pf c2 = 22 pf r1 = 2.2k c1 = 82 pf c2 = 22 pf r1 = 2.2k c1 = 56 pf c2 = 22 pf r1 = 2.2k c1 = 33 pf c2 = 22 pf 16?20 1 0 r1 = 2.2k c1 = 680 pf c2 = 22 pf r1 = 2.2k c1 = 330 pf c2 = 22 pf r1 = 2.2k c1 = 220 pf c2 = 22 pf r1 = 2.2k c1 = 150 pf c2 = 22 pf 20?24 1 0 r1 = 2.2k c1 = 470 pf c2 = 22 pf r1 = 2.2k c1 = 220 pf c2 = 22 pf r1 = 2.2k c1 = 150 pf c2 = 22 pf r1 = 2.2k c1 = 100 pf c2 = 22 pf 24?28 1 0 r1 = 2.2k c1 = 220 pf c2 = 22 pf r1 = 2.2k c1 = 100 pf c2 = 22 pf r1 = 2.2k c1 = 82 pf c2 = 22 pf r1 = 2.2k c1 = 56 pf c2 = 22 pf 28?32 1 0 r1 = 4.7k c1 = 220 pf c2 = 0 pf r1 = 4.7k c1 = 100 pf c2 = 0 pf r1 = 4.7k c1 = 68 pf c2 = 0 pf r1 = 4.7k c1 = 47 pf c2 = 0 pf 32?36 1 0 r1 = 4.7k c1 = 120 pf c2 = 0 pf r1 = 4.7k c1 = 68 pf c2 = 0 pf r1 = 4.7k c1 = 47 pf c2 = 7 pf r1 = 4.7k c1 = 27 pf c2 = 15 pf 36?40 1 0 r1 = 4.7k c1 = 100 pf c2 = 0 pf r1 = 4.7k c1 = 33 pf c2 = 0 pf r1 = 4.7k c1 = 27 pf c2 = 0 pf r1 = 4.7k c1 = 18 pf c2 = 0 pf 40?44 1 1 r1 = 2.2k c1 = 470 pf c2 = 0 pf r1 = 2.2k c1 = 180 pf c2 = 22 pf r1 = 2.2k c1 = 120 pf c2 = 22 pf r1 = 2.2k c1 = 82 pf c2 = 22 pf 44?48 1 1 r1 = 2.2k c1 = 330 pf c2 = 0 pf r1 = 2.2k c1 = 150 pf c2 = 22 pf r1 = 2.2k c1 = 120 pf c2 = 16 pf r1 = 2.2k c1 = 82 pf c2 = 10 pf 48?52 1 1 r1 = 2.2k c1 = 270 pf c2 = 0 pf r1 = 2.2k c1 = 120 pf c2 = 0 pf r1 = 2.2k c1 = 100 pf c2 = 0 pf r1 = 2.2k c1 = 68 pf c2 = 0 pf 52?56 1 1 r1 = 2.2k c1 = 220 pf c2 = 0 pf r1 = 2.2k c1 = 100 pf c2 = 0 pf r1 = 2.2k c1 = 82 pf c2 = 0 pf r1 = 2.2k c1 = 56 pf c2 = 0 pf 56?60 1 1 r1 = 2.2k c1 = 220 pf c2 = 0 pf r1 = 2.2k c1 = 100 pf c2 = 0 pf r1 = 2.2k c1 = 68 pf c2 = 0 pf r1 = 2.2k c1 = 39 pf c2 = 0 pf 60?64 1 1 r1 = 7.5k c1 = 120 pf c2 = 33 pf r1 = 7.5k c1 = 68 pf c2 = 0 pf r1 = 7.5k c1 = 47 pf c2 = 0 pf r1 = 7.5k c1 = 33 pf c2 = 0 pf 64?68 1 1 r1 = 7.5k c1 = 120 pf c2 = 33 pf r1 = 7.5k c1 = 68 pf c1 = 0 pf r1 = 7.5k c1 = 47 pf c2 = 0 pf r1 = 7.5k c1 = 27 pf c2 = 0 pf notes 1. 0 pf means that the capacitor is removed. 2. when clock frequency is on boundary between two ranges, it is recommended that the higher range be used. not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 8 of 20 table 2. recommended loop filter values (v dd = 3.3 vdc, +/? 10%) [3, 4] input (mhz) rs1 rs0 bw = 1% (+/?0.5%) bw = 2% (+/?1%) bw = 3% (+/?1.5%) bw = 4% (+/?2%) 4?8 0 0 r1 = 2.2k c1 = 220 pf c2 = 22 pf r1 = 2.2k c1 = 100 pf c2 = 22 pf r1 = 2.2k c1 = 68 pf c2 = 22 pf r1 = 2.2k c1 = 39 pf c2 = 22 pf 8?12 0 1 r1 = 2.2k c1 = 470 pf c2 = 22 pf r1 = 2.2k c1 = 220 pf c2 = 22 pf r1 = 2.2k c1 = 150 pf c2 = 22 pf r1 = 2.2k c1 = 100 pf c2 = 22 pf 12?16 0 1 r1 = 2.2k c1 = 120 pf c2 = 22 pf r1 = 2.2k c1 = 56 pf c2 = 22 pf r1 = 2.2k c1 = 39 pf c2 = 22 pf r1 = 2.2k c1 = 27 pf c2 = 8 pf 16?20 1 0 r1 = 2.2k c1 = 680 pf c2 = 22 pf r1 = 2.2k c1 = 390 pf c2 = 22 pf r1 = 2.2k c1 = 270 pf c2 = 22 pf r1 = 2.2k c1 = 180 pf c2 = 22 pf 20?24 1 0 r1 = 2.2k c1 = 560 pf c2 = 22 pf r1 = 2.2k c1 = 220 pf c2 = 22 pf r1 = 2.2k c1 = 120 pf c2 = 22 pf r1 = 2.2k c1 = 82 pf c2 = 22 pf 24?28 1 0 r1 = 2.2k c1 = 220 pf c2 = 22 pf r1 = 2.2k c1 = 82 pf c2 = 22 pf r1 = 2.2k c1 = 56 pf c2 = 22 pf r1 = 2.2k c1 = 39 pf c2 = 10 pf 28?32 1 0 r1 = 4.7k c1 = 180 pf c2 = 0 pf r1 = 4.7k c1 = 68 pf c2 = 0 pf r1 = 4.7k c1 = 39 pf c2 = 0 pf r1 = 4.7k c1 = 27 pf c2 = 0 pf 32?36 1 0 r1 = 4.7k c1 = 82 pf c2 = 0 pf r1 = 4.7k c1 = 33 pf c2 = 0 pf r1 = 4.7k c1 = 22 pf c2 = 0 pf r1 = 4.7k c1 = 12 pf c2 = 0 pf 36?40 1 1 r1 = 47k c1 = 1.0 f c2 = 390 pf r1 = 47k c1 = 1.0 f c2 = 220 pf r1 = 47k c1 = 1.0 f c2 = 150 pf r1 = 47k c1 = 1.0 f c2 = 100 pf 40?44 1 1 r1 = 2.2k c1 = 680 pf c2 = 0 pf r1 = 2.2k c1 = 270 pf c2 = 0 pf r1 = 2.2k c1 = 180 pf c2 = 10 pf r1 = 2.2k c1 = 120 pf c2 = 10 pf 44?48 1 1 r1 = 2.2k c1 = 330 pf c2 = 0 pf r1 = 2.2k c1 = 180 pf c2 = 0 pf r1 = 2.2k c1 = 120 pf c2 = 0 pf r1 = 2.2k c1 = 82 pf c2 = 0 pf 48?52 1 1 r1 = 2.2k c1 = 270 pf c2 = 0 pf r1 = 2.2k c1 = 120 pf c2 = 0 pf r1 = 2.2k c1 = 82 pf c2 = 0 pf r1 = 2.2k c1 = 56 pf c2 = 0 pf 52?56 1 1 r1 = 2.2k c1 = 220 pf c2 = 0 pf r1 = 2.2k c1 = 100 pf c2 = 0 pf r1 = 2.2k c1 = 68 pf c2 = 0 pf r1 = 2.2k c1 = 33 pf c2 = 0 pf 56?60 1 1 r1 = 2.2k c1 = 150 pf c2 = 0 pf r1 = 2.2k c1 = 68 pf c2 = 5 pf r1 = 3.3k c1 = 47 pf c2 = 12 pf r1 = 4.7k c1 = 33 pf c2 = 22 pf 60?64 1 1 r1 = 4.7k c1 = 100 pf c2 = 0 pf r1 = 4.7k c1 = 47 pf c2 = 0 pf r1 = 4.7k c1 = 27 pf c2 = 0 pf r1 = 4.7k c1 = 18 pf c2 = 0 pf 64?68 1 1 r1 = 7.5k c1 = 68 pf c2 = 0 pf r1 = 7.5k c1 = 33 pf c1 = 0 pf r1 = 7.5k c1 = 22 pf c2 = 0 pf r1 = 7.5k c1 = 15 pf c2 = 0 pf notes 3. 0 pf means that the capacitor is removed. 4. when clock frequency is on boundary between two ranges, it is recommended that the higher range be used. not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 9 of 20 sscg modulation profile the modulation rate of the CYIFS731 is determined by the input frequency and the operating range. the input frequency is divided by a fixed number, depending on the operating range that is selected. the modulation rate of the CYIFS731 can be determined from ta b l e 3 . example: freq. of x in = 25 mhz operating range = 16?40 mhz modrate = fxin/240 = 104.166 khz. figure 4. frequency profile in time domain table 3. chart for determinati on of modulation rate of CYIFS731 x in range mod. rate divider 4?8 mhz 60 8?16 mhz 120 16?40 mhz 240 40?68 mhz 480 not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 10 of 20 theory of operation the CYIFS731 is a phase lock loop (pll) type clock generator using direct digital synthesis (d ds). by precisely controlling the bandwidth of the output clo ck, the CYIFS731 becomes a low emi clock generator. the theory and detailed operation of the CYIFS731 will be discussed in the following sections. emi all clocks generate unwanted energy in their harmonics. conventional digital clocks are square waves with a duty cycle that is very close to 50%. becaus e of the 50/50 du ty cycle, digital clocks generate most of thei r harmonic energy in the odd harmonics, i.e.; 3 rd , 5 th , 7 th etc. it is possible to reduce the amount of energy contained in the fundamental and harmonics by increasing the bandwidth of the fundamental clock frequency. conventional digital clocks have a very high q factor, which means that all of the energy at that frequency is concentrated in a very narrow bandwidth, consequently, higher energy peaks. regulatory agencies test electroni c equipment by the amount of peak energy radiated from the equipment. by reducing the peak energy at the fundamental and harmonics, the equipment under test is able to satisfy agency requirements for electro-magnetic interference (emi). conventiona l methods of reducing emi have been to use shielding, filtering, multi-layer pcb?s etc. the CYIFS731 uses the approach of r educing the peak energy in the clock by increasing the clock bandwidth, and lowering the q. sscg the CYIFS731 uses a proprietary technique to modulate the clock over a very narrow bandwidth and controlled rate of change, both pea k and cycle to cycle. t he CYIFS731 takes a narrow band digital reference clock in the range 4?68 mhz and produces a clock that sweeps between a controlled start and stop frequency and precise rate of change. to understand what happens to an sscg clock, consider that we have a 20 mhz clock with a 50% duty cycle. from a 20 mhz clock we know the following. figure 5. sscg clock consider that this 20 mhz clock is applied to the xin input of the CYIFS731, either as an externally driven clock or as the result of a parallel resonant crystal connected to pins 1 and 2 of the CYIFS731. also consider that the CYIFS731 is operating from a 5 volt dc power supply and the loop filter is set for a total bandwidth spread of 2%. refer to table 1 on page 7 . from the above parameters, the output clock at modout will be sweeping symmetrically around a center frequency of 20 mhz. the minimum and maximum extremes of this clock will be +200 khz and ?200 khz. so, we have a clock that is sweeping from 19.8 mhz to 20.2 mhz and back again. if we were to look at this clock on a spectrum analyzer we would see the picture in figure 6 . keep in mind that this is a drawing of a perfect clock with no noise. we see that the original 20 mhz reference clock is at the center frequency, f c , and the minimum and maximum extremes are positioned symmetrically about th e center frequency. this type of modulation is called center-spread. figure 6 illustrates this as it is seen on a spectrum analyzer. figure 6. perfect clock with no noise not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 11 of 20 figure 7 on page 11 shows a 20 mhz clock as it would be seen on an oscilloscope. the top trace is the non-modulated reference clock, or the refout clock at pin 7. the bottom trace is the modulated clock at pin 6. from this comparison chart you can see that the frequency is decreasing and the period of each successive clock increasing. the t c measurements on the left and right of the bottom trace indi cate the max. and min. extremes of the clock. intermediate clock changes are small and accumulate to achieve the total period deviation. the reverse of this figure would show the clock going from min. extreme back to the high extreme. figure 7. period comparison chart the CYIFS731 is a center spread clock, meaning that it symmetrically spreads above and below the reference frequency. looking at figure 6 on page 10 , you will note that the peak amplitude of the 20 mhz non-modulated clock is higher than the wideband modulated clock. this difference in peak amplitudes between modulated and unmodulated clocks is the reason why sscg clocks are so effective in digital systems. the figure 6 on page 10 refers to the fundamental frequency of a clock. a very important characteristic of the sscg clock is that the bandwidth of the harmonics is multiplied by the harmonic number. in other words, if the bandwidth of a 20 mhz clock is 200 khz, the bandwidth of the 3 rd harmonic will be 3 times 200 khz, or 600 khz. the amount of bandwidth is relative to the amount of energy in the clock. consequently, the wider the bandwidth, the greater the energy reduction of the clock. most applications will not have a problem meeting agency specifications at the fundament al frequency. it is the higher harmonics that usually cause the most problems. with an sscg clock, the bandwidth and peak energy reduction increases with the harmonic number. consider that the 11 th harmonic of a 20 mhz clock is 220 mhz. with a total spread of 200 khz at 20 mhz, the spread at the 11 th harmonic would be 2.20 mhz which greatly reduces the peak energy content. the difference in the peak energy of the modulated clock and the non-modulated clock in typical applications will see a 2?3 db reduction at the fundamental and as much as 8?10 db reduction at the intermediate harmonics, 3 rd , 5 th , 7 th etc. at the higher harmonics, it is quite possible to reduce the peak harmonic energy, compared to the unmodulated clock, by as much as 12 to 18 db. the following images are actual scans of the cyifs741. the cyifs741 is the same part as the CYIFS731 but has a times 2 output instead of the refout.t hese scans are from a spectrum analyzer and time domain analyzer of the cyifs741 at various frequencies running at 3.3 volts dc. figure 8 at the right shows a modulated 10 mhz clock at modout of the cyifs741. the following pa rameters apply to this scan; fin = 10 mhz. bw = 2% (total) vertical scale = 6 db/div. from this scan it can be seen the bandwidth of the clock is wider than a conventional clock. notice the emi filters displayed at the bottom of the image. this is the same filter settings that are used by regulatory agencies. figure 8. modulated 10 mhz clock at modout of cyifs741 it is clear from figure 8 , that the peak amplitude of the modulated clock is lower in amplitude than the non-modulated clock. in fact, this image indicates that the difference between the two peaks is approximately 2 db. not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 12 of 20 figure 9 on page 12 , shows the 3 rd harmonic of the 10 mhz clock in figure 8 . the big difference here is that the bandwidth of the 3rd. harmonic is 3 times greater than the bandwidth at the fundamental frequency. since the energy is spread over a much wider bandwidth, the peak energy reduction will be greater. as can be seen in this picture, the difference between the modulated and un-modulated peaks is approximately 8 db. with the bandwidth of the fundamental at 2% or 200 khz, the bandwidth at the 3rd. harmonic will be 600 khz. figure 9. 3 rd harmonic of the 10 mhz clock modulation rate the CYIFS731 moves from max to min frequencies of its bandwidth at a pre-determined rate and profile. the modulation frequency is determined by the input frequency and the range that is selected. the cyifs 731 has four input frequency operating ranges, 4?8 mhz, 8?16 mhz, 16?40 mhz and 40?68 mhz. the modulation rate is determined by a divider that results in 1/60, 1/120, 1/240 and 1/480 of the input frequency in each range, respectively. refer to the table 3 on page 9 . figure 10. frequency modulation profile the x in reference clock determines the modulation frequency but the internal sscg control logic determines the actual modulation profile. it is very im portant to note that the bandwidth of the clock modulation is determ ined by the values of the loop filter applied to pin 4. figure 10 shows the modulation profile of the CYIFS731. this type of test is done with a time domain analyzer. what this shows is the amount of time that the clock spends at any one frequency within its modulation envelope. fr om this type of picture, the amount of modulation percentage and modulation rate can be determined. this picture shows that the CYIFS731 is modulating 2% around the 10 mhz input and the modulation rate is 83.06 khz. not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 13 of 20 application notes and schematics the schematic diagram shown below is a simple minimum component application example of an cyif s731 design. in the case shown below, the control lines are configured for the following parameters. figure 11. simple minimum component application example of an CYIFS731 design [5] the circuit shown in figure 12 is the equivalent oscillator circuit used in the CYIFS731. figure 12. equivalent oscillator circuit used in the CYIFS731 calculating db reduction the db reduction for a give frequency and spread can be calculated using a simple formula. this formula is only helpful in determining a relative db reduction for a given application. this formula assumes an ideal cl ock with 50% duty cycle and therefore only predicts the emi reduction of odd harmonics. other circumstances such as non-ideal clock and noise will affect the actual db reduction. the formula is as follows; db = 6.5 + 9(log10(f)) + 9(log10(p)) where; f = frequency in mhz, p = total % spread (2.5% = 0.025) using a 50 mhz clock with a 2. 5% spread, the theoretical db reduction would be; db @ 50 mhz (fund) = 6.5 + 15.29 ? 14.42 = 7.37 db @ 150 mhz (3 rd ) = 6.5 + 19.58 ? 14.42 = 11.66 db @ 550 mhz (11 th ) = 6.5 + 24.66 ? 14.42 = 16.74 CYIFS731 note 5. c3 and c4 values assume a first order crystal with c l = 18 pf. not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 14 of 20 absolute maximum ratings item symbol min max units operating voltage v dd 3.0 6.0 vdc input, relative to v ss v irvss ?0.3 v dd + 0.3 vdc output, relative to v ss v orvss ?0.3 v dd + 0.3 vdc temperature, operating t op 0+70c temperature, storage t st ?65 +150 c esd protection, jedec standard js-001-2012 esd hbm 1300 ? v electrical characteristics characteristic symbol min typ max units input low voltage v il ??0.8vdc input high voltage v ih 2.0 ? ? vdc input low current i il ??100a input high current i ih ??100a output low voltage i ol = 8 ma, v dd = 5 v v ol ??0.4vdc output high voltage i oh = 8 ma, v dd = 5 v v oh v dd ? 1.0 ? ? vdc output low voltage i ol = 5 ma, v dd = 3.3 v v ol ??0.4vdc output high voltage i oh = 3 ma, v dd = 3.3 v v oh 2.4 ? ? vdc input capacitance (pin 1) c in1 ?34pf output capacitance (pin 2) c in2 ?56pf tri-state leakage current (pin 7) i oz ??5.0a 5 volt supply current @30 mhz, no load. i dd ?2025ma 3.3 volt supply current @ 30 mhz, no load. i dd ?912m a short circuit current (refout or modout) i sc ??25m a test measurements performed at v dd = 3.3 v and 5.0 v 10%, x in = 30 mhz, t a = 0 c to 70 c not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 15 of 20 timing characteristics characteristic symbol min typ max units output rise time measured at 10%?90% @ 5 vdc t tlh 4.5 5.1 5.7 ns output fall time measured at 10%?90% @ 5 vdc t thl 4.0 4.3 4.7 ns output rise time measured at 0.8 v?2.0 v @ 5 vdc t tlh 850 900 975 ps output fall time measured at 0.8 v?2.0 v @ 5 vdc t thl 1.3 1.4 1.5 ns output rise time measured at 10%?90% @ 3.3 vdc t tlh 5.0 5.3 5.9 ns output fall time measured at 10%?90% @ 3.3 vdc t thl 4.8 5.1 5.4 ns output rise time measured at 0.8 v?2.0 v @ 3.3 vdc t tlh 1.8 1.9 2.0 ns output fall time measured at 0.8 v?2.0 v @ 3.3 vdc t thl 2.0 2.2 2.4 ns output duty cycle ts y m f 1 45 50 55 % ccj, jitter @ 5.0 vdc, 50 mhz ccj ? 300 350 ps ccj, jitter @ 3.3 vdc, 50 mhz ccj ? 200 250 ps measurements performed at v dd = 3.3 v and 5.0 v 10%, t a = 0 c to 70 c, c l = 15 pf, x in = 30 mhz. not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 16 of 20 ordering code definitions ordering information ordering code part and package type operating range CYIFS731sxc 8-pin soic commercial, 0 c to 70 c CYIFS731sxct 8-pin soic, tape and reel commercial, 0 c to 70 c t = tape and reel; blank = tube temperature range: c = commercial, 0 c to 70 c pb-free package type: s = 8-pin soic (150 mil) part identifier company id: cy = cypress ifs731 x s c cy t not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 17 of 20 package diagram figure 13. 8-pin soic (150 mils) s0815/sz815/sw815 package outline, 51-85066 51-85066 *f not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 18 of 20 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor dds direct digital synthesis emi electromagnetic interference ic integrated circuit i/o input/output lan local area network lcd liquid crystal display lf loop filter pcb printed circuit board pll phase locked loop soic small-outline integrated circuit ttl transistor-transistor logic wan wide area network symbol unit of measure c degree celsius db decibel khz kilohertz k? kilohm mhz megahertz a microampere ma milliampere mw milliwatt ns nanosecond % percent pf picofarad vvolt not recommended for new designs
CYIFS731 document number: 001-73426 rev. *d page 19 of 20 document history page document title: CYIFS731, low emi spread spectrum clock document number: 001-73426 rev. ecn no. issue date orig. of change description of change ** 3403637 10/12/2011 puru new data sheet. *a 4457908 07/26/2014 xht updated block diagram . updated package diagram : spec 51-85066 ? changed revision from *e to *f. updated to new template. *b 4526925 10/07/2014 xht post to external web. *c 4565316 11/09/2014 xht updated absolute maximum ratings : added esd hbm parameter and its details. added watermark ?not recommended for new designs?. completing sunset review. *d 4598681 12/16/2014 xht added related documentation hyperlink in page 1. not recommended for new designs
document number: 001-73426 rev. *d revised december 16, 2014 page 20 of 20 all products and company names mentioned in this document may be the trademarks of their respective holders. CYIFS731 ? cypress semiconductor corporation, 2011-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support not recommended for new designs

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Price & Availability of CYIFS731

Part #	Manufacturer	Description	Price	BuyNow Qty.
CYIFS731SXC	Cypress Semiconductor	Clock Generator PDSO8 '	1000: USD2.05 500: USD2.17 100: USD2.27 25: USD2.36 1: USD2.41	13723
CYIFS731SXCT	Cypress Semiconductor	Clock Generator PDSO8 '	1000: USD2.05 500: USD2.17 100: USD2.27 25: USD2.36 1: USD2.41	5291

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