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sic770cd www.vishay.com vishay siliconix s13-1119-rev. a, 27-may-13 1 document number: 62727 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 drmos integrated power stage description the sic770 is an integrated power stage solution optimized for synchronous buck applications to offer high current, high efficiency and high power de nsity performance. packaged in vishays proprietary 6 mm x 6 mm mlp package, sic770 enables voltage regulator design to deliver in excess of 40 a per phase current. the internal power mosfets utilizes vishays state-of-the-art trenchfet gen iv technology that delivers industry bench-mark performa nce to significantly reduce switching and conduction losses. the sic770 incorporates an advanced mosfet gate driver ic that features high current driving capability, adaptive dead-time control, and inte grated bootstrap schottky diode, a thermal warning (thwn) alerts the system of excessive junction temperature. this driver is also compatible with wide range of pwm controllers with the support of tri-state pwm, 5 v pwm logic, and skip mode (zcd) for improve light load efficiency. features ? industry benchmark mosfet with integrated schottky diode ? delivers in excess of 40 a continuous current ? 91 % peak efficiency ? high frequency operation up to 1 mhz ? power mosfets optimize d for 19 v input stage ? 5 v pwm logic with tri-state and hold-off ? automatic skip mode operation (zcd) for light load efficiency ? built-in bootstrap schottky diode ? thermal monitor flag ?v cin under voltage lockout ? compliant with intel drmos 4.0 specification ? thermally enhanced powerpak ? mlp6x6-40l package ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? synchronous buck converters ? muliti-phase vrds for cpu, gpu and memory ? dc/dc pol modules typical application diagram fig. 1 - sic770 typica l application diagram pwm controller gate driver 5v vin vout vcin zcd_en# d s bl # pwm thwn vdrv gh vin boot s w pgnd gl cgnd pha s e
sic770cd www.vishay.com vishay siliconix s13-1119-rev. a, 27-may-13 2 document number: 62727 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pinout configuration fig. 2 - sic770 pin configuration pin description pin# name function 1 zcd_en# ls fet turn-off logic; active low 2v cin supply voltage for internal logic circuitry 3v drv supply voltage for internal gate driver 4 boot high side driver bootstrap voltage 5, 37, p1 c gnd analog ground for the driver ic 6 gh high side gate signal 7 phase return path of hs gate driver 8 to 14, p2 v in power stage input voltage. drain of high side mosfet 15, 29 to 35, p3 v swh phase node of the power stage 16 to 28 p gnd power ground 36 gl low side gate signal 38 thwn thermal warning open drain output 39 dsbl# disable pin; active low 40 pwm pwm input logic ordering information part number packa g e markin g code sic770cd-t1-ge3 powerpak mlp66-40l sic770cd SIC770DB reference board zcd_en# vcin 2 vdrv 3 boot 4 c g nd 5 g h 6 pha s e 7 vin 8 vin 9 vin 10 vin 11 vin 12 vin 13 vin 14 v s wh 15 p g nd 16 p g nd 17 p g nd 18 p g nd 19 p g nd 20 28 p g nd 27 p g nd 26 p g nd 25 p g nd 24 p g nd 23 p g nd 22 p g nd 21 p g nd 30 v s wh 29 v s wh 31 v s wh 32 v s wh 33 v s wh 34 v s wh 35 v s wh 36 g l 37 c g nd 38 thwn 39 d s bl# 40 pwm cgnd vin v s wh zcd_en# vcin 2 vdrv 3 boot 4 c g nd 5 g h 6 pha s e 7 vin 8 vin 9 vin 10 vin 11 vin 12 vin 13 vin 14 v s wh 15 p g nd 16 p g nd 17 p g nd 18 p g nd 19 p g nd 20 28 p g nd 27 p g nd 26 p g nd 25 p g nd 24 p g nd 23 p g nd 22 p g nd 21 p g nd 30 v s wh 29 v s wh 31 v s wh 32 v s wh 33 v s wh 34 v s wh 35 v s wh 36 g l 37 c g nd 38 thwn 39 d s bl# 40 pwm cgnd vin v s wh
sic770cd www.vishay.com vishay siliconix s13-1119-rev. a, 27-may-13 3 document number: 62727 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes ? stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any ot her conditions beyond those indicated in the operational section s of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y. (1) the specification values indicated ac is vsw to pgnd - 8 v (< 20 ns, 10 j), minimum and 35 v (< 50 ns), maximum. absolute maximum ratings electrical parameter symbol limits unit input voltage v in - 0.3 to 30 v control input voltage v cin - 0.3 to 7 v drive input voltage v drv - 0.3 to 7 v switch node (dc) v sw - 0.3 to 30 v switch node (ac) (1) - 8 to 35 v boot voltage (dc voltage) v bs - 0.3 to 32 v boot to switching node (dc voltage) vbs_sw - 0.3 to 7 v all logic inputs and outputs (pwm, dsbl, smod, and thdn) - 0.3 to v cin + 0.3 v max. operating junction temperature t j 150 c ambient temperature t a - 40 to 125 c storage temperature - 65 to 150 c recommended operating range electrical min. typ. max. unit input voltage (v in )4.524v drive input voltage (v drv ) 4.5 5 5.5 v control input voltage (v cin ) 4.5 5 5.5 v switching node (lx, dc voltage) 27 v boot-sw 44.55.5v thermal resistance thermal resistance from junction to case (to p3 pad vswh) 2.5 c/w thermal resistance from junction to pcb 5 c/w
sic770cd www.vishay.com vishay siliconix s13-1119-rev. a, 27-may-13 4 document number: 62727 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes (1) typical limits are established by characterization and are not production tested. (2) guaranteed by design. (3) min. and max. parameters ar e not 100 % production tested. electrical specifications (dsbl# = 5 v, smod = 5 v, v in = 19 v, v drv and v cin = 5 v, t a = 25 c) parameter symbol test conditions unless specified min. typ. max. unit power supplies control logic input current i vcin v dsbl# = 0 v, no switching 21 a v dsbl# = 5 v, no switching 350 v dsbl# = 5 v, f s = 300 khz, d = 0.1 500 drive input current (dynamic) i vdrv f s = 300 khz, d = 0.1 14 ma f s = 1 mhz, d = 0.1 40 bootstrap supply bootstrap switch forward voltage v f v cin = 5 v, forward bias current 2 ma 0.6 v pwm control input rising threshold pwm th_r 3.5 3.9 4.2 v falling threshold pwmt h_f 0.8 1.0 1.2 v tri-state voltage v tri pwm pin floating 2.3 v tri-state rising threshold v tri_th_r 0.9 1.3 1.8 v tri-state falling threshold v tri_th_f 3.4 3.7 4.0 v tri-state rising threshold hysteresis v tri_hys_r 280 mv tri-state falling threshold hysteresis v tri_hys_f 180 mv pwm input current i pwm v pwm = 5 v 250 a v pwm = 0 v - 250 timin g specifications tri-state to gh/gl rising propagation delay t pd_r_tri no load, see fig. 4 20 ns tri-state hold-off time t tsho 150 ns gh - turn off propagation delay t pd_off_gh 20 ns gh - turn on propagation delay (dead time rising) t pd_on_gh 15 ns gl - turn off propagation delay t pd_off_gl 20 ns gl - turn on propagation delay (dead time falling) t pd_on_gl 20 ns dsbl# hi to gh/gl risi ng propagation delay t pd_r_dsbl 500 ns dsbl# lo to gh/gl fal ling propagation delay t pd_f_dsbl 200 ns dsbl# , zcd_en# input dsbl# logic input voltage v dsbl enable 2 v disenable 0.8 zcd_en# logic input voltage v smod high state 2 v low state 0.8 protection under voltage lockout v uvlo rising, on threshold 3.3 3.9 v falling, off threshold 2.3 2.95 under voltage lockout hysteresis 400 mv thwn flag set (2) (2) 160 c thwn flag clear (2) 135 c thwn flag hysteresis (2) 25 c thwn output low 0.02 v
sic770cd www.vishay.com vishay siliconix s13-1119-rev. a, 27-may-13 5 document number: 62727 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 detailed operational description pwm input with tri-state function the pwm input receives the pwm control signal from the vr controller ic. the pwm input is designed to be compatible with standard controllers using two state logic (h and l) and advanced controllers that incorporate tri-state logic (h, l, and tri-state) on the pwm output. for two state logic, the pwm input operates as follows. when pwm is driven above v th_pwm_r the low side is turned off and the high side is turned on. when pwm input is driven below v th_pwm_f the high side turns off and the lo w side turns on. for tri-state logic, the pwm input operates as above for driving the mosfets. however, there is an third state that is entered into as the pwm output of tri-state compatible controller enters its high impedance state during shut-down. the high impedance state of the controllers pwm output allows the sic770 to pull the pwm input into the tri-state region (see the tri-state voltage threshold diagram below). if the pwm input stays in this region for the tri-state hold-off period, t tsho , both high side and low si de mosfets are turned off. this function allows the vr phase to be disabled without negative output voltage swing caused by inductor ringing and saves a schottky diode cl amp. the pwm and tri-state regions are separated by h ysteresis to prevent false triggering. the sic770cd incorporates pwm voltage thresholds that are compatible with 5 v logic. disable (dsbl#) in the low state, the dsbl# pi n shuts down the driver ic and disables both high-side and lo w-side mosfet. in this state, the standby current is mini mized. if dsbl# is left unconnected an internal pull-down resistor will pull the pin down to cgnd and shut down the ic. diode emulation mode (zcd_en#) skip when zcd_en# pin is low the diode emulation mode is enabled. this is a non-synch ronous conversion mode that improves light load efficiency by reducing switching losses. conducted losses that occur in synchronous buck regulators when inductor current is negative are also reduced. circuitry in the gate drive ic detects the inductor valley current when inductor current crosses zero and automatically stops switchin g the low side mosfet. see zcd_en# operation diagram fo r additional details. this function can be also be used for a pre-biased output voltage. if zcd_en# is left un-connected, an internal pull up resistor will pull the pin up to v cin (logic high) to disable the zcd_en# function. thermal shutdown warning (thwn) the thwn pin is an open drain signal that flags the presence of excessive junction tempe rature. connect a maximum of 20 k ? to pull this pin up to v cin . an internal temperature sensor detects the junction temperature. the temperature threshold is 160 c. when this junction temperature is exceeded the thwn flag is set. when the junction temperature drops below 135 c the device will clear the thwn signal. the sic770 does not stop operation when the flag is set. the decision to shutdown must be made by an external thermal control function. voltage input (v in ) this is the power input to th e drain of the high-side power mosfet. this pin is connected to the high power intermediate bus rail. switch node (v swh and phase) the switch node v swh is the circuit pwm regulated output. this is the output applied to the filter circuit to deliver the regulated high output for th e buck converter. the phase pin is internally connecte d to the switch node v swh . this pin is to be used exclusively as the return pin for the boot capacitor. a 20 k ? resistor is connected between gh and phase to provide a discharge path for the hs mosfet in the event that v cin goes to zero while v in is still applied. g round connections (c g nd and p g nd ) p gnd (power ground) should be externally connected to c gnd (control signal ground). the layout of the printed circuit board should be such that th e inductance separating the c gnd and p gnd should be a minimum. transient differences due to inductance effects between these two pins should not exceed 0.5 v. control and drive supp ly voltage input (v drv , v cin ) v cin is the bias supply for th e gate drive control ic. v drv is the bias supply for the gate drivers. it is recommended to separate these pins through a resistor. this creates a low pass filtering effect to avoid coupling of high frequency gated rive noise into the ic. bootstrap circuit (boot) the internal bootstrap switch and an external bootstrap capacitor form a charge pump that supplies voltage to the boot pin. an integrated boot strap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. connect a b oot strap capacitor with one leg tied to boot pin and the other tied to phase pin.
sic770cd www.vishay.com vishay siliconix s13-1119-rev. a, 27-may-13 6 document number: 62727 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 shoot-through protection and adaptive dead time (ast) the sic770 has an internal adaptive logic to avoid shoot through and optimize dead time. the shoot through protection ensures that bo th high-side and low-side mosfet are not turned on the same time. the adaptive dead time control operates as follows. the hs and ls gate voltages are monitored to preve nt the one turning on until the other's gate voltage is sufficiently low (1.0 v), that and built in delays ensure the one power mos is completely off, before the other can be turn ed on. this feature helps to adjust dead time as gate tran sitions change with respect to output current and temperature. under voltage lockout (uvlo) during the start up cycle, the uvlo disables the gate drive holding high-side and low-side mosfet gate low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. the sic770 also incorporates logic to clamp the gate drive signals to zero when the uvlo falling edge triggers the shutdown of the device. as an added precaution, a 20.2 k ? resistor is connected between gh and ph ase to provide a discharge path for the hs mosfet. functional block diagram fig. 3 - sic770 functi onal block diagram device truth table dsbl# smod pwm gh gl open x x l l lxxll h l l l h (il > 0), l (il ? 0) hlhhl hhhhl hhl lh dsbl# vin boot gh gl zcd_en# tristate pwm pwm dhoe pgnd adt cntl dcm detect vswh vdrv uvlo thermal shutdown thwn phase vcin
sic770cd www.vishay.com vishay siliconix s13-1119-rev. a, 27-may-13 7 document number: 62727 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pwm timing diagram fig. 4 - definition of pwm logic and tri-state pwm timing diagram fig. 5 - zcd_en# oper ation timing diagram fig. 6 - dsbl# functi on timing diagram pwm th_r pwm th_f pwm tri_r pwm tri_f pwm gh gl t pd_off_gl t tsho t pd_on_gh t pd_off_gh t pd_off_gl t tsho t pd_r_tri t pd_r_tri ! pwm hg lg zcd_en# high low pwm controller gate driver vin vout zcd_en# pwm vin boot sw pgnd cgnd phase il sense cs zcd il 0a i l = 0a pwm dsbl# gh gl t pwm dsbl# gh gl t dsbl# hi to gh rising propagation delay dsbl# hi to gl rising propagation delay enable pwm dsbl# gh gl dsbl# lo to gh falling propagation delay t dsbl# lo to gl falling propagation delay pwm dsbl# gh gl t disable
sic770cd www.vishay.com vishay siliconix s13-1119-rev. a, 27-may-13 8 document number: 62727 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics efficiency performance vs. f sw v in = 12 v, v out = 1.8 v power loss vs. sw itching frequency v in = 19 v, v out = 1.8 v, i out = 15 a, rboot = 4.7 ? , inductance = 0.47 h driver current vs. switching frequency v in = 12 v, v out = 1.8 v, i out = 20 a, v cin = v drv = 5 v efficiency performance vs. f sw v in = 19 v, v out = 1.8 v power loss vs. input voltage v out = 1.8 v, i out = 15 a, f sw = 300 khz, rboot = 4.7 ? , inductance = 0.47 h v cin current vs. switching frequency v in = 12 v, v out = 1.8 v, i out = 20 a, v cin = v drv = 5 v 80 82 84 86 88 90 92 94 96 0.1 1 10 e?ciency (%) load (a) o/p inductor 350khz ihlp-5050-fd 0.56uh dcr=1.20m 800khz ihlp-5050-fd 0.22uh dcr=0.63m 1mhz ihlp-5050-fd 0.15uh dcr=0.53m fsw - 350khz fsw - 800khz fsw - 1mhz 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 200 300 400 500 600 700 800 900 1000 power loss (w) switching frequency (khz) 5 10 15 20 25 30 35 40 45 50 200 300 400 500 600 700 800 900 1000 i drv current (ma) switching frequency (khz) 80 82 84 86 88 90 92 94 0.1 1 10 e?ciency (%) load (a) o/p inductor 350khz ihlp-5050-fd 0.56uh dcr=1.20m 800khz ihlp-5050-fd 0.22uh dcr=0.63m 1mhz ihlp-5050-fd 0.15uh dcr=0.53m fsw - 350khz fsw - 800khz fsw - 1mhz 2.1 2.15 2.2 2.25 2.3 2.35 2.4 2.45 2.5 5 7 9 1113151719 power loss (w) input voltage (v) 1.1 1.15 1.2 1.25 1.3 1.35 1.4 200 300 400 500 600 700 800 900 1000 i cin current (ma) switching frequency (khz)
sic770cd www.vishay.com vishay siliconix s13-1119-rev. a, 27-may-13 9 document number: 62727 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 switching waveform at pwm rising edge v in = 19 v, v o = 1.8 v, i o = 20 a, f sw = 500 khz switching waveform at zcd_en# - high v in = 12 v, v o = 1.8 v, , i l = 1 a, f sw = 500 khz dsbl# hi to g h rising propagation delay v in = 12 v, t on = 200 ns, f sw = 500 khz, i o = 0 a switching waveform at pwm falling edge v in = 19 v, v o = 1.8 v, i o = 20 a, f sw = 500 khz switching waveform at zcd_en# - low v in = 12 v, v o = 1.8 v, , i l = dcm, t on = 200 ns dsbl# hi to g l rising prop agation delay v in = 12 v, t on = 200 ns, f sw = 500 khz, i o = 0 a
sic770cd www.vishay.com vishay siliconix s13-1119-rev. a, 27-may-13 10 document number: 62727 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dsbl# lo to g h falling propagation delay dsbl# lo to g l falling propagation delay
sic770cd www.vishay.com vishay siliconix s13-1119-rev. a, 27-may-13 11 document number: 62727 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package mechanical drawing notes 1. use millimeters as the primary measurement 2. dimensioning and tolerances conform to asme y14.5m. - 1994 3. n is the number of terminals. nd is the number of terminals in x-direction and ne is the number of terminals in y-direction 4. dimension b applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip 5. the pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of packag e body 6. exact shape and size of this feature is optional 7. package warpage max. 0.08 mm 8. applied only for terminals vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62727 . dim. millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.078 0.098 0.011 d 6.00 bsc 0.236 bsc e 0.50 bsc 0.019 bsc e 6.00 bsc 0.236 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n (3) 40 40 nd (3) 10 10 ne (3) 10 10 d2-1 1.45 1.50 1.55 0.057 0.059 0.061 d2-2 1.45 1.50 1.55 0.057 0.059 0.061 d2-3 2.35 2.40 2.45 0.095 0.094 0.096 e2-1 4.35 4.40 4.45 0.171 0.173 0.175 e2-2 1.95 2.00 2.05 0.076 0.078 0.080 e2-3 1.95 2.00 2.05 0.076 0.078 0.080 k1 0.73 bsc 0.028 bsc k2 0.21 bsc 0.008 bsc 40 1 2 x 2 x pin 1 dot by marking mlp66-40 (6 mm x 6 mm) 10 11 20 21 30 31 56 4 top view bottom view side view a b c d 0.10 c b e 0.10 c a a 0.08 c a1 a2 0.41 k2 k1 d2-1 pin #1 dent e2-1 e d2-3 d2-2 e2-3 e2-2 (nd-1)x e ref. (nd-1)x e ref. 0.10 m c a b
package information www.vishay.com vishay siliconix revision: 12-jan-15 1 document number: 64846 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 powerpak ? mlp66-40 case outline notes 1. use millimeters as the primary measurement 2. dimensioning and tolerances conform to asme y14.5m. - 1994 3. n is the number of terminals. nd is the number of terminals in x-direction and ne is the number of terminals in y-direction 4. dimension b applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip 5. the pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of packag e body 6. exact shape and size of this feature is optional 7. package warpage max. 0.08 mm 8. applied only for terminals dim. millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.078 0.098 0.011 d 6.00 bsc 0.236 bsc e 0.50 bsc 0.019 bsc e 6.00 bsc 0.236 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n (3) 40 40 nd (3) 10 10 ne (3) 10 10 d2-1 1.45 1.50 1.55 0.057 0.059 0.061 d2-2 1.45 1.50 1.55 0.057 0.059 0.061 d2-3 2.35 2.40 2.45 0.095 0.094 0.096 e2-1 4.35 4.40 4.45 0.171 0.173 0.175 e2-2 1.95 2.00 2.05 0.076 0.078 0.080 e2-3 1.95 2.00 2.05 0.076 0.078 0.080 k1 0.73 bsc 0.028 bsc k2 0.21 bsc 0.008 bsc ecn: t14-0826-rev. b, 12-jan-15 dwg: 5986 40 1 2 x 2 x pin 1 dot by marking mlp66-40 (6 mm x 6 mm) 10 11 20 21 30 31 56 4 top view bottom view side view a b c d 0.10 c b e 0.10 c a a 0.0 8 c a1 a2 0.41 k2 k1 d2-1 e2-1 e d2-3 d2-2 e2-3 e2-2 ( n d-1)x e ref. ( n d-1)x e ref. 0.10 m c a b
legal disclaimer notice www.vishay.com vishay revision: 13-jun-16 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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Part #	Manufacturer	Description	Price	BuyNow Qty.
SIC770DB 78-SIC770DB	Vishay Intertechnologies	Gate Drivers Reference Board for SIC770 series	1: USD112.09 10: USD106.79 25: USD104.52 50: USD103.76	0

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