1 ps8862l 05/01/09 pin description pin name description buf_in input clk [0:9] outputs gnd ground v dd power pin con guration 1 2 3 4 516 615 714 813 20 19 18 17 buf_in gnd clk0 v dd clk1 gnd clk2 v dd clk3 gnd v dd clk9 clk8 gnd clk7 v dd clk6 gnd clk5 clk4 9 10 11 12 block diagram features ? high-speed, low-noise, non-inverting 1-10 buffer ? maximum frequency up to 250 mhz ? low output skew < 60ps ? low duty cycle distortion < 200ps ? low propagation delay < 2.0ns ? multiple v dd , gnd pins for noise reduction ? 1.8v or 2.5v supply voltage ? packages (pb-free & green): ? 20-pin, tssop (l20) ? 20-pin, ssop (h20) 1.8v/2.5v, 250mhz, 1:10 networking clock buffer pi6c10807 description the pi6c10807 is a 1.8v, or 2.5v high-speed, low-noise 1-10 non-inverting clock buffer. the key goal in de sign ing the pi6c10807 is to target networking applications that re quire low- skew, low-jitter, and high-frequency clock distribution. providing output-to-output skew as low as 60ps, the pi6c10807 is an ideal clock distribution de vice for syn chro nous sys tems. de- sign ing syn chro nous net work ing sys tems re quires a tight level of skew from a large number of outputs. 09-0084
2 ps8862l 05/01/09 pi6c10807 1.8v/2.5v, 250mhz, 1:10 networking clock buffer storage temperature ...........................................................?65c to +150c v dd voltage ..........................................................................?0.5v to +3.6v output voltage (max. 3.6v) .......................................... ?0.5v to v dd +0.5v input voltage (max 3.6v) .............................................. ?0.5v to v dd +0.5v 2.5v absolute maximum ratings (above which the useful life may be impaired. for user guidelines only, not tested.) note: stresses greater than those listed under maxi- mum rat ings may cause permanent damage to the device. this is a stress rating only and functional op er a tion of the device at these or any other con di tions above those indicated in the operational sec tions of this spec i ca tion is not implied. ex po sure to absolute maximum rating con di- tions for extended periods may affect re li abil i ty. 2.5v ac characteristics (over operating range: v dd = 2.5v 0.2v, t a = -40 to 85c) parameters de scrip tion test conditions 1 min. typ max. units f in input frequency 0 250 mhz t r /t f clkn rise/fall time 20% to 80% 1.0 ns t sk(p) 3. 5 pulse skew between opposite transitions (t phl -t plh ) of the same output vin > v dd c l = 5pf, 125 mhz 100 200 ps t plh, t phl 2, 5 propagation delay buf_in to clkn c l = 5pf, 125 mhz 1.0 1.5 2.0 ns t sk(o) 3, 5 output to output skew between any two outputs of the same device @ same transition 60 ps t sk(t) 3, 5 part to part skew between two identical out- puts of different parts on the same board 4 300 t dc_in 5 duty cycle in @ ins edge rate 45 55 % t dc_out 5 duty cycle out 40 57.5 notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. skew measured at worst case temperature (max. temp). 4. identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 5. outputs are measured at v dd /2 2.5v dc characteristics (over operating range: v dd = 2.5v 0.2v, t a = -40 to 85c) parameters description test conditions 1 min. typ. 2 max. units v dd supply voltage 2.3 2.5 2.7 v ih input high voltage logic high level 1.7 3.6 v v il input low voltage logic low level -0.3 0.7 i i input current v dd = max, vin = v dd or gnd 15 a v oh output high voltage v dd = min., v in = v ih or v il i oh = -1ma 2.0 v i oh = -2ma 1.7 i oh = -8ma 1.7 v ol output low voltage v dd = min., v in - v ih or v il i ol = 1ma 0.1 i ol = 2ma 0.2 i ol = 8ma 0.2 notes: 1. for max. or min. conditions, use appropriate operating range values. 2. typical values are at v dd = 2.5v, +25c ambient and maximum loading. 09-0084
3 ps8862l 05/01/09 pi6c10807 1.8v/2.5v, 250mhz, 1:10 networking clock buffer 1.8v ac characteristics (over operating range: v dd = 1.8v 0.15v, t a = -40 to 85c) parameters de scrip tion test conditions (1) min. typ max. units f in input frequency 0 180 mhz t r /t f clkn rise/fall time 20% to 80% 1.0 ns t sk(p) 3. 5 pulse skew between opposite transitions (t phl -t plh ) of the same output vin > v dd c l = 5pf, 125 mhz 100 200 ps t plh, t phl 2, 5 propagation delay buf_in to clkn c l = 5pf, 125 mhz 1.0 1.5 2.0 ns t sk(o) 3, 5 output to output skew between any two outputs of the same device @ same transition 60 ps t sk(t) 3, 5 part to part skew between two identical out- puts of different parts on the same board 4 300 t dc_in 5 duty cycle in @ ins edge rate 45 55 % t dc_out 5 duty cycle out 40 57.5 notes: 1. see test circuit and waveforms 2. minimum limits are guaranteed but not tested on propagation delays. 3. skew measured at worst case temperature (max. temp). 4. identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.. 5. outputs are measured at v dd /2 storage temperature ...........................................................?65c to +150c v dd voltage ..........................................................................?0.5v to +2.5v output voltage (max 2.5v) .......................................... ?0.5v to v dd +0.5v input voltage (max 2.5v) ............................................. ?0.5v to v dd +0.5v 1.8v absolute maximum ratings (above which the useful life may be impaired. for user guidelines only, not tested.) note: stresses greater than those listed under maxi- mum rat ings may cause permanent damage to the device. this is a stress rating only and functional op er a tion of the device at these or any other con di tions above those indicated in the operational sec tions of this spec i ca tion is not implied. ex po sure to absolute maximum rating con di - tions for extended periods may affect re li abil i ty. 1.8v dc characteristics (over operating range: v dd = 1.8v 0.15v, t a = -40 to 85c) parameters description test conditions (1) min. typ. (2) max. units v dd supply voltage 1.65 1.8 1.95 v ih input high voltage logic high level 1.1 2.7 v v il input low voltage logic low level -0.3 0.35*v dd i i input current (3) v dd = max, vin = v dd or gnd 15 a v oh output high voltage v dd = min., v in = v ih or v il i oh = -2ma 1.35 v i oh = -8ma 1.2 v ol output low voltage v dd = min., v in - v ih or v il i ol = 2ma 0.1 i ol = -8ma 0.2 notes: 1. for max. or min. conditions, use appropriate operating v dd and ta values. 2. typical values are at v dd = 1.8v, +25c ambient and maximum loading. 3. this parameter is determined by device characterization but is not production tested. 09-0084
4 ps8862l 05/01/09 pi6c10807 1.8v/2.5v, 250mhz, 1:10 networking clock buffer test circuits for all outputs de nitions: c l = load capacitance: includes jig and probe capacitance. capacitance (t a = 25c, f = 1 mhz) parameters (1) de scrip tion test conditions typ max. units c in input capacitance v in = 0v 3.0 4 pf c out output capacitance v out = 0v ? 6 note: 1. this parameter is determined by device characterization but is not production tested. pulse generator f = 125mhz d.u.t. 50-ohm 33-ohm c l 5p f v dd power supply characteristics parameters description test conditions (1) min. typ. (2) max. units i ddq quiescent power supply current v dd = 2.7v v in = gnd or v dd 10 a v dd = 1.95v 10 i ddn dynamic power supply current per output v dd = 2.7v all outputs toggling, c l = 5pf, f in = 125mhz 1.8 ma v dd = 1.95v 3.5 i dd_tot total power supply current v dd = 2.7v v in = v dd or gnd, all outputs toggling, c l = 5pf, f in = 125mhz 48 v dd = 1.95v 35 ?i cc static supply current per inputs @ high level v dd = 2.7v v inx = v dd - 0.6v (3) 500 a v dd = 1.95v v inx = v dd - 0.6v (3) 450 notes: 1. for max. or min. conditions, use appropriate value speci ed under electrical characteristics. 2. typical values are at v dd = 1.5v, 1.8v or 2.5v, and +25c ambient. 3. per ttl driven input (v in = v dd - 0.6v); all other inputs at v dd or gnd. 09-0084
5 ps8862l 05/01/09 pi6c10807 1.8v/2.5v, 250mhz, 1:10 networking clock buffer switching waveforms propagation delay package skew ? t sk(t) pulse skew ? t sk(p) output skew ? t sk(o) input t plh v ih v dd /2 v il output v oh v dd /2 v ol t phl t r t f input t plh v dd v dd /2 0v output v oh v dd /2 v ol t phl t sk(p) = | t plh - t plh | input t plhx v dd v dd /2 0v clkx v oh v dd /2 v ol t phlx t sk(o) clky v oh v dd /2 v ol t sk(o) t plhy t phly t sk(o) = | t plhy - t plhx | or | t phly - t phlx | input t plh1 v dd v dd /2 0v part #1 output v oh v dd /2 v ol t phl1 t sk(t) part #2 output v oh v dd /2 v ol t sk(t) t plh2 t phl2 t sk(t) = | t plh2 - t plh1 | or | t phl2 - t phl1 | 09-0084
6 ps8862l 05/01/09 pi6c10807 1.8v/2.5v, 250mhz, 1:10 networking clock buffer 1 description: 20-pin, 173-mil wide, tssop package code: l document control no. pd - 1311 revision: e date: 03/09/05 pericom semiconductor corporation 3545 n. 1st street, san jose, ca 95134 1-800-435-2335 ? www.pericom.com .252 .260 .047 1.20 .002 .006 seating plane .0256 bsc .018 .030 .004 .008 .238 .269 1 20 .169 .177 0.05 0.15 6.1 6.7 0.45 0.75 0.09 0.20 4.3 4.5 6.4 6.6 0.65 0.19 0.30 .007 .012 max note: 1. package outline exclusive of mold flash and metal burr 2. controlling dimentions in millimeters 3. ref: jedec mo-153f/ac packaging mechanical: 20-pin, tssop (l) 09-0084
7 ps8862l 05/01/09 pi6c10807 1.8v/2.5v, 250mhz, 1:10 networking clock buffer ordering information (1-3) ordering code package code package type PI6C10807LE l pb-free & green, 20-pin 173-mil wide tssop pi6c10807he h pb-free & green, 20-pin 209-mil wide ssop notes: 1. thermal characteristics can be found on the web at www.pericom.com/packaging/ 2. e = lead-free and green 3. adding an x suf x = tape/reel pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com 1 : 20-pin, 209-mil wide, ssop noitpircsed :edoc egakcap 1240 -dp :# lortnoc tnemucod e:noisiver 80/01/40 :etad h20 08-0140 packaging mechanical: 20-pin, ssop (h) 09-0084
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