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| logic devices incorporated www.logicdevices.com 1 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product ddr2 10.5mm x 12.5mm 84 ball fbga ddr2 10.5mm x 12.5mm 84 ball fbga ddr2 10.5mm x 12.5mm 84 ball fbga ddr2 10.5mm x 12.5mm 84 ball fbga ddr2 10.5mm x 12.5mm 84 ball fbga fast, low power, high density, wide word memory ddr2 25mm2 module [imod]: x 0 z r u g v x [ [ [ z r u g z l g w k v + l j k s h u i r u p d q f h x 0 e s v x 7 ( 0 3 ( 5 $ 7 8 5 ( & ? & w r ? & , ? & w r ? & ( ? & w r ? & 0 ? & w r ? & / r z s r z h u x 9 v x s s o \ x : d w w v p d [ 6 s d f h v d y l q j i r r w s u l q w x p p [ p p [ p d w u l [ z e d o o v p p s l w f k x p p o r z s u r i l o h k h l j k w features 7 k h u p d o o \ h q k d q f h g , p s h g d q f h p d w f k h g l q w h j u d w h g s d f n d j l q j ' l i i h u h q w l d o g d w d v w u r e h q e l w s u h i h w f k d u f k l w h f w x u h * e * e l q w h u q d o e d q n v 1 r p l q d o d q g g \ q d p l f r q g l h w h u p l q d - w l r q 2 ' 7 i r u g d w d v w u r e h d q g p d v n v l j q d o v 3 u r j u d p p d e o h & $ 6 o d w h q f \ & / d q g ) l [ h g e x u v w o h q j w k % / r i d q g e x u v w f k r s % & r i 6 h o h f w d e o h % & r u % / r q w k h i o \ 2 7 ) 6 h o i $ x w r 5 h i u h v k p r g h v x p v f \ f o h u h i u h v k 2 x w s x w ' u l y h u & d o l e u d w l r q $ g m x v w d e o h g u l y h v w u h q j w k 5 h g x f h g , 2 5 h g x f h g w u d f h o h q j w k v g x h w r w k h k l j k o \ l q w h j u d w h g l p s h g d q f h p d w f k h g s d f n d j l q j 7 k h u p d o o \ h q k d q f h g s d f n d j l q j w h f k q r o r j \ d o o r z v l o l f r q l q w h j u d w l r q z l w k r x w s h u i r u p d q f h g h j u d g d w l r q g x h w r s r z h u g l v v l s d w l r q k h d w + l j k 7 & ( r u j d q l f o d p l q d w h l q w h u - s r v h u i r u l p s u r y h g j o d v v v w d e l o l w \ r y h u d z l g h r s h u d w l q j w h p s h u d w x u h 6 x l w d e l o l w \ r i x v h l q + l j k 5 h o l d e l o l w \ d s s o l f d w l r q v u h t x l u l q j 0 l o w h p s q r q k h u p h w l f g h y l f h r s h u d w l r q 5 r + 6 f r p s o l d q w benefits l9d2xxmxxsbg5 product offerings: d ensity : * e * e * e * e * e * e d epth : 32m 32m 32m 0 0 0 p art n umber : l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 w ord w idths : [ [ [ [ [ [ ddr2 10.5mm x 12.5mm 84 ball fbga ddr2 10.5mm x 12.5mm 84 ball fbga ddr2 10.5mm x 12.5mm 84 ball fbga l9d2xxmxxsbg5 available timings: c lock : 0 + ] 0 + ] 0 + ] d ata r ate : 0 e v 0 e v 0 e v ddr2-800 ddr2-667 ddr2-533 c ycle t ime : q v q v q v integrated module products l9d264m80sbg5
gnd (core) gnd (i/o) data (i/o) v+ (core power) v+ (i/o power) unpopulated nc cntrl ref level address dnu vssdl vddl rfu dq0 dq14 dq15 vss vss a9 a10 a11 a8 vddq vddq dq16 dq17 dq31 vss a dq1 dq2 dq12 dq13 vss vss a0 a7 a6 a1 vdd vdd dq18 dq19 dq29 dq30 b dq3 dq4 dq10 dq11 vdd vdd a2 a5 a4 a3 vss vss dq20 dq21 dq27 dq28 c dq6 dq5 dq8 dq9 vddq vddq a12 nc vss nc vss vss dq22 dq23 dq26 dq25 d dq7 ldm0 vdd udm0 udqs3 ldqs0 udqs0 ba0 ba1 ldqs1 udqs1 vref ldm1 vss nc dq24 e cas0\ we0\ vdd \ 1 e w \ 1 s a r 3 s q d l 0 k l c vss udm1 clk1 f g 1 e k c \ 1 k l c s s v \ 1 s c \ 1 s a c \ 0 k l c 0 e k c d d v \ 0 s a r \ 0 s c h d d v q d d v s s v s s v dl d v sdl s v q d d v d d v s s v s s v j d d v q d d v s s v s s v d d v s s v q d d v d d v s s v s s v clk3\ cke3 vdd cs3\ clk2\ cke2 vss ras2\ cs2\ k nc clk3 vdd 2 k l c 2 s q d l \ 3 s a r \ 3 s a c vss we2\ cas2\ l dq56 udm3 vdd we3\ ldm3 udm2 vss ldm2 dq39 m dq57 dq58 dq55 dq54 udqs2 dq41 dq40 dq37 dq38 n p 5 3 q d 6 3 q d 2 4 q d 3 4 q d d d v d d v s s v s s v 2 5 q d 3 5 q d 9 5 q d 0 6 q d r 3 3 q d 4 3 q d 4 4 q d 5 4 q d s s v s s v d d v d d v 0 5 q d 1 5 q d 1 6 q d 2 6 q d t d d v 2 3 q d 6 4 q d 7 4 q d s s v s s v q d d v q d d v 8 4 q d 9 4 q d 3 6 q d s s v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq nc nc ldqs2\ odt nc nc ldqs3\ udqs3\ ldqs0\ udqs0\ dnu udqs1\ ldqs1\ nc nc nc dnu udqs2\ rfu nc rfu nc c n c n rfu vdd rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu logic devices incorporated www.logicdevices.com 2 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2.0 gb, ddr2, 32 m x 64 integrated memory module (imod) l9d232m64sbg5 high performance, integrated memory module product f igure 1a - sdram : ddr2 p inout t op v iew ball /signal location diagram: gnd (core) gnd (i/o) data (i/o) v+ (core power) v+ (i/o power) unpopulated nc cntrl ref level address dnu vssdl vddl rfu dq0 dq14 dq15 vss vss a9 a10 a11 a8 vddq vddq dq16 dq17 dq31 vss a dq1 dq2 dq12 dq13 vss vss a0 a7 a6 a1 vdd vdd dq18 dq19 dq29 dq30 b dq3 dq4 dq10 dq11 vdd vdd a2 a5 a4 a3 vss vss dq20 dq21 dq27 dq28 c dq6 dq5 dq8 dq9 vddq vddq a12 nc vss nc vss vss dq22 dq23 dq26 dq25 d dq7 ldm0 vdd udm0 udqs3 ldqs0 udqs0 ba0 ba1 ldqs1 udqs1 vref ldm1 vss nc dq24 e cas0\ we0\ vdd \ 1 e w \ 1 s a r 3 s q d l 0 k l c vss udm1 clk1 f g 1 e k c \ 1 k l c s s v \ 1 s c \ 1 s a c \ 0 k l c 0 e k c d d v \ 0 s a r \ 0 s c h d d v q d d v s s v s s v dl d v sdl s v q d d v d d v s s v s s v j d d v q d d v s s v s s v d d v s s v q d d v d d v s s v s s v clk3\ cke3 vdd cs3\ ldqs4 clk2\ cke2 vss ras2\ cs2\ k nc clk3 vdd cas3\ ras3\ ldqs2 clk2 vss we2\ cas2\ l dq56 udm3 vdd we3\ ldm3 cke4 clk4 cas4\ we4\ ras4\ cs4\ udm2 vss ldm2 dq39 m dq57 dq58 dq55 dq54 udqs4 clk4\ dq71 dq70 ldm4 udqs2 dq41 dq40 dq37 dq38 n dq60 dq59 dq53 dq52 vss vss dq69 dq68 vdd vdd dq43 dq42 dq36 dq35 p dq62 dq61 dq51 dq50 vdd vdd dq67 dq66 vss vss dq45 dq44 dq34 dq33 r vss dq63 dq49 dq48 vddq vddq dq65 dq64 vss vss dq47 dq46 dq32 vdd t 12345678910111213141516 a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq ldqs4\ nc nc ldqs2\ rfu rfu rfu rfu rfu rfu rfu rfu odt udqs4\ nc nc ldqs3\ udqs3\ ldqs0\ udqs0\ dnu udqs1\ ldqs1\ nc nc nc dnu udqs2\ nc f igure 1b - sdram : ddr2 p inout t op v iew ball /signal location diagram: logic devices incorporated www.logicdevices.com 3 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2.2 gb, ddr2, 32 m x 72 integrated memory module (imod) l9d232m72sbg5 high performance, integrated memory module product dq0 dq14 dq15 vss vss a9 a10 a11 a8 dq1 dq2 dq12 dq13 vss vss a0 a7 a6 a1 vdd vdd dq18 dq1 dq29 dq30 b dq3 dq4 dq10 dq11 vdd vdd a2 a5 a4 a3 vss vss dq20 dq21 dq27 dq28 c dq6 dq5 dq8 dq9 vddq vddq nc vss vss dq22 dq23 dq26 dq25 d dq7 ldm0 vdd udm0 udqs3 ldqs0 udqs0 ba0 ba1 ldqs1 udqs1 vref ldm1 vss nc dq24 e cas0\ we0\ vdd \ 1 e w \ 1 s a r 3 s q d l 0 k l c vss udm1 clk1 f g 1 e k c \ 1 k l c s s v \ 1 s c \ 1 s a c \ 0 k l c 0 e k c d d v \ 0 s a r \ 0 s c h d d v q d d v s s v s s v dl d v q d d v d d v s s v s s v j d d v q d d v s s v s s v d d v s s v q d d v d d v s s v s s v k \ 2 s c \ 2 s a r s s v 2 e k c \ 2 k l c 4 s q d l \ 3 s c d d v 3 e k c \ 3 k l c nc clk3 vdd 2 k l c 2 s q d l \ 3 s a r \ 3 s a c vss we2\ cas2\ l dq56 udm3 vdd we3\ ldm3 cke4 udm4 clk4 cas4\ we4\ ras4\ cs4\ udm2 vss ldm2 dq39 m dq57 dq58 dq55 dq54 udqs4 clk4\ dq73 dq72 dq71 dq70 ldm4 udqs2 dq41 dq40 dq37 dq38 n dq60 dq59 dq53 dq52 vss vss dq75 dq74 dq69 dq68 vdd vdd dq43 dq42 dq36 dq35 p dq62 dq61 dq51 dq50 vdd vdd dq77 dq76 dq67 dq66 vss vss dq45 dq44 dq34 dq33 r vss dq63 dq49 dq48 dq79 dq78 dq65 dq64 vss vss dq47 dq46 dq32 vdd t 12345678910111213141516 a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq ldqs4\ nc nc ldqs2\ odt udqs4\ nc nc ldqs3\ udqs3\ ldqs0\ udqs0\ dnu udqs1\ ldqs1\ nc nc nc dnu udqs2\ a12 vssdl vddq vddq dq16 dq17 dq31 vss a vddq vddq vss nc gnd (core) gnd (i/o) data (i/o) v+ (core power) v+ (i/o power) unpopulated nc cntrl ref level address dnu vssdl vddl f igure 1c - sdram : ddr2 p inout t op v iew ball /signal location diagram: logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2.5 gb, ddr2, 32 m x 80 integrated memory module (imod) L9D232M80SBG5 high performance, integrated memory module product gnd (core) gnd (i/o) data (i/o) v+ (core power) v+ (i/o power) unpopulated nc cntrl ref level address dnu vssdl vddl dq0 dq14 dq15 vss vss a9 a10 a11 a8 vddq vddq dq16 dq17 dq31 vss a dq1 dq2 dq12 dq13 vss vss a0 a7 a6 a1 vdd vdd dq18 dq19 dq29 dq30 b dq3 dq4 dq10 dq11 vdd vdd a2 a5 a4 a3 vss vss dq20 dq21 dq27 dq28 c dq6 dq5 dq8 dq9 vddq vddq a12 nc ba2 nc vss vss dq22 dq23 dq26 dq25 d dq7 ldm0 vdd udm0 udqs3 ldqs0 udqs0 ba0 ba1 ldqs1 udqs1 vref ldm1 vss nc dq24 e cas0\ we0\ vdd \ 1 e w \ 1 s a r 3 s q d l 0 k l c vss udm1 clk1 f g 1 e k c \ 1 k l c s s v \ 1 s c \ 1 s a c \ 0 k l c 0 e k c d d v \ 0 s a r \ 0 s c h d d v q d d v s s v s s v dl d v sdl s v q d d v d d v s s v s s v j d d v q d d v s s v s s v d d v s s v q d d v d d v s s v s s v clk3\ cke3 vdd cs3\ clk2\ cke2 vss ras2\ cs2\ k nc clk3 vdd 2 k l c 2 s q d l \ 3 s a r \ 3 s a c vss we2\ cas2\ l dq56 udm3 vdd we3\ ldm3 udm2 vss ldm2 dq39 m dq57 dq58 dq55 dq54 udqs2 dq41 dq40 dq37 dq38 n p 5 3 q d 6 3 q d 2 4 q d 3 4 q d d d v d d v s s v s s v 2 5 q d 3 5 q d 9 5 q d 0 6 q d r 3 3 q d 4 3 q d 4 4 q d 5 4 q d s s v s s v d d v d d v 0 5 q d 1 5 q d 1 6 q d 2 6 q d t d d v 2 3 q d 6 4 q d 7 4 q d s s v s s v q d d v q d d v 8 4 q d 9 4 q d 3 6 q d s s v 1 2 3 4 5 6 7 8 9 10111213141516 a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq nc nc ldqs2\ rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu odt nc nc ldqs3\ udqs3\ ldqs0\ udqs0\ dnu udqs1\ ldqs1\ nc nc nc dnu udqs2\ rfu nc rfu nc rfu c n c n rfu rfu rfu rfu rfu vdd rfu rfu rfu rfu rfu f igure 1d- sdram : ddr2 p inout t op v iew ball /signal location diagram: logic devices incorporated www.logicdevices.com 5 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 4.0 gb, ddr2, 64 m x 64 integrated memory module (imod) l9d264m64sbg5 high performance, integrated memory module product gnd (core) gnd (i/o) data (i/o) v+ (core power) v+ (i/o power) unpopulated nc cntrl ref level address dnu vssdl vddl rfu dq0 dq14 dq15 vss vss a9 a10 a11 a8 vddq vddq dq16 dq17 dq31 vss a dq1 dq2 dq12 dq13 vss vss a0 a7 a6 a1 vdd vdd dq18 dq19 dq29 dq30 b dq3 dq4 dq10 dq11 vdd vdd a2 a5 a4 a3 vss vss dq20 dq21 dq27 dq28 c dq6 dq5 dq8 dq9 vddq vddq a12 nc ba2 nc vss vss dq22 dq23 dq26 dq25 d dq7 ldm0 vdd udm0 udqs3 ldqs0 udqs0 ba0 ba1 ldqs1 udqs1 vref ldm1 vss nc dq24 e cas0\ we0\ vdd \ 1 e w \ 1 s a r 3 s q d l 0 k l c vss udm1 clk1 f g 1 e k c \ 1 k l c s s v \ 1 s c \ 1 s a c \ 0 k l c 0 e k c d d v \ 0 s a r \ 0 s c h d d v q d d v s s v s s v dl d v sdl s v q d d v d d v s s v s s v j d d v q d d v s s v s s v d d v s s v q d d v d d v s s v s s v clk3\ cke3 vdd cs3\ ldqs4 clk2\ cke2 vss ras2\ cs2\ k nc clk3 vdd cas3\ ras3\ ldqs2 clk2 vss we2\ cas2\ l dq56 udm3 vdd we3\ ldm3 cke4 clk4 cas4\ we4\ ras4\ cs4\ udm2 vss ldm2 dq39 m dq57 dq58 dq55 dq54 udqs4 clk4\ dq71 dq70 ldm4 udqs2 dq41 dq40 dq37 dq38 n dq60 dq59 dq53 dq52 vss vss dq69 dq68 vdd vdd dq43 dq42 dq36 dq35 p dq62 dq61 dq51 dq50 vdd vdd dq67 dq66 vss vss dq45 dq44 dq34 dq33 r vss dq63 dq49 dq48 vddq vddq dq65 dq64 vss vss dq47 dq46 dq32 vdd t 1 2 3 4 5 6 7 8 9 10111213141516 a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq ldqs4\ nc nc ldqs2\ rfu rfu rfu rfu rfu rfu rfu rfu odt udqs4\ nc nc ldqs3\ udqs3\ ldqs0\ udqs0\ dnu udqs1\ ldqs1\ nc nc nc dnu udqs2\ vdd f igure 1e- sdram : ddr2 p inout t op v iew ball /signal location diagram: logic devices incorporated www.logicdevices.com 6 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 4.5 gb, ddr2, 64 m x 72 integrated memory module (imod) l9d264m72sbg5 high performance, integrated memory module product gnd (core) gnd (i/o) data (i/o) v+ (core power) v+ (i/o power) unpopulated nc cntrl ref level address dnu vssdl vddl dq0 dq14 dq15 vss vss a9 a10 a11 a8 dq1 dq2 dq12 dq13 vss vss a0 a7 a6 a1 vdd vdd dq18 dq19 dq29 dq30 b dq3 dq4 dq10 dq11 vdd vdd a2 a5 a4 a3 vss vss dq20 dq21 dq27 dq28 c dq6 dq5 dq8 dq9 vddq vddq nc ba2 nc vss vss dq22 dq23 dq26 dq25 d dq7 ldm0 vdd udm0 udqs3 ldqs0 udqs0 ba0 ba1 ldqs1 udqs1 vref ldm1 vss nc dq24 e cas0\ we0\ vdd \ 1 e w \ 1 s a r 3 s q d l 0 k l c vss udm1 clk1 f g 1 e k c \ 1 k l c s s v \ 1 s c \ 1 s a c \ 0 k l c 0 e k c d d v \ 0 s a r \ 0 s c h d d v q d d v s s v s s v dl d v q d d v d d v s s v s s v j d d v q d d v s s v s s v d d v s s v q d d v d d v s s v s s v k \ 2 s c \ 2 s a r s s v 2 e k c \ 2 k l c 4 s q d l \ 3 s c d d v 3 e k c \ 3 k l c nc clk3 vdd 2 k l c 2 s q d l \ 3 s a r \ 3 s a c vss we2\ cas2\ l dq56 udm3 vdd we3\ ldm3 cke4 udm4 clk4 cas4\ we4\ ras4\ cs4\ udm2 vss ldm2 dq39 m dq57 dq58 dq55 dq54 udqs4 clk4\ dq73 dq72 dq71 dq70 ldm4 udqs2 dq41 dq40 dq37 dq38 n dq60 dq59 dq53 dq52 vss vss dq75 dq74 dq69 dq68 vdd vdd dq43 dq42 dq36 dq35 p dq62 dq61 dq51 dq50 vdd vdd dq77 dq76 dq67 dq66 vss vss dq45 dq44 dq34 dq33 r vss dq63 dq49 dq48 dq79 dq78 dq65 dq64 vss vss dq47 dq46 dq32 vdd t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq ldqs4\ nc nc ldqs2\ odt udqs4\ nc nc ldqs3\ udqs3\ ldqs0\ udqs0\ dnu udqs1\ ldqs1\ nc nc nc dnu udqs2\ a12 vssdl vddq vddq dq16 dq17 dq31 vss a vddq vddq f igure 1f- sdram : ddr2 p inout t op v iew ball /signal location diagram: logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 5.0 gb, ddr2, 64 m x 80 integrated memory module (imod) l9d264m80sbg5 high performance, integrated memory module product logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product t able 1: p in /b all l ocations and d escriptions ball assignments symbol type description l6 ) * ) * l13, k12, l2, k1 0 1 * * . k2, m6 g1, g13, k16 . 0 g2, f12, k15 l5, m11 f1, g12, l16 / 0 f2, f13, l15 0 0 ( ) 0 0 0 e2, e13 m15, m5, n11 ( ( n12, e5 n5 ) ) l11, f6 k6 e6, e10 l12, f5 k5 ) ) l10, g6 / % % & & & & % % $ $ $ $ ' ' ' ' ( ( > ' @ e12 b11,b12,c5,c6,e3,f3, g3,h3,h16,j3,j12, - . / 0 3 3 5 5 7 $ $ ' ' + + - - 7 7 $ $ $ % % & & ' ' ( ) * + + + + - - - - - . / 0 3 3 5 2 ' 7 clk0, clk0\, clk1, ck1\ clk2, clk2\, clk3, clk3\ & / . & / . ? cke0, cke1, cke2 & . ( & . ( cs0\, cs1\, cs2\ & 6 ? & 6 ? 5 $ 6 ? 5 $ 6 ? 5 $ 6 ? 5 $ 6 ? 5 $ 6 ? & $ 6 ? & $ 6 ? & $ 6 ? & $ 6 ? & $ 6 ? : ( ? : ( ? : ( ? : ( ? : ( ? 8 ' 0 8 ' 0 8 ' 0 8 ' 0 8 ' 0 ldm0, ldm1 / ' 0 / ' 0 / ' 0 8 ' 4 6 8 ' 4 6 8 ' 4 6 8 ' 4 6 8 ' 4 6 8 ' 4 6 ? 8 ' 4 6 ? 8 ' 4 6 ? 8 ' 4 6 ? 8 ' 4 6 ? / ' 4 6 / ' 4 6 / ' 4 6 / ' 4 6 / ' 4 6 / ' 4 6 ? / ' 4 6 ? / ' 4 6 ? / ' 4 6 ? / ' 4 6 ? $ $ $ $ $ $ $ $ $ $ $ $ $ 5 ) 8 % $ % $ > % $ @ 9 u h i 9 dd 9 dd 4 9 v v on-die termination: 5 h j l v w h u h g + l j k h q d e o h v r q g d w d e x v w h u p l q d w l r q ' l i i h u h q w l d o l q s x w f o r f n v r q h v h w i r u h d f k [ e l w v & o r f n h q d e o h z k l f k d f w l y d w h v d o o r q v l o l f r q f o r f n l q j f l u f x l w & k l s 6 h o h f w v r q h i r u h d f k e l w v r i w k h g d w d e x v z l g w k & r p p d q g l q s x w z k l f k d o r q j z l w k & $ 6 ? : ( ? d q g & 6 ? g h i l q h r s h u d w l r q v & r p p d q g l q s x w z k l f k d o r q j z l w k 5 $ 6 ? : ( ? d q g & 6 ? g h i l q h r s h u d w l r q v & r p p d q g l q s x w z k l f k d o r q j z l w k 5 $ 6 ? & $ 6 ? d q g & 6 ? g h i l q h r s h u d w l r q v 2 q h ' d w d 0 d v n f q w o i r u h d f k x s s h u e l w v r i d [ z r u g 2 q h ' d w d 0 d v n f q w o i r u h d f k o r z h u e l w v r i d [ z r u g ' d w d 6 w u r e h l q s x w i r u x s s h u e \ w h r i h d f k [ z r u g ' l i i h u h q w l d o l q s x w r i 8 ' 4 6 [ r q o \ x v h g z k h q ' l i i h u h q w l d o ' 4 6 p r g h l v h q d e o h g ' d w d 6 w u r e h l q s x w i r u o r z h u e \ w h r i h d f k [ z r u g ' l i i h u h q w l d o l q s x w r i / ' 4 6 [ r q o \ x v h g z k h q ' l i i h u h q w l d o ' 4 6 p r g h l v h q d e o h g $ u u d \ $ g g u h v v l q s x w v s u r y l g l q j 5 2 : d g g u h v v h v i r u $ f w l y h f r p p d q g v d q g w k h f r o x p q d g g u h v v d q g d x w r s u h f k d u j h e l w $ i r u 5 ( $ ' : 5 , 7 ( f r p p d q g v ) x w x u h $ g g u h v v % d q n $ g g u h v v l q s x w v % d q n $ g g u h v v l q s x w v % $ r q * e r q o \ 6 6 7 / b 9 r o w d j h 5 h i h u h q f h 3 r z h u 6 x s s o \ , 2 3 r z h u 6 x s s o \ * u r x q g u h w x u q cntl input cntl input cntl input cntl input cntl input cntl input cntl input cntl input cntl input cntl input cntl input cntl input cntl input input future input input supply supply supply supply logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 9 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 9 v v 4 9 6 6 ' / 9 ' ' / d0, d1, d2, d3 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' d20, d21, d22, d23 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' d60, d61, d62, d63 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' nc do not use unpopulated supply supply supply input/output t able 1: p in /b all l ocations and d escriptions c ontinued ball assignments symbol type description 5 7 7 7 * * * * + + + + - - - - . . . . h5 h12 $ % % & & ' ' ( ' ' & & % % $ $ $ $ % % & & ' ' e16,d16,d15,c15 & % % $ 7 5 5 3 3 1 1 0 1 1 3 3 5 5 7 7 7 7 5 5 3 3 1 1 0 1 1 3 3 5 5 7 7 7 5 5 3 3 1 1 1 1 3 3 5 5 7 7 e15,g11,h6,h11,j6, - / / / f9,k11 $ , 2 * u r x q g u h w x u q ' / / 3 r z h u ' / / * u r x q g ' d w d e l g l u h f w l r q d o l q s x w 2 x w s x w s l q v 1 r f r q q h f w l r q 5 ( 6 ( 5 9 ( ' ) 2 5 6 3 ( & , $ / & 2 1 6 , ' ( 5 $ 7 , 2 1 3 , 1 6 8 q s r s x o d w h g e d o o p d w u l [ o r f d w l r q o r f d w l r q u h j l v w u d w l r q d l g logic devices incorporated www.logicdevices.com 10 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2.0 gb, ddr2, 32 m x 64 integrated memory module (imod) l9d232m64sbg5 high performance, integrated memory module product d0 512mb aba vref odt vdd vddq vss vssq dq 0 dq 7 dq 8 dq 15 dq 0 dq 7 dq 8 dq 15 cs0\ cke0 clk0 clk0\ ras0\ cas0\ we0\ ldqs0 ldqs0\ udqs0 udqs0\ ldm0 udm0 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm vssq vss vddq vdd odt vref a0-a12, ba0-1 a d2 512mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 32 ! ! ! dq 39 dq 40 ! ! ! dq 47 cs2\ cke2 clk2 clk2\ ras2\ cas2\ we2\ ldqs2 ldqs2\ udqs2 udqs2\ ldm2 udm2 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d1 512mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 16 ! ! ! dq 23 dq 24 ! ! ! dq 31 cs1\ cke1 clk1 clk1\ ras1\ cas1\ we1\ ldqs1 ldqs1\ udqs1 udqs1\ ldm1 udm1 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d3 512mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 48 ! ! ! dq 55 dq 56 ! ! ! dq 63 cs3\ cke3 clk3 clk3\ ras3\ cas3\ we3\ ldqs3 ldqs3\ udqs3 udqs3\ ldm3 udm3 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm a f igure 2a - f unctional b lock d iagram logic devices incorporated www.logicdevices.com 11 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2.2 gb, ddr2, 32 m x 72 integrated memory module (imod) l9d232m72sbg5 high performance, integrated memory module product 1. d0 512mb aba vref odt vdd vddq vss vssq dq 0 dq 7 dq 8 dq 15 dq 0 dq 7 dq 8 dq 15 cs0\ cke0 clk0 clk0\ ras0\ cas0\ we0\ ldqs0 ldqs0\ udqs0 udqs0\ ldm0 udm0 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm vssq vss vddq vdd odt vref a0-a12, ba0-1 a d2 512mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 32 ! ! ! dq 39 dq 40 ! ! ! dq 47 cs2\ cke2 clk2 clk2\ ras2\ cas2\ we2\ ldqs2 ldqs2\ udqs2 udqs2\ ldm2 udm2 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d1 512mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 16 ! ! ! dq 23 dq 24 ! ! ! dq 31 cs1\ cke1 clk1 clk1\ ras1\ cas1\ we1\ ldqs1 ldqs1\ udqs1 udqs1\ ldm1 udm1 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d3 512mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 48 ! ! ! dq 55 dq 56 ! ! ! dq 63 cs3\ cke3 clk3 clk3\ ras3\ cas3\ we3\ ldqs3 ldqs3\ udqs3 udqs3\ ldm3 udm3 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d4 256mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 64 ! ! ! dq 71 cs4\ cke4 clk4 clk4\ ras4\ cas4\ we4\ ldqs4 ldqs4\ udqs4 udqs4\ ldm4 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm a a f igure 2b - f unctional b lock d iagram logic devices incorporated www.logicdevices.com 12 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2.5 gb, ddr2, 32 m x 80 integrated memory module (imod) L9D232M80SBG5 high performance, integrated memory module product d0 512mb aba vref odt vdd vddq vss vssq dq 0 dq 7 dq 8 dq 15 dq 0 dq 7 dq 8 dq 15 cs0\ cke0 clk0 clk0\ ras0\ cas0\ we0\ ldqs0 ldqs0\ udqs0 udqs0\ ldm0 udm0 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm vssq vss vddq vdd odt vref a0-a12, ba0-1 a d2 512mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 32 ! ! ! dq 39 dq 40 ! ! ! dq 47 cs2\ cke2 clk2 clk2\ ras2\ cas2\ we2\ ldqs2 ldqs2\ udqs2 udqs2\ ldm2 udm2 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d1 512mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 16 ! ! ! dq 23 dq 24 ! ! ! dq 31 cs1\ cke1 clk1 clk1\ ras1\ cas1\ we1\ ldqs1 ldqs1\ udqs1 udqs1\ ldm1 udm1 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d3 512mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 48 ! ! ! dq 55 dq 56 ! ! ! dq 63 cs3\ cke3 clk3 clk3\ ras3\ cas3\ we3\ ldqs3 ldqs3\ udqs3 udqs3\ ldm3 udm3 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d4 512mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 64 ! ! ! dq 71 dq 72 ! ! ! dq 79 cs4\ cke4 clk4 clk4\ ras4\ cas4\ we4\ ldqs4 ldqs4\ udqs4 udqs4\ ldm4 udm4 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm a a f igure 2c - f unctional b lock d iagram logic devices incorporated www.logicdevices.com 13 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 4.0 gb, ddr2, 64 m x 64 integrated memory module (imod) l9d264m64sbg5 high performance, integrated memory module product d0 1024mb aba vref odt vdd vddq vss vssq dq 0 dq 7 dq 8 dq 15 dq 0 dq 7 dq 8 dq 15 cs0\ cke0 clk0 clk0\ ras0\ cas0\ we0\ ldqs0 ldqs0\ udqs0 udqs0\ ldm0 udm0 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm vssq vss vddq vdd odt vref a0-a12, ba0-2 a d2 1024mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 32 ! ! ! dq 39 dq 40 ! ! ! dq 47 cs2\ cke2 clk2 clk2\ ras2\ cas2\ we2\ ldqs2 ldqs2\ udqs2 udqs2\ ldm2 udm2 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d1 1024mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 16 ! ! ! dq 23 dq 24 ! ! ! dq 31 cs1\ cke1 clk1 clk1\ ras1\ cas1\ we1\ ldqs1 ldqs1\ udqs1 udqs1\ ldm1 udm1 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d3 1024mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 48 ! ! ! dq 55 dq 56 ! ! ! dq 63 cs3\ cke3 clk3 clk3\ ras3\ cas3\ we3\ ldqs3 ldqs3\ udqs3 udqs3\ ldm3 udm3 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm a f igure 2d - f unctional b lock d iagram logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 4.5 gb, ddr2, 64 m x 72 integrated memory module (imod) l9d264m72sbg5 high performance, integrated memory module product d0 1024mb aba vref odt vdd vddq vss vssq dq 0 dq 7 dq 8 dq 15 dq 0 dq 7 dq 8 dq 15 cs0\ cke0 clk0 clk0\ ras0\ cas0\ we0\ ldqs0 ldqs0\ udqs0 udqs0\ ldm0 udm0 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm vssq vss vddq vdd odt vref a0-a12, ba0-2 a d2 1024mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 32 ! ! ! dq 39 dq 40 ! ! ! dq 47 cs2\ cke2 clk2 clk2\ ras2\ cas2\ we2\ ldqs2 ldqs2\ udqs2 udqs2\ ldm2 udm2 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d1 1024mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 16 ! ! ! dq 23 dq 24 ! ! ! dq 31 cs1\ cke1 clk1 clk1\ ras1\ cas1\ we1\ ldqs1 ldqs1\ udqs1 udqs1\ ldm1 udm1 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d3 1024mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 48 ! ! ! dq 55 dq 56 ! ! ! dq 63 cs3\ cke3 clk3 clk3\ ras3\ cas3\ we3\ ldqs3 ldqs3\ udqs3 udqs3\ ldm3 udm3 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d4 512mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 64 ! ! ! dq 71 cs4\ cke4 clk4 clk4\ ras4\ cas4\ we4\ ldqs4 ldqs4\ udqs4 udqs4\ ldm4 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm a a f igure 2e - f unctional b lock d iagram logic devices incorporated www.logicdevices.com 15 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 5.0 gb, ddr2, 64 m x 80 integrated memory module (imod) l9d264m80sbg5 high performance, integrated memory module product d0 1024mb aba vref odt vdd vddq vss vssq dq 0 dq 7 dq 8 dq 15 dq 0 dq 7 dq 8 dq 15 cs0\ cke0 clk0 clk0\ ras0\ cas0\ we0\ ldqs0 ldqs0\ udqs0 udqs0\ ldm0 udm0 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm vssq vss vddq vdd odt vref a0-a12, ba0-2 a d2 1024mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 32 ! ! ! dq 39 dq 40 ! ! ! dq 47 cs2\ cke2 clk2 clk2\ ras2\ cas2\ we2\ ldqs2 ldqs2\ udqs2 udqs2\ ldm2 udm2 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d1 1024mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 16 ! ! ! dq 23 dq 24 ! ! ! dq 31 cs1\ cke1 clk1 clk1\ ras1\ cas1\ we1\ ldqs1 ldqs1\ udqs1 udqs1\ ldm1 udm1 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d3 1024mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 48 ! ! ! dq 55 dq 56 ! ! ! dq 63 cs3\ cke3 clk3 clk3\ ras3\ cas3\ we3\ ldqs3 ldqs3\ udqs3 udqs3\ ldm3 udm3 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm d4 1024mb aba vref odt vdd vddq vss vssq dq 0 ! ! ! dq 7 dq 8 ! ! ! dq 15 dq 64 ! ! ! dq 71 dq 72 ! ! ! dq 79 cs4\ cke4 clk4 clk4\ ras4\ cas4\ we4\ ldqs4 ldqs4\ udqs4 udqs4\ ldm4 udm4 cs\ cke ck ck\ ras\ cas\ we\ ldqs ldqs\ udqs udqs\ ldm udm a a f igure 2f - f unctional b lock d iagram logic devices incorporated www.logicdevices.com 16 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product command decode control logic mode registers cke ck ck# cs# ras# cas# we# odt refresh counter row- address mux row- address latch and decoder bank 1 bank 2 bank 3 13 sense amplifiers 64 bank control logic column decoder 8 2 column- address counter/ latch 2 address register a0-a12 ba0-ba1 16 13 10 16 13 8,192 16,384 3 i/o gating dm mask logic udm, ldm udqs, udqs# ldqs, ldqs# dq0-dq15 256 (x64) bank 1 bank 2 bank 3 memory array (8,192 x 256 x 64) sense amplifier bank 0 bank 0 64 read latch 16 16 16 16 mux col0, col1 16 drvrs dll ck, ck# dqs generator 4 data udqs, udqs# ldqs, ldqs# 64 write fifo and drivers ck out ck in ck, ck# 8 input registers 64 data 16 16 16 16 2 2 2 2 16 16 16 16 2 2 2 2 2 16 rcvrs 4 odt control sw1 sw2 sw3 sw1 v dd q sw2 sw3 r1 r2 r3 r1 r2 r3 sw1 sw2 sw3 r1 r2 r3 r1 r2 r3 sw1 sw2 sw3 r1 r2 r3 r1 r2 r3 v ss q col0, col1 f igure 2g - 32 m eg x 16 i nternal d ie c onfiguration f unctional b lock d iagram logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product command decode control logic mode registers cke ck ck# cs# ras# cas# we# odt refresh counter row- address mux row- address latch and decoder bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 13 sense amplifiers 64 bank control logic column decoder 8 2 column- address counter/ latch 2 address register a0-a12 ba0-ba2 16 13 10 16 13 8,192 16,384 3 i/o gating dm mask logic udm, ldm udqs, udqs# ldqs, ldqs# dq0-dq15 256 (x64) bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 memory array (8,192 x 256 x 64) sense amplifier bank 0 bank 0 64 read latch 16 16 16 16 mux col0, col1 16 drvrs dll ck, ck# dqs generator 4 data udqs, udqs# ldqs, ldqs# 64 write fifo and drivers ck out ck in ck, ck# 8 input registers 64 data 16 16 16 16 2 2 2 2 16 16 16 16 2 2 2 2 2 16 rcvrs 4 odt control sw1 sw2 sw3 sw1 v dd q sw2 sw3 r1 r2 r3 r1 r2 r3 sw1 sw2 sw3 r1 r2 r3 r1 r2 r3 sw1 sw2 sw3 r1 r2 r3 r1 r2 r3 v ss q col0, col1 f igure 2h - 64 m eg x 16 i nternal d ie c onfiguration f unctional b lock d iagram logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product command decode control logic mode registers cke ck ck# cs# ras# cas# we# odt refresh counter row- address mux row- address latch and decoder bank 1 bank 2 bank 3 14 sense amplifiers 32 bank control logic column decoder 8 2 column- address counter/ latch 2 address register a0-a12 ba0-ba1 17 14 10 17 14 16,384 8,192 3 i/o gating dm mask logic dm dqs, dqs# dq0-dq7 256 (x32) bank 1 bank 2 bank 3 memory array (16,384 x 256 x 32) sense amplifier bank 0 bank 0 32 read latch 8 8 8 8 mux col0, col1 8 drvrs dll ck, ck# dqs generator 2 data udqs, udqs# ldqs, ldqs# 32 write fifo and drivers ck out ck in ck, ck# 4 input registers 32 data 8 8 8 8 2 2 2 2 8 8 8 8 2 2 2 2 2 8 rcvrs 2 odt control sw1 sw2 sw3 sw1 v dd q sw2 sw3 r1 r2 r3 r1 r2 r3 sw1 sw2 sw3 r1 r2 r3 r1 r2 r3 sw1 sw2 sw3 r1 r2 r3 r1 r2 r3 v ss q col0, col1 rdqs rdqs# f igure 2i - 64 m eg x 8 i nternal d ie c onfiguration f unctional b lock d iagram logic devices incorporated www.logicdevices.com 19 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product command decode control logic mode registers cke ck ck# cs# ras# cas# we# odt refresh counter row- address mux row- address latch and decoder bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 14 sense amplifiers 32 bank control logic column decoder 8 2 column- address counter/ latch 2 address register a0-a12 ba0-ba2 17 14 10 17 14 16,384 8,192 3 i/o gating dm mask logic dm dqs, dqs# dq0-dq7 256 (x32) bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 memory array (16,384 x 256 x 32) sense amplifier bank 0 bank 0 32 read latch 8 8 8 8 mux col0, col1 8 drvrs dll ck, ck# dqs generator 2 data udqs, udqs# ldqs, ldqs# 32 write fifo and drivers ck out ck in ck, ck# 4 input registers 32 data 8 8 8 8 2 2 2 2 8 8 8 8 2 2 2 2 2 8 rcvrs 2 odt control sw1 sw2 sw3 sw1 v dd q sw2 sw3 r1 r2 r3 r1 r2 r3 sw1 sw2 sw3 r1 r2 r3 r1 r2 r3 sw1 sw2 sw3 r1 r2 r3 r1 r2 r3 v ss q col0, col1 rdqs rdqs# f igure 2j - 128 m eg x 8 i nternal d ie c onfiguration f unctional b lock d iagram c = commercial & r p p h u f l d o f o d v v l q w h j u d w h g f r p s r q h q w i x o o \ d f u r v v ? & w r ? & i = industrial , q g x v w u l d o f o d v v l q w h j u d w h g f r p s r q h q w i x o o \ d f u r v v ? & w r ? & e = extended ( [ w h q g h g f o d v v l q w h j u d w h g f r p s r q h q w r s h u d e o h d f u r v v ? & w r ? & m = mil-temp 0 l o 7 h p s h u d w x u h r q o \ f o d v v l q w h j u d w h g f r p s r q h q w r s h u d e o h d f u r v v ? & w r ? & logic devices incorporated www.logicdevices.com 20 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product features & r q i l j x u d w l r q 5 h i u h v k & r x q w 5 2 : $ g g u h v v l q j % d f n $ g g u h v v l q j & r o x p q $ g g u h v v l q j > 0 h j [ e d q n v [ @ [ l 0 2 ' . . $ > @ % $ > @ % $ > @ . $ > @ ldi imod addressing t able 2: a ddressing 25 3 q v q v q v 533 533 533 ldi part number speed grade t ck avg t able 3: k ey p arameters cl=3 cl=4 cl=5 cl=6 data rate [mbps] l9d2xxmxxsbg5[c, i, e, m]25 l9d2xxmxxsbg5[c, i, e, m]3 / ' [ [ 0 [ [ 6 % * > & , ( 0 @ sample part number: l9d2xxmxxsbg5 core frequency mhz 333 400 38 3 25 l9d2 note: not all options can be combined. please see our part catalog for available offerings. bg5 logic ddr2 integrated module 25 x 25 x 1.7mm 255 ball array clk temperature commercial (0 o c to 70 o c) industrial (-40 o c to 85 o c) extended (-40 o c to 105 o c) c i e code m military (-55 o c to 125 o c) temp speed data rate mbs 667 800 word = 32m 64m xxm xxs wordwidth = x64 x72 x80 s= single channel 267 533 features f igure 3 - ddr2 p art n umbers logic devices incorporated www.logicdevices.com 21 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product logic devices incorporated www.logicdevices.com 22 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product functional description general description 7 k h / 2 * , & ' h y l f h v * e ' ' 5 6 ' 5 $ 0 , q w h j u d w h g 0 h p r u \ 0 r g x o h , 0 2 ' d u h v l [ p h p e h u v r i r x u , q w h j u d w h g 0 r g x o h i d p l o \ 7 k l v i d p l o \ r i , q w h j u d w h g p h p r u \ p r g x o h v f r q w d l q v ' ' 5 ' ' 5 d q g i x w x u h ' ' 5 g h y l f h g h i l q l w l r q v 7 k l v ' ' 5 s u r g x f w g h i l q l w l r q l v s d f n d j h g l q d p p [ p p y e d o o 3 % * $ i r r w s u l q w z l w k d p p e d o o s l w f k 7 k l v g h y l f h d k l j k v s h h g & 0 2 6 u d q g r p d f f h v v l q w h j u d w h g p h p r u \ g h y l f h e d v h g r q x v h r i v l o l f r q g h y l f h v h d f k f r q w d l q l q j 0 e l w v ( d f k f k l s l v l q w h u q d o o \ f r q i l j x u h g d v d q e d q n 6 ' 5 $ 0 ( d f k r i w k h f k l s v e l w e d q n v l v r u j d q l ] h g d v u r z v e \ f r o x p q v 7 k h * e ' ' 5 l 0 2 ' x v h v w k h g r x e o h g d w d u d w h ' ' 5 d u f k l w h f w x u h w r d f k l h y h k l j k v s h h g r s h u d w l r q 7 k h g r x e o h g d w d u d w h d u f k l w h f w x u h l v d q s u h i h w f k d u f k l w h f w x u h z l w k d q l q w h u i d f h g h v l j q h g w r w u d q v i h u w z r g d w d z r u g v s h u f o r f n f \ f o h y l d w k h , 2 s l q v $ v l q j o h 5 ( $ ' r u : 5 , 7 ( d f f h v v i r u w k h * e ' ' 5 l 0 2 ' h i i h f w l y h o \ f r q v l v w v r i d v l q j o h q e l w z l g h r q h f o r f n f \ f o h w u d q v i h u $ e l g l u h f w l r q d o g d w d v w u r e h r q h s h u x s s h u d q g o r z h u e \ w h / ' 4 6 [ / ' 4 6 [ ? 8 ' 4 6 [ d q g 8 ' 4 6 [ ? l v w u d q v p l w w h g h [ w h u q d o o \ d o r q j z l w k g d w d i r u x v h l q g d w d f d s w x u h d w w k h h q g s r l q w u h f h l y h u ' d w d 6 w u r e h v d u h w u d q v p l w w h g e \ w k h ' ' 5 6 ' 5 $ 0 g x u l q j 5 ( $ ' r s h u d w l r q v d q g e \ w k h p h p r u \ f r q w u r o o h u g x u l q j : 5 , 7 ( r s h u d w l r q v ( d f k v w u r e h f r q w u r o v h d f k r i w z r e \ w h v f r q w d l q h g z l w k l q h d f k r i w k h v l o l f r q f k l s v f r q w d l q h g l q / ' , u v , 0 2 ' 7 k h * e ' ' 5 6 ' 5 $ 0 r s h u d w h g i u r p d g l i i h u h q w l d o f o r f n & / . [ & / . [ ? w k h f u r v v l q j r i & / . [ j r l q j + , * + d q g & / . [ ? j r l q j / 2 : z l o o e h u h i h u u h g w r d v w k h s r v l w l y h h g j h r i & / . & r p p d q g v d g g u h v v d q g f r q w u r o v l j q d o v d u h u h j l v w h u h g d w h y h u \ s r v l w l y h h g j h r i & / . , q s x w g d w d l v u h j l v - w h u h g r q e r w k h g j h v r i [ ' 4 6 d q g r x w s x w g d w d l v u h i h u h q f h g w r e r w k h g j h v r i [ ' 4 6 d v z h o o d v w r e r w k h g j h v r i & / . 5 ( $ ' d q g : 5 , 7 ( d f f h v v h v w r w k h ' ' 5 p h p r u \ d u h e x u v w r u l h q w h g d f f h v v h v v w d u w d w d v h o h f w h g o r f d - w l r q d q g f r q w l q x h i r u d s u r j u d p p h g q x p e h u r i o r f d w l r q v l q d s u r j u d p p h g v h t x h q f h $ f f h v v h v e h j l q z l w k w k h u h j l v w u d w l r q r i d q $ & 7 , 9 ( f r p p d q g z k l f k l v w k h q i r o o r z h g e \ d 5 ( $ ' r u : 5 , 7 ( f r p p d q g 7 k h d g g u h v v e l w v u h j l v w h u h g f r l q f l g h q w z l w k w k h 5 ( $ ' r u : 5 , 7 ( f r p p d q g d u h x v h g w r v h o h f w w k h e d q n d q g w k h v w d u w l q j f r o x p q o r f d w l r q i r u w k h e x u v w d f f h v v 7 k h ' ' 5 6 ' 5 $ 0 s u r y l g h v i r u s u r j u d p p d e o h 5 ( $ ' r u : 5 , 7 ( e x u v w o h q j w k v r i i r x u r u h l j k w o r f d w l r q v ' ' 5 6 ' 5 $ 0 v v x s s r u w i r u l q w h u - u x s w l q j d % 8 5 6 7 5 ( $ ' r i h l j k w z l w k d q r w k h u 5 ( $ ' r u % 8 5 6 7 : 5 , 7 ( r i h l j k w w k h q d q r w k h u : 5 , 7 ( $ q $ 8 7 2 3 5 ( & + $ 5 * ( i x q f w l r q p d \ e h h q d e o h g w r s u r y l g h 6 ( / ) 7 , 0 ( ' u r z 3 5 ( & + $ 5 * ( w k d w l v l q l w l d w h g d w w k h h q g r i w k h e x u v w d f f h v v 7 k h s l s h o l q h g p x o w l e d q n h g d u f k l w h f w x u h r i w k h ' ' 5 6 ' 5 $ 0 d u f k l w h f w x u h d o o r z v i r u f r q f x u u h q w r s h u d w l r q v w k h u h i r u h s u r y l g l q j k l j k h i i h f w l y h e d q g - z l g w k e \ k l g l q j u r z 3 5 ( & + $ 5 * ( d q g d f w l y d w l r q w l p h general notes x 7 k h i x q f w l r q d o l w \ d q g w k h w l p l q j o l v w h g l q / ' , u v / ' [ [ * [ [ % * g d w d v k h h w d u h i r u w k h ' / / h q d e o h g p r g h r i r s h u d w l r q x 7 k u r x j k r x w w k h g d w d v k h h w w k h y d u l r x v i l j x u h v d q g w h [ w u h i h u w r ' 4 ' 4 [ [ d v v ' 4 w 7 k h ' 4 w h u p l v w r e h l q w h u s u h w h g d v d q \ r u d o o r i w k h v > @ > @ w ' 4 o l q h v s u h v h q w l q w k l v s u r g x f w g h i l q l w l r q x , q i h u h q f h w r f r p s o h w h i x q f w l r q d o l w \ l v g h v f u l e h g w k u r x j k r x w w k l v g r f x p h q w $ q \ s d j h r u g l v f x v v l r q z l w k l q d s d j h p d \ k d y h e h h q v l p s o l i l h g w r f r q y h \ v w k h w w r s l f d q g p d \ q r w e h l q f o x v l y h r i d o o u h t x l u h p h q w v e \ e l w v ( d f k r i w k h 6 l o l f r q g h y l f h v f r q w d l q h g l q / 2 * , & u v l 0 2 ' g h y l f h h t x d w h v w r d : 2 5 ' r u ' 8 $ / % < 7 ( 6 h d f k % < 7 ( f r q w d l q l q j ' d w d 0 d v n d q g ' d w d 6 w u r e h v 7 k l v p r g x o h u v f r q w u r o v w u x f w x u h l v g h i l q h g z l w k h d f k r i w k h v l o l f r q g l h l q w h u q d o w r w k h l 0 2 ' k d y l q j & 6 ? & . ( & / . & / . ? 5 $ 6 ? & $ 6 ? d q g : ( d v z h o o d v w k h ' d w d 0 d v n d q g 6 w u r e h f r q w u r o e x v i r u w k h , 2 7 k h v h f r q w u r o v d u h / ' 4 6 / ' 4 6 ? 8 ' 4 6 8 ' 4 6 ? / ' 0 d q g 8 ' 0 logic devices incorporated www.logicdevices.com 23 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product bank active reading writing activating refreshing self refresh idle active power- down zq calibration from any state power applied reset procedure power on initialization mrs, mpr, write leveling preharge power- down writing automatic sequence command sequence preharging read read read read ap read ap read ap pre, prea pre, prea pre, prea write write cke l cke l cke l write write ap write ap write ap pde pde pdx pdx srx sre ref mrs act reset zqcl zqcl/zqcs reading act = activate prea=precharge all srx = self refresh exit mpr = multipurpose register read = rd, rds4, rds8 write = wr, wrs4, wrs8 mrs = mode register set read ap = rdap, rdaps4, rdaps8 write ap = wrap, wraps4, wraps8 pde = power-down entry ref = refresh zqcl = zq long calibration pdx = power-down exit reset = start reset procedure zqcs = zq short calibration pre = precharge sre = self refresh entry state diagram f igure 4 - s implified s tate d iagram 1 r w h $ o o g l p h q v l r q v l q p p l9d264m80sbg5 255 x 0.75 nom 25 0.1 0.6 0.1 2.975 nom 25 0.1 1.2 max 19.05 nom 1.27 nom 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t r p n m l k j h g f e d c b a 1.27 nom 2.975 nom 2.975 nom 2.975 nom logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 5 - m echanical d rawing logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 25 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product symbol parameter min max uni t 9 dd 9 in 9 2 8 7 7 6 7 * 7 & $ 6 ( i i i 4 = i 9 5 ( ) 9 9 c c ? $ ? $ ? $ ? $ ? $ t able 4: a bsolute m aximum dc r atings -5 -5 9 r o w d j h r q 9 dd s l q u h o d w l y h w r 9 v v 9 r o w d j h r q d q \ s l q u h o d w l y h w r 9 v v 6 w r u d j h 7 h p s h u d w x u h ' h y l f h 2 s h u d w l q j 7 h p s h u d w x u h , q s x w / h d n d j h f x u u h q w $ q \ l q s x w 9 9 in 9 dd 9 ref l q s x w 9 9 in 9 2 w k h u s l q v q r w x q g h u w h v w 9 & 0 ' $ ' 5 5 $ 6 ? & $ 6 ? : ( ? & 6 ? & . ( ck, ck\ dm 5 5 p ackage o utline d imensions parameter symbol min typ max units 6 x s s o \ 9 r o w d j h , 2 5 h i h u h q f h 9 r o w d j h , 2 7 h u p l q d w l r q 9 r o w d j h t able 5: r ecommended dc o perating c onditions [ 9 dd 9 5 ( ) ' & 9 9 9 9 dd 9 5 ( ) ' & 9 7 7 [ 9 dd 9 5 ( ) ' & [ 9 dd 9 5 ( ) ' & 1 2 7 ( 6 / ' , u v ' ' 5 3 % * $ l 0 2 ' l q w h u q d o o \ w l h v 9 dd d q g 9 dd 4 w r j h w k h u d v z h o o d v 9 v v d q g 9 v v 4 9 ref l v h [ s h f w h g w r h t x d o 9 dd r i w k h w u d q v p l w w l q j g h y l f h d q g w r w u d f n y d u l d w l r q v l q w k h ' & o h y h o r i w k h v d p h 3 h d n w r 3 h d n y d u l d w l r q v l q w k h ' & o h y h o r i w k h v d p h 3 h d n w r 3 h d n q r l v h q r q f r p p r q p r g h r q 9 ref p d \ q r w h [ f h h g ? s h u f h q w r i w k h ' & y d o x h 3 h d n w r 3 h d n $ & q r l v h r q 9 ref p d \ q r w h [ f h h g ? s h u f h q w r i 9 ref ' & 7 k l v p h d v x u h p h q w l v w r e h w d n h q d w w k h q h d u h v w 9 ref e \ s d v v f d s d f l w r u 9 7 7 l v q r w d s s o l h g g l u h f w o \ w r w k h g h y l f h 9 7 7 l v d v \ v w h p v x s s o \ i r u v l j q d o w h u p l q d w l r q u h v l v w r u v l v h [ s h f w h g w r e h v h w h t x d o w r 9 ref , d q g p x v w w u d f n y d u l d w l r q v l q w k h ' & o h y h o r i 9 ref logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 26 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product i dd parameters cl (i dd t rcd (i dd t rc (i dd trrd (i dd t ck (i dd t 5 $ 6 , dd t 5 3 , dd t rfc (i dd t ) $ : , dd t able 7: g eneral i dd p arameters t ck q v q v q v q v q v q v q v q v 5 15 60 10 3 15 105 25 800mbps 3 667mbps 6 15 60 10 15 105 units 25 3 $ 0 5 $ 0 ' ' $ 1 5 $ 1 ' ' $ 2 5 $ 2 ' ' $ 3 5 $ 3 d d d d d d d d d d $ 0 5 $ 0 ' ' $ 1 5 $ 1 ' ' $ 2 5 $ 2 ' ' $ 3 5 $ 3 d d d d d d speed grade t able 8: i dd7 t iming p atterns (4 - b ank interleave read o peration ) i dd7 timing patterns p ackage o utline d imensions parameter symbol min typ max units notes , q s x w f d s d f l w d q f h & . [ d q g & . [ ? , q s x w f d s d f l w d q f h $ [ % $ [ 2 ' 7 , q s x w 2 x w s x w f d s d f l w d q f h ' 4 [ / ' 4 6 [ / ' 4 6 [ ? 8 ' 4 6 [ 8 ' 4 6 [ ? / ' 0 [ 8 ' 0 [ & 6 [ ? 5 $ 6 [ ? & $ 6 [ ? : ( [ ? & . ( [ t able 6: i nput , i nput /o utput c apacitance c ck c i c io 30 1 1 1 1 2 7 ( 6 7 k l v s d u d p h w h u l v v d p s o h g 9 dd 9 ? 9 9 dd 4 9 dd l q w h u q d o o \ w l h g 9 ref 9 v v i 0 + ] 7 f ? & 9 2 8 7 ' & 9 dd 9 r x w s h d n w r s h d n 9 [ ' 0 [ l q s x w l v j u r x s h g z l w k , 2 e d o o v u h i o h f w l q j w k h i d f w w k d w w k h \ d u h p d w f k h g l q o r d g l q j 7 k h f d s d f l w d q f h s h u e d o o j u r x s z l o o q r w g l i i h u e \ p r u h w k d q w k l v p d [ l p x p d p r x q w i r u d q \ j l y h q l 0 2 ' g h y l f h 20 25 pf pf pf logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product t able 9: ddr2 i dd s pecifications and c onditions parameter t cl= t ck(i dd t rc= t rc(i dd t 5 $ 6 t 5 $ 6 0 , 1 , dd & . ( l v + , * + & 6 ? l v + , * + e h w z h h q y d o l g f r p p d q g v $ g g u h v v e x v v z l w f k l q j ' d w d e x v v z l w f k l q j i 2 8 7 p d % / & / & / i dd $ / t ck = t ck(i dd t rc t rc(i dd t 5 $ 6 t 5 $ 6 min(i dd t rcd= t rcd(i dd & . ( l v + , * + & 6 ? l v + , * + e h w z h h q y d o l g f r p - p d q g v $ g g u h v v e x v l v v z l w f k l q j ' d w d e x v l v v z l w f k l q j $ o o e d q n v l g o h t ck- t ck(i dd & . ( l v / 2 : 2 w k h u f r q w u r o d q g d g g u h v v e x v l q s x w v d u h v w d e o h ' d w d e x v l q s x w v d u h i o r d w l q j $ o o e d q n v l g o h t ck= t ck(i dd & . ( l v + , * + & 6 ? l v + , * + 2 w k h u f r q w u r o d q g d g g u h v v e x v l q s x w v d u h v w d e o h ' d w d e x v l q s x w v d u h i o r d w l q j $ o o e d q n v l g o h t ck-= t ck(i dd & . ( l v + , * + & 6 ? l v + , * + 2 w k h u f r q w u r o d q g d g g u h v v e x v l q s x w v d u h v z l w f k l q j ' d w d e x v l q s x w v d u h v z l w f k l q j $ o o e d q n v r s h q t ck= t ck(i dd t 5 $ 6 0 $ ; , dd t 5 3 t 5 3 , dd & . ( l v + , * + & 6 ? l v + , * + e h w z h h q y d o l g f r p p d q g v 2 w k h u f r q w u r o d q g d g g u h v v e x v l q s x w v d u h v z l w f k l q j ' d w d e x v l q s x w v d u h v z l w f k l q j $ o o e d q n v r s h q f r q w l q x r x v e x u v w z u l w h v % / & / & / , dd t 5 3 t 5 3 , dd & . ( l v + , * + & 6 ? l v + , * + e h w z h h q y d o l g f r p p d q g v $ g g u h v v e x v l q s x w v d u h v z l w f k l q j ' d w d e x v l q s x w v d u h v z l w f k l q j $ o o e d q n v r s h q f r q w l q x r x v e x u v w 5 ( $ ' 6 , r x w p $ % / & / & / i dd $ / t cl= t ck(i dd t 5 $ 6 t 5 $ 6 0 $ ; i dd t 5 3 t 5 3 i dd & . ( l v + , * + cs\ l v + , * + e w z y d o l g f r p p d q g v $ g g u h v v d q g ' d w d e x v l q s x w v v z l w f k l q j t ck= t ck(i dd u h i u h v k f r p p d q g d w h y h u \ t rfc(i dd l q w h u y d o & . ( l v + , * + & 6 ? l v + , * + e w z y d o l g f r p p d q g v 2 w k h u f r q w u r o $ g g u h v v d q g ' d w d e x v l q s x w v d u h v z l w f k l q j & . d q g & . ? d w 9 & . ( d 9 2 w k h u f r q w u r o d g g u h v v d q g g d w d l q s x w v d u h i o r d w l q j $ o o e d q n l q w h u o h d y l q j 5 ( $ ' 6 , 2 8 7 p $ % / & / & / , dd $ / t rcd(i dd 1x t ck(i dd t ck= t ck(i dd t rc= t rc(i dd t rrd= t rrd(i dd & . ( l v + , * + & 6 ? l v + , * + e h w z h h q y d o l g f r p p d q g v $ g g u h v v e x v l q s x w v d u h v w d e o h g x u l q j g h v h o h f w v ' d w d e x v l q s x w v d u h v z l w f k l q j 2 s h u d w l q j & x u u h q w 2 q h e d q n d f w l y h s u h f k d u j h symbol 0 e s v 25 0 e s v 3 mrs[12]=0 mrs[12]=1 idd0 idd1 , ' ' 3 , ' ' 4 idd2n , ' ' 3 idd3n , ' ' : , ' ' 5 idd5 idd6 idd6l , ' ' 35 130 150 100 50 35 25 1300 35 130 130 50 160 625 35 25 1150 units p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ 3 u h f k d u j h 6 7 $ 1 ' % < f x u u h q w 3 u h f k d u j h t x l h w 6 7 $ 1 ' % < f x u u h q w 3 u h f k d u j h 3 2 : ( 5 ' 2 : 1 f x u u h q w 2 s h u d w l q j & x u u h q w 2 q h e d q n d f w l y h 5 ( $ ' s u h f k d u j h f x u u h q w $ f w l y h 3 2 : ( 5 ' 2 : 1 f x u u h q w $ f w l y h 6 7 $ 1 ' % < f x u u h q w 2 s h u d w l q j % x u v w : 5 , 7 ( f x u u h q w 2 s h u d w l q j % x u v w 5 ( $ ' f x u u h q w % x u v w 5 ( ) 5 ( 6 + f x u u h q w 6 h o i 5 ( ) 5 ( 6 + f x u u h q w 2 s h u d w l q j e d q n , q w h u o h d y h 5 ( $ ' f x u u h q w logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 3 -125 -125 -250 -350 - - 100 300 300 125 125 250 350 - - - - [i] 25 0 + ] 0 e s v [i, e, m] 3 0 + ] 0 e s v parameter symbol min max min max units notes & o r f n & \ f o h 7 l p h & o r f n + l j k 7 l p h & o r f n / r z 7 l p h + d o i & o r f n 3 h u l r g $ e v r o x w h t ck $ e v r o x w h t & . k l j k o h y h o z l g w k $ e v r o x w h t & . o r z o h y h o z l g w k & o r f n - l w w h u 3 h u l r g & o r f n - l w w h u + d o i 3 h u l r g & o r f n - l w w h u & \ f o h w r & \ f o h & x p x o d w l y h - l w w h u h u u r u f \ f o h v & x p x o d w l y h - l w w h u h u u r u f \ f o h v & x p x o d w l y h - l w w h u h u u r u f \ f o h v & x p x o d w l y h - l w w h u h u u r u f \ f o h v ' 4 6 r x w s x w d f f h v v w l p h i u r p & . & . ? ' 4 6 5 ( $ ' s u h d p e o h ' 4 6 5 ( $ ' s r v w d p e o h ' 4 6 / r z = z l q g r z i u r p & . & . ? 3 r v l w l y h ' 4 6 o d w f k l q j h g j h w r d v v r f & o r f n h g j h ' 4 6 l q s x w k l j k s x o v h z l g w k ' 4 6 l q s x w o r z s x o v h z l g w k ' 4 6 i d o o l q j h g j h w r & . u l v l q j v h w x s w l p h ' 4 6 i d o o l q j h g j h i u r p & . u l v l q j k r o g w l p h : 5 , 7 ( s u h d p e o h v h w x s w l p h ' 4 6 : 5 , 7 ( s u h d p e o h ' 4 6 : 5 , 7 ( s r v w d p e o h : 5 , 7 ( f r p p d q g w r i l u v w ' 4 6 o d w f k l q j w u d q v l w l r q ' 4 r x w s x w d f f h v v w l p h i u r p & . & . ? ' 4 6 ' 4 v n h z ' 4 6 w r o d v w ' 4 y d o l g s h u j u r x s s h u d f f h v v ' 4 k r o g i u r p q h [ w ' 4 6 v w u r e h ' 4 ' 4 6 + r o g ' 4 6 w r i l u v w ' 4 w r j r q r q y d o l g s h u d f f h v v ' d w d r x w + l j k = z l q g r z i u r p & . & . ? ' 4 / r z = z l q g r z i u r p & . & . ? ' d w d y d o l g r x w s x w z l q g r z ' 9 : ' 4 d q g ' 0 l q s x w v h w x s w l p h u h o d w l y h w r ' 4 6 ' 4 d q g ' 0 l q s x w k r o g w l p h u h o d w l y h w r ' 4 6 ' 4 d q g ' 0 l q s x w v h w x s w l p h u h o d w l y h w r ' 4 6 ' 4 d q g ' 0 l q s x w k r o g w l p h u h o d w l y h w r ' 4 6 ' 4 d q g ' 0 l q s x w s x o v h z l g w k i r u h d f k l q s x w cl=6 cl=5 & / t ck $ 9 * t ck $ 9 * t ck $ 9 * t ch $ 9 * t cl $ 9 * t + 3 t ck d e v t ch d e v t cl d e v t - , 7 3 ( 5 t - , 7 ' 7 < t - , 7 cc t err 3 ( 5 t err 3 ( 5 t err 3 ( 5 t err 3 ( 5 t ' 4 6 & . t 5 3 5 ( t 5 3 6 7 t / = t ' 4 6 6 t ' 4 6 + t ' 4 6 / t dss t dsh t : 3 5 ( 6 t : 3 5 ( t : 3 6 7 - t $ & t ' 4 6 4 t 4 + 6 t 4 + t + = t / = t ' 9 : t ds b t dh b t ds $ t dh $ t ' , 3 : data-in data-out data strobe-in strobe-out clock jitter clock d ata 3 -100 -100 -150 -200 -300 -350 - - 50 125 250 250 100 100 150 200 300 350 200 300 - - - - q v t ck s v s v s v s v s v s v s v s v s v s v s v s v t ck t ck s v t ck t ck t ck t ck t ck s v t ck t ck t ck s v s v s v s v s v s v s v s v s v s v s v t ck 6-9 10 11 12 13 15 15 15,16 15 19 19,21,22 19 19,21,29 19,21,22 26,30,31 26,30,31 26,30,31 26,30,31 0 , 1 / h v v h u r i t & + d q g t & / 0 $ ; q d min = t & . $ 9 * 0 , 1 t - , 7 3 ( 5 0 , 1 0 $ ; t & . $ 9 * 0 $ ; t - , 7 3 ( 5 0 $ ; min = t & . $ 9 * 0 , 1 [ t & + $ 9 * 0 , 1 t - , 7 3 ( 5 0 , 1 0 $ ; t & . $ 9 * 0 $ ; [ t & + $ 9 * 0 $ ; t - , 7 ' 7 < 0 $ ; min = t & . $ 9 * 0 , 1 [ t & + $ 9 * 0 , 1 t - , 7 3 ( 5 0 , 1 0 $ ; t & . $ 9 * 0 $ ; [ t & + $ 9 * 0 $ ; t - , 7 ' 7 < 0 $ ; 200 250 0 , 1 [ t & . 0 $ ; [ t ck 0 , 1 [ t & . 0 $ ; [ t ck min = t $ & 0 , 1 0 $ ; t $ & 0 $ ; 0 , 1 [ t & . 0 $ ; [ t ck 0 , 1 [ t & . 0 $ ; q d 0 , 1 [ t & . 0 $ ; q d 0 , 1 [ t & . 0 $ ; q d 0 , 1 [ t & . 0 $ ; q d 0 , 1 0 $ ; q d 0 , 1 [ t & . 0 $ ; q d 0 , 1 [ t & . 0 $ ; [ t ck 0 , 1 : / t ' 4 6 6 0 $ ; : / t ' 4 6 6 min = t + 3 t 4 + 6 0 $ ; q d 0 , 1 q d 0 $ ; t $ & 0 $ ; min = 2 x t $ & 0 , 1 0 $ ; t $ & 0 $ ; min = t 4 + t ' 4 6 4 0 $ ; q d 0 , 1 [ t & . 0 $ ; q d units notes t able 10: ac t iming s pecifications logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 29 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product min limit = t 5 ) & 0 , 1 0 $ ; o l p l w q d 0 , 1 o l p l w 0 $ ; o l p l w q d min limit = t , 6 0 $ ; o l p l w q d 2 min limit = t $ & 0 , 1 0 $ ; o l p l w t $ & 0 $ ; min limit = t $ & 0 , 1 0 $ ; o l p l w [ t & . t $ & 0 $ ; min limit = t $ & 0 , 1 0 $ ; o l p l w [ t & . t $ & 0 $ ; t able 10: ac t iming s pecifications c ontinued [i] 25 0 + ] 0 e s v [i, e, m] 3 0 + ] 0 e s v parameter symbol min max min max units notes $ g g u h v v d q g & r q w u r o l q s x w s x o v h z l g w k i r u h d f k l q s x w $ g g u h v v d q g & r q w u r o l q s x w v h w x s w l p h $ g g u h v v d q g & r q w u r o l q s x w k r o g w l p h $ g g u h v v d q g & r q w u r o l q s x w v h w x s w l p h $ g g u h v v d q g & r q w u r o l q s x w k r o g w l p h & $ 6 ? w r & $ 6 ? f r p p d q g g h o d \ $ & 7 , 9 ( w r $ & 7 , 9 ( f r p p d q g v d p h e d q n $ & 7 , 9 ( e d q n d w r $ & 7 , 9 ( e d q n e & r p p d q g $ & 7 , 9 ( w r 5 ( $ ' r u : 5 , 7 ( g h o d \ % d q n d f w l y d w h s h u l r g $ & 7 , 9 ( w r 3 5 ( & + $ 5 * ( , q w h u q d o 5 ( $ ' w r 3 5 ( & + $ 5 * ( f r p p d q g g h o d \ : 5 , 7 ( u h f r y h u \ w l p h $ x w r 3 5 ( & + $ 5 * ( : 5 , 7 ( u h f r y h u \ 3 5 ( & + $ 5 * ( w l p h , q w h u q d o : 5 , 7 ( w r 5 ( $ ' f r p p d q g g h o d \ 3 5 ( & + $ 5 * ( f r p p d q g s h u l r g 3 5 ( & + $ 5 * ( $ / / f r p p d q g s h u l r g / 2 $ ' 0 2 ' ( f r p p d q g & \ f o h w l p h & . ( / 2 : w r & . & . ? x q f h u w d l q w \ 5 ( ) 5 ( 6 + w r $ & 7 , 9 ( r u 5 ( ) 5 ( 6 + w r 5 ( ) 5 ( 6 + f r p p d q g l q w h u y d o $ y h u d j h s h u l r g l f 5 ( ) 5 ( 6 + l q w h u y d o > l q g x v w u l d o w h p s @ $ y h u d j h s h u l r g l f 5 ( ) 5 ( 6 + l q w h u y d o > h [ w h q g h g w h p s @ $ y h u d j h s h u l r g l f 5 ( ) 5 ( 6 + l q w h u y d o > p l o l w d u \ w h p s @ ( [ l w 6 ( / ) 5 ( ) 5 ( 6 + w r 1 2 1 5 ( $ ' f r p p d q g ( [ l w 6 ( / ) 5 ( ) 5 ( 6 + w r 5 ( $ ' f r p p d q g ( [ l w 6 ( / ) 5 ( ) 5 ( 6 + w l p l q j u h i h u h q f h 2 ' 7 w x u q r q g h o d \ 2 ' 7 w x u q r q g h o d \ 2 ' 7 w x u q r i i g h o d \ 2 ' 7 w x u q r i i g h o d \ 2 ' 7 w x u q r q s r z h u g r z q p r g h 2 ' 7 w x u q r i i s r z h u g r z q p r g h 2 ' 7 w r s r z h u g r z q h q w u \ o d w h q f \ 2 ' 7 w r s r z h u g r z q h [ l w o d w h q f \ 2 ' 7 h q d e o h i u r p 0 5 6 f r p p d q g ( [ l w d f w l y h 3 2 : ( 5 ' 2 : 1 w r 5 ( $ ' f r p p d q g 0 5 > @ ( [ l w d f w l y h 3 2 : ( 5 ' 2 : 1 w r 5 ( $ ' f r p p d q g 0 5 > @ ( [ l w 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 w r d q \ q r q 5 ( $ ' & . ( 0 l q + , * + / 2 : w l p h t , 3 : t is b t ih b t is $ t ih $ t ccd t rc t rrd t rcd t ) $ : t 5 $ 6 t 5 7 3 t : 5 t ' $ / t : 7 5 t 5 3 t 5 3 $ t mrd t ' ( / $ < t rfc t ref[i] t ref[e] t ref[m] t ; 6 1 5 t ; 6 5 ' t , 6 ; 5 t $ 2 1 ' t $ 2 1 t $ 2 3 ' t $ 2 ) t $ 2 1 3 ' t $ 2 ) 3 ' t $ 1 3 ' t $ ; 3 ' t mod t ; $ 5 ' t ; $ 5 ' t ; 3 v cke pwr-dn odt s. refresh refresh command and address 250 2 55 10 15 15 15 2 - - - t $ & 0 , 1 3 10 12 2 $ / 2 3 - - - - - - - - - - - - - - - - - t $ & 0 $ ; - - - - - - - 200 2 55 10 15 50 15 15 2 - - - t $ & 0 , 1 3 12 2 $ / 2 3 - - - - - - - - - - - - - - - - - t $ & 0 $ ; - - - - - - - t ck s v s v s v s v t ck q v t ck q v q v q v q v q v q v q v q v q v t ck q v q v ? v ? v ? v q v t ck s v t ck s v t ck s v s v s v t ck t ck q v t ck t ck t ck t ck 31,33 31,33 31,33 31,33 min = t : 5 t 5 3 0 $ ; q d min limit = t , 6 t & . t , + 0 $ ; o l p l w q d logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 30 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product n otes $ o o y r o w d j h v d u h u h i h u h q f h g w r 9 v v 7 h v w v i r u $ & w l p l q j , dd d q g h o h f w u l f d o $ & d q g ' & f k d u d f w h u l v w l f v p d \ e h f r q g x f w h g d w q r p l q d o u h i h u h q f h v x s s o \ y r o w d j h o h y h o v e x w w k h u h o d w h g v s h f l i l f d w l r q v d q g w k h r s h u d w l r q r i w k h g h y l f h d u h z d u u d q w h g i r u w k h i x o o y r o w d j h u d q j h v s h f l i l h g 2 ' 7 l v g l v d e o h g i r u d o o p h d v x u h p h q w v w k d w d u h q r w 2 ' 7 v s h f l i l f 2 x w s x w v p h d v x u h g z l w k h t x l y d o h q w o r d g $ & w l p l q j d q g , dd w h v w v p d \ x v h d 9 il w r 9 ih v z l q j r i x s w r 9 l q w k h w h v w h q y l u r q p h q w d q g s d u d p h w h u v s h f l i l f d w l r q v d u h j x d u d q w h h g i r u w k h v s h f l i l h g $ & l q s x w o h y h o v x q g h u q r u p d o x v h f r q g l w l r q v 7 k h v o h z u d w h i r u w k h l q s x w v l j q d o v x v h g w r w h v w w k h g h y l f h l v 9 q v i r u v l j q d o v l q w k h u d q j h e h w z h h q 9 il $ & d q g 9 ih $ & 6 o h z u d w h v r w k h u w k d q 9 q v p d \ u h t x l u h w k h w l p l q j s d u d p h w h u v w r e h g h u d w h g d v v s h f l i l h g 7 k h $ & d q g ' & l q s x w o h y h o v s h f l i l f d w l r q v d u h d v g h i l q h g l q w k h 6 6 7 / b v w d q g d u g & . d q g & . ? l q s x w v o h z u d w h l v u h i h u h q f h g d w 9 q v 9 q v l i p h d v x u h g g l i i h u h q w l d o o \ 2 s h u d w l q j i u h t x h q f \ l v r q o \ d o o r z h g w r f k d q j h g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + p r g h 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 p r g h r u 6 < 6 7 ( 0 5 ( 6 ( 7 f r q - g l w l r q 6 6 & d o o r z v i r u v p d o o g h y l d w l r q v l q r s h u d w l q j i u h t x h q f \ s u r y l g h g w k h 6 6 & j x l g h o l q h v d u h v d w l v i l h g 7 k h & o r f n u v t & . $ 9 * l v w k h d y h u d j h f o r f n r y h u d q \ f r q v h f x w l y h f o r f n v d q g t & . $ 9 * 0 , 1 l v w k h v p d o o h v w f o r f n u d w h d o o r z h g h [ f h s w i r u d g h y l d w l r q g x h w r d o o r z h g f o r f n m l w w h u , q s x w f o r f n m l w w h u l v d o o r z h g s u r y l g h g l w g r h v q r w h [ f h h g y d o x h v v s h f l i l h g $ o v r w k h m l w w h u p x v w e h r i d u d q g r p * d x v v l d q g l v w u l e x w l r q l q q d w x u h 6 s u h d g v s h f w u x p l v q r w l q f o x g h g l q w k h m l w w h u v s h f l i l f d w l r q y d o x h v + r z - h y h u w k h l q s x w f o r f n f d q d f f r p p r g d w h v s u h d g v s h f w u x p d w d v z h h s u d w h l q w k h u d q j h r i n + ] z l w k d q d g g l w l r q d o r q s h u f h q w t & . $ 9 * k r z h y h u w k h v s u h d g v s h f w u x p p d \ q r w x v h d f o r f n u d w h e h o r z t & . $ 9 * 0 , 1 r u d e r y h t & . $ 9 * 0 $ ; min ( t cl, t & + u h i h u v w r w k h v p d o o h u r i w k h d f w x d o f o r f n / 2 : w l p h d q g w k h d f w x d o f o r f n + , * + w l p h g u l y h q w r w k h g h y l f h 7 k h f o r f n u v k d o i s h u l r g p x v w d o v r e h r i d * d x v v l d q g l v w u l e x w l r q t & + $ 9 * d q g t & / $ 9 * p x v w e h p h w z l w k r u z l w k r x w f o r f n m l w w h u d q g z l w k r u z l w k r x w g x w \ f \ f o h m l w w h u t & + $ 9 * d q g t & / $ 9 * d u h w k h d y h u d j h r i d q \ f r q v h f x w l y h & . i d o o l q j h g j h v t & + o l p l w v p d \ e h h [ f h h g h g l i w k h g x w \ f \ f o h m l w w h u l v v p d o o h q r x j k w k d w w k h d e v r o x w h k d o i s h u l r g o l p l w v t & + > $ % 6 @ t & / > $ % 6 @ d u h q r w y l r o d w h g t + 3 0 , 1 l v w k h o h v v h u r i t & / d q g w & + d f w x d o o \ d s s o l h g w r w k h g h y l f h & . d q g & . ? l q s x w v w k x v t + 3 0 , 1 t w k h o h v v h u r i t & / $ % 6 0 , 1 d q g t & + $ % 6 0 , 1 7 k h s h u l r g m l w w h u t - , 7 3 ( 5 l v w k h p d [ l p x p g h y l d w l r q l q w k h f o r f n s h u l r g i u r p w k h d y h u d j h r u q r p l q d o f o r f n d o o r z h g l q h l w k h u w k h s r v l w l y h r u q h j d - w l y h g l u h f w l r q - ( ' ( & v s h f l i l h v w l j k w h u m l w w h u q x p e h u v g x u l q j ' / / o r f n l q j w l p h ' x u l q j ' / / o r f n w l p h w k h m l w w h u y d o x h v v k r x o g e h s h u f h q w o h v v w k d q w k r v h q r w h g w k h 7 d e o h w l w o h g v ' / / / 2 & . ( ' w 7 k h k d o i s h u l r g m l w w h u t - , 7 ' 7 < d s s o l h v w r h l w k h u w k h k l j k s x o v h r i f o r f n r u w k h o r z s x o v h r i w k h f o r f n k r z h y h u w k h w z r f x p x o d w l y h o \ f d q q r w h [ f h h g t - , 7 3 ( 5 7 k h f \ f o h w r f \ f o h m l w w h u t - , 7 f f l v w k h d p r x q w r i w k h f o r f n s h u l r g w k d w f d q g h y l d w h i u r p r q h f \ f o h w r w k h q h [ w - ( ' ( & v s h f l i l h v w l j k w h u m l w w h u q x p e h u v g x u l q j ' / / / r f n l q j w l p h ' x u l q j ' / / o r f n w l p h w k h m l w w h u y d o x h v v k r x o g e h s h u f h q w o h v v w k d q w k r v h q r w h g l q w k h w d e o h q d p h g v ' / / / 2 & . ( ' w 7 k h f x p x o d w l y h m l w w h u h u u r u t err 1 3 ( 5 z k h u h q l v r u l v w k h d p r x q w r i f o r f n w l p h d o o r z h g w r f r q v h f x w l y h o \ d f f x p x o d w h d z d \ i u r p w k h d y h u d j h f o r f n r y h u d q \ q x p e h u r i f o r f n f \ f o h v - ( ' ( & v s h f l i l h v x v l q j t err 3 ( 5 z k h q g h u d w l q j f o r f n u h o d w h g r x w s x w w l p l q j v h h q r w h v d q g / ' , u h t x l u h v o h v v g h u d w l q j r q l w u v l 0 2 ' e \ d o o r z l q j t err 3 ( 5 w r e h x v h g 7 k l v s d u d p h w h u l v q r w u h i h u h q f h g w r d v s h f l i l f y r o w d j h o h y h o e x w l v v s h f l - i l h g z k h q w k h g h y l f h l v q r o r q j h u g u l y l q j t 5 3 6 7 r u e h j l q q l q j w r g u l y h ( t 5 3 5 ( 7 k h l q s x w v w r w k h ' ' 5 6 ' 5 $ 0 p x v w e h d o l j q h g w r w k h d v v r f l d w h g f o r f n w k d w l v w k h d f w x d o f o r f n w k d w o d w f k h v l w l q + r z h y h u w k h l q s x w w l p l q j l q q v u h i h u h q f h v w r w k h t & . $ 9 * z k h q g h w h u p l q l q j w k h u h t x l u h g q x p e h u r i f o r f n v 7 k h i r o o r z l q j l q s x w s d u d p h w h u v d u h g h w h u p l q h g e \ w d n l q j w k h v s h f l i l h g s h u f h q w d j h w l p h v w k h t & . $ 9 * u d w k h u w k d q t ck: t , 3 : t ' , 3 : t ' 4 6 6 t ' 4 6 + t ' 4 6 / w ' 6 6 t dsh, t : 3 6 7 d q g t : 3 5 ( 7 k h ' ' 5 6 ' 5 $ 0 r x w s x w w l p l q j l v d o l j q h g w r w k h q r p l q d o r u d y h u - d j h f o r f n 0 r v w r x w s x w s d u d p h w h u v p x v w e h g h u d w h g e \ w k h d f w x d o m l w w h u h u u r u z k h q l q s x w f o r f n k l w w h u l v s u h v h q w w k l v z l o o u h v x o w l q h d f k s d u d p - h w h u e h f r p l q j o d u j h u 7 k h i r o o r z l q j s d u d p h w h u v d u h u h t x l u h g w r e h g h u d w h g e \ v x e w u d f w l q j t err 3 ( 5 0 $ ; t $ & 0 , 1 t ' 4 6 & . 0 , 1 t / = ' 4 6 0 , 1 t / = ' 4 0 , 1 t $ 2 1 0 , 1 z k l o h w k h i r o o r z l q j s d u d p h w h u v d u h u h t x l u h g w r e h g h u d w h g e \ v x e w u d f w l q j t err 3 ( 5 0 , 1 t $ & 0 $ ; t ' 4 6 & . 0 $ ; t + = 0 $ ; t / = ' 4 6 0 $ ; t / = ' 4 0 $ ; t $ 2 1 0 $ ; 7 k h s d u d p h w h u t 5 3 5 ( 0 , 1 l v g h u d w h g e \ v x e w u d f w l q j t - , 7 3 ( 5 0 $ ; z k l o h t 5 3 5 ( 0 $ ; l v g h u d w h g e \ v x e w u d f w l q j t - , 7 3 ( 5 0 , 1 7 k h s d u d p h w h u t 5 3 6 7 0 , 1 l v g h u d w h g e \ v x e w u d f w l q j t - , 7 ' 7 < 0 $ ; z k l o h t 5 3 6 7 0 $ ; l v g h u d w h g e \ v x e w u d f w l q j t - , 7 ' 7 < 0 , 1 2 x w s x w w l p l q j v w k d w u h t x l u h w ( 5 5 s h u g h u d w l q j f d q e h r e v h u y h g w r k d y h r i i v h w v u h o d w l y h w r w k h f o r f n k r z h y h u w k h w r w d o z l q g r z z l o o q r w g h j u d g h : k h q ' 4 6 l v x v h g v l q j o h h q g h g w k h p l q l p x p o l p l w l v u h g x f h g e \ s v t + = d q g w / = w u d q v l w l r q v r f f x u l q w k h v d p h d f f h v v w l p h z l q g r z v d v y d o l g g d w d w u d q v l w l r q v 7 k h v h s d u d p h w h u v d u h q r w u h i h u h q f h g w r d v s h f l i l f y r o w - d j h o h y h o e x w v s h f l i \ z k h q w k h g h y l f h r x w s x w l v q r w o r q j h u g u l y l q j t + = r u e h j l q v g u l y l q j t / = t / = 0 , 1 z l o o s u h y d l o r y h u d t ' 4 6 & . 0 , 1 t 5 3 5 ( 0 $ ; f r q g l w l r q 7 k l v l v q r w d g h y l f h o l p l w 7 k h g h y l f h z l o o r s h u d w h z l w k d q h j d w l y h y d o x h e x w v \ v w h p s h u i r u p d q f h f r x o g e h g h j u d g h g g x h w r e x v w x u q d u r x q g , w l v u h f r p p h q g h g w k d w ' 4 v e h y d o l g + , * + r u / 2 : r q r u e h i r u h w k h : 5 , 7 ( f r p p d q g 7 k h f d v h v k r z q ' 4 6 j r l q j i u r p + , * + = w r o r j l f / 2 : d s s o l h v z k h q q r : 5 , 7 ( 6 z h u h s u h y l r x v o \ l q s u r j u h v v r q w k h e x v , i d s u h y l r x v : 5 , 7 ( z d v l q s u r j u h v v ' 4 6 f r x o g e h + , * + g x u l q j w k l v w l p h g h s h q g l q j r q t ' 4 6 6 7 k h l q w h q w r i w k h v ' 2 1 u 7 & $ 5 ( w v w d w h d i w h u f r p s o h w l r q r i w k h s r v w d p e o h l v w k d w w k h ' 4 6 g u l y h q v l j q d o v k r x o g h l w k h u e h + , * + / 2 : r u + , * + = d q g w k d w d q \ v l j q d o w u d q v l w l r q z l w k l q w k h l q s x w v z l w f k l q j u h j l r q p x v w i r o o r z y d o l g l q s x w u h t x l u h p h q w v 7 k d w l v l i ' 4 6 w u d q v l w l r q v + , * + d e r y h 9 ih > ' & @ 0 , 1 w k h q l w p x v w q r w w u d q v l w l r q / 2 : e h o r z 9 ih > ' & @ s u l r u w r t ' 4 6 + 0 , 1 logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 31 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product n otes c ontinued 5 h i h u h q f h g w r h d f k r x w s x w j u r x s / ' 4 6 / ' 4 6 ? z l w k ' 4 8 ' 4 6 8 ' 4 6 ? z l w k ' 4 / ' 4 6 / ' 4 6 ? z l w k ' 4 8 ' 4 6 8 ' 4 6 ? z l w k ' 4 / ' 4 6 / ' 4 6 ? z l w k ' 4 8 ' 4 6 8 ' 4 6 ? z l w k ' 4 / ' 4 6 / ' 4 6 ? z l w k ' 4 8 ' 4 6 8 ' 4 6 ? z l w k ' 4 / ' 4 6 / ' 4 6 ? z l w k ' 4 d q g 8 ' 4 6 8 ' 4 6 ? z l w k ' 4 7 k h g d w d y d o l g z l q g r z l v g h u l y h g e \ d f k l h y l q j r w k h u v s h f l i l f d w l r q v t + 3 ( t & . t ' 4 6 4 d q g t 4 + t 4 + t + 3 t 4 + 6 7 k h g d w d y d o l g z l q g r z g h u - d w h v l q g l u h f w s u r s r u w l r q w r w k h f o r f n g x w \ f \ f o h d q g d s u d f w l f d o g d w d y d o l g z l q g r z f d q e h g h u l y h g t 4 + t + 3 t 4 + 6 w k h z r u v w f d v h t 4 k z r x o g e h w k h o h v v h u r i t & / $ % 6 0 $ ; r u t & + $ % 6 0 $ ; w l p h v t & . $ % 6 0 , 1 t 4 + 6 0 l q l p l ] l q j w k h d p r x q w r i t & + $ 9 * r i i v h w d q g y d o x h r i t - , 7 3 ( 5 z l o o s u r y l g h d o d u j h u t 4 + z k l f k l q w x u q z l o o s u r y l g h d o d u j h u y d o l g g d w d r x w z l q g r z 7 k l v p d [ l p x p y d o x h l v g h u l y h g i u r p w k h u h i h u h q f h g w h v w o r d g t + = 0 $ ; z l o o s u h y d l o r y h u t ' 4 6 & . 0 $ ; t 5 3 6 7 0 $ ; f r q g l w l r q 7 k h y d o x h v o l v w h g d u h i r u w k h g l i i h u h q w l d o / ' 4 6 [ / ' 4 6 [ ? 8 ' 4 6 [ d q g 8 ' 4 6 [ ? v w u r e h v z l w k d g l i i h u h q w l d o v o h z u d w h r i 9 q v 9 q v i r u h d f k v l q j o h h q g h g v l j q d o 7 k h u h d u h w z r v h w v r i y d o x h v o l v w h g t ' 6 d t ' + d d q g t dsb, t ' + e 7 k h v d w y d o x h v i r u u h i h u h q f h r q o \ d u h h t x l y d o h q w w r w k h e d v h o l q h y d o x h v r i w k h v e w d w 9 ref z k h q w k h v o h z u d w h l v 9 q v g l i i h u h q - w l d o o \ 7 k h e d v h o l q h y d o x h v t dsb, t ' + e d u h w k h - ( ' ( & g h i l q h g y d o x h v u h i h u h q f h g i u r p w k h o r j l f w u l s s r l q w v t ' 6 e l v u h i h u h q f h g i u r p 9 ih $ & i r u d u l v l q j v l j q d o d q g v il $ & i r u d i d o o l q j v l j q d o z k l o h t ' + e l v u h i h u - h q f h g i u r p 9 il ' & i r u d u l v l q j v l j q d o d q g 9 ih ' & i r u d i d o o l q j v l j q d o , i w k h g l i i h u h q w l d o ' 4 6 v o h z u d w h l v q r w h t x d o w r 9 q v w k h q w k h e d v h o l q h y d o x h v p x v w e h g h u d w h g e \ d g g l q j w k h y d o x h v i u r p 7 d e o h d q g 7 d e o h , i w k h ' 4 6 g l i i h u h q w l d o v w u r e h i h d w x u h l v q r w h q d e o h g w k h q w k h ' 4 6 v w u r e h l v v l q j o h h q g h g d q g w k h e d v h o l q h y d o x h v p x v w e h g h u d w h g x v l q j 7 d e o h 6 l q j o h h q g h g ' 4 6 g d w d w l p l q j l v u h i h u h q f h g d w ' 4 6 f u r v v - l q j 9 ref 7 k h f r u u h f w w l p l q j y d o x h v i r u d v l q j o h h q g h g ' 4 6 v w u r e h d u h o l v w h g l q 7 d e o h / l v w h g y d o x h v d u h d o u h d g \ g h u d w h g i r u v o h z u d w h y d u l d w l r q d q g f r q y h u w h g i u r p e d v h o l q h y d o x h v w r 9 ref y d o x h v 9 il 9 ih ' ' 5 r y h u v k r r w x q g h u v k r r w 6 h h $ & 2 y h u v k r r w 8 q g h u v k r r w 6 s h f l i l f d w l r q ) r u h d f k l q s x w v l j q d o q r w w k h j u r x s f r o o h f w l y h o \ 7 k h u h d u h w z r v h w v r i y d o x h v o l v w h g i r u f r p p d q g d g g u h v v t , 6 d t , + d d q g t isb, t , + e 7 k h v d w y d o x h v i r u u h i h u h q f h r q o \ d u h h t x l y d o h q w w r w k h e d v h - o l q h y d o x h v r i w k h v e w v l j q d o v d w 9 ref z k h q w k h v o h z u d w h l v 9 q v 7 k h e d v h o l q h y d o x h v v e w d u h w k h - ( ' ( & g h i l q h g y d o x h v u h i h u h q f h g i r u p w k h o r j l f w u l s s r l q w v t , 6 e l v u h i h u h q f h g i u r p 9 ih $ & i r u d u l v l q j v l j q d o d q g 9 il $ & i r u d i d o o l q j v l j q d o , i w k h f r p p d q g d g g u h v v v o h z u d w h l v q r w h t x d o w r 9 q v w k h q w k h e d v h o l q h y d o x h v p x v w e h g h u d w h g e \ d g g l q j w k h y d o x h z i u r p 7 d e o h d q g 7 d e o h 7 k l v l v d s s o l f d e o h w r 5 ( $ ' f \ f o h v r q o \ : 5 , 7 ( f \ f o h v j h q h u d o o \ u h t x l u h d g g l w l r q d o w l p h g x h w r t : 5 g x u l q j d x w r s u h f k d u j h 5 ( $ ' v d q g : 5 , 7 ( v z l w k $ 8 7 2 3 5 ( & + $ 5 * ( d u h d o o r z h g w r e h l v v x h g e h i r u h t 5 $ 6 0 , 1 l v v d w l v i l h g e h f d x v h w k h t 5 $ 6 o r f n r x w i h d w x u h l v v x s s r u w h g l q w k h ' ' 5 6 ' 5 $ 0 d u f k l w h f w x u h : k h q d v l q j o h e d q n 3 5 ( & + $ 5 * ( f r p p d q g l v l v v x h g t 5 3 w l p l q j d s s o l h v t 5 3 $ w l p l q j d s s o l h v z k h q w k h 3 5 ( & + $ 5 * ( $ / / f r p p d q g l v l v v x h g u h j d u g o h v v r i w k h q x p e h u r i e d q n v r s h q 7 k l v s d u d p h w h u l k d v d w z r f o r f n p l q l p x p u h t x l u h p h q w d w d q \ t ck 7 k h t ) $ : 0 , 1 s d u d p h w h u d s s o l h v w r d o o e d q n ' ' 5 g h y l f h v 1 r p r u h w k d q e d q n $ & 7 , 9 $ 7 ( f r p p d q g v p d \ e h l v v x h g l q d j l y h q t ) $ : 0 , 1 s h u l r g t 5 5 ' 0 , 1 u h v w u l f w l r q v w l o o d s s o l h v 7 k h p l q l p x p l q w h u q d o 5 ( $ ' w r 3 5 ( & + $ 5 * ( w l p h 7 k l v l v w k h w l p h i u r p z k l f k w k h o d v w e l w s u h i h w f k e h j l q v w r z k h q w k h 3 5 ( & + $ 5 * ( f r p p d q g f d q e h l v v x h g $ e l w s u h i h w f k l v z k h q w k h 5 ( $ ' f r p - p d q g l q w h u q d o o \ o d w f k h v w k h 5 ( $ ' v r w k d w g d w d z l o o r x w s x w & / o d w h u 7 k l v s d u d p h w h u l v r q o \ d s s o l f d e o h z k h q t 5 7 3 [ t & . ! v x f k d v i u h t x h q - f l h v i d v w h u w k d q 0 + ] z k h q t 5 7 3 q v , i t 5 7 3 [ t & . d 1, w k h q h t x d w l r q $ / % / d s s o l h v t 5 $ 6 0 , 1 k d v w r e h v d w l v i l h g d v z h o o 7 k h ' ' 5 6 ' 5 $ 0 z l o o d x w r p d w l f d o o \ g h o d \ w k h l q w h u q d o 3 5 ( & + $ 5 * ( f r p p d q g x q w l o t 5 $ 6 0 , 1 k d v e h h q v d w l v i l h g t ' $ / q : 5 t 5 3 t & . ( d f k r i w k h v h w h u p v l i q r w d o u h d g \ d q l q w h - j h u v k r x o g e h u r x q g h g x s w r w k h q h [ w l q w h j h u t & . u h i h u v w r w k h d s s o l - f d w l r q f o r f n s h u l r g q : 5 u h i h u v w r w k h t : 5 s d u d p h w h u v w r u h g l q w k h 0 5 0 5 ) r u h [ d p s o h d w t & . q v z l w k t : 5 s u r j u d p p h g w r i r x u f o r f n v z r x o g k d y h t ' $ / q v q v f o r f n v f o r f n v f o r f n v 7 k h u h i u h v k s h u l r g l v p v , q g x v w u l d o ? & p v ( [ w h q g h g ? & d q g 0 l o 7 h p s ? & 7 k l v h t x d w h v w r d u h i u h v k u d w h r i ? v , q g x v w u l d o ? v ( [ w h q g h g d q g ? v 0 l o 7 h p s 7 r h q v x u h d o o u r z v r i d o o e d q n v d u h s u r s h u o \ u h i u h v k h g f r p p d q g v p x v w e h l v v x h g h y h u \ r u p v 7 k h - ( ' ( & t 5 ) & 0 $ ; r i q v l v q r w u h t x l u h g d v e x u v w l q j r i $ 8 7 2 5 ( ) 5 ( 6 + f r p p d q g v l v d o o r z h g t ' ( / $ < l v f d o f x o d w h g i u r p t , 6 t & . t , + v r w k d w & . ( u h j l v w u d w l r q / 2 : l v j x d u d q w h h g s u l r u w r t & . & . ? e h l q j u h p r y h g l q d v \ v w h p 5 ( 6 ( 7 f r q g l w l r q v h h 5 ( 6 ( 7 t , 6 ; 5 l v h t x d o w r t , 6 d q g l v x v h g i r u & . ( v h w x s w l p h g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + h [ l w t & . ( 0 , 1 r i w k u h h f o r f n v p h d q v & . ( p x v w e h u h j l v w h u h g r q w k u h h f r q v h f x w l y h s r v l w l y h f o r f n h g j h v & . ( p x v w u h p d l q d w w k h y d o l g l q s x w o h y h o w k h h q w l u h w l p h l w w d n h v w r d f k l h y h w k h w k u h h f o r f n v r i u h j l v w u d w l r q 7 k x v d i w h u d q \ & . ( w u d q v l w l r q & . ( p d \ q r w w u d q v l w l r q i u r p l w v y d o l g o h y h o g x u l q j w k h w l p h s h u l r g r i t , 6 [ t & . t , + 7 k h k d o i f o r f n r i w $ 2 ) ' u v t & . d v v x p h v d f o r f n g x w \ f \ f o h 7 k l v k d o i f o r f n y d o x h p x v w e h g h u d w h g e \ w k h d p r x q w r i w k h k d o i f o r f n g x w \ f \ f o h h u u r u ) r u h [ d p s o h l i w k h f o r f n g x w \ f \ f o h z d v t $ 2 ) ' z r x o g d f w x d o o \ e h r u i r u t $ 2 ) 0 , 1 d q g r u i r u t $ 2 ) 0 $ ; 2 ' 7 w x u q r q w l p h t $ 2 1 0 , 1 l v z k h q w k h g h y l f h o h d y h v + l j k = d q g 2 ' 7 u h v l v w d q f h e h j l q v w r w x u q r q 2 ' 7 w x u q r q w l p h t $ 2 1 0 $ ; l v z k h q w k h 2 ' 7 u h v l v w d q f h l v i x o o \ r q % r w k d u h p h d v x u h g i u r p t $ 2 1 ' 2 ' 7 w x u q r i i w l p h t $ 2 ) 0 , 1 l v z k h q w k h g h y l f h v w d u w v w r w x u q r i i 2 ' 7 u h v l v w d q f h 2 ' 7 w x u q r i i w l p h t $ 2 ) 0 $ ; l v z k h q w k h e x v l v l q + , * + = % r w k d u h p h d v x u h g i u r p t $ 2 ) ' + d o i & o r f n r x w s x w s d u d p h w h u v p x v w e h g h u d w h g e \ w k h d f w x d o w ( 5 5 s h u d q g t - , 7 ' 7 < z k h q l q s x w f o r f n m l w w h u l v s u h v h q w w k l v z l o o u h v x o w l q h d f k s d u d p h w h u e h f r p l q j o d u j h u 7 k h s d u d p h w h u t $ 2 ) 0 , 1 l v u h t x l u h g w r e h g h u d w h g e \ v x e w u d f w l q j e r w k w ( 5 5 s h u 0 $ ; d q g t err 5per 0 , 1 d q g t - , 7 ' 7 < 0 , 1 logic devices incorporated www.logicdevices.com 32 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product p ackage o utline d imensions 1 2 7 ( 6 r 7 7 h i i d q g 5 7 7 h i i d u h g h w h u p l q h g e \ v h s d u d w h o \ d s s o \ l q j 9 ih $ & d q g 9 il ' & w r w k h e d o o e h l q j w h v w h g d q g w k h q p h d v x u l q j f x u u h q w , 9 ih > $ & @ d q g , 9 il > $ & @ u h v s h f w l y h o \ 0 l q l p x p , l q g x v w u l d o ( h [ w h q g h g d q g 0 0 l o 7 h p s d u h g h u d w h g e \ v l [ s h u f h q w z k h q w k h g h y l f h v r s h u d w h e h w z h h q ? & d q g ? & d q g s h u - f h q w z k h q w k h g h y l f h v r s h u d w h g e h w z h h q ? & d q g ? & 0 h d v x u h y r o w d j h 9 0 d w w h v w h g e d o o z l w k q r o r d g parameter/condition symbol min typ ma x units notes r tt effective impedance value for 75 : setting ( 0 5 $ $ r tt effective impedance value for 150 : setting ( 0 5 $ $ r tt effective impedance value for 50 : setting ( 0 5 $ $ deviation of vm with respect to v dd q/2 : : : 1,2 1,2 1,2 3 t able 11: odt e lectrical c haracteristics 90 60 6 150 50 - 60 120 -6 r 7 7 h i i r 7 7 h i i r 7 7 h i i ' 9 0 [ 9 0 9 dd 4 ' 9 0 -1 x 100 p ackage o utline d imensions 1 2 7 ( 6 9 dd 4 p y d o o r z h g s u r y l g h g 9 l v q r w h [ f h h g h g parameter/condition symbol min max units , q s x w + , * + o r j l f y r o w d j h , q s x w / 2 : o r j l f y r o w d j h p 9 p 9 t able 12: i nput dc l ogic l evels 9 dd 4 9 ref ' & 9 ref ' & -300 9 ih ' & 9 ih ' & p ackage o utline d imensions 1 2 7 ( 6 9 dd 4 p y d o o r z h g s u r y l g h g 9 l v q r w h [ f h h g h g parameter/condition symbol min max units , q s x w + , * + o r j l f y r o w d j h , q s x w + , * + o r j l f y r o w d j h , q s x w / 2 : o r j l f y r o w d j h , q s x w / 2 : o r j l f y r o w d j h p 9 p 9 p 9 p 9 t able 13: i nput ac l ogic l evels 9 dd 4 9 dd 4 9 ref ( dc 9 ref ( dc 9 ref ( dc 9 ref ( dc -300 -300 9 ih $ & 9 ih $ & 9 il $ & 9 il $ & 650mv 775mv 864mv 882mv 900mv 918mv 936mv 1,025mv v ref + ac noise v ref + dc error v ref - dc error v ref - ac noise 1,150mv v ih (ac) v ih (dc) v il (dq) v il (ac) operating conditions f igure 6 - s ingle e nded i nput s ignal l evels 1 r w h 1 x p e h u v l q g l d j u d p u h i o h f w q r p l q d o ' ' 5 ' ' 5 y d o x h v logic devices incorporated www.logicdevices.com 33 september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product p ackage o utline d imensions parameter/condition symbol min max units notes ' & l q s x w v l j q d o 9 r o w d j h ' & g l i i h u h q w l d o l q s x w 9 r o w d j h $ & g l i i h u h q w l d o l q s x w 9 r o w d j h $ & g l i i h u h q w l d o f u r v v s r l q w 9 r o w d j h , q s x w p l g s r l q w 9 r o w d j h p 9 p 9 p 9 p 9 p 9 1,6 2,6 3,6 5 t able 14: d ifferential i nput l ogic l evel 9 dd 4 9 dd 4 9 dd 4 [ 9 dd 4 950 -300 250 500 [ 9 dd 4 9 in ' & 9 id ' & 9 id $ & 9 , ; $ & 9 0 3 ' & logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 1 2 7 ( 6 9 in ' & v s h f l i l h v w k h d o o r z d e o h ' & h [ h f x w l r q r i h d f k l q s x w r i g l i i h u h q - w l d o s d l u v x f k d v & . [ & . [ ? ' 4 6 [ ' 4 6 [ ? / ' 4 6 [ / ' 4 6 [ ? 8 ' 4 6 [ d q g 8 ' 4 6 [ ? 9 id ' & v s h f l i l h v w k h l q s x w g l i i h u h q w l d o y r o w d j h > 9 7 5 9 & 3 @ u h t x l u h g i r u v z l w f k l q j z k h u h l q s x w v x f k d v & . [ ? ' 4 6 [ ? / ' 4 6 [ ? d q g 8 ' 4 6 [ ? o h y h o 7 k h p l q l p x p y d o x h l v h t x d o w r 9 ih ' & 9 il ' & ' l i i h u h q w l d o l q s x w v l j q d o o h y h o v d u h v k r z l q ) l j x u h 9 id $ & v s h f l i l h v w k h l q s x w g l i i h u h q w l d o y r o w d j h > 9 7 5 9 & 3 @ u h t x l u h g i r u v z l w f k l q j z k h u h 9 7 5 l v w k h w u x h l q s x w v x f k d v & . [ ' 4 6 [ / ' 4 6 [ d q g 8 ' 4 6 [ o h y h o 7 k h p l q l p x p y d o x h l v h t x d o w r 9 ih ' & l v h t x d o w r 9 ih $ & 9 il $ & d v v k r z q l q 7 d e o h 7 k h w \ s l f d o y d o x h r i 9 , ; $ & l v h [ s h f w h g w r e h d e r x w [ 9 dd 4 r i w k h w u d q v p l w w l q j g h y l f h d q g 9 , ; $ & l v h [ s h f w h g w r w u d f n y d u l d w l r q v l q 9 dd 4 9 , ; $ & l q g l f d w h v w k h y r o w d j h d w z k l f k g l i i h u h q w l d o l q s x w v l j q d o v p x v w f u r v v d v v k r z q l q ) l j x u h 9 0 3 ' & v s h f l i l h v w k h l q s x w g l i i h u h q w l d o f r p p r q p r g h y r o w d j h 9 7 5 9 & 3 z k h u h 9 7 5 l v w k h w u x h l q s x w & . [ ' 4 6 [ o h y h o d q g 9 & 3 l v w k h f r p s o h p h q w d u \ l q s x w & . [ ? ' 4 6 [ ? 9 dd 4 p y d o o r z h g s u r y l g h g 9 l v q r w h [ f h h g h g tr 2 cp 2 2.1v v dd q = 1.8v v in (dc)max v in (dc)min 1 C0.30v 0.9v 1.075v 0.725v v id (ac) 6 v id (dc) 5 x v mp (dc) 3 v ix (ac) 4 x 1 . f igure 7 - d ifferential i nput s ignal l evels 1 r w h v 7 5 d q g & 3 p d \ q r w e h p r u h s r v l w l y h w k d q 9 dd 4 9 r u p r u h q h j d w l y h w k d q 9 ; ; 9 7 5 u h s u h v h q w v w k h & . ' 4 6 5 ' 4 6 / ' 4 6 d q g 8 ' 4 6 v l j q d o v & 3 u h s u h v h q w v & . ' 4 6 5 ' 4 6 / ' 4 6 d q g 8 ' 4 6 v l j q d o v 7 k l v s u r y l g h v d p l q l p x p r i p 9 w r d p d [ l p x p r i p 9 d q g l v h [ s h f w h g w r e h 9 dd 4 7 5 d q g & 3 p x v w f u r v v l q w k l v u h j l r q 7 5 d q g & 3 p x v w p h h w d w o h d v w 9 id ' & p l q z k h q v w d w l f d q g l v f h q w h u h g d u r x q g 9 0 3 ' & 7 5 d q g & 3 p x v w k d y h d p l q l p x p p 9 s h d n w r s h d n v z l q j 1 x p e h u v l q g l d j u d p u h i o h f w q r p l q d o y d o x h v 9 dd 4 9 logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 35 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product p ackage o utline d imensions parameter/condition symbol value units notes 2 x w s x w 0 , 1 v r x u f h ' & f x u u h q w 2 x w s x w 0 , 1 v l q n ' & f x u u h q w p 9 p 9 t able 16: o utput dc c urrent d rive 9 dd ' & 9 ref ' & i oh i ol p ackage o utline d imensions parameter symbol min max unit s notes $ & g l i i h u h q w l d o f u r v v s r l q w 9 r o w d j h $ & g l i i h u h q w l d o 9 r o w d j h v z l q j p 9 p 9 1,6 t able 15: d ifferential ac o utput p arameters [ 9 dd 4 - [ 9 dd 4 1 9 2 ; $ & 9 v z l q j crossing point v ox v ss q vswing v dd q v tr v cp logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 36 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 1 2 7 ( 6 7 k h w \ s l f d o y d o x h r i 9 2 ; $ & l v h [ s h f w h g w r e h d e r x w [ 9 dd 4 r i w k h w u d q v p l w w l q j g h y l f h d q g 9 2 ; $ & l v h [ s h f w h g w r w u d f n y d u l d w l r q v l q 9 dd 4 9 2 ; $ & l q g l f d w h v w k h y r o w d j h d w z k l f k g l i i h u h q w l d o r x w s x w v l j q d o v p x v w f u r v v f igure 8 - d ifferential o utput s ignal l evels 1 2 7 ( 6 for l oh ' & 9 dd 4 9 9 2 8 7 p 9 9 2 8 7 9 dd 4 , oh p x v w e h o h v v w k d q : i r u y d o x h v r i 9 2 8 7 e h w z h h q 9 dd 4 d q g 9 dd 4 p 9 for l ol ' & 9 dd 4 9 9 2 8 7 p 9 9 r x w o ol p x v w e h o h v v w k d q 21 : i r u y d o x h v r i 9 2 8 7 e h w z h h q 9 d q g p 9 7 k h ' & y d o x h r i 9 ref d s s o l h g w r w k h u h f h l y l q j g h y l f h l v v h w w r 9 7 7 7 k h y d o x h v r i o oh ' & d q g o ol ' & d u h e d v h g r q w k h f r q g l w l r q v j l y h q l q 1 r w h v d q g 7 k h \ d u h x v h g w r w h v w g h y l f h g u l y h f x u u h q w f d s d e l o l w \ w r h q v x u h 9 ih 0 , 1 s o x v d q r l v h p d u j l q d q g 9 il 0 $ ; p l q x v d q r l v h p d u j l q d u h g h o l y h u h g w r d q 6 6 7 / b u h f h l y h u 7 k h d f w x d o f x u u h q w y d o x h v d u h g h u l y h g e \ v k l i w l q j w k h g h v l u h g g u l y h u r s h u d w l q j s r l q w v h h r x w s x w , 9 f x u y h v d o r q j d : o r d g o l q h w r g h i l q h d f r q y h q l h q w g u l y h u f x u u h q w i r u p h d v x u h p h q w p ackage o utline d imensions parameter min typ max units notes 2 x w s x w , p s h g d q f h 3 x o o x s d q g s x o o g r z q p l v p d w f k 2 x w s x w v o h z u d w h t able 17: o utput c haracteristics 0 1,2 1,2,3 - - 5 : : 9 q v 6 h h 2 x w s x w ' u l y h u & k d u d f w h u l v w l f v output (v out ) reference point 25 v tt = v dd q/2 logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 1 2 7 ( 6 $ e v r o x w h v s h f l i l f d w l r q v ? & d 7 c d ? & 9 dd 4 9 9 dd 9 ? 9 , p s h g d q f h p h d v x u h p h q w f r q g l w l r q v i r u r x w s x w v r x u f h ' & f x u u h q w 9 dd 4 9 r x w p 9 9 2 8 7 9 dd 4 o oh p x v w e h o h v v w k d q : i r u y d o x h v r i 9 r x w e h w z h h q 9 dd 4 d q g 9 dd 4 p 9 7 k h l p s h g d q f h p h d v x u h p h q w f r q g l w l r q i r u r x w s x w v l q n ' & f x u u h q w 9 dd 4 9 9 r x w p 9 9 r x w o r o p x v w e h o h v v w k d q : i r u y d o x h v r i 9 2 8 7 e h w z h h q 9 d q g p 9 0 l v p d w f k l v d q g d e v r o x w h y d o x h e h w z h h q s x o o x s d q g s x o o g r z q e r w k d u h p h d v x u h g d w w k h v d p h w h p s h u d w x u h d q g y r o w d j h 2 x w s x w v o h z u d w h i r u i d o o l q j d q g u l v l q j h g j h v l v p h d v x u h g e h w z h h q 9 7 7 p 9 d q g 9 7 7 p 9 i r u v l q j o h h q g h g v l j q d o v ) r u g l i i h u h q - w l d o v l j q d o v ' 4 6 [ ' 4 6 [ ? r x w s x w v o h z u d w h l v p h d v x u h g e h w z h h q ' 4 6 [ ' 4 6 [ ? p 9 2 x w s x w v o h z u d w h l v j x d u d q w h h g e \ g h v l j q e x w l v q r w q h f h v v d u l o \ w h v w h g r q h d f k g h y l f h 7 k h d e v r o x w h y d o x h r i w k h v o h z u d w h d v p h d v x u h g i u r p 9 il ' & 0 $ ; w r 9 ih ' & 0 , 1 l v h t x d o w r r u j u h d w h u w k d q w k h v o h z u d w h d v p h d v x u h g i u r p 9 il $ & 0 $ ; w r 9 ih $ & 0 , 1 7 k l v l v j x d u d q w h h g e \ g h v l j q $ o o g h y l f h v , 1 ' 8 6 7 5 , $ / ( ; 7 ( 1 ' ( ' d q g 0 , / 7 ( 0 3 g h y l f h v u h t x l u h d q d g g l w l r q d o 9 q v l q w k h 0 $ ; o l p l w z k h q 7 f l v e h w z h h q ? & d q g ? & f igure 9 - o utput s lew r ate l oad v out (v) 0.0 0.5 1.0 1.5 120 100 80 60 40 20 0 i out (ma) logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product p ackage o utline d imensions voltage (v) min typ max units p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ t able 18: f ull s trength p ull -d own c urrent ( ma ) f igure 10 - f ull s trength p ull d own c haracteristics v ddq - v out (v) 0 C20 C40 C60 C80 C100 C120 0 0.5 1.0 1.5 i out (ma) logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 39 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product p ackage o utline d imensions voltage (v) min typ max units p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ t able 19: f ull s trength p ull -u p c urrent ( ma ) f igure 11 - f ull s trength p ull u p c haracteristics 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 v out (v) i out (mv) logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product p ackage o utline d imensions voltage (v) min typ max units p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ t able 20: r educed s trength p ull -d own c urrent ( ma ) f igure 12 - r educed s trength p ull d own c haracteristics 0 C10 C20 C30 C40 C50 C60 C70 0.0 0.5 1.0 1.5 v ddq - v out (v) i out (mv) logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product p ackage o utline d imensions voltage (v) min typ max units p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ t able 21: r educed s trength p ull -u p c urrent ( ma ) f igure 13 - r educed s trength p ull u p c haracteristics logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product p ackage o utline d imensions voltage (v) across clamp min power clamp current min ground clamp current units p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ p $ t able 22: i nput c lamp c haracteristics f igure 14 - i nput c lamp c haracteristics voltage across clamp (v) minimum clamp current (ma) 25 20 15 10 5 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 f igure 15 & 16: o vershoot /u ndershoot s pecifications maximum amplitude overshoot area v dd /v dd q time (ns) volts (v) maximum amplitude undershoot area time (ns) v ss /v ss q volts (v) v ss /v ss q figure 15: overshoot figure 16: undershoot logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product p ackage o utline d imensions parameter 25 3 units 0 d [ l p x p s h d n d p s o l w x g h i r u r y h u v k r r w d u h d v h h ) l j x u h 0 d [ l p x p s h d n d p s o l w x g h d o o r z h g i r u x q g h u v k r r w d u h d v h h ) l j x u h 0 d [ l p x p r y h u v k r r w d u h d d e r y h 9 dd v h h ) l j x u h 0 d [ l p x p x q g h u v k r r w d u h d e h o r z 9 v v v h h ) l j x u h t able 23: a ddress and c ontrols p ins 9 9 9 q v 9 q v specifications p ackage o utline d imensions parameter 25 3 units 0 d [ l p x p s h d n d p s o l w x g h i r u r y h u v k r r w d u h d v h h ) l j x u h 0 d [ l p x p s h d n d p s o l w x g h d o o r z h g i r u x q g h u v k r r w d u h d v h h ) l j x u h 0 d [ l p x p r y h u v k r r w d u h d d e r y h 9 dd 4 v h h ) l j x u h 0 d [ l p x p x q g h u v k r r w d u h d e h o r z 9 v v 4 v h h ) l j x u h t able 24: c lock , d ata , s trobe , and m ask p ins 9 9 9 q v 9 q v specifications see note 2 see note 5 9 , ; $ & p ackage o utline d imensions parameter/condition symbol min max units notes , q s x w v h w x s w l p l q j p h d v x u h p h q w u h i h u h q f h o h y h o d g g u h v v e d o o v e d q n d g g u h v v e d o o v & 6 ? 5 $ 6 ? & $ 6 ? : ( ? 2 ' 7 ' 0 8 ' 0 / ' 0 d q g & . ( , q s x w k r o g w l p l q j p h d v x u h p h q w u h i h u h q f h o h y h o d g g u h v v e d o o v e d q n d g g u h v v e d o o v & 6 ? 5 $ 6 ? & $ 6 ? : ( ? 2 ' 7 ' 0 8 ' 0 / ' 0 d q g & . ( , q s x w w l p l q j p h d v x u h p h q w u h i h u h q f h o h y h o v l q j o h h q g h g 8 ' 4 6 [ / ' 4 6 [ , q s x w w l p l q j p h d v x u h p h q w u h i h u h q f h o h y h o g l i i h u h q w l d o & . & . ? 8 ' 4 6 [ 8 ' 4 6 [ ? / ' 4 6 [ / ' 4 6 [ ? 9 9 t able 25: ac i nput t est c onditions 9 dd 4 [ 9 dd 4 [ 9 rs 9 rh 9 ref ' & 9 rd 1 2 7 ( 6 $ o o y r o w d j h v u h i h u h q f h g w r 9 v v , q s x w z d y h i r u p v h w x s w l p l q j t , 6 e l v u h i h u h q f h g i u r p w k h l q s x w v l j q d o f u r v v l q j d w w k h 9 ih $ & o h y h o i r u d u l v l q j v l j q d o d q g 9 il $ & i r u d i d o o l q j v l j q d o d s s o l h g w r w k h g h y l f h x q g h u w h v w d v v k r z q l q ) l j x u h 6 h h , q s x w 6 o h z 5 d w h ' h u d w l q j 7 k h v o h z u d w h i r u v l q j o h h q g h g l q s x w v l v p h d v x u h g i u r p ' & o h y h o w r $ & o h y h o 9 il ' & w r 9 ih $ & r q w k h u l v l q j h g j h d q g 9 il $ & w r 9 ih ' & r q w k h i d o o l q j h g j h ) r u v l j q d o v u h i h u h q f h g w r 9 ref w k h y d o l g l q w h u v h f w l r q l v z k h u h w k h v w d q j h q w w o l q h l q w h u v h f w v 9 ref d v v k r z q l q ) l j x u h d q g , q s x w z d y h i r u p k r o g t , + e w l p l q j l v u h i h u h q f h g i u r p w k h l q s x w v l j q d o f u r v v l q j d w w k h 9 il ' & o h y h o i r u d u l v l q j v l j q d o d q g 9 ih ' & i r u d i d o o l q j v l j q d o d s s o l h g w r w k h g h y l f h x q g h u w h v w d v v k r z q l q ) l j x u h , q s x w z d y h i r u p v h w x s w l p l q j t ' 6 d q g k r o g w l p l q j t ' + z k h q v l q j o h h q g h g g d w d v w u r e h l v h q d e o h g l v u h i h u h q f h g i u r p w k h f u r v v l q j r i ' 4 6 8 ' 4 6 r u / ' 4 6 w k u r x j k w k h 9 ref o h y h o d s s o l h g w r w k h g h y l f h x q g h u w h v w d v v k r z q l q ) l j x u h , q s x w z d y h i r u p v h w x s w l p l q j t ' 6 d q g k r o g w l p l q j t ' + z k h q g l i i h u h q - w l d o g d w d v w u r e h l v h q d e o h g l v u h i h u h q f h g i u r p w k h f u r v v s r l q w r i ' 4 6 [ ' 4 6 [ ? 8 ' 4 6 [ 8 ' 4 6 [ ? / ' 4 6 [ / ' 4 6 [ ? d v v k r z q l q ) l j x u h , q s x w z d y h i r u p w l p l q j l v u h i h u h q f h g w r w k h f u r v v l q j s r l q w o h y h o 9 l [ r i w z r l q s x w v l j q d o v 9 w u d q g 9 f s d s s o l h g w r w k h g h y l f h x q g h u w h v w z k h u h 9 w u l v w k h w u x h l q s x w v l j q d o d q g 9 f s l v w k h f r p s o h p h q w d u \ l q s x w v l j q d o d v v k r z q l q ) l j x u h 7 k h v o h z u d w h i r u g l i i h u h q w l d o o \ h q g h g l q s x w v l v p h d v x u h g i u r p w z l f h w k h ' & o h y h o w r w z l f h w k h $ & o h y h o [ 9 il ' & w r [ 9 ih $ & r q w k h i d o o l q j h g j h i r u h [ d p s o h w k h & . & . ? z r x o g e h p 9 w r p 9 i r u & . u l v l q j h g j h d q g z r x o g e h p 9 w r p 9 i r u & . i d o o l q j h g j h logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product i nput s lew r ate d erating ) r u d o o l q s x w v l j q d o v w k h w r w d o t , 6 v h w x s w l p h d q g t , + k r o g w l p h u h t x l u h g l v f d o f x o d w h g e \ d g g l q j w k h g d w d v k h h w t , 6 e d v h d q g t , + e d v h y d o x h w r w k h ' t , 6 d q g ' t , + g h u d w l q j y d o x h u h v s h f w l y h o \ 6 h w x s d q g k r o g w l p h v d u h e d v h g r q p h d v x u h p h q w v d w w k h g h y l f h 1 r w h w k d w d g g u h v v d q g f r q w u r o s l q v s u h v - h q w w k h f d s d f l w d q f h r i p x o w l s o h g l h w r w k h v \ v w h p 7 k l v f d s d f l w d q f h l v o h v v w k d q w k h h t x l y d o h q w q x p e h u r i g l v f u h w h g h y l f h v g x h w r w k h k l j k h u o h y h o r i g l h l q w h j u d w l r q k r z h y h u l w p x v w e h d f f r x q w h g i r u z k h q g u l y l q j w k h v h s l q v 6 o h z u d w h v r q w k h v h s l q v z l o o e h v o r z h u w k d q s l q v z l w k r q o \ r q h g l h o r d g x q o h v v p h d v x u h v d u h p d g h w r l q f u h d v h w k h v w u h q j w k r i w k h v l j q d o g u l y h u d q g o r z h u w k h w u d f h l p s h g d q f h s u r s r u w l r q d o o \ r q v l j q d o v f r q q h f w l q j w r p x o w l s o h l q w h u q d o g l h t , 6 w k h q r p l q d o v o h z u d w h i r u d u l v l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 ref ' & d q g w k h i l u v w f u r v v l q j r i 9 ih $ & 0 , 1 6 h w x s q r p l q d o v o h z u d w h t , 6 i r u d i d o o l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 ref ' & d q g w k h i l u v w f u r v v l q j r i 9 il $ & 0 $ ; , i w k h d f w x d o v l j q d o l v o d w h u w k d q w k h q r p l q d o v o h z u d w h o l q h d q \ z k h u h e h w z h h q w k h v k d g h g v 9 ref ' & w r $ & u h j l r q v x v h w k h q r p l q d o v o h z u d w h i r u w k h g h u d w l q j y d o x h , i w k h d f w x d o v l j q d o l v o d w h u w k d q w k h q r p l q d o v o h z u d w h o l q h d q \ z k h u h e h w z h h q w k h v k d g h g v 9 ref ' & w r $ & u h j l r q w w k h v o h z u d w h r i d w d q j h q w o l q h w r w k h d f w x d o v l j q d o i u r p w k h $ & o h y h o w r ' & o h y h o l v x v h g i r u w k h g h u d w l q j y d o x h t , + w k h q r p l q d o v o h z u d w h i r u d u l v l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 il ' & 0 $ ; d q g w k h i l u v w f u r v v l q j r i 9 ref ' & t , + q r p l q d o v o h z u d w h i r u d i d o o l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 ih ' & 0 , 1 d q g w k h i l u v w f u r v v l q j r i 9 ref ' & , i w k h d f w x d o v l j q d o l v d o z d \ v o d w h u w k d q w k h q r p l q d o v o h z u d w h o l q h e h w z h h q v k d g h g v ' & w r 9 ref ' & u h j l r q w x v h w k h q r p l q d o v o h z u d w h i r u w k h g h u d w l q j y d o x h , i w k h d f w x d o v l j q d o l v h d u o l h u w k d q w k h q r p l q d o v o h z u d w h o l q h d q \ z k h u h e h w z h h q v k d g h g v ' & w r 9 ref ' & u h j l r q v w k h v o h z u d w h r i d w d q j h q w o l q h w r w k h d f w x d o v l j q d o i u r p w k h ' & o h y h o w r 9 ref ' & o h y h o l v x v h g i r u w k h g h u d w l q j y d o x h $ o w k r x j k w k h w r w d o v h w x s w l p h p l j k w e h q h j d w l y h i r u v o r z v o h z u d w h v d y d o l g l q s x w v l j q d o z l o o q r w k d y h u h d f k h g 9 ih > $ & @ 9 il > $ & @ d w w k h w l p h r i w k h u l v l q j f o r f n w u d q v l w l r q d y d o l g l q s x w v l j q d o l v v w l o o u h t x l u h g w r f r p s o h w h w k h w u d q v l w l r q d q g u h d f k 9 ih $ & 9 il $ & ) r u v o h z u d w h v l q e h w z h h q w k h y d o x h v o l v w h g 7 d e o h d q g 7 d e o h w k h g h u d w - l q j y d o x h v p d \ e h r e w d l q h g e \ o l q h d u l q w h u s r o d w l r q t able 26: ddr2-400/533 s etup and h old t ime d erating v alues ( t is/ t ih) cmd/addr slew rate v/ns 150 125 0 -11 -25 -110 -350 -525 21 0 -31 -125 -292 -500 -1125 209 155 113 30 19 5 -13 -255 -320 119 113 105 51 30 16 -1 -53 -95 -262 -1095 239 210 60 29 6 -23 -65 -232 -315 -1065 135 105 60 29 6 -23 -65 -232 -315 -1065 s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v 2.0v/ns 1.5v/ns 1.0v/ns ck, ck\ differential slew rate units ' t is ' t ih ' t is ' t ih ' t is ' t ih logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product t able 27: ddr2-667/800 s etup and h old t ime d erating v alues ( t is/ t ih) cmd/addr slew rate v/ns 150 133 120 100 0 -5 -13 -22 -60 -100 -200 -325 -1000 21 0 -31 -125 -292 -500 -1125 163 150 30 25 -30 -295 119 113 105 51 30 16 -1 -53 -95 -262 -1095 210 203 193 160 60 55 36 0 -265 135 105 60 29 6 -23 -65 -232 -315 -1065 s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v 2.0v/ns 1.5v/ns 1.0v/ns ck, ck\ differential slew rate units ' t is ' t ih ' t is ' t ih ' t is ' t ih v ss ck# ck t ih t is t ih setup slew rate rising signal setup slew rate falling signal tf tr tf = v ih(ac)min - v ref (dc) tr = v ddq t is nominal slew rate v ref to ac region v ref to ac region v ref (dc) - v il(ac)max v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min nominal slew rate setup slew rate rising signal tf tr tangent li ne (v ih[ac]min - v ref[dc] ) tr = tangent line tangent line v ref to ac region nominal line t ih t is t ih t is v ss ck# ck v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)max v il(ac)max v ref to ac region nominal line logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 17 - n ominal s lew r ate for t is f igure 18 - t angent l ine for t is tr tf nominal slew rate dc to v ref region t ih t is t is v ss ck# ck v ddq v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min dc to v ref region nominal slew rate t ih tangent line dc to v ref region t ih t is t is v ss v ddq v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min dc to v ref region tangent line t ih ck ck# hold slew rate falling signal tf tr (v ih [dc ]min - v ref[dc] ) tf = nominal line hold slew rate rising signal tangent line (v ref[dc] - v il [dc] max ) tr = nominal line tangent line logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 19 - n ominal s lew r ate for t ih f igure 20 - t angent l ine for t ih logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product t able 28 - ddr2-400/533 t ds, t dh d erating values with d ifferential s trobe dq slew rate v/ns 125 0 -11 - - - - 21 0 - - - - 125 0 -11 -25 - - - - 21 0 -31 - - - - - 95 12 1 -13 -31 - - - - 33 12 -2 -19 - - - - - 13 -1 -19 - - - - 10 -30 -59 - - - - - 25 11 -31 - - - - 22 5 - - - - - 23 5 -19 -62 - - - - -6 -35 - - - - - -50 -115 - - - - - 6 -23 -65 - - - - - - 5 -103 - - - - - - -11 -53 -116 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns 0.8v/ns dqsx, dqsx\ differential slew rate 21 0 - - - - - 125 0 - - - - - 1 2 7 ( 6 ) r u d o o l q s x w v l j q d o v w k h w r w d o t ' 6 d q g t ' + u h t x l u h g l v f d o f x o d w h g e \ d g g l q j w k h g d w d v k h h w y d o x h w r w k h g h u d w l q j y d o x h o l v w h g l q w k h d e r y h w d e o h t ' 6 q r p l q d o v o h z u d w h i r u d u l v l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 ref ' & d q g w k h i l u v w f u r v v l q j r i 9 ih $ & 0 , 1 t ' 6 q r p l q d o v o h z u d w h i r u d i l u v w f u r v v l q j r i 9 il $ & 0 $ ; ) l j x u h l i w k h d f w x d o v l j q d o l v d o z d \ v h d u o l h u w k d q w k h q r p l q d o v o h z u d w h o l q h e h w z h h q w k h v k d g h g v 9 ref ' & w r $ & u h j l r q w x v h w k h q r p l q d o v o h z u d w h i r u w k h g h u d w l q j y d o x h , i w k h d f w x d o v l j q d o l v o d w h u w k d q w k h q r p l q d o v o h z u d w h o l q h d q \ z k h u h e h w z h h q w k h v k d g h g v 9 ref ' & w r $ & u h j l r q w w k h v o h z u d w h r i d w d q j h q w o l q h w r w k h d f w x d o v l j q d o i u r p w k h $ & o h y h o w r w k h ' & o h y h o l v x v h g i r u w k h g h u d w l q j y d o x h ) l j x u h t ' + q r p l q d o v o h z u d w h i r u d u l v l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 il ' & 0 $ ; d q g w k h i l u v w f u r v v l q j r i 9 ref ' & t ' + q r p l q d o v o h z u d w h i r u d i d o o l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 ih ' & 0 , 1 d q g w k h i l u v w f u r v v - l q j r i 9 ref ' & , i w k h d f w x d o v l j q d o l v d o z d \ v o d w h u w k d q w k h q r p l q d o v o h z u d w h o l q h e h w z h h q w k h v k d g h g v ' & o h y h o w r 9 ref ' & u h j l r q w x v h w k h q r p l q d o v o h z u d w h i r u g h u d w l q j y d o x h ) l j x u h , i w k h d f w x d o v l j q d o l v h d u o l h u w k d q w k h q r p l q d o v o h z u d w h o l q h d q \ z k h u h e h w z h h q v k d g h g v ' & w r 9 ref ' & u h j l r q w w k h u d w h r i d w d q j h q w o l q h w r w k h d f w x d o v l j q d o i u r p w k h ' & o h y h o w r 9 ref ' & o h y h o l v x v h g i r u w k h g h u d w l q j y d o x h v h h ) l j x u h $ o w k r x j k w k h w r w d o v h w x s w l p h p l j k w e h q h j d w l y h i r u v o r z v o h z u d w h v d y d o l g l q s x w v l j q d o z l o o q r w k d y h u h d f k h g 9 ih > $ & @ 9 il > $ & @ d w w k h w l p h r i w k h u l v l q j f o r f n w u d q v l w l r q d y d o l g l q s x w v l j q d o l v v w l o o u h t x l u h g w r f r p - s o h w h w k h w u d q v l w l r q d q g u h d f k 9 ih $ & 9 il $ & ) r u v o h z u d w h v e h w z h h q w k h y d o x h v o l v w h g l q w k l v w d e o h w k h g h u d w l q j y d o x h v p d \ e h r e w d l q h g y l d o l q h d u l q w h u s r o d w l r q 7 k h v h y d o x h v d u h w \ s l f d o o \ q r w v x e m h f w w r s u r g x f w l r q w h v w 7 k h \ d u h y h u l - i l h g e \ g h v l j q d q g f k d u d f w h u l ] d w l r q 6 l q j o h h q g h g ' 4 6 [ u h t x l u h v v s h f l d o g h u d w l q j 7 k h y d o x h v l q 7 d e o h d u h w k h ' 4 6 v l q j o h h q g h g v o h z u d w h g h u d w l q j z l w k ' 4 6 u h i h u h q f h g d w 9 ref d q g ' 4 u h i h u h q f h g d w w k h o r j l f o h y h o v t ' 6 e d q g t ' + e & r q y h u w l q j w k h g h u d w h g e d v h y d o x h v i u r p ' 4 u h i h u h q f h g w r w k h $ & ' & w u l s s r l q w v w r ' 4 u h i h u h q f h g w r 9 ref l v o l v w h g l q 7 d e o h d q g 7 d e o h s u r y l g h v w k h 9 ref e d v h g i x o o \ g h u d w h g y d o x h v i r u w k h ' 4 t ' 6 d d q g t ' + d i r u ' ' 5 7 d e o h s u r y l g h v w k h 9 ref e d v h g i x o o \ g h u d w h g y d o x h v i r u w k h ' 4 t ' 6 d d q g t ' + d i r u ' ' 5 ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 50 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product t able 29 - ddr2-667/800 t ds, t dh d erating values with d ifferential s trobe dq slew rate v/ns 100 0 -5 -13 -22 -60 -100 63 0 -31 -125 100 0 -5 -13 -22 -60 -100 63 0 -31 -125 112 12 -1 -10 -22 12 -2 -19 -113 91 19 11 2 -10 -36 66 10 -30 -59 -101 136 103 36 31 23 2 99 36 22 5 -152 115 35 26 -12 -52 111 90 -6 -35 160 60 55 26 0 123 102 60 29 6 -23 -65 139 59 50 12 135 -11 -53 -116 4.0v/ns 3.0v/ns 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns 0.8v/ns dqsx, dqsx\ differential slew rate 63 0 -31 -125 100 0 -5 -13 -22 -60 -100 1 2 7 ( 6 ) r u d o o l q s x w v l j q d o v w k h w r w d o t ' 6 d q g t ' + u h t x l u h g l v f d o f x o d w h g e \ d g g l q j w k h g d w d v k h h w y d o x h w r w k h g h u d w l q j y d o x h o l v w h g l q w k h d e r y h w d e o h t ' 6 q r p l q d o v o h z u d w h i r u d u l v l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 ref ' & d q g w k h i l u v w f u r v v l q j r i 9 ih $ & 0 , 1 t ' 6 q r p l q d o v o h z u d w h i r u d i l u v w f u r v v l q j r i 9 il $ & 0 $ ; ) l j x u h l i w k h d f w x d o v l j q d o l v d o z d \ v h d u o l h u w k d q w k h q r p l q d o v o h z u d w h o l q h e h w z h h q w k h v k d g h g v 9 ref ' & w r $ & u h j l r q w x v h w k h q r p l q d o v o h z u d w h i r u w k h g h u d w l q j y d o x h , i w k h d f w x d o v l j q d o l v o d w h u w k d q w k h q r p l q d o v o h z u d w h o l q h d q \ z k h u h e h w z h h q w k h v k d g h g v 9 ref ' & w r $ & u h j l r q w w k h v o h z u d w h r i d w d q j h q w o l q h w r w k h d f w x d o v l j q d o i u r p w k h $ & o h y h o w r w k h ' & o h y h o l v x v h g i r u w k h g h u d w l q j y d o x h ) l j x u h t ' + q r p l q d o v o h z u d w h i r u d u l v l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 il ' & 0 $ ; d q g w k h i l u v w f u r v v l q j r i 9 ref ' & t ' + q r p l q d o v o h z u d w h i r u d i d o o l q j v l j q d o l v g h i l q h g d v w k h v o h z u d w h e h w z h h q w k h o d v w f u r v v l q j r i 9 ih ' & 0 , 1 d q g w k h i l u v w f u r v v - l q j r i 9 ref ' & , i w k h d f w x d o v l j q d o l v d o z d \ v o d w h u w k d q w k h q r p l q d o v o h z u d w h o l q h e h w z h h q w k h v k d g h g v ' & o h y h o w r 9 ref ' & u h j l r q w x v h w k h q r p l q d o v o h z u d w h i r u g h u d w l q j y d o x h ) l j x u h , i w k h d f w x d o v l j q d o l v h d u o l h u w k d q w k h q r p l q d o v o h z u d w h o l q h d q \ z k h u h e h w z h h q v k d g h g v ' & w r 9 ref ' & u h j l r q w w k h u d w h r i d w d q j h q w o l q h w r w k h d f w x d o v l j q d o i u r p w k h ' & o h y h o w r 9 ref ' & o h y h o l v x v h g i r u w k h g h u d w l q j y d o x h v h h ) l j x u h $ o w k r x j k w k h w r w d o v h w x s w l p h p l j k w e h q h j d w l y h i r u v o r z v o h z u d w h v d y d o l g l q s x w v l j q d o z l o o q r w k d y h u h d f k h g 9 ih > $ & @ 9 il > $ & @ d w w k h w l p h r i w k h u l v l q j f o r f n w u d q v l w l r q d y d o l g l q s x w v l j q d o l v v w l o o u h t x l u h g w r f r p - s o h w h w k h w u d q v l w l r q d q g u h d f k 9 ih $ & 9 il $ & ) r u v o h z u d w h v e h w z h h q w k h y d o x h v o l v w h g l q w k l v w d e o h w k h g h u d w l q j y d o x h v p d \ e h r e w d l q h g y l d o l q h d u l q w h u s r o d w l r q 7 k h v h y d o x h v d u h w \ s l f d o o \ q r w v x e m h f w w r s u r g x f w l r q w h v w 7 k h \ d u h y h u l - i l h g e \ g h v l j q d q g f k d u d f w h u l ] d w l r q 6 l q j o h h q g h g ' 4 6 u h t x l u h v v s h f l d o g h u d w l q j 7 k h y d o x h v l q 7 d e o h d u h w k h ' 4 6 v l q j o h h q g h g v o h z u d w h g h u d w l q j z l w k ' 4 6 u h i h u h q f h g d w 9 ref d q g ' 4 u h i h u h q f h g d w w k h o r j l f o h y h o v t ' 6 e d q g t ' + e & r q y h u w l q j w k h g h u d w h g e d v h y d o x h v i u r p ' 4 u h i h u h q f h g w r w k h $ & ' & w u l s s r l q w v w r ' 4 u h i h u h q f h g w r 9 ref l v o l v w h g l q 7 d e o h 7 d e o h s u r y l g h v w k h 9 ref e d v h g i x o o \ g h u d w h g y d o x h v i r u w k h ' 4 t ' 6 d d q g t ' + d i r u ' ' 5 , w l v q r w d g y l v h g w r r s h u d w h ' ' 5 g h y l f h v z l w k v l q j o h h q g h g ' 4 6 k r z h y h u 7 d e o h z r x o g e h x v h g z l w k w k h e d v h y d o x h v ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 51 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product t able 30 - s ingle -e nded dqs s lew r ate d erating v alues u sing t ds b , t dh b dq slew rate v/ns 130 30 25 5 53 32 -10 -93 -135 130 30 25 5 53 32 -10 -93 -135 130 30 25 5 53 32 -10 -93 -135 130 30 25 5 53 32 -10 -93 -135 112 32 20 -13 -63 -15 -29 -69 -203 155 122 55 50 30 -3 -53 -32 -102 -206 160 60 55 26 0 123 102 60 29 6 -23 -65 139 59 50 12 135 -11 -53 -116 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns 0.8v/ns 0.6v/ns 0.4v/ns dqsx single-ended slew rate derated (at v ref ) 53 32 -10 -93 -135 130 30 25 5 t able 31 - s ingle -e nded dqs s lew r ate f ully d erated (dqs, dq at v ref ) at ddr2-667 dq slew rate v/ns 330 330 330 391 522 291 290 290 290 290 290 290 290 330 330 330 391 522 291 290 290 290 290 290 290 290 330 330 330 391 522 291 290 290 290 290 290 290 290 330 330 330 391 522 291 290 290 290 290 290 290 290 362 355 355 355 392 365 365 365 392 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns 0.8v/ns 0.6v/ns 0.4v/ns dqsx single-ended slew rate derated (at v ref ) 291 290 290 290 290 290 290 290 330 330 330 391 522 t able 32 - s ingle -e nded dqs s lew r ate f ully d erated (dqs, dq at v ref ) at ddr2-533 dq slew rate v/ns 351 510 339 351 510 339 351 510 339 351 510 339 395 525 662 336 335 335 335 335 335 335 335 535 332 332 332 332 332 331 332 332 331 390 399 329 329 555 692 326 325 325 325 325 325 325 325 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns 0.8v/ns 0.6v/ns 0.4v/ns dqsx single-ended slew rate derated (at v ref ) 339 351 510 ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 52 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product t able 33 - s ingle -e nded dqs s lew r ate f ully d erated (dqs, dq at v ref ) at ddr2-400 dq slew rate v/ns 513 560 622 391 390 390 390 390 390 390 390 513 560 622 391 390 390 390 390 390 390 390 513 560 622 391 390 390 390 390 390 390 390 513 560 622 391 390 390 390 390 390 390 390 595 605 2.0v/ns 1.8v/ns 1.6v/ns 1.4v/ns 1.2v/ns 1.0v/ns 0.8v/ns 0.6v/ns 0.4v/ns dqsx single-ended slew rate derated (at v ref ) 391 390 390 390 390 390 390 390 513 560 622 ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh ' t ds ' t dh v ref to ac region v ref to ac region setup slew rate rising signal setup slew rate falling signal tf tr v ref(dc) - v il(ac)max tf = v ih(ac)min - v ref(dc) tr = nominal slew rate v ss dqs# 1 dqs 1 v ddq v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min t dh t ds nominal slew rate t dh t ds note: 1. dqs, dqs# signals must be monotonic between v il(dc)max and v ih(dc)min . tf tr setup slew rate rising signal setup slew rate falling signal tangent line (v ref[dc] - v il[ac]max ) tf = tangent line (v ih[ac]min - v ref[dc] ) tr = t dh t ds t dh t ds v ss dqs# 1 dqs 1 v ddq v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min nominal line tangent line nominal line tangent line v ref to ac region v ref to ac region note: 1. dqs, dqs# signals must be monotonic between v il(dc)max and v ih(dc)min. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 53 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 21 - n ominal s lew r ate for t ds f igure 22 - t angent l ine for t ds logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 23 - n ominal s lew r ate for t dh hold slew rate falling signal hold slew rate rising signal v ref(dc) - v il(dc)max tr = v ih(dc)min - v ref(dc) tf = tr tf nominal slew rate dc to v ref region t ih t is t is v ss dqs# 1 dqs 1 v ddq v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min dc to v ref region nominal slew rate t ih note: 1. dqs, dqs# signals must be monotonic between v il(dc)max and v ih(dc)min. f igure 24 - t angent l ine for t dh tangent line dc to v ref region t ih t is t is v ss v ddq v ih(dc)min v ref(dc) v il(ac)max v il(dc)max v ih(ac)min dc to v ref region tangent line t ih dqs 1 dqs# 1 hold slew rate falling signal tf tr tangent line (v ih[dc]min - v ref[dc] ) tf = nominal line hold slew rate rising signal tangent line (v ref[dc] - v il[dc]max ) tr = nominal line note: 1. dqs, dqs# signals must be monotonic between v il(dc)max and v ih(dc)min. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 55 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 25 - ac i nput t est s ignal w aveform c ommand /a ddress b alls t is a logic levels v ref levels t ih a t is a t ih a t is b t ih b t is b t ih b ck# ck v ddq v ih(ac)min v ih(dc)min v ref(dc) v il(dc)min v il(ac)min v ssq vswing (max) f igure 26 - ac i nput t est s ignal w aveform for d ata with dqs, dqs# (d ifferential ) dqs# dqs t ds a t dh a t ds a t dh a t ds b t dh b t ds b t dh b logic levels v ref levels v ref(dc) v il (dc)max v il (ac)max v ssq v ih(dc)min v ih(ac)min v ddq vswing (max) logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 56 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 27 - ac i nput t est s ignal w aveform for d ata with dqs (s ingle -e nded ) dqs v ref v ref(dc) v il(dc)max v il(ac)max v ssq v ih(dc)min v ih(ac)min v ddq vswing (max) logic levels v ref levels t ds a t dh a t ds a t dh a t ds b t dh b t ds b t dh b f igure 28 - ac i nput t est s ignal w aveform (d ifferential ) v tr vswing v cp v ddq v ssq v ix crossing point logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product p ackage o utline d imensions function cycle cycle cs\ ras\ cas\ we\ ba 1 -ba 0 a n -a 11 a 10 a 9 -a 10 notes load mode refresh self refresh ( 1 7 5 < self refresh ( ; , 7 precharge 6 , 1 * / ( % $ 1 . precharge $ / / % $ 1 . 6 bank activate write write z l w k $ 8 7 2 3 5 ( & + $ 5 * ( read read z l w k $ 8 7 2 3 5 ( & + $ 5 * ( no operation device deselect power-down ( 1 7 5 < power-down ( ; , 7 1-3 1-3 1-3,6 1-3 1-3 1-3 1-3,9 1-3,9 t able 34: t ruth t able - ddr2 c ommands l l l ; h l l l h h h h h ; ; h ; h l l l ; h h h h l l l l h ; ; h ; h l h h ; h l l h l l h h h ; ; h ; h % $ ; ; ; % $ ; % $ % $ % $ % $ % $ ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; l h l h l h ; ; ; ; ; ; ; ; ; ; ; ; ; h h l h h h h h h h h ; ; l h l l l h l l l l l l l l l h h l h l cke prev current d g g u h v v l q j g h s h q g l q j r q g h q v l w \ d q g f r q i l j x u d w l r q % d q n $ g g u h v v h v % $ g h w h u p l q h v z k l f k e d q n l v w r e h r s h u d w h g x s r q % $ g x u l q j d / 2 $ ' 0 2 ' ( f r p p d q g v h o h f w v z k l f k p r g h u h j l v w h u l v s u r j u d p p h g 6 ( / ) 5 ( ) 5 ( 6 + h [ l w l v d v \ q f k u r q r x v % x u v w 5 ( $ ' 6 r u : 5 , 7 ( 6 d w % / f d q q r w e h w h u p l q d w h g r u l q w h u - u x s w h g 7 k h 3 2 : ( 5 ' 2 : 1 p r g h g r h v q r w s h u i r u p d q \ 5 ( ) 5 ( 6 + r s h u d - w l r q v 7 k h g x u d w l r q r i 3 2 : ( 5 ' 2 : 1 l v o l p l w h g e \ w k h 5 ( ) 5 ( 6 + u h t x l u h p h q w v r x w o l q h g l q w k h $ & s d u d p h w u l f v h f w l r q 1 2 7 ( 6 $ o o ' ' 5 6 ' 5 $ 0 f r p p d q g v d u h g h i l q h g e \ v w d w h v r i & 6 ? 5 $ 6 ? & $ 6 ? : ( ? d q g & . ( d w w k h u l v l q j h g j h r i w k h f o r f n 7 k h v w d w h r i 2 ' 7 g r h v q r w d i i h f w w k h v w d w h v g h v f u l e h g l q w k l v w d e o h 7 k h 2 ' 7 i x q f w l r q l v q r w d y d l o d e o h g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + 6 h h 2 ' 7 w l p l q j i r u g h w d l o v v ; w g h q r w h v h l w k h u d v + w r u t / w e x w d g h i l q h g / 2 * , & / h y h o i r u y d o l g , dd p h d v x u h p h q w v % $ % $ i r u g h q v l w l h v x s w r * e p r g x o h v % $ l q f o x g h g i r u e d q n d g g u h v v r q t * e p r g x o h v $ q q l v w k h p r v w v l j q l i l f d q w d g g u h v v e l w i r u d j l y h q g h q v l w \ d q g f r q i l j x u d - w l r q 6 r p h o d u j h u d g g u h v v e l w v p d \ e h v ' 2 1 u 7 & $ 5 ( w g x u l q j f r o x p q commands truth table h h h l h h h h h h h h h h l & r o x p q $ g g u h v v & r o x p q $ g g u h v v & r o x p q $ g g u h v v & r o x p q $ g g u h v v & r o x p q $ g g u h v v & r o x p q $ g g u h v v & r o x p q $ g g u h v v & r o x p q $ g g u h v v 5 2 : $ g g u h v v 2 3 & r g h logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product current state any idle row active read $ x w r 3 u h f k d u j h ' l v d e o h g write $ x w r 3 u h f k d u j h ' l v d e o h g t able 35: t ruth t able - c urrent s tate b ank n - c ommand to b ank n ; h h h l h l l h h l h l l cs\ ras\ command/action notes deselect 1 2 3 f r q w l q x h s u h y l r x v r s h u d w l r q no operation 1 2 3 f r q w l q x h s u h y l r x v r s h u d w l r q activate v h o h f w d q g d f w l y d w h 5 2 : refresh load mode read v h o h f w & 2 / 8 0 1 d q g v w d u w 5 ( $ ' e x u v w write v h o h f w & 2 / 8 0 1 d q g v w d u w : 5 , 7 ( e x u v w precharge g h d f w l y d w h 5 2 : l q e d q n r u e d q n v read v h o h f w & 2 / 8 0 1 d q g v w d u w 5 ( $ ' e x u v w write v h o h f w & 2 / 8 0 1 d q g v w d u w : 5 , 7 ( e x u v w precharge v w d u w 3 5 ( & + $ 5 * ( read v h o h f w & 2 / 8 0 1 d q g v w d u w 5 ( $ ' e x u v w write v h o h f w & 2 / 8 0 1 d q g v w d u w : 5 , 7 ( e x u v w precharge v w d u w 3 5 ( & + $ 5 * ( 1-6 1-6 1-6 1-6,9 1-6,9 1-6,9 1 2 7 ( 6 7 k l v w d e o h d s s o l h v z k h q & . ( q z d v + , * + d q g & . ( q l v + , * + d q g d i w h u t ; 6 1 5 k d v e h h q p h w l i w k h s u h y l r x v v w d w h z d v 6 ( / ) 5 ( ) 5 ( 6 + 7 k l v w d e o h l v e d q n v s h f l i l f h [ f h s w z k h u h q r w h g w k h f x u u h q w v w d w h l v i r u d v s h f l i l f e d q n d q g w k h f r p p d q g v v k r z q d u h w k r v h d o o r z h g w r e h l v v x h g w r w k d w e d q n z k h q l q w k d w v w d w h ( [ f h s w l r q v d u h f r y h u h g l q w k h e h o r z & x u u h q w v w d w h g h i l q l w l r q v 7 k h i r o o r z l q j v w d w h v p x v w q r w e h l q w h u u x s w h g e \ d f r p p d q g l v v x h g w r w k h v d p h e d q n , v v x h ' ( 6 ( / ( & 7 r u 1 2 3 f r p p d q g v r u d o o r z d e o h f r p p d q g v w r w k h r w k h u e d q n r q d q \ f o r f n h g j h r f f x u u l q j g x u l q j w k h v h v w d w h v $ o o r z d e o h f r p p d q g v w r w k h r w k h u e d q n d u h g h w h u p l q h g e \ l w v f x u u h q w v w d w h d q g w k l v w d e o h d q g d f f r u g l q j w r 7 d e o h cas\ we\ ; h h l l l l h l l h l l h ; h l l l h h l h h l h h l h l l l l l l l l l l l l l idle: row active read write 7 k h e d q n k d v e h h q s u h f k d u j h g t 5 3 k d v e h h q p h w d q g d q \ 5 ( $ ' e x u v w l v f r p s o h w h $ 5 2 : l q d e d q n k d v e h h q d f w l y d w h g d q g t 5 & ' k d v e h h q p h w 1 r g d w d e x u v w v d f f h v v h v d q g q r u h j l v w h u d f f h v v h v d u h l q s u r j u h v v $ 5 ( $ ' e x u v w k d v e h h q l q l w l d w h g z l w k d x w r s u h f k d u j h g l v d e o h g d q g k d v q r w \ h w w h u p l q d w h g $ : 5 , 7 ( e x u v w k d v e h h q l q l w l d w h g z l w k d x w r s u h f k d u j h g l v d e o h g d q g k d v q r w \ h w w h u p l q d w h g precharge read w/ auto pre- charge enabled row activate write w/ auto pre- charge enabled 6 w d u w v z l w k u h j l v w u d w l r q r i d 3 5 ( & + $ 5 * ( f r p p d q g d q g h q g v z k h q t 5 3 l v p h w w k h e d q n z l o o e h l q w k h l g o h v w d w h 6 w d u w v z l w k u h j l v w u d w l r q r i d 5 ( $ ' f r p p d q g z l w k $ x w r 3 u h f k d u j h h q d e o h g d q g h q g v z k h q t 5 3 k d v e h h q p h w $ i w h u t 5 3 l v p h w w k h e d q n z l o o e h l q w k h l g o h v w d w h 6 w d u w v z l w k u h j l v w u d w l r q r i d : 5 , 7 ( f r p p d q g z l w k $ x w r 3 u h f k d u j h h q d e o h g d q g h q g v z k h q t 5 & ' l v p h w w k h e d q n z l o o e h l q w k h 5 2 : d f w l y h v w d w h 6 w d u w v z l w k u h j l v w u d w l r q r i d : 5 , 7 ( f r p p d q g z l w k $ x w r 3 u h f k d u j h h q d e o h g d q g h q g v z k h q t 5 3 k d v e h h q p h w $ i w h u t 5 3 l v p h w w k h e d q n z l o o e h l q w k h l g o h v w d w h logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 59 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product refresh accessing mode register precharge all 6 w d u w v z l w k u h j l v w u d w l r q r i d 5 ( ) 5 ( 6 + f r p p d q g d q g h q g v z k h q t 5 ) & l v p h w w k h ' ' 5 6 ' 5 $ 0 z l o o e h l q w k h d o o e d q n v l g o h v w d w h 6 w d u w v z l w k u h j l v w u d w l r q r i d w k h / 2 $ ' 0 2 ' ( f r p p d q g d q g h q g v z k h q t 0 5 ' k d v e h h q p h w $ i w h u t 0 5 ' l v p h w w k h ' ' 5 6 ' 5 $ 0 z l o o e h l q w k h d o o e d q n v l g o h v w d w h 6 w d u w v z l w k u h j l v w u d w l r q r i d 3 5 ( & + $ 5 * ( $ / / f r p p d q g d q g h q g v z k h q t 5 3 l v p h w $ i w h u t 5 3 l v p h w d o o e d q n v z l o o e h l q w k h l g o h v w d w h 7 k h i r o o r z l q j v w d w h p x v w q r w e h l q w h u u x s w h g e \ d q \ h [ h f x w d e o h f r p p d q g ' ( 6 ( / ( & 7 r u 1 2 3 f r p p d q g v p x v w e h d s s o l h g r q h d f k s r v l w l y h f o r f n h g j h g x u l q j w k h v h v w d w h v $ o o v w d w h v d q g v h t x h q f h v q r w v k r z q d u h l o o h j d o r u u h v h u y h g 1 r w e d q n v s h f l i l f u h t x l u h v w k d w d o o e d q n v d u h l g o h d q g e x u v w v d u h q r w l q s u r j u h v v 5 ( $ ' v r u : 5 , 7 ( v o l v w h g l q w k h & r p p d q g $ f w l r q f r o x p q l q f o x g h 5 ( $ ' v r u : 5 , 7 ( v z l w k $ 8 7 2 3 5 ( & + $ 5 * ( h q d e o h g d q g 5 ( $ ' v d q g : 5 , 7 ( v z l w k $ 8 7 2 3 5 ( & + $ 5 * ( g l v d e o h g 0 d \ r u p d \ q r w e h e d q n v s h f l i l f l i p x o w l s o h e d q n v d u h w r e h s u h f k d u j h g h d f k p x v w e h l q d y d o l g v w d w h i r u s u h f k d u j l q j $ : 5 , 7 ( f r p p d q g p d \ e h d s s o l h g d i w h u w k h f r p s o h w l r q r i w k h 5 ( $ ' e x u v w ; h ; h h l l h h l l h h l l h h l l h h l l command/action notes deselect 1 2 3 f r q w l q x h s u h y l r x v r s h u d w l r q no operation 1 2 3 f r q w l q x h s u h y l r x v r s h u d w l r q $ q \ f r p p d q g r w k h u z l v h d o o r z h g w r e d q n p activate v h o h f w d q g d f w l y d w h 5 2 : read v h o h f w & 2 / 8 0 1 d q g v w d u w 5 ( $ ' e x u v w write v h o h f w & 2 / 8 0 1 d q g v w d u w : 5 , 7 ( e x u v w precharge activate v h o h f w d q g d f w l y d w h 5 2 : read v h o h f w & 2 / 8 0 1 d q g v w d u w q h z 5 ( $ ' e x u v w write v h o h f w & 2 / 8 0 1 d q g v w d u w : 5 , 7 ( e x u v w precharge activate v h o h f w d q g d f w l y d w h 5 2 : read v h o h f w & 2 / 8 0 1 d q g v w d u w 5 ( $ ' e x u v w write v h o h f w & 2 / 8 0 1 d q g v w d u w q h z : 5 , 7 ( e x u v w precharge activate v h o h f w d q g d f w l y d w h 5 2 : read v h o h f w & 2 / 8 0 1 d q g v w d u w q h z 5 ( $ ' e x u v w write v h o h f w & 2 / 8 0 1 d q g v w d u w : 5 , 7 ( e x u v w precharge activate v h o h f w d q g d f w l y d w h 5 2 : read v h o h f w & 2 / 8 0 1 d q g v w d u w 5 ( $ ' e x u v w write v h o h f w & 2 / 8 0 1 d q g v w d u w q h z : 5 , 7 ( e x u v w precharge 1-6 1-6 1-6 1-6 1-6 1-6 1-6 1-6 1-6 1-6 1-6 1-6 1-6 cas\ we\ ; h ; h l l h h l l h h l l h h l l h h l l h current state any idle row active, active, or precharge read $ x w r 3 u h f k d u j h ' l v d e o h g write $ x w r 3 u h f k d u j h ' l v d e o h g read $ x w r 3 u h f k d u j h write $ x w r 3 u h f k d u j h t able 36: t ruth t able - c urrent s tate b ank n - c ommand to b ank m cs\ ras\ ; h ; l h h l l h h l l h h l l h h l l h h l h l ; l l l l l l l l l l l l l l l l l l l l n otes c ontinued logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 60 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 7 k l v w d e o h d s s o l h v z k h q & . ( q z d v + , * + d q g & . ( q l v + , * + d q g d i w h u t ; 6 1 5 k d v e h h q p h w l i w k h s u h y l r x v v w d w h z d v 6 ( / ) 5 ( ) 5 ( 6 + 7 k l v w d e o h l v e d q n v s h f l i l f h [ f h s w z k h u h q r w h g w k h f x u u h q w v w d w h l v i r u d v s h f l i l f e d q n d q g w k h f r p p d q g v v k r z q d u h w k r v h d o o r z h g w r e h l v v x h g w r w k d w e d q n z k h q l q w k d w v w d w h ( [ f h s w l r q v d u h f r y h u h g l q w k h e h o r z & x u u h q w v w d w h g h i l q l w l r q v 7 k h p l q l p x p g h o d \ i u r p d 5 ( $ ' r u : 5 , 7 ( f r p p d q g z l w k $ 8 7 2 3 5 ( & + $ 5 * ( h q d e o h g w r d f r p p d q g w r d g l i i h u h q w e d q n l v v x p p d u l ] h g l q 7 d e o h 5 ( ) 5 ( 6 + d q g / 2 $ ' 0 2 ' ( f r p p d q g v p d \ r q o \ e h l v v x h g z k h q d o o e d q n v d u h l g o h 1 r w 8 v h g $ o o v w d w h v d q g v h t x h q f h v q r w v k r z q d u h l o o h j d o r u u h v h u y h g 5 ( $ ' v d q g : 5 , 7 ( v o l v w h g l q w k h & r p p d q g $ f w l r q f r o x p q l q f o x g h 5 ( $ ' v r u : 5 , 7 ( v z l w k $ 8 7 2 3 5 ( & + $ 5 * ( h q d e o h g d q g 5 ( $ ' v r u : 5 , 7 ( v z l w k $ 8 7 2 3 5 ( & + $ 5 * ( g l v d e o h g $ : 5 , 7 ( f r p p d q g p d \ e h d s s o l h g d i w h u w k h f r p s o h w l r q r i w k h 5 ( $ ' e x u v w 5 h t x l u h v d s s u r s u l d w h ' 0 7 k h q x p e h u r i f o r f n f \ f o h v u h t x l u h g w r p h h w t : 7 5 l v h l w k h u w z r r u t : 7 5 t & . z k l f k h y h u l v j u h d w h u idle: row active read write read z l w k auto precharge h q d e o h g write z l w k auto precharge h q d e o h g 7 k h e d q n k d v e h h q s u h f k d u j h g t 5 3 k d v e h h q p h w d q g d q \ 5 ( $ ' e x u v w l v f r p s o h w h $ 5 2 : l q d e d q n k d v e h h q d f w l y d w h g d q g t 5 & ' k d v e h h q p h w 1 r g d w d e x u v w v d f f h v v h v d q g q r u h j l v w h u d f f h v v h v d u h l q s u r j u h v v $ 5 ( $ ' e x u v w k d v e h h q l q l w l d w h g z l w k d x w r s u h f k d u j h g l v d e o h g d q g k d v q r w \ h w w h u p l q d w h g $ : 5 , 7 ( e x u v w k d v e h h q l q l w l d w h g z l w k d x w r s u h f k d u j h g l v d e o h g d q g k d v q r w \ h w w h u p l q d w h g 7 k h 5 ( $ ' z l w k $ x w r 3 u h f k d u j h h q d e o h g r u : 5 , 7 ( z l w k $ x w r 3 u h f k d u j h h q d e o h g v w d w h v f d q e h e u r n h q l q w r w z r s d u w v w k h d f f h v v s h u l r g d q g w k h 3 u h f k d u j h s h u l r g ) r u 5 ( $ ' z l w k $ x w r 3 u h f k d u j h w k h s u h f k d u j h s h u l r g l v g h i l q h g d v l i w k h v d p h e x u v w z d v h [ h f x w h g z l w k $ x w r 3 u h f k d u j h g l v d e o h g d q g w k h q i r o o r z h g z l w k w k h h d u o l h v w s r v v l e o h 3 5 ( & + $ 5 * ( f r p p d q g w k d w v w l o o d f f h v v h v d o o r i w k h g d w d l q w k h e x u v w ) r u : 5 , 7 ( z l w k $ x w r 3 u h f k d u j h w k h s u h f k d u j h s h u l r g e h j l q v z k h q t : 5 h q g v z l w k t : 5 p h d v x u h g d v l i $ x w r 3 u h f k d u j h z d v g l v d e o h g 7 k h d f f h v v s h u l r g v w d u w v z l w k u h j l v w u d w l r q r i w k h f r p p d q g d q g h q g v z k h u h w k h s u h f k d u j h period (or t 5 3 e h j l q v 7 k l v g h y l f h v x s s r u w v f r q f x u u h q w $ x w r 3 u h f k d u j h v x f k w k d w z k h q d 5 ( $ ' z l w k $ x w r 3 u h f k d u j h l v h q d e o h g r u d : 5 , 7 ( z l w k $ x w r 3 u h f k d u j h l v h q d e o h g d q \ f r p p d q g w r r w k h u e d q n v l v d o o r z h g d v o r q j d v w k d w f r p p d q g g r h v q r w l q w h u u x s w w k h 5 ( $ ' r u : 5 , 7 ( g d w d w u d q v i h u d o u h d g \ l q s u r f h v v , q h l w k h u f d v h d o o r w k h u u h o d w h g o l p l w d w l r q v d s s o \ f r q w h q w l r q e h w z h h q 5 ( $ ' g d w d d q g : 5 , 7 ( g d w d p x v w e h d y r l g h g from command (bank n) write with auto precharge read with auto precharge t able 37: m inimum d elay with a uto p recharge e nabled minimum delay (with concurrent auto pre- charge) units (cl - 1) + (bl/2) + t wtr (bl/2) 1 (bl/2) (bl/2) + 2 1 t ck t ck 5 ( $ ' r u 5 ( $ ' z l w k $ x w r 3 u h f k d u j h : 5 , 7 ( r u : 5 , 7 ( z l w k $ x w r 3 u h f k d u j h 3 5 ( & + $ 5 * ( r u $ & 7 , 9 $ 7 ( 5 ( $ ' 2 5 5 ( $ ' : , 7 + $ x w r 3 u h f k d u j h : 5 , 7 ( r u : 5 , 7 ( z l w k $ x w r 3 u h f k d u j h 3 5 ( & + $ 5 * ( r u $ & 7 , 9 $ 7 ( to command (bank m) n otes logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 61 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 7 k h ' ( 6 ( / ( & 7 i x q f w l r q & 6 ? + , * + s u h y h q w v q h z f r p p d q g v i u r p e h l q j h [ h f x w h g e \ w k h ' ' 5 6 ' 5 $ 0 7 k h ' ' 5 6 ' 5 $ 0 l v h i i h f w l y h o \ g h v h o h f w h g 2 s h u d w l r q v d o u h d g \ l q s u r j u h v v d u h q r w d i i h f w h g ' ( 6 ( / ( & 7 l v d o v r u h i h u u h g w r d v & 2 0 0 $ 1 ' , 1 + , % , 7 deselect 7 k h 3 5 ( & + $ 5 * ( f r p p d q g l v x v h g w r g h d f w l y d w h w k h r s h q u r z l q d s d u - w l f x o d u e d q n r u w k h r s h q u r z l q d o o e d q n v 7 k h e d q n v z l o o e h d y d l o d e o h i r u v x e v h t x h q w u r z d f w l y d w l r q d w d v s h f l i l h g w l p h t 5 3 d i w h u w k h 3 5 ( & + $ 5 * ( f r p p d q g l v l v v x h g h [ f h s w l q w k h f d v h r i f r q f x u u h q w $ 8 7 2 3 5 ( & + $ 5 * ( z k h u h d 5 ( $ ' r u : 5 , 7 ( f r p p d q g w r d g l i i h u h q w e d q n l v d o o r z h g d v o r q j d v l w g r h v q r w l q w h u u x s w w k h g d w d w u d q v i h u l q w k h f x u u h q w e d q n d q g g r h v q r w y l r o d w h d q \ r w k h u w l p l q j s d u d p h w h u v $ i w h u d e d q n k d v e h h q s u h f k d u j h g l w l v l q w k h l g o h v w d w h d q g p x v w e h d f w l y d w h g s u l r u w r d q \ 5 ( $ ' d q g r u : 5 , 7 ( f r p p d q g v e h l q j l v v x h g w r d e d q n l g o h v w d w h r u l i w k h s u h y l r x v o \ r s h q u r z l v d o u h d g \ l q w k h s u r f h v v r i s u h f k d u j l q j + r z h y h u w k h 3 5 ( & + $ 5 * ( s h u l r g z l o o e h g h w h u p l q h g e \ w k h o d v w 3 5 ( & + $ 5 * ( f r p p d q g l v v x h g w r w k h e d q n precharge 7 k h 1 2 2 3 ( 5 $ 7 , 2 1 1 2 3 f r p p d q g l v x v h g w r l q v w u x f w w k h v h o h f w h g ' ' 5 g h y l f h w r s h u i r u p d 1 2 3 & 6 ? l v / 2 : 5 $ 6 ? & $ 6 ? d q g : ( ? d u h + , * + 7 k l v s u h y h q w v x q z d q w h g f r p p d q g v i u r p e h l q j u h j l v w h u h g g x u l q j l g o h r u z d l w v w d w h v 2 s h u d w l r q v d o u h d g \ l q s u r j u h v v d u h q r w d i i h f w h g no operation (nop) 7 k h : 5 , 7 ( f r p p d q g l v x v h g w r l q l w l d w h d e x u v w : 5 , 7 ( d f f h v v w r d q d f w l y h u r z 7 k h y d o x h r q w k h e d q n v h o h f w l q s x w v v h o h f w v w k h e d q n d q g w k h d g g u h v v r q w k h d g g u h v v l q s x w v $ 0 $ i z k h u h $ i l v w k h p r v w v l j q l i l f d q w f r o x p q d g g u h v v e l w i r u d j l y h q f r q i l j x u d w l r q v h o h f w w k h v w d u w l q j f r o x p q o r f d w l r q 7 k h y d o x h r q l q s x w $ 10 g h w h u p l q h v z k h w k h u r u q r w $ 8 7 2 3 5 ( & + $ 5 * ( l v x v h g , i $ 8 7 2 3 5 ( & + $ 5 * ( l v v h o h f w h g w k h u r z e h l q j d f f h v v h g z l o o e h s u h f k d u j h g d w w k h h q g r i : 5 , 7 ( e x u v w l i $ 8 7 2 3 5 ( & + $ 5 * ( l v q r w v h o h f w h g w k h u r z z l o o u h p d l q r s h q i r u v x e v h t x h q w d f f h v v h v / 2 * , & u v ' ' 5 l 0 2 ' v d o v r v x s s r u w w k h $ / i h d w x u h z k l f k d o o r z v : 5 , 7 ( r u 5 ( $ ' f r p p d q g v w r e h l v v x h g s u l r u w r t 5 & ' 0 , 1 e \ g h o d \ l q j w k h d f w x d o u h j l v w u d - w l r q r i w k h 5 ( $ ' : 5 , 7 ( f r p p d q g w r w k h l q w h u q d o g h y l f h e \ $ / f o r f n f \ f o h v , q s x w g d w d d s s h d u l q j r q w k h ' 4 u v l v z u l w w h q w r w k h p h p r u \ d u u d \ v x e m h f w w r w k h ' 0 l q s x w o r j l f o h y h o d s s h d u l q j f r l q f l g h q w z l w k w k h g d w d , i d j l y h q ' 0 v l j q d o l v u h j l v w h u h g / 2 : w k h f r u u h v s r q g l q j g d w d z l o o e h z u l w w h q w r p h p r u \ l i w k h ' 0 v l j q d o l v u h j l v w h u h g + , * + w k h f r u u h v s r q g l q j g d w d l q s x w v z l o o e h l j q r u h g d q g d : 5 , 7 ( z l o o q r w e h h [ h f x w h g w r w k d w e \ w h f r o x p q o r f d w l r q write 7 k h p r g h u h j l v w h u v d u h o r d g h g y l d e d q n d g g u h v v d q g d g g u h v v l q s x w v 7 k h e d q n d g g u h v v e d o o v g h w h u p l q h z k l f k p r g h u h j l v w h u z l o o e h s u r j u d p p h g 7 k h / 0 f r p p d q g f d q r q o \ e h l v v x h g z k h q d o o e d q n v d u h l g o h d q g d v x e - v h t x h q w h [ h f x w d e o h f r p p d q g f d q q r w e h l v v x h g x q w l o t 0 5 ' l v p h w load mode (lm) 7 k h $ & 7 , 9 $ 7 ( f r p p d q g l v x v h g w r r s h q r u d f w l y d w h d u r z l q d s d u w l f x o d u e d q n i r u d v x e v h t x h q w d f f h v v 7 k h y d o x h r q w k h e d q n d g g u h v v l q s x w v g h w h u - p l q h v w k h e d q n d q g w k h d g g u h v v l q s x w v v h o h f w w k h u r z 7 k l v u r z u h p d l q v d f w l y h r u r s h q i r u d f f h v v h v x q w l o d s u h f k d u j h f r p p d q g l v l v v x h g w r w k d w e d q n $ s u h f k d u j h f r p p d q g p x v w e h l v v x h g e h i r u h r s h q l q j d g l i i h u h q w u r z l q w k h v d p h e d q n activate 7 k h 5 ( $ ' f r p p d q g l v x v h g w r l q l w l d w h d e x u v w 5 ( $ ' d f f h v v w r d q d f w l y h u r z 7 k h y d o x h r q w k h e d q n d g g u h v v l q s x w v g h w h u p l q h w k h e d q n d q g w k h d g g u h v v s u r y l g h g r q w k h d g g u h v v l q s x w v $ 0 $ i z k h u h $ i l v w k h p r v w v l j - q l i l f d q w f r o x p q d g g u h v v e l w i r u d j l y h q f r q i l j x u d w l r q v h o h f w v w k h v w d u w l q j f r o x p q o r f d w l r q 7 k h y d o x h r q l q s x w $ g h w h u p l q h v z k h w k h u r u q r w $ 8 7 2 3 5 ( & + $ 5 * ( l v x v h g , i $ 8 7 2 3 5 ( & + $ 5 * ( l v q r w v h o h f w h g w k h u r z z l o o u h p d l q r s h q i r u v x e v h t x h q w d f f h v v h v / 2 * , & u v ' ' 5 l 0 2 ' v d o v r v x s - s r u w w k h $ / i h d w x u h z k l f k d o o r z v d 5 ( $ ' r u : 5 , 7 ( f r p p d q g w r e h l v v x h g s u l r u w r t 5 & ' 0 , 1 e \ g h o d \ l q j w k h d f w x d o u h j l v w u d w l r q r i w k h 5 ( $ ' : 5 , 7 ( f r p p d q g w r w k h l q w h u q d o g h y l f h e \ $ / f o r f n f \ f o h v read 5 ( ) 5 ( 6 + l v v x h g g x u l q j q r u p d o r s h u d w l r q r i / 2 * , & u v ' ' 5 l 0 2 ' d q g l v d q d o r j r x v w & $ 6 ? e h i r u h 5 $ 6 ? & % 5 5 ( ) 5 ( 6 + $ o o e d q n v p x v w e h l q w k h l g o h p r g h s u l r u w r l v v x l q j d 5 ( ) 5 ( 6 + f r p p d q g 7 k l v f r p p d q g l v q r q s h u v l v w h q w v r l w p x v w e h l v v x h g h d f k w l p h d 5 ( ) 5 ( 6 + f r p p d q g l v u h t x l u h g 7 k h d g g u h v v l q j l v j h q h u d w h g e \ w k h l q w h u q d o u h i u h v k f r q w u r o o h u 7 k l v p d n h v w k h d g g u h v v e l w v d v ' r q u w & d u h w g x u l q j d 5 ( ) 5 ( 6 + f r p p d q g refresh 7 k h 6 ( / ) 5 ( ) 5 ( 6 + f r p p d q g f d q e h x v h g w r u h w d l q g d w d l q / 2 * , & u v ' ' 5 l 0 2 ' h y h q l i w k h u h v w r i w k h v \ v w h p l v s r z h u h g g r z q : k h q l q w k h 6 ( / ) 5 ( ) 5 ( 6 + p r g h w k h ' ' 5 g h y l f h u h w d l q v g d w d z l w k r x w h [ w h u q d o f o r f n l q j $ o o s r z h u v x s s o \ l q s x w v l q f o x g l q j 9 ref p x v w e h p d l q w d l q h g d w y d o l g o h y h o v x s r q h q w u \ h [ l w d q g g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + r s h u d w l r q self refresh 7 k h 0 2 ' ( 5 ( * , 6 7 ( 5 l v x v h g w r g h i l q h w k h v s h f l i l f p r g h r i r s h u d w l r q r i / 2 * , & u v ' ' 5 l 0 2 ' 7 k l v g h i l q l w l r q l q f o x g h v w k h v h o h f w l r q r i d e x u v w o h q j w k e x u v w w \ s h & $ 6 o d w h q f \ r s h u d w l q j p r g h ' / / 5 ( 6 ( 7 : 5 , 7 ( u h f r y h u \ d q g 3 2 : ( 5 ' 2 : 1 p r g h d v v k r z q l q ) l j x u h & r q w h q w v r i w k h 0 2 ' ( 5 ( * , 6 7 ( 5 f d q e h d o w h u h g e \ u h h [ h f x w l q j w k h / 2 $ ' 0 2 ' ( / 0 f r p p d q g , i w k h x v h u f k r r v h v w r p r g l i \ r q o \ d v x e v h w r i w k h 0 5 y d u l d e o h v d o o y d u l d e o h v p x v w e h s u r j u d p p h g z k h q w k h f r p p d q g l v l v v x h g 7 k h 0 5 l v s u r j u d p p h g y l d w k h / 0 f r p p d q g d q g z l o o u h w d l q w k h v w r u h g l q i r u p d w l r q x q w l o l w l v s u r j u d p p h g d j d l q r u x q w l o w k h g h y l f h o r v h v s r z h u h [ f h s w i r u e l w 0 z k l f k l v 6 ( / ) & / ( $ 5 , 1 * 5 h s u r j u d p p l q j w k h p r g h u h j l v w h u z l o o q r w d o w h u w k h f r q w h q w v r i w k h p h p r u \ d u u d \ s u r y l g h g l w l v s h u - i r u p h g f r u u h f w o \ 7 k h / 0 f r p p d q g f d q r q o \ e h l v v x h g r u u h l v v x h g z k h q d o o e d q n v d u h l q w k h 3 5 ( & + $ 5 * ( ' v w d w h l g o h v w d w h d q g q r e x u v w v d u h l q s u r j u h v v 7 k h 0 h p r u \ f r q w u r o o h u p x v w z d l w w k h v s h f l i l h g w l p h t 0 5 ' e h i r u h l q l w l d w l q j d q \ v x e v h t x h q w r s h u d w l r q v v x f k d v d q $ & 7 , 9 $ 7 ( f r p p d q g 9 l r - o d w l q j h l w k h u r i w k h v h u h t x l u h p h q w v z l o o u h v x o w l q d q x q v s h f l i l h g r s h u d w l r q mode register (mr) burst length cas# bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 76543 8 210 a10 a12 a11 ba0 ba1 10 11 12 n 0 0 14 burst length reserved reserved 4 8 reserved reserved reserved reserved m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 0 1 burst type sequential interleaved m3 cas latency (cl) reserved reserved reserved 3 4 5 6 7 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 0 1 mode normal test m7 15 dll tm 0 1 dll reset no yes m8 write recovery reserved 2 3 4 5 6 7 8 m9 0 1 0 1 0 1 0 1 m10 0 0 1 1 0 0 1 1 m11 0 0 0 0 1 1 1 1 wr an 2 mr m14 0 1 0 1 mode register definition mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) m15 0 0 1 1 m12 0 1 pd mode fast exit (normal) slow exit (low power) latency 16 ba2 1 % x u v w o h q j w k l v g h i l q h g e \ e l w v 0 0 -m 2 d v v k r z q l q ) l j x u h 5 ( $ ' d q g : 5 , 7 ( d f f h v v h v w r w k h ' ' 5 g h y l f h d u h e x u v w r u l h q w h g z l w k % 8 5 6 7 / ( 1 * 7 + e h l q j s u r j u d p p d e o h w r h l w k h u i r x u r u h l j k w 7 k h % 8 5 6 7 / ( 1 * 7 + g h w h u p l q h v w k h p d [ l p x p q x p e h u r i f r o x p q o r f d w l r q v w k d w f d q e h d f f h v v h g i r u d j l y h q 5 ( $ ' r u : 5 , 7 ( f r p p d q g : k h q d 5 ( $ ' r u : 5 , 7 ( f r p p d q g l v l v v x h g d e o r f n r i f r o x p q v h t x d o w r w k h % 8 5 6 7 / ( 1 * 7 + l v h i i h f w l y h o \ v h o h f w h g $ o o d f f h v v h v i r u w k d w % 8 5 6 7 w d n h s o d f h z l w k l q w k l v e o r f n p h d q l q j w k d w w k h e x u v w z l o o z u d s z l w k l q w k h e o r f n l i d e r x q g d u \ l v u h d f k h g 7 k h e o r f n l v x q l t x h o \ v h o h f w h g e \ $ 0 $ i z k h q % / d q g e \ $ 3 $ l z k h q % / z k h u h $ l l v w k h p r v w v l j q l i l f d q w f r o x p q d g g u h v v e l w i r u d j l y h q f r q i l j x u d w l r q 7 k h u h p d l q l q j o h d v w v l j q l i l f d q w d g g u h v v e l w v l v d u h x v h g w r v h o h f w w k h v w d u w l q j o r f d w l r q z l w k l q w k h e o r f n 7 k h s u r j u d p p h g e x u v w o h q j w k d s s o l h v w r e r w k 5 ( $ ' d q g : 5 , 7 ( e x u v w v burst length f igure 29 - mr d efinitions 1 r w h v 0 % $ l v r q o \ d s s o l f d e o h i r u g h q v l w l h v ? * e u h v h u y h g i r u i x w x u h x v h d q g p x v w e h s u r j u d p p h g w r 3 0 r g h e l w v 0 q z l w k f r u u h v s r q g l q j d g g u h v v e d o o v $ q j u h d w h u w k d q 0 $ d u h u h v h u y h g i r u i x w x u h x v h d q g p x v w e h s u r j u d p p h g w r 3 1 r w d o o o l v w h g : 5 d q g & / r s w l r q v d u h v x s s r u w h g l q d q \ l q g l y l g x d o v s h h g j u d g h logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 62 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product burst length address (a[2,1,0]) type = sequential type = interleav ed 0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0 t able 38: b urst d efinition order of accesses within a burst 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 100 101 110 111 starting column logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 63 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product $ f f h v v h v z l w k l q d j l y h q e x u v w p d \ e h s u r j u d p p h g w r e h h l w k h u v h t x h q w l d o r u l q w h u o h d y h g 7 k h % 8 5 6 7 7 < 3 ( l v v h o h f w h g y l d e l w 0 3 d v v k r z q l q ) l j x u h 7 k h r u g h u l q j r i d f f h v v h v z l w k l q d e x u v w l v g h w h u p l q h g e \ w k h % 8 5 6 7 / ( 1 * 7 + % 8 5 6 7 7 < 3 ( d q g w k h v w d u w l q j f r o x p q d g g u h v v d v v k r z q l q 7 d e o h / 2 * , & u v ddr2 imod burst type 7 k h q r u p d o r s h u d w l q j p r g h l v v h o h f w h g e \ l v v x l q j d f r p p d q g z l w k e l w 0 v h w w r v w d q g d o o r w k h u e l w v v h w w r w k h g h v l u h g y d o x h v d v v k r z q l q ) l j x u h : k h q e l w 0 l v v w q r r w k h u e l w v r i w k h 0 2 ' ( 5 ( * , 6 7 ( 5 d u h s u r j u d p p h g 3 u r j u d p p l q j e l w 0 w r v w s o d f h v w k h ' ' 5 l 0 2 ' l q w r d w h v w p r g h w k d w l v r q o \ x v h g e \ w k h p d q x i d f w x u h u d q g v k r x o g q r w e h x v h g 1 r r s h u d w l r q r u i x q f w l r q d o l w \ l v j x d u d q w h h g l i 0 e l w l v v w operating mode : 5 , 7 ( 5 ( & 2 9 ( 5 < : 5 w l p h l v g h i l q h g e \ e l w v 0 9 -m 11 d v v k r z q l q ) l j x u h 7 k h : 5 u h j l v w h u l v x v h g e \ w k h ' ' 5 l 0 2 ' g x u l q j : 5 , 7 ( z l w k $ 8 7 2 3 5 ( & + $ 5 * ( r s h u d w l r q ' x u l q j : 5 , 7 ( z l w k $ 8 7 2 3 5 ( & + $ 5 * ( r s h u d w l r q w k h ' ' 5 l 0 2 ' g h o d \ v w k h l q w h u q d o $ 8 7 2 3 5 ( & + $ 5 * ( r s h u d - w l r q e \ : 5 f o r f n v s u r j u d p p h g l q e l w v 0 9 -m 11 i u r p w k h o d v w g d w d e x u v w : 5 y d o x h v r i r u f o r f n v p d \ e h x v h g i r u s u r j u d p p l q j e l w v 0 9 -m 11 7 k h x v h u l v u h t x l u h g w r s u r j u d p w k h y d o x h r i : 5 z k l f k l v f d o f x o d w h g e \ g l y l g l q j t : 5 l q q d q r v h f r q g v e \ t & . l q q d q r v h f r q g v d q g u r x q g l q j x s d q r q l q w h j h u y d o x h w r w k h q h [ w l q w h j h u : 5 f \ f o h v t : 5 q v t & / q v 5 h v h u y h g v w d w h v v k r x o g q r w e h x v h g d v d q x q n q r z q r s h u d w l r q r u l q f r p s d w l e l o l w \ z l w k i x w x u h y h u v l r q v p d \ u h v x o w write recovery ' / / 5 ( 6 ( 7 l v g h i l q h g e \ e l w 0 d v v k r z q l q ) l j x u h 3 u r j u d p p l q j e l w m w r v w z l o o d f w l y d w h w k h ' / / 5 ( 6 ( 7 i x q f w l r q % l w 0 l v 6 ( / ) & / ( $ 5 , 1 * p h d q l q j l w u h w x u q v e d f n w r d y d o x h r i v w d i w h u w k h ' / / 5 ( 6 ( 7 i x q f w l r q k d v e h h q l v v x h g $ q \ w l p h w k h ' / / 5 ( 6 ( 7 i x q f w l r q l v x v h g f o r f n f \ f o h v p x v w r f f x u e h i r u h d 5 ( $ ' f r p p d q g f d q e h l v v x h g w r d o o r z w l p h i r u w k h l q w h u q d o f o r f n w r e h v \ q f k u r q l ] h g z l w k w k h h [ w h u q d o f o r f n ) d l o l q j w r z d l w i r u w k h u h t x l u h g f o r f n f \ f o h v z k l f k v \ q f k u r q l ] h v w k h ' / / p d \ u h v x o w l q d y l r o d w l r q r i w k h t $ & r u t ' 4 6 & . s d u d p h w h u v dll reset do n + 3 do n + 2 do n + 1 ck ck# command dq dqs, dqs# cl = 3 (al = 0) read t0 t1 t2 dont care transitioning data nop nop nop do n t3 t4 t5 nop nop t6 nop do n + 3 do n + 2 do n + 1 ck ck# command dq dqs, dqs# cl = 4 (al = 0) read t0 t1 t2 nop nop nop do n t3 t4 t5 nop nop t6 nop notes: 1. bl = 4. 2. posted cas# additive latency (al) = 0. 3. shown with nominal t ac, t dqsck, and t dqsq. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 30 - cl $ f w l y h 3 2 : ( 5 ' 2 : 1 3 ' p r g h l v g h i l q h g e \ e l w 0 12 d v v k r z q l q ) l j x u h 3 ' p r g h h q d e o h v w k h x v h u w r g h w h u p l q h w k h d f w l y h s r z h u g r z q p r g h z k l f k g h w h u p l q h v s h u i r u p d q f h y h u v x v s r z h u v d y l q j v 3 ' p r g h e l w 0 12 g r h v q r w d s s o \ w r 3 5 ( & + $ 5 * ( 3 ' p r g h : k h q e l w 0 12 v w d q g d u g d f w l y h 3 ' p r g h r u v i d v w h [ l w w d f w l y h 3 ' p r g h l v h q d e o h g 7 k h w ; $ 5 ' s d u d p h w h u l v x v h g i r u i d v w h [ l w w l p l q j 7 k h ' / / l v h [ s h f w h g w r e h h q d e o h g d q g u x q q l q j g x u l q j w k l v p r g h : k h q e l w 0 12 d o r z h u s r z h u d f w l y h 3 ' p r g h r u v v o r z h [ l w w d f w l y h 3 ' p r g h l v h q d e o h g 7 k h t ; $ 5 ' 6 s d u d p h w h u l v x v h g i r u w k h v o r z h [ l w d f w l y h 3 ' h [ l w w l p l q j 7 k h ' / / f d q e h h q d e o h g e x w v i u r ] h q w g x u l q j $ & 7 , 9 ( 3 ' p r g h e h f d x v h w k h h [ l w w r 5 ( $ ' f r p p d q g w l p l q j l v u h o d [ h g 7 k h s r z h u g l i i h u h q f h h [ s h f w h g e h w z h h q , dd 3 q r u p d o d q g , dd 3 o r z s r z h u p r g h l v g h i l q h g l q w k h ' ' 5 , dd 6 s h f l i l f d w l r q v d q g & r q g l w l r q v w d e o h 7 k h & $ 6 / $ 7 ( 1 & < & / l v g h i l q h g e \ e l w v 0 -m 6 d v v k r z q l q ) l j x u h & / l v w k h g h o d \ l q f o r f n f \ f o h v e h w z h h q w k h u h j l v w u d w l r q r i d 5 ( $ ' f r p - p d q g d q g w k h d y d l o d e l o l w \ r i w k h i l u v w e l w r i r x w s x w g d w d 7 k h & / f d q e h v h w w r r u f o r f n v g h s h q g l q j r q w k h v s h h g j u d g h r s w l r q r i w k h l 0 2 ' e h l q j x v h g 7 k h / 2 * , & ' ' 5 l 0 2 ' g r h v q r w v x s s r u w d q \ k d o i f o r f n o d w h q f l h v 5 h v h u y h g v w d w h v v k r x o g q r w e h x v h g d v d q x q n q r z q v w d w h r u r s h u d w l r q r u l q f r p s d w l e l o l w \ z l w k i x w x u h u h y l v l r q v p d \ u h v x o w 7 k h ' ' 5 l 0 2 ' d o v r v x s s r u w v d i h d w x u h f d o o h g s r v w h g & $ 6 d g g l w l y h o d w h q f \ $ / 7 k l v i h d w x u h d o o r z v w k h 5 ( $ ' f r p p d q g w r e h l v v x h g s u l r u to t 5 & ' 0 , 1 e \ g h o d \ l q j w k h l q w h u q d o f r p p d q g w r w k h ' ' 5 l 0 2 ' e \ $ / f o r f n v 7 k h $ / i h d w x u h l v g h v f u l e h g l q i x u w k h u g h w d l o l q w k h 3 r v w h g & $ 6 $ g g l - w l y h / d w h q f \ g h v f u l s w l r q ( [ d p s o h v r i & / d q g & / d u h v k r z q l q ) l j x u h e r w k d v v x p h $ / , i d 5 ( $ ' f r p p d q g l v u h j l v w h u h g d w f o r f n h g j h q d q g w k h & / l v p f o r f n v w k h g d w d z l o o e h d y d l o d e o h q r p l q d o o \ f r l q f l g h q w z l w k f o r f n h g j h q p w k l v d v v x p h v $ / power-down mode cas latency (cl) dll p osted cas# r tt o ut a 9 a 7 a 6 a 5 a 4 a 3 a 8 a 2 a 1 a 0 extended mode register (ex) address bus 976543 8210 a 10 a 12 b a 0 b a 1 10 11 12 n 0 14 e1 0 1 output drive strength fu ll redu c ed posted cas# additive latency (al) 3 0 1 2 3 4 5 6 reser v ed e3 0 1 0 1 0 1 0 1 e4 0 0 1 1 0 0 1 1 e5 0 0 0 0 1 1 1 1 0 1 dll enable enab l e (norma l ) disab l e (test / debug) e0 15 e11 0 1 rdqs enable no y es o cd p rogram a n 2 o ds r tt dqs# e10 0 1 dqs# enable enab l e disab l e rdqs r tt (nominal) r tt disab l ed 75 150 50 e2 0 1 0 1 e6 0 0 1 1 0 1 o utputs enab l ed disab l ed e12 0 1 0 1 mode register set m ode register ( m r) extended mode register (e m r) extended mode register (e m r 2 ) extended mode register (e m r 3 ) e15 0 0 1 1 e14 m rs b a 2 1 16 0 ocd operation 4 o cd exit reser v ed reser v ed reser v ed enab l e o cd defau l ts e7 0 1 0 0 1 e8 0 0 1 0 1 e9 0 0 0 1 1 notes: 1 . e 16 ( b a 2 ) is on ly app l i c ab l e for densities 8 1g b, reser v ed for future use, and must be programmed to 0 . 2 . m ode bits (en) wit h c orresponding address ba ll s (a n ) greater t h an e 12 (a 12 ) are reser v ed for future use and must be programmed to 0 . 3 . not a ll l isted al options are supported in an y indi v idua l speed grade. 4 .as detai l ed in t h e initia l i z ation (page 82 ) se c tion notes, during initia l i z ation of t h e o cd operation, a ll t h ree bits must be set to 1 for t h e o cd defau l t state, t h en set to 0 before initia l i z ation is fi nis h ed. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 65 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 7 k h ( ; 7 ( 1 ' ( ' 0 2 ' ( 5 ( * , 6 7 ( 5 f r q w u r o v i x q f w l r q v e h \ r q g w k r v h d y d l o d e o h d q g f r q w u r o o h g y l d w k h 0 2 ' ( 5 ( * , 6 7 ( 5 0 5 w k h v h d g g l w l r q d o i x q f w l r q v d u h ' / / h q d e o h g l v d e o h 2 8 7 3 8 7 ' 5 , 9 ( v w u h q j w k 2 q ' l h 7 h u p l q d w l r q 2 ' 7 3 r v w h g $ / 2 i i & k l s ' u l y h u , p s h g d q f h f d o l e u d w l r q 2 & ' ' 4 6 ? h q d e o h g l v d e o h d q g 2 x w s x w g l v d e o h h q d e o h 7 k h v h i x q f w l r q d u h f r q w u r o o h g y l d w k h e l w v v k r z q l q ) l j x u h 7 k h ( 0 5 l v s u r j u d p p h g y l d w k h / 0 f r p p d q g d q g z l o o u h w d l q w k h v w r u h g l q i r u p d w l r q x q w l o l w l v s u r j u d p p h g d j d l q r u w k h l 0 2 ' o r v h v s r z h u 5 h s u r j u d p p l q j w k h ( 0 5 z l o o q r w d o w h u w k h f r q w h q w v r i w k h p h p r u \ d u u d \ s u r y l g h g l w l v s h u i r u p h g f r u u h f w o \ 7 k h ( 0 5 p x v w e h o r d g h g z k h q d o o e d q n v d u h l g o h d q g q r e x u v w v d u h l q s u r j u h v v d q g w k h f r q w u r o o h u p x v w z d l w w k h v s h f l i l h g w l p h t 0 5 ' e h i r u h l q l w l d w l q j d q \ v x e v h t x h q w r s h u d w l r q v 9 l r o d w l q j h l w k h u r i w k h v h u h t x l u h p h q w v f r x o g u h v x o w l q d q x q v s h f l i l h g r s h u d w l r q extended mode register (emr) f igure 31 - emr d efinitions logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 66 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 7 k h ' / / p d \ e h ( 1 $ % / ( ' r u ' , 6 $ % / ( ' e \ s u r j u d p p l q j e l w ( 0 g x u l q j w k h / 0 f r p p d q g d v v k r z q l q ) l j x u h 7 k h v h v s h f l i l f d w l r q v d u h d s s o l f d - e o h z k h q w k h ' / / l v h q d e o h g i r u q r u p d o r s h u d w l r q ' / / ( 1 $ % / ( l v u h t x l u h g g x u l q j 3 2 : ( 5 8 3 l q l w l d o l ] d w l r q d q g x s r q u h w x u q l q j w r q r u p d o r s h u d w l r q d i w h u k d y l q j g l v d e o h g w k h ' / / i r u w k h s x u s r v h r i g h e x j j l q j r u h y d o x d w l r q ( q d e o l q j w k h ' / / v k r x o g d o z d \ v e h i r o o r z h g e \ u h v h w w l q j w k h ' / / x v l q j w k h / 0 f r p p d q g 7 k h ' / / l v d x w r p d w l f d o o \ ' , 6 $ % / ( ' z k h q h q w h u l q j 6 ( / ) 5 ( ) 5 ( 6 + r s h u d w l r q d q g l v d x w r p d w l f d o o \ u h h q d e o h g d q g u h v h w x s r q h [ l w r i 6 ( / ) 5 ( ) 5 ( 6 + r s h u d w l r q v $ q \ w l p h w k h ' / / l v ( 1 $ % / ( ' d q g v x e v h t x h q w o \ u h v h w f o r f n f \ f o h v p x v w r f f x u e h i r u h d 5 ( $ ' f r p p d q g f d q e h l v v x h g w r d o o r z w l p h i r u w k h l q w h u q d o f o r f n w r v \ q f k u r q l ] h z l w k w k h h [ w h u q d o f o r f n ) d l o l q j w r z d l w i r u v \ q f k u r q l ] d w l r q w r r f f x u p d \ u h v x o w l q d y l r o d w l r q r i w k h t $ & r u t ' 4 6 & . s d u d p h w h u v $ q \ w l p h w k h ' / / l v ' , 6 $ % / ( ' d q g w k h l 0 2 ' l v r s h u d w h g e h o r z 0 + ] d q \ $ 8 7 2 5 ( ) 5 ( 6 + f r p p d q g v k r x o g e h i r o o r z h g e \ d 3 5 ( & + $ 5 * ( $ / / f r p p d q g dll enabled/disabled 2 ' 7 h i i h f w l y h u h v l v w d q f h 5 7 7 ( ) ) l v g h i l q h g e \ e l w v ( 2 d q g ( 6 r i w k h ( 0 5 d v v k r z q l q ) l j x u h 7 k h 2 ' 7 i h d w x u h l v g h v l j q h g w r l p s u r y h v l j q d o l q w h j u l w \ r i w k h p h p r u \ f k d q q h o e \ d o o r z l q j w k h ' ' 5 p h p r u \ f r q - w u r o o h u w r l q g h s h q g h q w o \ w x u q r q r u r i i 2 ' 7 i r u d q \ r u d o o g h y l f h v 5 7 7 h i i h f - w l y h u h v l v w d q f h y d o x h v r i : : d q g : d u h v h o h f w d e o h d q g d s s o \ w r h d f k ' 4 ' 4 6 ' 4 6 ? 8 ' 4 6 8 ' 4 6 ? / ' 4 6 / ' 4 6 ? 8 ' 0 / ' 0 v l j q d o v % l w v ( 6 ,e 2 g h w h u p l q h z k d w 2 ' 7 u h v l v w d q f h l v h q d e o h g e \ w x u q l q j r q r i i v v z v z r u v z w 7 k h 2 ' 7 h i i h f w l y h u h v l v w d q f h y d o x h l v v h o h f w h g e \ h q d e o l q j v z l w f k v v z w z k l f k h q d e o h v d o o 5 y d o x h v w k d w d u h : h d f k h q d e o l q j d q h i i h f w l y h u h v l v w d q f h r i : (r 7 7 > ( ) ) @ 5 6 l p l o d u o \ l i v v z w l v h q d e o h g d o o 5 y d o x h v w k d w d u h : h d f k h q d e o h d q h i i h f w l y h 2 ' 7 u h v l v w d q f h r i : h d f k h q d e o l q j d q h i i h f w l y h u h v l v w d q f h r i : (r 7 7 > ( ) ) @ 5 6 l p l - o d u o \ l i v v z w l v h q d e o h g d o o 5 y d o x h v w k d w d u h : h d f k h q d e o h d q g h i i h f w l y h 2 ' 7 u h v l v w d q f h r i : 5 h v h u y h g v w d w h v v k r x o g q r w e h x v h g d v d q x q n q r z q r s h u d w l r q r u l q f r p s d w l e l o l w \ z l w k i x w x u h y h u v l r q v p d \ u h v x o w 7 k h 2 ' 7 f r q w u r o e d o o l v x v h g w r g h w h u p l q h z k h q 5 7 7 ( ) ) l v w x u q h g r q d q g r i i d v v x p l q j 2 ' 7 k d v e h h q h q d e o h g y l d e l w v ( d q g ( r i w k h ( 0 5 7 k h 2 ' 7 i h d w x u h d q g 2 ' 7 l q s x w e d o o d u h r q o \ x v h g g x u l q j $ & 7 , 9 ( $ & 7 , 9 ( 3 2 : ( 5 ' 2 : 1 e r w k i d v w h [ l w d q g v o r z h [ l w p r g h v d q g 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 p r g h v r i r s h u d w l r q 2 ' 7 p x v w e h w x u q h g r i i s u l r u w r h q w h u l q j 6 ( / ) 5 ( ) 5 ( 6 + p r g h ' x u l q j 3 2 : ( 5 8 3 d q g , 1 , 7 , $ / , = $ 7 , 2 1 r i w k h ' ' 5 l 0 2 ' 2 ' 7 v k r x o g e h g l v - d e o h g x q w l o w k h ( 0 5 f r p p d q g l v l v v x h g 7 k l v z l o o h q d e o h w k h 2 ' 7 i h d w x u h d w z k l f k s r l q w w k h 2 ' 7 e d o o z l o o g h w h u p l q h w k h 5 7 7 ( ) ) y d o x h $ q \ w l p h w k h ( 0 5 h q d e o h v w k h 2 ' 7 i x q f w l r q 2 ' 7 p d \ q r w e h g u l y h q + , * + x q w l o h l j k w f o r f n v d i w h u w k h ( 0 5 k d v e h h q h q d e o h g on-die-termination (odt) 7 k h ' 4 6 ? e d o o l v ( 1 $ % / ( ' e \ e l w ( 10 ' 4 6 ? l v w k h f r p s o h p h q w r i w k h g l i i h u h q w l d o g d w d v w u r e h s d l u : k h q ' , 6 $ % / ( ' ' 4 6 ? v k r x o g e h o h i w i o r d w - l q j k r z h y h u l w p d \ e h w l h g w r j u r x q g y l d d : to 10k : u h v l v w r u dqs\ enable/disable 7 k h 2 8 7 3 8 7 ' 5 , 9 ( 6 7 5 ( 1 * 7 + l v g h i l q h g e \ e l w ( 1 d v v k r z q l q ) l j x u h 7 k h 1 2 5 0 $ / ' 5 , 9 ( 6 7 5 ( 1 * 7 + i r u d o o r x w s x w v l v v s h f l i l h g w r e h 6 6 7 / b 3 u r j u d p p l q j e l w ( 1 v h o h f w v q r u p d o i x o o v w u h q j w k ' 5 , 9 ( 6 7 5 ( 1 * 7 + i r u d o o r x w s x w v 6 h o h f w l q j d 5 ( ' 8 & ( ' ' 5 , 9 ( 6 7 5 ( 1 * 7 + r s w l r q ( 1 z l o o u h g x f h d o o r x w s x w v w r d s s u r [ l p d w h o \ w r s h u f h q w r i w k h 6 6 7 / ' 5 , 9 ( 6 7 5 ( 1 * 7 + 7 k l v r s w l r q l v l q w h q g h g i r u w k h v x s s r u w r i o l j k w h u o r d g d q g r u s r l q w w r s r l q w h q y l u r q p h q w v output drive strength 7 k h 2 8 7 3 8 7 ( 1 $ % / ( ' , 6 $ % / ( i x q f w l r q l v g h i l q h g e \ e l w ( 12 d v v k r z q l q ) l j x u h : k h q ( 1 $ % / ( ' ( 12 d o o r x w s x w v ' 4 ' 4 6 ' 4 6 ? i x q f - w l r q q r u p d o o \ : k h q ' , 6 $ % / ( ' ( 12 d o o r x w s x w v d u h ' , 6 $ % / ( ' w k x v u h p r y l q j r x w s x w e x i i h u f x u u h q w 7 k h r x w s x w ' , 6 $ % / ( i h d w x u h l v l q w h q g h g w r e h x v h g g x u l q j , dd f k d u d f w h u l ] d w l r q r i 5 ( $ ' f x u u h q w output enable/disable 7 k h 2 ) ) & + , 3 ' 5 , 9 ( 5 2 & ' i x q f w l r q l v d q r s w l r q d o ' ' 5 - ( ' ( & i h d - w x u h z k l f k l v q r w v x s s r u w h g e \ / 2 * , & ' h y l f h v l 0 2 ' g h y l f h w k h u h i r u h w k l v i x q f w l r q p x v w e h v h w d q g p d l q w d l q h g l q w k h g h i d x o w v w d w h ( q d e o l q j w k l v i x q f - w l r q r x w v l g h r i w k h g h i d x o w v h w w l q j v z l o o d o w h u w k h , 2 g u l y h f k d u d f w h u l v w l f v d q g w k h w l p l q j d q g r x w s x w , 2 v s h f l i l f d w l r q v z l o o q r o r q j h u e h y d o l g off-chip driver (ocd) impedance calibration 3 2 6 7 ( ' & $ 6 $ ' ' , 7 , 9 ( $ / l v v x s s r u w h g w r p d n h w k h f r p p d q g d q g g d w d e x v h i i l f l h q w i r u v x v w d l q d e o h e d q g z l g w k v l q w k h ' ' 5 l 0 2 ' % l w v ( 3 -e 5 g h i l q h w k h y d o x h r i $ / % l w v ( 3 -e 5 d o o r z w k h x v h u w r s u r j u d p w k h ' ' 5 l 0 2 ' z l w k d q $ / r i r u f o r f n v 5 h v h u y h g v w d w h v v k r x o g q r w e h x v h g d v d q x q n q r z q r s h u d w l r q r u l q f r p s d w l e l o l w \ z l w k i x w x u h u h y l v l r q v p d \ u h v x o w , q w k l v r s h u d w l r q w k h ' ' 5 l 0 2 ' d o o r z v d 5 ( $ ' r u : 5 , 7 ( f r p p d q g w r e h l v v x h g s u l r u w r t 5 & ' 0 , 1 z l w k w k h u h t x l u h p h q w w k d w $ / d t 5 & ' 0 , 1 $ w \ s l f d o d s s o l f d w l r q x v l q j w k l v i h d w x u h z r x o g v h w $ / t 5 & ' 0 , 1 y [ t & . 7 k h 5 ( $ ' r u : 5 , 7 ( f r p p d q g l v k h o g i r u w k h w l p h r i w k h $ / e h i r u h l w l v l v v x h g l q w h u q d o o \ w r w k h ' ' 5 l 0 2 ' g h y l f h 5 / l v f r q w u r o o h g e \ w k h v x p r i $ / d q g & / 5 / $ / & / : 5 , 7 ( o d w h q f \ : / l v h t x d o w r 5 / p l q x v r q f o r f n : / $ / & / y [ t & . posted cas additive latency (al) do n + 3 do n + 2 do n + 1 ck ck# command dq dqs, dqs# al = 2 active n t0 t1 t2 dont care transitioning data read n nop nop do n t3 t4 t5 nop t6 nop t7 t8 nop nop cl = 3 rl = 5 t rcd (min) nop ck ck# command dq dqs, dqs# active n t0 t1 t2 dont care transitioning data nop nop t3 t4 t5 nop t6 nop di n + 3 di n + 2 di n + 1 wl = al + cl - 1 = 4 t7 nop di n t rcd (min) nop al = 2 cl - 1 = 2 write n notes: 1. bl = 4 2. shown with nominal t $ & t ' 4 6 & . d q g t dqsq. 3. rl = al + cl = 5. notes: 1. bl = 4 2. cl = 3. 3. wl = al + cl - 1 = 4 logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 32 - read l atency f igure 33 - write l atency a 9 a 7 a 6 a 5 a 4 a 3 a 8 a 2 a 1 a 0 extended mode register (ex) address bus 976543 8210 a 10 a 12 a 11 b a 0 b a 1 10 11 12 n 0 14 15 a n 2 e14 0 1 0 1 mode register set m ode register ( m r) extended mode register (e m r) extended mode register (e m r 2 ) extended mode register (e m r 3 ) e15 0 0 1 1 m rs 0 00 00 sr t0 00 00 0 0 b a 2 1 16 0 e7 0 1 srt enable 1x refres h rate ( 0 c to 85 c) 2x refres h rate ( >85 c) notes: 1 . e 16 ( b a 2 ) is on ly app l i c ab l e for densities 1g b, reser v ed for future use, and must be programmed to 0 . 2 . m ode bits (en) wit h c orresponding address ba ll s (a n ) greater t h an e 12 (a 12 ) are reser v ed for future use and must be programmed to 0 . logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 7 k h ( ; 7 ( 1 ' ( ' 0 2 ' ( 5 ( * , 6 7 ( 5 ( 0 5 f r q w u r o v i x q f w l r q v e h \ r q g w k r v h f r q w u r o o h g e \ w k h 0 2 ' ( 5 ( * , 6 7 ( 5 & x u u h q w o \ d o o e l w v l q w k h ( 0 5 d u h u h v h u y h g h [ f h s w i r u ( z k l f k l v x v h g l q f r p p h u f l d o r u k l j k w h p s h u d w x u h r s h u d w l r q v d v v k r z q l q ) l j x u h 7 k h ( 0 5 l v s u r j u d p p h g y l d w k h / 0 f r p p d q g d q g z l o o u h w d l q w k h v w r u h g l q i r u p d w l r q x q w l o l w l v s u r j u d p p h g d j d l q r u x q w l o w k h l 0 2 ' l v v x e m h f w h g w r d o r v v r i s r z h u f r q g l w l r q 5 h s u r j u d p p l q j w k h ( 0 5 z l o o q r w d o w h u w k h f r q w h q w v r i w k h d u u d \ s u r y l g h g l w k d v e h h q s h u i r u p h g f r u u h f w o \ bit e $ p x v w e h s u r j u d p p h g d v v w w r s u r y l g h d i d v w h u 5 ( ) 5 ( 6 + 5 $ 7 ( r q , 7 ( 7 r u 0 g h y l f h v l i 7 c l v r u g r h v h [ f h h g ? & ( 0 5 p x v w e h o r d g h g z k h q d o o e d q n v d u h l g o h d q g q r e x u v w v d u h l q s u r j u h v v d q g w k h f r q w u r o o h u p x v w z d l w w k h v s h f l i l h g w l p h t 0 5 ' e h i r u h l q l w l d w l q j d q \ v x e v h - t x h q w r s h u d w l r q 9 l r o d w l q j h l w k h u r i w k h v h u h t x l u h p h q w v f r x o g u h v x o w l q d q x q v s h f l i l h g l 0 2 ' r s h u d w l r q extended mode register 2 (emr2) f igure 34 - emr2 d efinitions e14 0 1 0 1 mode register set mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) e15 0 0 1 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 n 0 14 15 an 2 mrs 0 0 0 0 0 0 0 0 0 0 0 0 0 ba2 1 16 0 notes: 1. e16 (ba2) is only applicable for densities 1gb, reserved for future use, and must be programmed to 0. 2. mode bits (en) with corresponding address balls (an ) greater than e12 (a12) are reserved for future use and must be programmed to 0. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 69 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 7 k h ( ; 7 ( 1 ' ( ' 0 2 ' ( 5 ( * , 6 7 ( 5 ( 0 5 f r q w u r o v i x q f w l r q v e h \ r q g w k r v h f r q w u r o o h g e \ w k h 0 2 ' ( 5 ( * , 6 7 ( 5 & x u u h q w o \ d o o e l w v r i w k h ( 0 5 d u h u h v h u y h g d v v k r z q l q ) l j x u h 7 k h ( 0 5 l v s u r j u d p p h g y l d w k h / 0 f r p p d q g d q g z l o o u h w d l q w k h v w r u h g l q i r u p d w l r q x q w l o l w l v s u r j u d p p h g d j d l q r u x q w l o w k h l 0 2 ' l v v x e m h f w h g w r d o r v v r i s r z h u f r q g l w l r q 5 h s u r j u d p p l q j w k h ( 0 5 z l o o q r w d o w h u w k h f r q w h q w v r i w k h p h p r u \ d u u d \ s u r y l g h g l w l v s h u i r u p h g f r u u h f w o \ extended mode register 3 (emr3) f igure 35 - emr3 d efinitions t vtd 1 cke r tt power-up: v cc and stable clock (ck, ck#) t = 200 s (min) 3 high-z dm 15 dqs 15 high-z address 16 ck ck# t cl v tt 1 v ref v ddq c ommand nop 3 pre t0 ta0 dont care t cl t ck v dd odt dq 15 high-z tb0 200 cycles of ck are required before a read command can be issued mr with dll reset t rfc lm 8 pre 9 lm 7 ref 10 ref 10 lm 11 tg0 th0 ti0 tj0 mr without dll reset emr with ocd default tk0 tl0 tm0 te0 tf0 emr(2) emr(3) t mrd lm 6 lm 5 a10 = 1 t rpa tc0 td0 sstl_18 low level 2 valid 14 valid indicates a break in time scale lm 12 emr with ocd exit lm 13 normal operation code code a10 = 1 code code code code code t mrd t mrd t mrd t mrd t rpa t rfc v ddl t mrd t mrd emr t = 400 ns (min) 4 lvcmos low level 2 logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product ' ' 5 l 0 2 ' g h y l f h v p x v w e h 3 2 : ( 5 ( ' 8 3 d q g , 1 , 7 , $ / , = ( ' l q d s u h g h i l q h g p d q q h u 2 s h u d w l r q d o s u r f h g x u h v r w k h u w k d q w k r v h v s h f l i l h g p d \ u h v x o w l q x q g h - i l q h g r s h u d w l r q ) l j x u h l o o x v w u d w h v d q g w k h q r w h v r x w o l q h w k h v h t x h q f h u h t x l u h g i r u 3 2 : ( 5 8 3 d q g , 1 , 7 , $ / , = $ 7 , 2 1 initialization f igure 36 - ddr2 p ower -u p and i nitialization logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product % h i r u h d q 5 ( $ ' r u : 5 , 7 ( f r p p d q g v f d q e h l v v x h g w r d e d q n z l w k l q w k h ' ' 5 l 0 2 ' d u r z l q w k d w e d q n p x v w e h r s h q h g d f w l y d w h g h y h q z k h q d g g l w l y h o d w h q f \ l v x v h g 7 k l v l v d f f r p s o l v k h g y l d w k h $ & 7 , 9 $ 7 ( f r p p d q g z k l f k v h o h f w v e r w k w k h e d q n d q g w k h u r z w r e h d f w l y d w h g $ i w h u d u r z l v r s h q h g z l w k d q $ & 7 , 9 $ 7 ( f r p p d q g d 5 ( $ ' r u : 5 , 7 ( f r p p d q g p d \ e h l v v x h g w r w k d w u r z v x e m h f w w r w k h t 5 & ' v s h f l i l f d w l r q t 5 & ' 0 , 1 v k r x o g e h g h i l q h g e \ w k h f o r f n s h u l r g d q g u r x q g h g x s w r w k h q h [ w z k r o h q x p e h u w r g h w h u p l q h w k h h d u o l h v w f o r f n h g j h d i w h u w k h $ & 7 , 9 $ 7 ( f r p p d q g r q z k l f k d 5 ( $ ' r u : 5 , 7 ( f r p p d q g f d q e h h q w h u h g 7 k h v d p h s u r f h g x u h l v x v h g w r f r q y h u w r w k h u v s h f l i l f d w l r q o l p l w v i u r p w l p h x q l w v w r f o r f n f \ f o h v ) r u h [ d p s o h d t 5 & ' 0 , 1 v s h f l i l f d w l r q r i q v z l w k d 0 + ] f o r f n t & . q v u h v x o w v l q f o r f n v u r x q g h g x s w r 7 k l v l v v k r z q l q ) l j x u h $ v x e v h t x h q w $ & 7 , 9 $ 7 ( f r p p d q g w r d g l i i h u h q w u r z l q w k h v d p h e d q n f d q r q o \ e h l v v x h g d i w h u w k h s u h y l r x v d f w l y h u r z k d v e h h q f o r v h g s u h f k d u j h g 7 k h p l q l p x p w l p h l q w h u y d o e h w z h h q v x f f h v v l y h $ & 7 , 9 $ 7 ( f r p p d q g v w r w k h v d p h e d q n l v g h i l q h g e \ t 5 & $ v x e v h t x h q w $ & 7 , 9 $ 7 ( f r p p d q g w r d q r w k h u e d q n f d q e h l v v x h g z k l o h w k h i l u v w e d q n l v e h l q j d f f h v v h g z k l f k u h v x o w v l q u h g x f w l r q r i w r w d o u r z d f f h v v r y h u k h d g 7 k h p l q l p x p w l p h l q w h u y d o e h w z h h q v x f f h v v l y h $ & 7 , 9 $ 7 ( f r p p d q g v w r g l i i h u h q w e d q n v l v g h i l q h g e \ t 5 5 ' ' ' 5 z l w k e d q n d u f k l w h f w x u h v k d y h d q d g g l w l r q d o u h t x l u h p h q w t ) $ : 7 k l v u h t x l u h v q r p r u h w k d q i r x u $ & 7 , 9 $ 7 ( f r p p d q g v p d \ e h l v v x h g l q d q \ j l y h q t ) $ : 0 , 1 s h u l r g d v v k r z q l q ) l j x u h activate command don t care t1 t0 t2 t3 t4 t5 t6 t7 t rrd ( m in) row row read ac t ac t n op t fa w ( m in) b an k address c k # address c k t8 t9 co l b an k a ac t read read read ac t n op row co l row co l co l b an k c b an k b b an k d b an k c b an k e ac t row t10 b an k d b an k b b an k a note: 1 . ddr 2 - 533 (- 37 e, x 4 or x 8 ), t c k = 3 . 75 ns, b l = 4 , al = 3 , cl = 4 , t rrd ( m in) = 7 . 5 ns, t fa w ( in ) = 37 . 5 ns. command dont care t1 t0 t2 t3 t4 t5 t6 t7 t rrd t rrd row row col bank x bank y row bank z bank y nop act nop nop act nop nop rd/wr t rcd ck# address bank address ck t8 t9 nop nop f igure 37 - e xample : m eeting t rrd (min) and t rcd (min) f igure 38 - m ultibank a ctivate r estriction logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 5 ( $ ' e x u v w v d u h l q l w l d w h g z l w k d 5 ( $ ' f r p p d q g 7 k h v w d u w l q j f r o x p q d q g e d q n d g g u h v v h v d u h s u r y l g h g z l w k w k h 5 ( $ ' f r p p d q g d q g w k h $ 8 7 2 3 5 ( - & + $ 5 * ( l v h l w k h u h q d e o h g r u g l v d e o h g i r u w k d w % 8 5 6 7 v h t x h q f h r u d f f h v v , i $ 8 7 2 3 5 ( & + $ 5 * ( l v h q d e o h g w k h u r z e h l q j d f f h v v h g l v d x w r p d w l f d o o \ 3 5 ( - & + $ 5 * ( ' d w w k h f r p s o h w l r q r i w k h e x u v w , i $ 8 7 2 3 5 ( & + $ 5 * ( l v g l v d e o h g w k h u r z z l o o e h o h i w r s h q d i w h u w k h f r p s o h w l r q r i w k h e x u v w ' x u l q j 5 ( $ ' e x u v w v w k h y d o l g g d w d r x w h o h p h q w i u r p w k h v w d u w l q j f r o x p q d g g u h v v z l o o e h d y d l o d e o h 5 ( $ ' o d w h q f \ 5 / f o r f n v o d w h u 5 / l v g h i l q h g d v w k h v x p r i $ / d q g & / 5 / $ / & / 7 k h y d o x h r i $ / d q g & / d u h s u r j u d p p d e o h y l d w k h 0 5 d q g ( 0 5 f r p p d q g v u h v s h f w l y h o \ ( d f k v x e v h t x h q w g d w d r x w h o h p h q w z l o o e h y d o l g q r p l q d o o \ d w w k h q h [ w s r v l w l y h r u q h j d w l y h f o r f n h g j h d w w k h q h [ w f u r v v l q j r i & . [ d q g & . [ ? ) l j x u h v k r z v h [ d p s o h v r i 5 / e d v h g r q g l i i h u h q w $ / d q g & / v h w w l q j v ' 4 6 [ ' 4 6 [ ? l v g u l y h q e \ w k h ' ' 5 l 0 2 ' d o r q j z l w k r x w s x w g d w d 7 k h l q l w l d o / 2 : v w d w h r q ' 4 6 [ d q g w k h + , * + v w d w h r q ' 4 6 [ ? f r l q f l g h q w z l w k w k h o d v w g d w d r x w h o h p h q w d u h n q r z q d v w k h 5 ( $ ' s u h d p e o h t 3 5 ( 7 k h o r z v w d w h r q ' 4 6 [ d q g w k h + , * + v w d w h f r l q f l g h q w z l w k w k h o d v w g d w d r x w h o h p h q w d u h n q r z d v w k h 5 ( $ ' s r v w d p e o h t 3 5 6 7 8 s r q f r p s o h w l r q r i d % 8 5 6 7 d v v x p l q j q r r w k h u f r p p d q g v k d y h e h h q l q l w l d w h g w k h ' 4 e x v v z l o o j r + , * + = $ g h w d l o h g h [ s o d q d w l r q r i t ' 4 6 & . ' 4 6 [ w u d q v l - w l r q v n h z w r & / d q g t $ & g d w d r x w w u d q v l w l r q v n h z w r & . [ l v v k r z q l q ) l j x u h ' d w d i u r p d q \ 5 ( $ ' e x u v w p d \ e h f r q f d w h q d w h g z l w k g d w d i u r p d v x e v h t x h q w 5 ( $ ' f r p p d q g w r s u r y l g h d f r q w l q x r x v i o r z r i g d w d 7 k h i l u v w g d w d h o h p h q w i u r p w k h q h z e x u v w i r o o r z v w k h o d v w h o h p h q w r i d f r p s o h w h g e x u v w 7 k h q h z 5 ( $ ' f r p p d q g v k r x o g e h l v v x h g [ f \ f o h v d i w h u w k h i l u v w 5 ( $ ' f r p p d q g z k h u h [ h t x d o v % / f \ f o h v v h h ) l j x u h 1 r q f r q v h f x w l y h 5 ( $ ' g d w d l v l o o x v w u d w h g l q ) l j x u h ) x o o v s h h g u d q g r p 5 ( $ ' d f f h v v h v z l w k l q d s d j h r u s d j h v f d q e h s h u i r u p h g ' ' 5 l 0 2 ' g h y l f h v v x s s r u w w k h x v h r i f r q f x u u h q w $ 8 7 2 3 5 ( & + $ 5 * ( w l p l q j ' ' 5 l 0 2 ' g h y l f h v g r q r w d o o r z l q w h u u x s w l q j r u w u x q f d w l q j r i d q 5 ( $ ' e x u v w x v l q j % / r s h u d w l r q v 2 q f h w k h % / 5 ( $ ' f r p p d q g l v u h j l v w h u h g l w p x v w e h d o o r z h g w r f r p s o h w h w k h h q w l u h 5 ( $ ' e x u v w + r z h y h u d 5 ( $ ' z l w k $ 8 7 2 3 5 ( & + $ 5 * ( g l v d e o h g x v l q j 9 / r s h u d w l r q w k h 5 ( $ ' p d \ e h l q w h u u x s w h g d q g w u x q f d w h g r q o \ e \ d q r w k h u 5 ( $ ' e x u v w d v o r q j d v w k h l q w h u u x s w l r q r f f x u v r q d e l w e r x q g d u \ d q g w k l v d o o r z h g g x h w r w k h q s u h i h w f k d u f k l w h f - w x u h r i w k h ' ' 5 l 0 2 ' $ 6 v k r z q l q ) l j x u h 5 ( $ ' e x u v w % / r s h u d w l r q v p d \ q r w e h l q w h u u x s w h g r u w u x q f d w h g z l w k d q \ r w k h u f r p p d q g h [ f h s w i r u d q r w k h u 5 ( $ ' ' d w d i u r p d q \ 5 ( $ ' e x u v w p x v w e h f r p s o h w h g e h i r u h d v x e v h t x h q w : 5 , 7 ( e x u v w l v d o o r z h g $ q h [ d p s o h r i d 5 ( $ ' e x u v w i r o o r z h g e \ d : 5 , 7 ( e x u v w l v v k r z q l q ) l j x u h read read n op n op n op n op n op b an k a , co l n c k c k # command address dq dqs, dqs# d o n d o n t0 t1 t2 t3 t4 n t5 n t4 t5 c k c k # command read n op n op n op n op n op address b an k a, co l n rl = 3 (al = 0 , cl = 3 ) dq dqs, dqs# d o n t0 t1 t2 t3 t3 n t4 n t4 t5 c k c k # command read n op n op n op n op n op address b an k a, co l n rl = 4 (al = 0 , cl = 4 ) dq dqs, dqs# t0 t1 t2 t3 t3 n t4 n t4 t5 al = 1 cl = 3 rl = 4 (al = 1 + cl = 3 ) don t care t ransitioning data notes: 1 .d o n = data-out from c o l umn n . 2 . b l = 4 . 3 . th ree subse q uent e l ements of data-out appear in t h e programmed order fo ll owing d o n . 4 .s h own wit h nomina l t ac, t dqsc k , and t dqsq. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 39 - read l atency ck ck# command read nop read nop nop nop nop address bank, col n bank, col b command read nop read nop nop nop address bank, col n bank, col b rl = 3 ck ck# dq dqs, dqs# rl = 4 dq dqs, dqs# do n do b do n do b t0 t1 t2 t3 t3n t4n t4 t5 t6 t5n t6n t0 t1 t2 t3 t2n nop t3n t4n t4 t5 t6 t5n t6n dont care transitioning data t ccd t ccd notes: 1. do n (or b) = data-out from column n (or column b). 2. bl = 4. 3. three subsequent elements of data-out appear in the programmed order following do n. 4. three subsequent elements of data-out appear in the programmed order following do b. 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies only when read commands are issued to same device. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 40 - c onsecutive read b ursts command read nop nop nop nop nop nop nop read t0 t1 t2 t3 t3n t4 t5 t7 t8 t6 t4n t6n t7n ck ck# t5 t7 t8 t5n t6 t4n t7n command nop nop nop nop read nop nop nop read t0 t1 t2 t3 t4 dq do n do b dont care transitioning data address bank, col n bank, col b address bank, col n bank, col b ck ck# cl = 4 cl = 3 dq do n do b dqs, dqs# dqs, dqs# notes: 1. do n (or b) = data-out from column n (or column b). 2. bl = 4. 3. three subsequent elements of data-out appear in the programmed order following do n. 4. three subsequent elements of data-out appear in the programmed order following do b. 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies when read commands are issued to different devices or nonconsecutive reads. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 41 - n onconsecutive read b ursts t0 t1 t2 dont care transitioning data t3 t4 t5 t6 command read 1 nop 2 nop 2 valid valid valid read 3 valid valid valid t7 t8 t9 ck ck# cl = 3 (al = 0) t ccd address valid 4 valid 4 cl = 3 (al = 0) dq do do do do do do do do do do do do a10 valid 5 dqs, dqs# notes: 1. bl = 8 required; auto precharge must be disabled (a10 = low). 2. nop or command inhibit commands are valid. precharge command cannot be is- sued to banks used for reads at t0 and t2. 3. interrupting read command must be issued exactly 2 t ck from previous read. 4. read command can be issued to any valid bank and row address (read command at t0 and t2 can be either same bank or different bank). 5. auto precharge can be either enabled (a10 = high) or disabled (a10 = low) by the in- terrupting read command. 6. example shown uses al = 0; cl = 3, bl = 8, shown with nominal t ac, t dqsck, and t dqsq. ck ck# t0 t1 t2 dont care transitioning data t3 t4 t5 t6 t7 t8 t9 t1 0t11 al = 2 cl = 3 rl = 5 wl = rl - 1 = 4 t rcd = 3 command act n nop nop nop nop nop nop read n nop nop nop write dqs, dqs# dq do n do n + 1 do n + 2 do n + 3 di n di n + 1 di n + 2 di n + 3 notes: 1. bl = 4; cl = 3; al = 2. 2. shown with nominal t ac, t dqsck, and t dqsq. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 42 - read i nterrupted by read f igure 43 - read- to -write ck ck# t0 t1 t2 dont care transitioning data t3 t4 t5 t6 t7 address bank a bank a bank a t ras (min) t rtp (min) t rp (min) al + bl/2 - 2 ck + max ( t rtp/ t ck or 2ck) command read nop pre act nop nop nop nop 4-bit prefetch dq do do do do a10 valid valid cl = 3 al = 1 dqs, dqs# t rc (min) notes: 1. rl = 4 (al = 1, cl = 3); bl = 4. 2. t rtp 2 clocks. 3. shown with nominal t ac, t dqsck, and t dqsq. ck ck# t0 t1 t2 dont care transitioning data t3 t4 t5 t6 t7 t8 cl = 3 al = 1 dqs, dqs# first 4-bit prefetch second 4-bit prefetch t rtp (min) t rp (min) address bank a bank a bank a t rc (min) t ras (min) a10 valid valid al + bl/2 - 2ck + max ( t rtp/ t ck or 2ck) dq do do do do do do do do command read nop nop nop nop nop nop act pre notes: 1. rl = 4 (al = 1, cl = 3); bl = 8. 2. t rtp 2 clocks. 3. shown with nominal t ac, t dqsck, and t dqsq. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product $ 5 ( $ ' e x u v w p d \ e h i r o o r z h g e \ d 3 5 ( & + $ 5 * ( f r p p d q g w r w k h v d p h e d q n s u r y l g h g $ 8 7 2 3 5 ( & + $ 5 * ( l v q r w d f w l y d w h g 7 k h p l q l p x p 5 ( $ ' w r 3 5 ( - & + $ 5 * ( f r p p d q g v s d f l q j w r w k h v d p h e d q n k d v w z r u h t x l u h p h q w v w k d w p x v w e h v d w l v i l h g $ / % / f o r f n v d q g t 5 7 3 t 5 7 3 l v w k h p l q l p x p w l p h i u r p w k h u l v l q j f o r f n h g j h w k d w l q l w l d w h v w k h o d v w e l w 3 5 ( ) ( 7 & + r i d 5 ( $ ' f r p p d q g w r w k h 3 5 ( & + $ 5 * ( f r p p d q g ) r u % / w k l v l v w k h w l p h i u r p w k h d f w x d o 5 ( $ ' $ / d i w h u w k h 5 ( $ ' f r p p d q g w r 3 5 ( & + $ 5 * ( f r p p d q g ) r u % / w k l v l v w k h w l p h i u r p $ / [ & / d i w h u w k h 5 ( $ ' w r 3 5 ( & + $ 5 * ( f r p p d q g ) r o o r z l q j w k h 3 5 ( & + $ 5 * ( f r p p d q g d v x e v h t x h q w f r p p d q g w r w k h v d p h e d q n f d q q r w e h l v v x h g x q w l o t 5 3 l v p h w + r z h y h u s d u w r i w k h u r z 3 5 ( & + $ 5 * ( w l p h l v k l g g h q g x u l q j w k h d f f h v v r i w k h o d v w g d w d h o h p h q w v ( [ d p s o h v r i 5 ( $ ' w r 3 5 ( & + $ 5 * ( i r u % / d u h v k r z q l q ) l j x u h d q g l q ) l j x u h i r u % / 7 k h g h o d \ i u r p 5 ( $ ' w r 3 5 ( & + $ 5 * ( w r w k h v d p h l v $ / % / y & . 0 $ ; t 5 3 t & . r u [ & . z k h u h 0 $ ; p h d q v w k h o d u j h u r i w k h w z r read with precharge f igure 44 - read- to -precharge ? bl = 4 f igure 45 - read- to -precharge ? bl = 8 logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product , i $ 10 l v k l j k z k h q d 5 ( $ ' f r p p d q g l v l v v x h g w k h 5 ( $ ' z l w k $ 8 7 2 3 5 ( & + $ 5 * ( i x q f w l r q l v h q j d j h g 7 k h ' ' 5 l 0 2 ' v w d u w v d q $ 8 7 2 3 5 ( & + $ 5 * ( r s h u d w l r q r q w k h u l v l q j h g j h r i f o r f n w k d w l v $ / % / f \ f o h v o d w h u w k d q w k h 5 ( $ ' z l w k $ 8 7 2 3 5 ( & + $ 5 * ( f r p p d q g s u r y l g h g t 5 $ 6 0 , 1 d q g t 5 7 3 d u h v d w l v i l h g , i t 5 $ 6 0 , 1 l v q r w v d w l v i l h g d w w k l v u l v l q j f o r f n h g j h w k h v w d u w s r l q w r i w k h $ 8 7 2 3 5 ( & + $ 5 * ( r s h u d w l r q z l o o e h g h o d \ h g x q w l o t 5 $ 6 0 , 1 l v v d w l v i l h g : k h q w k h l q w h u q d o 3 5 ( & + $ 5 * ( l v s x v k h g r x w e \ t 5 7 3 t 5 3 v w d u w v d w w k h s r l q w z k h u h w k h l q w h u q d o 3 5 ( & + $ 5 * ( k d s s h q v : k h q % / w k h p l q l p x p w l p h i u r p 5 ( $ ' z l w k $ 8 7 2 3 5 ( & + $ 5 * ( w r w k h q h [ w $ & 7 , 9 $ 7 ( f r p p d q g l v $ / t 5 7 3 t 5 3 t & . : k h q % / w k h p l q l p x p w l p h i u r p 5 ( $ ' z l w k $ 8 7 2 3 5 ( & + $ 5 * ( w r w k h q h [ w $ & 7 , 9 $ 7 ( f r p p d q g l v $ / f o r f n v t 5 7 3 t 5 3 t & . 7 k h w h u p t 5 7 3 t 5 3 t & . l v d o z d \ v u r x q g h g x s w r w k h q h [ w l q w h j h u $ j h q h u d o s x u s r v h h t x d w l r q f d q d o v r e h x v h g $ / % ! y & . t 5 7 3 t 5 3 t & . , q d q \ h y h q w w k h l q w h u q d o 3 5 ( & + $ 5 * ( g r h v q r w v w d u w h d u o l h u w k d q w z r f o r f n v d i w h u w k h o d v w e l w s u h i h w f k 5 ( $ ' z l w k $ 8 7 2 3 5 ( & + $ 5 * ( f r p p d q g p d \ e h d s s o l h g w r r q h e d q n z k l o h d q r w k h u e d q n l v r s h u d w l r q d o 7 k l v l v u h i h u u h g w r d v & 2 1 & 8 5 5 ( 1 7 $ 8 7 2 3 5 ( - & + $ 5 * ( r s h u d w l r q ( [ d p s o h v r i 5 ( $ ' z l w k 3 5 ( & + $ 5 * ( d q g 5 ( $ ' z l w k $ 8 7 2 3 5 ( & + $ 5 * ( z l w k d s s o l f d e o h w l p l q j u h t x l u h p h q w v d u h v k r z q l q ) l j x u h read with auto precharge from command (bank n) read with auto precharge minimum delay (with concurrent auto pre- charge) units (bl/2) (bl/2) + 2 1 t ck 5 ( $ ' r u 5 ( $ ' z l w k $ x w r 3 u h f k d u j h : 5 , 7 ( r u : 5 , 7 ( z l w k $ x w r 3 u h f k d u j h 3 5 ( & + $ 5 * ( r u $ & 7 , 9 $ 7 ( to command (bank m) t able 39: read u sing concurrent auto precharge ck ck# cke a10 bank address t ck t ch t cl ra t rcd t ras 3 t rc t rp cl = 3 dm t0 t1 t2 t3 t4 t5 t7n t8n t6 t7 t8 dq 8 dqs, dqs# case 1: t ac (min) and t dqsck (min) case 2: t ac (max) and t dqsck (max) dq 8 dqs, dqs# t rpre t rpre t rpst t dqsck (min) t lz (min) t lz (max) t ac (min) t lz (min) do n t hz (max) t ac (max) t lz (min) do n nop 1 nop 1 command act ra col n pre 3 bank x ra ra bank x bank x 6 7 7 77 act bank x nop 1 nop 1 nop 1 nop 1 t hz (min) one bank all banks dont care transitioning data read 2 address 5 t rtp 4 t rpst t dqsck (max) t9 notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4 and al = 0 in the case shown. 3. the precharge command can only be applied at t6 if t ras (min) is met. 4. read-to-precharge = al + bl/2 - 2ck + max ( t rtp/ t ck or 2ck). 5. disable auto precharge. 6. dont care if a10 is high at t5. 7. i/o balls, when entering or exiting high-z, are not referenced to a specific voltage level, but to when the device begins to drive or no longer drives, respectively. 8. do n = data-out from column n; subsequent elements are applied in the programmed order. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 46 - b ank r ead ? w ithout a uto p recharge 4-bit prefetch ck ck# cke a10 bank address t ck t ch t cl ra t rcd t ras t rc t rp cl = 3 dm t0 t1 t2 t3 t4 t5 t7n t8n t6 t7 t8 dq 6 dqs, dqs# case 1: t ac (min) and t dqsck (min) case 2: t ac (max) and t dqsck (max) dq 6 dqs, dqs# t rpre t rpre t rpst t rpst t dqsck (min) t dqsck (max) t lz (min) t lz (max) t ac (min) t lz (min) t hz (max) t ac (max) t lz (max) do n nop 1 nop 1 command 1 act ra col n bank x ra ra bank x act bank x nop 1 nop 1 nop 1 nop 1 nop 1 t hz (min) dont care transitioning data read 2,3 address al = 1 t rtp internal precharge 4 5 5 55 do n notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4, rl = 4 (al = 1, cl = 3) in the case shown. 3. the ddr2 sdram internally delays auto precharge until both t ras (min) and t rtp (min) have been satisfied. 4. enable auto precharge. 5. i/o balls, when entering or exiting high-z, are not referenced to a specific voltage level, but to when the device begins to drive or no longer drives, respectively. 6. do n = data-out from column n; subsequent elements are applied in the programmed order. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 47 - b ank r ead ? with a uto p recharge dq (last data valid) 4 dq 4 dq 4 dq 4 dq 4 dq 4 dq 4 ldsq# ldqs 3 dq (last data valid) 4 dq (first data no longer valid) 4 dq (first data no longer valid) 4 dq0Cdq7 and ldqs collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 5 t qh 5 t dqsq 2 t dqsq 2 t dqsq 2 t dqsq 2 data valid window data valid window dq (last data valid) 7 dq 7 dq 7 dq 7 dq 7 dq 7 dq 7 udqs# udqs 3 dq (last data valid) 7 dq (first data no longer valid) 7 dq (first data no longer valid) 7 dq8Cdq15 and udqs collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n t qh 5 t qh 5 t qh 5 t qh 5 t dqsq 2 t dqsq 2 t dqsq 2 t dqsq 2 t hp 1 t hp 1 t hp 1 t hp 1 t hp 1 t hp 1 t qh 5 t qh 5 data valid window data valid window data valid window data valid window data valid window upper byte lower byte data valid window t qhs t qhs t qhs t qhs t qhs t qhs t qhs t qhs notes: 1. t hp is the lesser of t cl or t ch clock transitions collectively when a bank is active. 2. t dqsq is derived at each dqs clock edge, is not cumulative over time, begins with dqs transitions, and ends with the last valid transition of dq. 3. dq transitioning after the dqs transitions define the t dqsq window. ldqs defines the lower byte, and udqs defines the upper byte. 4. dq0, dq1, dq2, dq3, dq4, dq5, dq6, or dq7. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 46- x 4, x 8 d ata o utput t iming ? t dqsq, t qh, and d ata v alid w indow f igure 48 - d ata o utput t iming ? t dqsq, t qh, and d ata v alid w indow ck ck# dqs#/dqs or l dqs#/ldqs/udq#/udqs 3 t0 1 t1 t2 t3 t3n t4 t4n t5 t5n t6 t6n t7 t rpst t dqsck 2 (min) t dqsck 2 (max) dq (last data valid) dq (first data valid) all dqs collectively 4 t ac 5 (min) t ac 5 (max) t lz (min) t hz (max) t3 t3 t3n t4n t5n t6n t3n t3n t4n t4n t5n t5n t6n t6n t4 t5 t5 t6 t6 t3 t4 t5 t6 t4 t hz (max) t lz (min) t rpre 1 r w h v 5 ( $ ' f r p p d q g z l w k & / $ / l v v x h g d w 7 2. t ' 4 6 & . l v w k h ' 4 6 r x w s x w z l q g r z u h o d w l y h w r & . d q g l v w k h o r q j w h u p f r p s r q h q w r i ' 4 6 v n h z ' 4 w u d q v l w l r q l q j d i w h u ' 4 6 w u d q v l w l r q v g h ? q h t dqsq window. $ o o ' 4 p x v w w u d q v l w l r q e \ t ' 4 6 4 d i w h u ' 4 6 w u d q v l w l r q v u h j d u g o h v v r i t ac. 5. t $ & l v w k h ' 4 r x w s x w z l q g r z u h o d w l y h w r & . d q g l v w k h 3 o r q j w h u p f r p s r q h q w r i ' 4 v n h z 6. t lz (min) and t $ & 0 , 1 d u h w k h ? u v w y d o l g v l j q d o w u d q v l w l r q v w + = 0 $ ; d q g w $ & 0 $ ; d u h w k h o d w h v w y d o l g v l j q d o w u d q v l w l r q v , 2 e d o o v z k h q h q w h u l q j r u h [ l w l q j + l j k = d u h q r w u h i h u h q f h g w r d v s h f l ? f y r o w d j h o h y h o e x w w r z k h q w k h g h y l f h e h j l q v w r g u l y h r u q r o r q j h u g u l y h v u h v s h f w l y h o \ logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 46- x 4, x 8 d ata o utput t iming ? t dqsq, t qh, and d ata v alid w indow f igure 49 - d ata o utput t iming ? t ac and t dqsck : 5 , 7 ( e x u v w v d u h l q l w l d w h g z l w k d : 5 , 7 ( f r p p d q g ' ' 5 l 0 2 ' g h y l f h v x v h : / h t x d o w r 5 / p l q x v r q h f o r f n f \ f o h : / 5 / & . 7 k h v w d u w l q j f r o x p q d q g e d q n d g g u h v v h v d u h s u r y l g h g z l w k w k h : 5 , 7 ( f r p p d q g d q g $ 8 7 2 3 5 ( & + $ 5 * ( l v h l w k h u h q d e o h g r u g l v d e o h g i r u w k d w d f f h v v , i $ 8 7 2 3 5 ( & + $ 5 * ( l v h q d e o h g w k h u r z e h l q j d f f h v v h g l v 3 5 ( & + $ 5 * ( ' d w w k h f r p s o h w l r q r i w k h e x u v w ' x u l q j : 5 , 7 ( e x u v w v w k h i l u v w y d o l g g d w d l q h o h p h q w z l o o e h u h j l v w h u h g r q w k h i l u v w u l v l q j h g j h r i ' 4 6 [ i r o o r z l q j w k h : 5 , 7 ( f r p p d q g d q g v x e v h t x h q w g d w d h o h p h q w v z l o o e h u h j l v w h u h g r q v x f f h v v l y h h g j h v r i ' 4 6 [ 7 k h o r z v w d w h r q ' 4 6 [ e h w z h h q w k h : 5 , 7 ( f r p p d q g d q g w k h i l u v w u l v l q j h g j h l v n q r z q d v w k h : 5 , 7 ( s u h d p e o h w k h o r z v w d w h r q ' 4 6 [ i r o o r z l q j w k h o d v w g d w d l q h o h p h q w l v n q r z q d v w k h s r v w d p e o h 7 k h w l p h e h w z h h q w k h : 5 , 7 ( f r p p d q g d q g w k h i l u v w u l v l q j ' 4 6 [ h g j h l v : / ? t ' 4 6 6 6 x e v h t x h q w ' 4 6 [ s r v l w l y h u l v l q j h g j h v d u h w l p h g u h o d w l y h w r w k h d v v r f l d w h g f o r f n h g j h d v ? t ' 4 6 6 t ' 4 6 6 l v v s h f l i l h g z l w k d u h o d w l y h o \ z l g h u d q j h s h u f h q w r i r q f o r f n f \ f o h $ o o r i w k h : 5 , 7 ( g l d j u d p v v k r z w k h q r p l q d o f d v h d q g z k h u h w k h w z r h [ w u h p h f d v h v t ' 4 6 6 > 0 , 1 @ d q g t ' 4 6 6 > 0 $ ; @ p l j k w q r w e h l q w x l w l y h w k h \ k d y h d o v r e h h q l q f o x g h g ) l j x u h v k r z v w k h q r p l q d o f d v h d q g w k h h [ w u h p h v r i t ' 4 6 6 i r u % / 8 s r q f r p s o h w l r q r i d e x u v w d v v x p l q j q r r w k h u f r p p d q g v k d y h e h h q l q l w l d w h g w k h ' 4 z l o o u h p d l q + l j k = d q g d q \ d g g l w l r q d o l q s x w g d w d z l o o e h l j q r u h g ' d w d i r u d q \ : 5 , 7 ( e x u v w p d \ e h f r q f d w h q d w h g z l w k d v x e v h t x h q w : 5 , 7 ( f r p p d q g w r s u r y l g h f r q w l q x r x v g d w d i o r z r i l q s x w g d w d 7 k h i l u v w g d w d h o h p h q w i u r p w k h q h z e x u v w l v d s s o l h g d i w h u w k h o d v w h o h p h q w r i d f r p s o h w h g e x u v w 7 k h q h z : 5 , 7 ( f r p p d q g v k r x o g e h l v v x h g [ f \ f o h v d i w h u w k h i l u v w : 5 , 7 ( f r p p d q g z k h u h [ h t x d o v % / ) l j x u h v k r z v f r q f d w h q d w h g e x u v w v r i % / d q g k r z i x o o v s h h g u d q g r p : 5 , 7 ( d f f h v v h v z l w k l q d s d j h r u s d j h v f d q e h s h u i r u p h g $ q h [ d p s o h r i q r q f r q v h f x w l y h : 5 , 7 ( d f f h v v h v l v v k r z q l q ) l j x u h ' ' 5 l 0 2 ' g h y l f h v v x s s r u w f r q f x u u h q w $ 8 7 2 3 5 ( & + $ 5 * ( r s w l r q v d v v k r z q l q 7 d e o h ' ' 5 l 0 2 ' g h y l f h v g r q r w d o o r z l q w h u u x s w l q j r u w u x q f d w l q j d q \ : 5 , 7 ( e x u v w x v l q j % / r s h u d w l r q 2 q f h w k h % / : 5 , 7 ( f r p p d q g l v u h j l v w h u h g l w p x v w e h d o o r z h g w r f r p s o h w h w k h h q w l u h : 5 , 7 ( e x u v w f \ f o h + r z h y h u d : 5 , 7 ( % / r s h u d w l r q z l w k $ 8 7 2 3 5 ( & + $ 5 * ( g l v d e o h g p l j k w e h l q w h u u x s w h g d q g w u x q f d w h g r q o \ e \ d q r w k h u : 5 , 7 ( f r p p d q g d v v k r z q l q ) l j x u h ' d w d i r u d q \ : 5 , 7 ( e x u v w p d \ e h i r o o r z h g e \ d v x e v h t x h q w 5 ( $ ' f r p p d q g 7 r i r o o r z d : 5 , 7 ( t : 7 5 v k r x o g e h p h w d v v k r z q l q ) l j x u h 7 k h q x p e h u r i write dqs, dqs# t dqss (max) t dqss (nom) t dqss (min) dm dq ck ck# command write nop nop address bank a, col b nop nop t0 t1 t2 t3 t2n t4 t3n dqs, dqs# 5 dm dq dqs, dqs# dm dq di b di b di b dont care transitioning data t dqss 5 wl t dqss wl - t dqss t dqss 5 wl + t dqss notes: 1. subsequent rising dqs signals must align to the clock within t dqss. 2. di b = data-in for column b. 3. three subsequent elements of data-in are applied in the programmed order following di b. 4. shown with bl = 4, al = 0, cl = 3; thus, wl = 2. 5. a10 is low with the write command (auto precharge is disabled). logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f o r f n f \ f o h v u h t x l u h g w r p h h w t : 7 5 l v h l w k h u r u t : 7 5 t & . z k l f k h y h u l v j u h d w h u ' d w d i r u d q \ : 5 , 7 ( e x u v w p d \ e h i r o o r z h g e \ d v x e v h t x h q w 3 5 ( & + $ 5 * ( f r p p d q g t : 5 p x v w e h p h w d v v k r z q l q ) l j x u h t : 5 v w d u w v d w w k h h q g r i w k h g d w d e x u v w u h j d u g o h v v r i w k h g d w d p d v n f r q g l w l r q write continued units t ck from command (bank n) write with auto precharge minimum delay (with concurrent auto pre- charge) (cl-1) + (bl/2) + t wtr (bl/e) 1 5 ( $ ' r u 5 ( $ ' z l w k $ x w r 3 u h f k d u j h : 5 , 7 ( r u : 5 , 7 ( z l w k $ x w r 3 u h f k d u j h 3 5 ( & + $ 5 * ( r u $ & 7 , 9 $ 7 ( to command (bank m) t able 40: write u sing c oncurrent a uto p recharge f igure 46- x 4, x 8 d ata o utput t iming ? t dqsq, t qh, and d ata v alid w indow f igure 50 - w rite b urst logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 51 - c onsecutive write- to -write f igure 52 - n onconsecutive write- to -write ck ck# command write nop nop nop nop nop address bank, col b write bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t3n t5n t6 t6n dq dqs, dqs# dm di n di b t dqss (nom) wl t dqss dont care transitioning data wl = 2 wl = 2 1 11 notes: 1. subsequent rising dqs signals must align to the clock within t dqss. 2. di b (or n), etc. = data-in for column b (or column n). 3. three subsequent elements of data-in are applied in the programmed order following di b. 4. three subsequent elements of data-in are applied in the programmed order following di n. 5. shown with bl = 4, al = 0, cl = 3; thus, wl = 2. 6. each write command may be to any bank. ck ck# command write nop write nop nop nop address bank, col b nop bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t6 t5n t3n t1n dq dqs, dqs# dm di n di b dont care transitioning data wl t dqss t dqss (nom) wl = 2 t ccd wl = 2 1 1 1 notes: 1. subsequent rising dqs signals must align to the clock within t dqss. 2. di b, etc. = data-in for column b, etc. 3. three subsequent elements of data-in are applied in the programmed order following di b. 4. three subsequent elements of data-in are applied in the programmed order following di n. 5. shown with bl = 4, al = 0, cl = 3; thus, wl = 2. 6. each write command may be to any bank. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product ck ck# command dq dqs, dqs# wl = 3 write 1 a t0 t1 t2 dont care transitioning data di a t3 t4 t5 t6 write 3 b di b t7 t8 t9 wl = 3 2-clock requirement address a10 valid 6 valid 5 valid 5 valid 4 valid 4 valid 4 nop 2 nop 2 nop 2 nop 2 nop 2 77777 di a + 1 di a + 3 di a + 2 di b + 1 di b + 2 di b + 3 di b + 4 di b + 5 di b + 6 di b + 7 notes: 1. bl = 8 required and auto precharge must be disabled (a10 = low). 2. the nop or command inhibit commands are valid. the precharge command cannot be issued to banks used for writes at t0 and t2. 3. the interrupting write command must be issued exactly 2 t ck from previous write. 4. the earliest write-to-precharge timing for write at t0 is wl + bl/2 + t wr where t wr starts with t7 and not t5 (because bl = 8 from mr and not the truncated length). 5. the write command can be issued to any valid bank and row address (write command at t0 and t2 can be either same bank or different bank). 6. auto precharge can be either enabled (a10 = high) or disabled (a10 = low) by the interrupting write command. 7. subsequent rising dqs signals must align to the clock within t dqss. 8. example shown uses al = 0; cl = 4, bl = 8. f igure 53 - write i nterrupted by write t dqss (nom) ck ck# command write nop nop nop nop nop nop nop address bank a, col b bank a, col n read t0 t1 t2 t3 t2n t4 t5 t9n t3n t6 t7 t8 t9 t wtr 1 cl = 3 cl = 3 cl = 3 dq dqs, dqs# dm di b t dqss (min) dq dqs, dqs# dm di b t dqss (max) dq dqs, dqs# dm di b di di dont care transitioning data wl t dqss wl - t dqss wl + t dqss nop di 2 2 2 notes: 1. t wtr is required for any read following a write to the same device, but it is not required between module ranks. 2. subsequent rising dqs signals must align to the clock within t dqss. 3. di b = data-in for column b; do n = data-out from column n. 4. bl = 4, al = 0, cl = 3; thus, wl = 2. 5. one subsequent element of data-in is applied in the programmed order following di b. 6. t wtr is referenced from the first positive ck edge after the last data-in pair. 7. a10 is low with the write command (auto precharge is disabled). 8. the number of clock cycles required to meet t wtr is either 2 or t wtr/ t ck, whichever is greater. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 54 - write- to -read t dqss (nom) ck ck# command write nop nop nop nop nop address bank a, col b bank, (a or all ) nop t0 t1 t2 t3 t2n t4 t5 t3n t6 t7 t wr t rp dq dqs# dqs dm di b t dqss (min) dq dqs# dqs dm di b t dqss (max) dq dqs# dqs dm di b dont care transitioning data wl + t dqss wl - t dqss wl + t dqss pre 1 1 1 notes: 1. subsequent rising dqs signals must align to the clock within t dqss. 2. di b = data-in for column b. 3. three subsequent elements of data-in are applied in the programmed order following di b. 4. bl = 4, cl = 3, al = 0; thus, wl = 2. 5. t wr is referenced from the first positive ck edge after the last data-in pair. 6. the precharge and write commands are to the same bank. however, the precharge and write commands may be to different banks, in which case t wr is not required and the precharge command could be applied earlier. 7. a10 is low with the write command (auto precharge is disabled). logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 55 - write- to -precharge ck ck# cke a10 t ck t ch t cl ra t rcd t ras t rp t wr t0 t1 t2 t3 t5 t6 t6n t7 t8 t9 t5n nop 1 nop 1 command 3 5 act ra col n write 2 nop 1 one bank all banks bank x pre bank x nop 1 nop 1 nop 1 t dqsl t dqsh t wpst bank x 4 dq 6 dm di n dont care transitioning data wl t dqss (nom) t wpre dqs, dqs# address nop 1 wl = 2 t4 bank select notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4 and al = 0 in the case shown. 3. disable auto precharge. 4. dont care if a10 is high at t9. 5. subsequent rising dqs signals must align to the clock within t dqss. 6. di n = data-in for column n; subsequent elements are applied in the programmed order. 7. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. 8. t dss is applicable during t dqss (max) and is referenced from ck t6 or t7. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 56 - b ank w rite ? w ithout a uto p recharge ck ck# cke a10 bank select t ck t ch t cl ra t rcd t ras t rp wr 4 t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t6n nop 1 nop 1 command 3 act ra col n write 2 nop 1 bank x nop 1 bank x nop 1 nop 1 nop 1 t dqsl t dqsh t wpst dq 6 dm wl t dqss (nom) dont care transitioning data t wpre dqs, dqs# address t9 nop 1 wl = 2 di n 5 notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4 and al = 0 in the case shown. 3. enable auto precharge. 4. wr is programmed via mr9Cmr11 and is calculated by dividing t wr (in ns) by t ck and rounding up to the next integer value. 5. subsequent rising dqs signals must align to the clock within t dqss. 6. di n = data-in from column n; subsequent elements are applied in the programmed order. 7. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. 8. t dss is applicable during t dqss (max) and is referenced from ck t6 or t7. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 57 - b ank w rite ? with a uto p recharge ck ck# cke a10 bank select t ck t ch t cl ra t rcd t ras t rpa t wr 5 t0 t1 t2 t3 t4 t5 t7n t6 t7 t8 t6n nop 1 nop 1 command 3 act ra col n write 2 nop 1 one bank all banks bank x bank x nop 1 nop 1 nop 1 nop 1 nop 1 nop 1 t dqsl t dqsh t wpst bank x 4 dq 7 dm dont care transitioning data wl t dqss (nom) t wpre pre dqs, dqs# address t9 t10 t11 al = 1 wl = 2 di n 6 notes: 1. nop commands are shown for ease of illustration; other commands may be valid at these times. 2. bl = 4, al = 1, and wl = 2 in the case shown. 3. disable auto precharge. 4. dont care if a10 is high at t11. 5. t wr starts at the end of the data burst regardless of the data mask condition. 6. subsequent rising dqs signals must align to the clock within t dqss. 7. di n = data-in for column n; subsequent elements are applied in the programmed order. 8. t dsh is applicable during t dqss (min) and is referenced from ck t6 or t7. 9. t dss is applicable during t dqss (max) and is referenced from ck t7 or t8. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 90 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 58 - write ? dm o peration dqs dqs# t dqsh t wpst t dqsl t dss 2 t dsh 1 t dsh 1 t dss 2 dm dq ck ck# t1 t0 t1n t2 t2n t3 t4 t3n di dont care transitioning data t wpre 3 wl - t dqss (nom) notes: 1. t dsh (min) generally occurs during t dqss (min). 2. t dss (min) generally occurs during t dqss (max). 3. subsequent rising dqs signals must align to the clock within t dqss. 4. write command issued at t0. 5. for x16, ldqs controls the lower byte and udqs controls the upper byte. 6. write command with wl = 2 (cl = 3, al = 0) issued at t0. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 91 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 59 - d ata i nput t iming 3 5 ( & + $ 5 * ( f d q e h l q l w l d w h g e \ h l w k h u d p d q x d o 3 5 ( & + $ 5 * ( f r p p d q g r u e \ d q $ 8 7 2 3 5 ( & + $ 5 * ( l q f r q m x q f w l r q z l w k h l w k h u d 5 ( $ ' r u : 5 , 7 ( f r p - p d q g 3 5 ( & + $ 5 * ( z l o o g h d f w l y d w h w k h r s h q u r z l q d s d u w l f x o d u e d q n r u w k h r s h q u r z l q d o o e d q n v 7 k h 3 5 ( & + $ 5 * ( r s h u d w l r q l v v k r z q l q w k h s u h y l r x v 5 ( $ ' d q g : 5 , 7 ( r s h u d w l r q v h f w l r q v ' x u l q j d p d q x d o 3 5 ( & + $ 5 * ( f r p p d q g w k h $ 10 l q s x w g h w h u p l q h v z k h w k h u r q h r u d o o e d q n v d u h w r e h 3 5 ( & + $ 5 * ( ' , q w k h f d v h z k h u h r q o \ r q h e d q n l v w r e h s u h f k d u j h g e d q n d g g u h v v l q s x w v g h w h u p l q h w k h e d q n w r e h s u h f k d u j h g : k h q d o o e d q n v d u h w r e h s u h f k d u j h g w k h e d q n d g g u h v v l q s x w v d u h w u h d w h g d v v ' r q u w & d u h w 2 q f h d e d q n k d v e h h q 3 5 ( & + $ 5 * ( ' l w l v l q w k h l g o h v w d w h d q g p x v w e h d f w l y d w h g s u l r u w r d q \ 5 ( $ ' r u : 5 , 7 ( f r p p d q g v e h l q j l v v x h g w r w k d w e d q n : k h q d v l q j o h e d q n 3 5 ( & + $ 5 * ( f r p p d q g l v l v v x h g t 5 3 w l p l q j d s s o l h v : k h q w k h 3 5 ( & + $ 5 * ( $ / / f r p p d q g l v l v v x h g t 5 3 $ w l p l q j d s s o l h v u h j d u g o h v v r i w k h q x p e h u r i e d q n v r s h q h g precharge logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 92 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 7 k h , q g x v w u l d o w h p s h u d w x u h ' ' 5 l 0 2 ' g h y l f h v z k h q 7 c l v d ? & u h t x l u h v d 5 ( ) 5 ( 6 + f \ f o h d w d q d y h u d j h l q w h u y d o r i ? 6 0 $ ; d q g d o o u r z v l q d o o e d q n v p x v w e h u h i u h v k h g d w o h d v w r q f h h y h u \ p v 7 k h 5 ( ) 5 ( 6 + e h j l q v z k h q w k h 5 ( ) 5 ( 6 + f r p p d q g l v u h j l v w h u h g d q g h q g v t 5 ) & 0 , 1 o d w h u 7 k h d y h u d j h l q w h u y d o p x v w e h u h g x f h g w r ? 6 0 $ ; z k h q 7 c l v ! ? & refresh ck ck# command nop 1 nop 1 nop 1 pre cke ra address a10 bank bank(s) 3 ba ref nop 1 ref 2 nop 1 act nop 1 one bank all banks t ck t ch t cl ra dq 4 dm 4 dqs, dqs# 4 t rfc 2 t rp t rfc (min) t0 t1 t2 t3 t4 ta0 tb0 ta1 tb1 tb2 dont care indicates a break in time scale notes: 1. nop commands are shown for ease of illustration; other valid commands may be possi- ble at these times. cke must be active during clock positive transitions. 2. the second refresh is not required and is only shown as an example of two back-to- back refresh commands. 3. dont care if a10 is high at this point; a10 must be high if more than one bank is active (must precharge all active banks). 4. dm, dq, and dqs signals are all dont care/high-z for operations shown. f igure 60 - r efresh m ode ck 1 ck# command nop ref address cke 1 valid dq dm dqs#, dqs nop 4 t rp 8 t ch t cl t ck 1 t ck 1 t xsnr 2, 5, 10 t isxr 2 enter self refresh mode (synchronous) exit self refresh mode (asynchronous) t0 t1 ta2 ta1 dont care ta0 tc0 tb0 t xsrd 2, 7 valid 5 nop 4 t cke (min) 9 t2 odt 6 t aofd/ t aofpd 6 td0 valid 7 valid 5 indicates a break in time scale t ih t ih t cke 3 notes: 1. clock must be stable and meeting t ck specifications at least 1 t ck after entering self refresh mode and at least 1 t ck prior to exiting self refresh mode. 2. self refresh exit is asynchronous; however, t xsnr and t xsrd timing starts at the first ris- ing clock edge where cke high satisfies t isxr. 3. cke must stay high until t xsrd is met; however, if self refresh is being re-entered, cke may go back low after t xsnr is satisfied. 4. nop or deselect commands are required prior to exiting self refresh until state tc0, which allows any nonread command. 5. t xsnr is required before any nonread command can be applied. 6. odt must be disabled and r tt off ( t aofd and t aofpd have been satisfied) prior to enter- ing self refresh at state t1. 7. t xsrd (200 cycles of ck) is required before a read command can be applied at state td0. 8. device must be in the all banks idle state prior to entering self refresh mode. 9. after self refresh has been entered, t cke (min) must be satisfied prior to exiting self refresh. 10. upon exiting self refresh, odt must remain low until t xsrd is satisfied. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 93 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 7 k h 6 ( / ) 5 ( ) 5 ( 6 + f r p p d q g l v l q l w l d w h g z k h q & . ( l v o r z 7 k h g l i i h u h q w l d o f o r f n v k r x o g u h p d l q v w d e o h d q g p h h w t & . ( v s h f l i l f d w l r q v d w o h d v w [ t & . d i w h u h q w h u l q j 6 ( / ) 5 ( ) 5 ( 6 + p r g h 7 k h s u r f h g x u h i r u h [ l w l q j 6 ( / ) 5 ( ) 5 ( 6 + u h t x l u h v d v h t x h q f h r i f r p p d q g v ) l u v w w k h g l i i h u h q w l d o f o r f n p x v w e h v w d e o h d q g meet t & . v s h f l i l f d w l r q v d w o h d v w [ t & . s u l r u w r & . ( j r l q j e d f n w r + , * + 2 q f h & . ( l v + , * + t & . ( > 0 , 1 @ k d v e h h q v d w l v i l h g z l w k w k u h h f o r f n u h j l v w u d w l r q v w k h ' ' 5 l 0 2 ' p x v w k d y h 1 2 3 r u ' ( 6 ( / ( & 7 f r p p d q g v l v v x h g i r u t ; 6 1 5 $ v l p s o h d o j r u l w k p i r u p h h w l q j e r w k 5 ( ) 5 ( 6 + d q g ' / / u h t x l u h p h q w v l v x v h g w r d s s o \ 1 2 3 r u ' ( 6 ( / ( & 7 f r p p d q g v i r u f o r f n f \ f o h v e h i r u h d s s o \ l q j d q \ r w k h u f r p p d q g self refresh f igure 61 - s elf r efresh logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product ' ' 5 l 0 2 ' g h y l f h v v x s s r u w p x o w l s o h 3 2 : ( 5 ' 2 : 1 p r g h v w k d w d o o r z v l j q l i l f d q w s r z h u v d y l q j v r y h u q r u p d o r s h u d w l q j p r g h v & . ( l v x v h g w r h q w h u d q g h [ l w g l i i h u h q w 3 2 : ( 5 ' 2 : 1 p r g h v 3 2 : ( 5 ' 2 : 1 h q w u \ d q g h [ l w w l p l q j v d u h v k r z q l q ) l j x u h ' h w d l o h g 3 2 : ( 5 ' 2 : 1 h q w u \ f r q g l w l r q v d u h v k r z q l q ) l j x u h 7 d e o h l v w k h & . ( 7 u x w k 7 d e o h ' ' 5 l 0 2 ' g h y l f h u h t x l u h & / ( w r e h u h j l v w h u h g + , * + d f w l y h d w d o o w l p h v w k d w d q d f f h v v l v l q s u r j u h v v i u r p w k h l v v x l q j r i d 5 ( $ ' r u : 5 , 7 ( f r p p d q g x q w l o f r p s o h w l r q r i w k h e x u v w 7 k x v d f o r f n v x v s h q g l v q r w v x s s r u w h g ) r u 5 ( $ ' v d e x u v w f r p s o h w l r q l v g h i l q h g z k h q w k h 5 ( $ ' s r v w d p e o h d q g t : 5 : 5 , 7 ( w r 3 5 ( & + $ 5 * ( f r p p d q g r u t : 7 5 : 5 , 7 ( w r 5 ( $ ' f r p p d q g d u h v d w l v i l h g d v v k r z q l q ) l j x u h d q g ) l j x u h r u ) l j x u h 7 k h q x p e h u r i f o r f n f \ f o h v u h t x l u h g w r p h h w t : 7 5 l v h l w k h u w z r r u t : 7 5 w & . z k l f k h y h u l v j u h d w h u 3 2 : ( 5 ' 2 : 1 p r g h l v h q w h u h g z k h q & . ( l v u h j l v w h u h g o r z f r l q f l g h q w z l w k d q 1 2 3 r u ' ( 6 ( / ( & 7 f r p p d q g & . ( l v q r w d o o r z h g w r j r / 2 : g x u l q j d 0 2 ' ( 5 ( * , 6 7 ( 5 r u ( ; 7 ( 1 ' ( ' 0 2 ' ( 5 ( * , 6 7 ( 5 f r p p d q g w l p h r u z k l o h d 5 ( $ ' r u : 5 , 7 ( r s h u d w l r q l v l q s u r j u h v v , i 3 2 : ( 5 ' 2 : 1 r f f x u v z k h q d o o e d q n v d u h l g o h w k l v p r g h l v u h i h u u h g w r d v 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 , i 3 2 : ( 5 ' 2 : 1 r f f x u v z k h q w k h u h l v d u r z d f w l y h l q d q \ e d q n w k l v p r g h l v u h i h u u h g w r d v $ & 7 , 9 ( 3 2 : ( 5 ' 2 : 1 ( q w h u l q j 3 2 : ( 5 ' 2 : 1 g h d f w l y d w h v w k h l q s x w d q g r x w s x w e x i i h u v h [ f o x g l q j & . & . ? 2 ' 7 d q g & . ( ) r u p d [ l p x p s r z h u v d y l q j v w k h ' / / l v i u r ] h q g x u l q j 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 ( [ l w l q j $ & 7 , 9 ( 3 2 : ( 5 ' 2 : 1 u h t x l u h v w k h g h y l f h w r e h d w v d p h y r o w d j h d q g i u h t x h q f \ d v z k h q l w h q w h u h g 3 2 : ( 5 ' 2 : 1 ( [ l w l q j 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 u h t x l u h v w k h g h y l f h w r e h d w w k h v d p h y r o w d j h d v z k h q l w h q w h u h g 3 2 : ( 5 ' 2 : 1 k r z h y h u w k h f o r f n i u h t x h q f \ l v d o o r z h g w r f k d q j h 7 k h p d [ l p x p g x u d w l r q i r u h l w k h u $ & 7 , 9 ( r u 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 l v o l p l w h g e \ w k h 5 ( ) 5 ( 6 + u h t x l u h p h q w v r i w k h g h y l f h v t 5 ) & 0 $ ; 7 k h p l q l p x p g x u d w l r q i r u 3 2 : ( 5 ' 2 : 1 h q w u \ d q g h [ l w l v o l p l w h g e \ w k h t & . ( 0 , 1 s d u d p h w h u 7 k h i r o o r z l q j p x v w e h p d l q w d l q h g z k l o h l q 3 2 : ( 5 ' 2 : 1 p r g h & . ( / 2 : d v w d e o h f o r f n v l j q d o d v w d e o h s r z h u v x s s o \ v l j q d o d w w k h l q s x w v r i w k h ' ' 5 l 0 2 ' $ o o r w k h u l q s x w v l j q d o v d u h v ' r q u w & d u h w h [ f h s w 2 ' 7 7 k h 3 2 : ( 5 ' 2 : 1 v w d w h l v v \ q f k u r q r x v o \ h [ l w h g z k h q & . ( l v u h j l v w h u h g + , * + l q f r q m x q f w l r q z l w k d 1 2 3 r u ' ( 6 ( / ( & 7 f r p p d q g power down mode logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 95 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product ck ck# command nop nop nop address cke dq dm dqs, dqs# valid t ch t cl enter power-down mode 6 exit power-down mode dont care t cke (min) 2 t cke (min) 2 valid valid 1 valid t xp 3 , t xard 4 t xards 5 valid valid t is t ih t ih t1 t2 t3 t4 t5 t6 t7 t8 t ck notes: 1. if this command is a precharge (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. if this command is an activate (or if at least one row is already active), then the power-down mode shown is active power- down. 2. t cke (min) of three clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the three clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + 2 t ck + t ih. cke must not transition during its t is and t ih window. 3. t xp timing is used for exit precharge power-down and active power-down to any non- read command. 4. t xard timing is used for exit active power-down to read command if fast exit is selec- ted via mr (bit 12 = 0). 5. t xards timing is used for exit active power-down to read command if slow exit is selec- ted via mr (bit 12 = 1). 6. no column accesses are allowed to be in progress at the time power-down is entered. if the dll was not in a locked state when cke went low, the dll must be reset after exiting power-down mode for proper read operation. f igure 62 - p ower -d own logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 96 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product current state power-down self refresh bank(s) active all banks active t able 41: t ruth t able - cke action (n) notes 0 d l q w d l q 3 2 : ( 5 ' 2 : 1 3 2 : ( 5 ' 2 : 1 h [ l w 0 d l q w d l q 6 ( / ) 5 ( ) 5 ( 6 + self-refresh exit $ f w l y h 3 2 : ( 5 ' 2 : 1 h q w u \ 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 h q w u \ 6 ( / ) 5 ( ) 5 ( 6 + h q w u \ 1-6 command (n) cs\, ras\, cas\, we\ ; ' ( 6 ( / ( & 7 2 5 1 2 3 ; ' ( 6 ( / ( & 7 2 5 1 2 3 ' ( 6 ( / ( & 7 2 5 1 2 3 ' ( 6 ( / ( & 7 2 5 1 2 3 refresh l h l h l l l h l l l l h h h h cke curr. cycle (n) prev. cycle (n-1) 6 k r z q l q 7 d e o h 9 d o l g f r p p d q g v i r u 3 2 : ( 5 ' 2 : 1 ( q w u \ d q g ( [ l w d u h 1 2 3 d q g ' ( 6 ( / ( & 7 2 q o \ 2 q 6 ( / ) 5 ( ) 5 ( 6 + ( [ l w ' ( 6 ( / ( & 7 r u 1 2 3 f r p p d q g v p x v w e h l v v x h g r q h y h u \ f o r f n h g j h r f f x u u l q j g x u l q j w k h t ; 6 1 5 s h u l r g 5 ( $ ' f r p p d q g v p d \ e h l v v x h g r q o \ d i w h u t ; 6 5 ' f o r f n v l v v d w l v i l h g 9 d o l g f r p p d q g v i r u 6 ( / ) 5 ( ) 5 ( 6 + ( [ l w d u h 1 2 3 d q g ' ( 6 ( / ( & 7 r q o \ 3 2 : ( 5 ' 2 : 1 d q g 6 ( / ) 5 ( ) 5 ( 6 + f d q q r w e h h q w h u h g z k l o h 5 ( $ ' r u : 5 , 7 ( r s h u d w l r q v / 2 $ ' 0 2 ' ( r u 3 5 ( & + $ 5 * ( r s h u d w l r q v d u h l q s u r j u h v v 6 h h 6 ( / ) 5 ( ) 5 ( 6 + i r u d o l v w r i u h v w u l f w l r q v 0 l q l p x p & . ( + , * + w l p h l v t cke=3 x t & . 0 l q l p x p & . ( / 2 : w l p h l v t cke = 3 x t & . 7 k l v u h t x l u h v d p l q l p x p r i f o r f n f \ f o h v r i u h j l v w u d - w l r q 6 ( / ) 5 ( ) 5 ( 6 + p r g h f d q r q o \ e h h q w h u h g i u r p w k h $ / / % $ 1 . 6 l g o h v w d w h 0 x v w e h d o h j d o f r p p d q g d v g h i l q h g l q 7 d e o h 1 2 7 ( 6 & . ( q l v w k h o r j l f v w d w h r i & . ( d w f o r f n h g j h q & . ( q z d v w k h v w d w h r i & . ( d w w k h s u h y l r x v f o r f n h g j h & x u u h q w v w d w h l v w k h v w d w h r i w k h ' ' 5 6 ' 5 $ 0 l p p h g l d w h o \ s u l r u w r f o r f n h g j h q & r p p d q g q l v w k h f r p p d q g u h j l v w h u h g d w f o r f n h g j h q d q g d f w l r q q l v d u h v x o w r i f r p p d q g q 7 k h v w d w h r i 2 ' 7 g r h v q r w d i i h f w w k h v w d w h v g h v f u l e h g l q w k l v w d e o h 7 k h 2 ' 7 i x q f w l r q l v q r w d y d l o d e o h g x u l q j 6 ( / ) 5 ( ) 5 ( 6 + 3 2 : ( 5 ' 2 : 1 p r g h v g r q r w s h u i r u p d q \ 5 ( ) 5 ( 6 + r s h u d w l r q v 7 k h g x u d w l r q r i 3 2 : ( 5 ' 2 : 1 p r g h l v w k h u h i r u h o l p l w h g e \ w k h 5 ( ) 5 ( 6 + u h t x l u h p h q w v v ; w p h d q v v ' 2 1 u 7 & $ 5 ( w l q f o x g l q j i o r d w l q j d u r x q g 9 ref l q 6 ( / ) 5 ( ) 5 ( 6 + d q g 3 2 : ( 5 ' 2 : 1 + r z h y h u 2 ' 7 p x v w e h g u l y h q + , * + r u / 2 : l q 3 2 : ( 5 ' 2 : 1 l i w k h 2 ' 7 i x q f w l r q l v h q d e o h g y l d w k h ( 0 5 h [ w h q g h g p r g h u h j l v w h u $ o o v w d w h v d q g v h t x h q f h v q r w v k r z q d u h l o o h j d o r u u h v h u y h g x q o h v v h [ s o l f - l w o \ g h v f u l e h g h o v h z k h u h l q w k l v g r f x p h q w d o c k c k # command dq dqs, dqs# rl = 3 t0 t1 t2 don t care t ransitioning data n op n op t3 t4 t5 va l id t6 t7 t c k e ( m in) address a 10 n op c k e read va l id p ower-down 2 or se l f refres h entr y n op 1 va l id d o d o d o notes: 1 .in t h e examp l e s h own, read burst c omp l etes at t5; ear l iest power-down or se l f refres h entr y is at t6 . 2 . p ower-down or se l f refres h entr y ma y o cc ur after t h e read burst c omp l etes. ck ck# command dq dqs, dqs# rl = 3 t0 t1 t2 dont care transitioning data nop nop t3 t4 t 5 valid valid t6 t 7 t cke (min) address a10 nop cke read valid power-down or self refresh 2 entry nop 1 do do do do notes: 1. in the example shown, read burst completes at t5; earliest power-down or self refresh entry is at t6. 2. power-down or self refresh entry may occur after the read burst completes. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 63 - read- to -p ower -d own or s elf r efresh e ntry f igure 64 - read with a uto p recharge - to -p ower -d own or s elf r efresh e ntry logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product ck ck# command dq dqs, dqs# wl = 3 t0 t1 t2 dont care transitioning data nop nop do t3 t4 t5 valid valid t6 valid t7 t8 t cke (min) address a10 nop write valid power-down or self refresh entry 1 t wtr nop 1 do do do cke note: 1. power-down or self refresh entry may occur after the write burst completes. f igure 65 - write- to -p ower -d own or s elf r efresh e ntry ck ck# command dq dqs, dqs# rl = 3 t0 t1 t2 dont care transitioning data nop nop t3 t4 t 5 valid valid t6 t 7 t cke (min) address a10 nop cke read valid power-down or self refresh 2 entry nop 1 do do do do notes: 1. in the example shown, read burst completes at t5; earliest power-down or self refresh entry is at t6. 2. power-down or self refresh entry may occur after the read burst completes. f igure 66 - write with a uto p recharge - to -p ower -d own or s elf r efresh e ntry logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 99 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product ck ck# command dont care t0 t1 valid refresh t2 t3 t cke (min) cke power-down 1 entry 1 x t ck nop note: 1. the earliest precharge power-down entry may occur is at t2, which is 1 t ck after the refresh command. precharge power-down entry occurs prior to t rfc (min) being satisfied. f igure 67 - refresh c ommand - to -p ower -d own e ntry c k c k # command don t care t0 t1 va l id ac t t2 n op t3 t c k e ( m in) c k e p ower-down 1 entr y 1 t c k address valid note: 1. the earliest active power-down entry may occur is at t2, which is 1 t ck after the activate command. active power-down entry occurs prior to t rcd (min) being satisfied. f igure 68 - activate c ommand - to -p ower -d own e ntry ck ck# command dont care t0 t1 valid pre t2 nop t3 t cke (min) cke power-down 1 entry 1 x t ck address a10 valid all banks vs single bank note: 1. the earliest precharge power-down entry may occur is at t2, which is 1 t ck after the precharge command. precharge power-down entry occurs prior to t rp (min) being satisfied. logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 100 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 69 - precharge c ommand - to -p ower -d own e ntry logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 101 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product ck ck# command dont c t0 t1 valid lm t2 nop t3 t4 t cke (min) cke power-down 3 entry t mrd address valid 1 t rp 2 nop notes: 1. valid address for lm command includes mr, emr, emr(2), and emr(3) registers. 2. all banks must be in the precharged state and t rp met prior to issuing lm command. 3. the earliest precharge power-down entry is at t3, which is after t mrd is satisfied. f igure 70 - load mode c ommand - to -p ower -d own e ntry logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 102 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product : k h q w k h ' ' 5 l 0 2 ' g h y l f h l v l q 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 p r g h 2 ' 7 p x v w e h w x u q h g r i i d q g & . ( p x v w e h d w d o r j l f / 2 : o h y h o $ p l q l p x p r i w z r g l i i h u h q w l d o f o r f n f \ f o h v p x v w s d v v d i w h u & . ( j r h v / 2 : e h i r u h f o r f n i u h t x h q f \ p d \ f k d q j h 7 k h g h y l f h l q s x w f o r f n i u h t x h q f \ l v d o o r z h g w r f k d q j h r q o \ z l w k l q p l q l p x p d q g p d [ l p x p r s h u d w l q j i u h t x h q f l h v v s h f l i l h g i r u w k h s d u w l f x o d u v s h h g j u d g h ' x u l q j l q s x w o r f n i u h t x h q f \ f k d q j h 2 ' 7 d q g & . ( p x v w e h k h o g v w d e o h / 2 : o h y h o v : k h q w k h l q s x w f o r f n i u h t x h q f \ l v f k d q j h g q h z v w d e o h f o r f n v p x v w e h s u r y l g h g w r w k h g h y l f h e h i r u h 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 p d \ e h h [ l w h g d q g ' / / p x v w e h u h v h w y l d 0 5 d i w h u 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 h [ l w ' h s h q g l q j r q w k h q h z f o r f n i u h t x h q f \ d g g l w l r q d o / 0 f r p p d q g v p l j k w e h u h t x l u h g w r d g m x v w w k h & / : 5 $ / d q g v r i r u w k ' h s h q g l q j r q w k h q h z f o r f n i u h t x h q f \ d q g d g g l w l r q d o / 0 f r p p d q g p l j k w e h u h t x l u h g w r d s s u r s u l d w h o \ v h w w k h : 5 0 5 0 5 d q g 0 5 ' x u l q j w k h ' / / u h o r f n s h u l r g r i f \ f o h v 2 ' 7 p x v w u h p d l q r i i $ i w h u w k h ' / / / r f n w l p h w k h ' ' 5 l v u h d g \ w r r s h u d w h z l w k d q h z f o r f n i u h t x h q f \ precharge power down clock frequency change ck ck# command valid 4 nop address cke dq dm dqs, dqs# nop t ck enter precharge power-down mode exit precharge power-down mode t0 t1 t3 ta0 t2 dont care valid t cke (min) 3 t xp lm dll reset valid valid nop t ch t cl ta1 ta2 tb0 ta3 2 x t ck (min) 1 1 x t ck (min) 2 t ch t cl t ck odt 200 x t ck nop ta4 previous clock frequency new clock frequency frequency change indicates a break in time scale high-z high-z t cke (min) 3 notes: 1. a minimum of 2 t ck is required after entering precharge power-down prior to changing clock frequencies. 2. when the new clock frequency has changed and is stable, a minimum of 1 t ck is required prior to exiting precharge power-down. f igure 71 - i nput c lock f requency c hange d uring p recharge p ower -d own m ode logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 103 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 7 k h ' ' 5 d s s o l f d w l r q v p d \ i r u f h d 5 ( 6 ( 7 v w d w h w r w k h g h y l f h d q \ w l p h g x u l q j q r u p d o r s h u d w l r q , i d q d s s o l f d w l r q r u f r q w u r o e o r f n g l u h f w v w k h ' ' 5 g h y l f h r u d u u d \ w r h q w h u 5 ( 6 ( 7 f r q g l w l r q & . ( l v x v h g w r h q v x u h w k h g h y l f h u h v x p h v q r u p d o r s h u d w l r q d i w h u u h l q l w l d o l ] d w l r q $ o o g d w d z l o o e h o r v w g x u l q j d 5 ( 6 ( 7 f r q g l w l r q k r z h y h u w k h ' ' 5 l 0 2 ' z l o o f r q w l q x h w r r s h u d w h s u r s h u o \ l i w k h i r o o r z l q j f r q g l w l r q v r x w o l q h g l q w k l v v h f w l r q d u h v d w l v i l h g 7 k h 5 ( 6 ( 7 f r q g l w l r q g h i l q h g k h u h d v v x p h v d o o v x s s o \ y r o w d j h v d o o v x s s o \ y r o w d j h v d q g 9 ref d u h v w d e o h d q g p h h w d o o ' & v s h f l i l f d w l r q j x l g h o l q h v s u l r u w r g x u l q j d q g d i w h u w k h 5 ( 6 ( 7 r s h u d w l r q $ o o r w k h u l q s x w v r i w k h g h y l f h d u h d v ' r q u w & d u h w g x u l q j 5 ( 6 ( 7 z l w k w k h h [ f h s w l r q r i & . ( , i & . ( g u r s v / 2 : d v \ q f k u r q r x v o \ g x u l q j d q \ y d o l g r s h u d w l r q l q f o x g l q j d 5 ( $ ' r u : 5 , 7 ( e x u v w w k h p h p r u \ f r q w u r o o h u p x v w v d w l v i \ w k h w l p l q j s d u d p h w h u t ' ( / $ < e h i r u h w x u q l q j r i i w k h f o r f n v 6 w d e o h f o r f n v p x v w h [ l v w d w w k h & . & . ? l q s x w v r i w k h ' 5 $ 0 e h i r u h & . ( l v g u l y h q + , * + d w z k l f k w l p h w k h q r u p d o l q l w l d o - l ] d w l r q v h t x h q f h p x v w r f f x u 7 k h ' ' 5 g h y l f h l v q r z u h d g \ i r u q r u p d o r s h u d w l r q d i w h u w k h l q l w l d o l ] d w l r q v h t x h q f h ) l j x u h v k r z v w k h s u r s h u v h t x h q f h i r u d 5 ( 6 ( 7 r s h u d w l r q reset logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product cke r tt bank address high-z dm 3 dqs 3 high-z address a10 ck ck# t cl command nop 2 pre all banks ta0 dont care transitioning data t rpa t cl t ck odt dq 3 high-z t = 400ns (min) tb0 read nop 2 t0 t1 t2 col n bank a t delay 1 do do read nop 2 col n bank b high-z high-z unknown r tt on system reset t3 t4 t5 start of normal 5 initialization sequence nop 2 indicates a break in time scale 4 t cke (min) do notes: 1. vdd, vddl, vddq, vtt, and vref must be valid at all times. 2. either nop or deselect command may be applied. 3. dm represents dm for x4/x8 configuration and udm, ldm for x16 configuration. dqs represents dqs, dqs#, udqs, udqs#, ldqs, ldqs#, rdqs, and rdqs# for the appropri- ate configuration (x4, x8, x16). 4. in certain cases where a read cycle is interrupted, cke going high may result in the completion of the burst. 5. initialization timing is shown in figure 35. f igure 72 - reset f unction logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 105 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product 2 q f h d q v g h o d \ t 0 2 ' k d v e h h q v d w l v i l h g d q g d i w h u w k h 2 ' 7 i x q f w l r q k d v e h h q h q d e o h g y l d w k h ( 0 5 / 2 $ ' 0 2 ' ( f r p p d q g 2 ' 7 f d q e h d f f h v v h g x q g h u w z r w l p l q j f d w h j r u l h v 2 ' 7 z l o o r s h u d w h h l w k h u l q v \ q f k u r q r x v p r g h r u d v \ q f k u r q r x v p r g h g h s h q g l q j r q w k h v w d w h r i & . ( 2 ' 7 f d q v z l w f k d q \ w l p h h [ f h s w g x u l q j v h o i 5 ( ) 5 ( 6 + p r g h d q g d i h z f o r f n v d i w h u e h l q j h q d e o h g y l d w k h ( 0 5 d v v k r z q l q ) l j x u h 7 k h u h d u h w z r w l p l q j f d w h j r u l h v i r u 2 ' 7 7 8 5 1 2 1 d q g 7 8 5 1 2 ) ) ' x u l q j d f w l y h p r g h & . ( + , * + d q g i d v w h [ l w 3 2 : ( 5 ' 2 : 1 p r g h d q \ u r z r i d q \ e d q n r s h q & . ( / 2 : 0 5 > @ t $ 2 1 ' t $ 2 1 t $ 2 ) ' d q g t $ 2 ) w l p l q j s d u d p h w h u v d u h d s s o l h g d v v k r z q l q ) l j x u h ' x u l q j v o r z h [ l w 3 2 : ( 5 ' 2 : 1 p r g h d q g 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 p r g h w $ 2 1 3 ' d q g w $ 2 ) 3 ' w l p l q j s d u d p h w h u v d u h d s s o l h g d v v k r z q l q ) l j x u h 2 ' 7 w x u q r i i w l p l q j s u l r u w r h q w h u l q j d q \ 3 2 : ( 5 ' 2 : 1 p r g h l v g h w h u p l q h g e \ w k h s d u d p h w h u t $ 1 3 ' 0 , 1 d v v k r z q l q ) l j x u h $ w v w d w h 7 2 w k h 2 ' 7 + , * + v l j q d o v d w l v i l h v w $ 1 3 ' 0 , 1 s u l r u w r h q w h u l q j 3 2 : ( 5 ' 2 : 1 p r g h d w 7 5 : k h q t $ 1 3 ' 0 , 1 l v v d w l v i l h g t $ 2 ) ' d q g t $ 2 ) w l p l q j s d u d p h w h u v d s s o \ ) l j x u h d o v r v k r z v w k h h [ d p s o h z k h u h t $ 1 3 ' 0 , 1 l v 1 2 7 v d w l v i l h g e h f d x v h 2 ' 7 + , * + g r h v q r w r f f x u x q w l o v w d w h 7 3 : k h q t $ 1 3 ' 0 , 1 l v 1 2 7 v d w l v i l h g t $ 2 1 3 ' w l p l q j s d u d p h w h u v d s s o \ 2 ' 7 w x u q r q w l p l q j s u l r u w r h q w h u l q j d q \ 3 2 : ( 5 ' 2 : 1 p r g h l v g h w h u p l q h g e \ w k h s d u d p h w h u t $ 1 3 ' 0 , 1 d v v k r z q l q ) l j x u h $ w v w d w h 7 2 w k h 2 ' 7 + , * + v l j q d o v d w l v i l h v t $ 1 3 ' 0 , 1 s u l r u w r h q w h u l q j 3 2 : ( 5 ' 2 : 1 p r g h d w 7 5 : k h q t $ 1 3 ' 0 , 1 l v v d w l v i l h g t $ 2 ) ' d q g t $ 2 ) w l p l q j s d u d p h w h u v d s s o \ ) l j x u h d o v r v k r z v w k h h [ d p s o h z k h u h t $ 1 3 ' 0 , 1 l v 1 2 7 v d w l v i l h g e h f d x v h 2 ' 7 + , * + g r h v q r w r f f x u x q w l o v w d w h 7 3 : k h q t $ 1 3 ' 0 , 1 l v 1 2 7 v d w l v i l h g t $ 2 1 3 ' w l p l q j s d u d p h w h u v d s s o \ 2 ' 7 w x u q r i i w l p l q j d i w h u h [ l w l q j d q \ 3 2 : ( 5 ' 2 : 1 p r g h l v g h w h u p l q h g e \ w k h s d u d p h w h u t $ ; 3 ' 0 , 1 d v v k r z q l q ) l j x u h $ w v w d w h 7 d 1 w k h 2 ' 7 / 2 : v l j q d o v d w l v i l h v t $ ; 3 ' 0 , 1 d i w h u h [ l w l q j 3 2 : ( 5 ' 2 : 1 p r g h d w v w d w 7 1 : k h q t $ ; 3 ' 0 , 1 l v v d w l v i l h g t $ 2 3 ' d q g t $ 2 ) w l p l q j s d u d p h w h u v d s s o \ ) l j x u h d o v r v k r z v w k h h [ d p s o h z k h u h t $ ; 3 ' 0 , 1 l v 1 2 7 v d w l v i l h g e h f d x v h 2 ' 7 / 2 : r f f x u v d w v w d w h 7 d 0 : k h q t $ ; 3 ' 0 , 1 l v 1 2 7 v d w l v i l h g t $ 2 ) 3 ' w l p l q j s d u d p h w h u v d s s o \ 2 ' 7 w x u q r q w l p l q j d i w h u h [ l w l q j h l w k h u v o r z h [ l w 3 2 : ( 5 ' 2 : 1 p r g h r u 3 5 ( & + $ 5 * ( 3 2 : ( 5 ' 2 : 1 p r g h l v g h w h u p l q h g e \ w k h s d u d p h w h u t $ ; 3 ' 0 , 1 d v v k r z q l q ) l j x u h $ w v w d w h 7 d 1 w k h 2 ' 7 + , * + v l j q d o v d w l v i l h v t $ ; 3 ' 0 , 1 d i w h u h [ l w l q j 3 2 : ( 5 ' 2 : 1 p r g h d w v w d w h 7 1 : k h q t $ ; 3 ' 0 , 1 l v v d w l v i l h g t $ 2 1 ' d q g t $ 2 1 w l p l q j s d u d p h w h u v d s s o \ ) l j x u h d o v r v k r z v w k h h [ d p s o h z k h u h t $ ; 3 ' 0 , 1 l v 1 2 7 v d w l v i l h g e h f d x v h 2 ' 7 + , * + r f f x u v d w 7 d 0 : k h q t $ ; 3 ' 0 , 1 l v 1 2 7 v d w l v i l h g t $ 2 1 3 ' w l p l q j s d u d p h w h u v d s s o \ odt timing t anpd (3 t cks) first cke latched low t axpd (8 t cks) first cke latched high synchronous applicable modes applicable timing parameters synchronous synchronous or asynchronous any mode except self refresh mode any mode except self refresh mode active power-down fast (synchronous) active power-down slow (asynchronous) precharge power-down (asynchronous) t aond/ t aofd (synchronous) t aonpd/ t aofpd (asynchronous) t aond/ t aofd t aond/ t aofd cke f igure 73 - odt t iming for e ntering and e xiting p ower -d own m ode logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 106 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 74 - t iming for mrs c ommand to odt u pdate d elay ck# ck odt 2 internal r tt setting emrs 1 nop nop nop nop nop command t mod old setting undefined new setting 0ns 2 t is t aofd indicates a break in time scale t0 ta0 ta1 ta2 ta3 ta4 ta5 notes: 1. the lm command is directed to the mode register, which updates the information in emr (a6, a2), that is, r tt (nominal). 2. to prevent any impedance glitch on the channel, the following conditions must be met: t aofd must be met before issuing the lm command; odt must remain low for the entire duration of the t mod window until t mod is met. ' x u l q j q r u p d o r s h u d w l r q w k h y d o x h r i w k h h i i h f w l y h w h u p l q d w l r q u h v l v w d q f h f d q e h f k d q j h g z l w k d q ( 0 5 6 v h w f r p p d q g t 0 2 ' 0 $ ; x s g d w h v w k h 5 7 7 v h w w l q j mrs command to odt update delay t1 t0 t2 t3 t4 t5 t6 valid valid valid valid valid valid valid ck# ck odt r tt t aof (max) t aon (min) t aond address t aofd t aon (max) t aof (min) valid valid valid valid valid valid valid command t ch t cl dont care r tt unknown r tt on t ck cke logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 75 - odt t iming for a ctive or f ast -e xit p ower -d own m ode logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 76 - odt t iming for s low -e xit or p recharge p ower -d own m odes dont car e t1 t0 t2 t3 t4 t5 t6 valid valid valid valid valid valid valid ck# ck cke odt address valid valid valid valid valid valid valid command t c h t cl t aonpd (min) t aonpd (max) t aofpd (min) t aofpd (max) transitioning r tt t7 valid valid r tt unknown r tt on t ck r tt logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 109 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 77 - odt t urn -o ff t imings w hen e ntering p ower -d own m ode t1 t0 t2 t3 t4 t5 t6 nop nop nop nop nop nop nop ck# ck command cke odt r tt t aof (min) t aof (max) t aofd odt r tt t aofpd (min) dont care transitioning r tt r tt unknown r tt on t anpd (min) t aofpd (max) logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 110 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 78 - odt t urn -o n t iming w hen e ntering p ower -d own m ode t1 t0 t2 t3 t4 t5 t6 nop nop nop nop nop nop nop ck# ck r tt t aon (min) t aon (max) odt r tt t aonpd (min) t aonpd (max) dont care transitioning r tt r tt unknown r tt on odt command t aond cke t anpd (min) logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 111 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product f igure 79 - odt t urn -o ff t iming w hen e xiting p ower -d own m ode transitioning r tt t1 t0 t2 t3 t4 ta0 ta1 nop nop nop nop nop nop nop ck# ck cke t axpd (min) odt r tt t aof (max) odt r tt t aofpd (min) t aofpd (max) command ta2 ta3 ta4 ta5 nop nop nop nop dont care r tt unknown t aof (min) indicates a break in time scale r tt on t cke (min) t aofd logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 112 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product list of figures ) l j x u h 6 ' 5 $ 0 ' ' 5 3 l q r x w 9 l h z ) l j x u h ) x q f w l r q d o % o r f n ' l d j u d p ) l j x u h ' ' 5 3 d u w 1 x p e h u v ) l j x u h 6 l p s o l i l h g 6 w d w h ' l d j u d p ) l j x u h 0 h f k d q l f d o ' u d z l q j ) l j x u h 6 l q j o h ( q g h g , q s x w 6 l j q d o / h y h o v ) l j x u h ' l i i h u h q w l d o , q s x w 6 l j q d o / h y h o v ) l j x u h ' l i i h u h q w l d o 2 x w s x w 6 l j q d o / h y h o v ) l j x u h 2 x w s x w 6 o h z 5 d w h / r d g ) l j x u h ) x o o 6 w u h q j w k 3 x o o ' r z q & k d u d f w h u l v w l f v ) l j x u h ) x o o 6 w u h q j w k 3 x o o 8 s & k d u d f w h u l v w l f v ) l j x u h 5 h g x f h g 6 w u h q j w k 3 x o o ' r z q & k d u d f w h u l v w l f v ) l j x u h 5 h g x f h g 6 w u h q j w k 3 x o o 8 s & k d u d f w h u l v w l f v ) l j x u h , q s x w & o d p s & k d u d f w h u l v w l f v ) l j x u h 2 y h u v k r r w 6 s h f l i l f d w l r q v ) l j x u h 8 q g h u v k r r w 6 s h f l i l f d w l r q v ) l j x u h 1 r p l q d o 6 o h z 5 d w h i r u t , 6 ) l j x u h 7 d q j h q w / l q h i r u t , 6 ) l j x u h 1 r p l q d o 6 o h z 5 d w h i r u t , + ) l j x u h 7 d q j h q w / l q h i r u t , + ) l j x u h 1 r p l q d o 6 o h z 5 d w h i r u t ds 53 ) l j x u h 7 d q j h q w / l q h i r u t ds 53 ) l j x u h 1 r p l q d o 6 o h z 5 d w h i r u t ' + ) l j x u h 7 d q j h q w / l q h i r u t ' + ) l j x u h $ & , q s x w 7 h v w 6 l j q d o : d y h i r u p & r p p d q g $ g g u h v v % d o o v ) l j x u h $ & , q s x w 7 h v w 6 l j q d o : d y h i r u p i r u ' d w d z l w k ' 4 6 ' 4 6 ' l i i h u h q w l d o ) l j x u h $ & , q s x w 7 h v w 6 l j q d o : d y h i r u p i r u ' d w d z l w k ' 4 6 6 l q j o h ( q g h g ) l j x u h $ & , q s x w 7 h v w 6 l j q d o : d y h i r u p ' l i i h u h q w l d o ) l j x u h 0 5 ' h i l q l w l r q v ) l j x u h & / ) l j x u h ( 0 5 ' h i l q l w l r q v ) l j x u h 5 ( $ ' / d w h q f \ ) l j x u h : 5 , 7 ( / d w h q f \ ) l j x u h ( 0 5 ' h i l q l w l r q v ) l j x u h ( 0 5 ' h i l q l w l r q v ) l j x u h ' ' 5 3 r z h u 8 s d q g , q l w l d o l ] d w l r q ) l j x u h ( [ d p s o h 0 h h w l q j t 5 5 ' 0 , 1 d q g t 5 & ' 0 , 1 ) l j x u h 0 x o w l e d q n $ f w l y d w h 5 h v w u l f w l r q ) l j x u h 5 ( $ ' / d w h q f \ ) l j x u h & r q v h f x w l y h 5 ( $ ' % x u v w v ) l j x u h 1 r q f r q v h f x w l y h 5 ( $ ' % x u v w v ) l j x u h 5 ( $ ' , q w h u u x s w h g e \ 5 ( $ ' ) l j x u h 5 ( $ ' w r : 5 , 7 ( ) l j x u h 5 ( $ ' w r 3 5 ( & + $ 5 * ( % / ) l j x u h 5 ( $ ' w r 3 5 ( & + $ 5 * ( % / ) l j x u h % d q n 5 h d g : l w k r x w $ x w r 3 u h f k d u j h ) l j x u h % d q n 5 h d g : l w k $ x w r 3 u h f k d u j h ) l j x u h ' d w d 2 x w s x w 7 l p l q j t ' 4 6 4 t 4 + d q g ' d w d 9 d o l g : l q g r z logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 113 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product ) l j x u h ' d w d 2 x w s x w 7 l p l q j t $ & d q g t ' 4 6 & . ) l j x u h : u l w h % x u v w ) l j x u h & r q v h f x w l y h : 5 , 7 ( w r : 5 , 7 ( ) l j x u h 1 r q f r q v h f x w l y h : 5 , 7 ( w r : 5 , 7 ( ) l j x u h : 5 , 7 ( , q w h u u x s w h g e \ : 5 , 7 ( ) l j x u h : 5 , 7 ( w r 5 ( $ ' ) l j x u h : 5 , 7 ( w r 3 5 ( & + $ 5 * ( ) l j x u h % d q n : u l w h : l w k r x w $ x w r 3 u h f k d u j h ) l j x u h % d q n : u l w h : l w k $ x w r 3 u h f k d u j h ) l j x u h : 5 , 7 ( ' 0 2 s h u d w l r q ) l j x u h ' d w d , q s x w 7 l p l q j ) l j x u h 5 h i u h v k 0 r g h ) l j x u h 6 h o i 5 h i u h v k ) l j x u h 3 r z h u ' r z q ) l j x u h 5 ( $ ' w r 3 r z h u ' r z q r u 6 h o i 5 h i u h v k ( q w u \ ) l j x u h 5 ( $ ' z l w k $ x w r 3 u h f k d u j h w r 3 r z h u ' r z q r u 6 h o i 5 h i u h v k ( q w u \ ) l j x u h : 5 , 7 ( w r 3 r z h u ' r z q r u 6 h o i 5 h i u h v k ( q w u \ ) l j x u h : 5 , 7 ( z l w k $ x w r 3 u h f k d u j h w r 3 r z h u ' r z q r u 6 h o i 5 h i u h v k ( q w u \ ) l j x u h 5 ( ) 5 ( 6 + & r p p d q g w r 3 r z h u ' r z q ( q w u \ ) l j x u h $ & 7 , 9 $ 7 ( & r p p d q g w r 3 r z h u ' r z q ( q w u \ ) l j x u h 3 5 ( & + $ 5 * ( & r p p d q g w r 3 r z h u ' r z q ( q w u \ ) l j x u h / 2 $ ' 0 2 ' ( & r p p d q g w r 3 r z h u ' r z q ( q w u \ ) l j x u h , q s x w & o r f n ) u h t x h q f \ & k d q j h ' x u l q j 3 u h f k d u j h 3 r z h u ' r z q 0 r g h ) l j x u h 5 ( 6 ( 7 ) x q f w l r q ) l j x u h 2 ' 7 7 l p l q j i r u ( q w h u l q j d q g ( [ l w l q j 3 r z h u ' r z q 0 r g h ) l j x u h 7 l p l q j i r u 0 5 6 & r p p d q g w r 2 ' 7 8 s g d w h ' h o d \ ) l j x u h 2 ' 7 7 l p l q j i r u $ f w l y h r u ) d v w ( [ l w 3 r z h u ' r z q 0 r g h ) l j x u h 2 ' 7 7 l p l q j i r u 6 o r z ( [ l w r u 3 u h f k d u j h 3 r z h u ' r z q 0 r g h v ) l j x u h 2 ' 7 7 x u q 2 i i 7 l p l q j v : k h q ( q w h u l q j 3 r z h u ' r z q 0 r g h ) l j x u h 2 ' 7 7 x u q 2 q 7 l p l q j : k h q ( q w h u l q j 3 r z h u ' r z q 0 r g h ) l j x u h 2 ' 7 7 x u q 2 i i 7 l p l q j : k h q ( [ l w l q j 3 r z h u ' r z q 0 r g h logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product list of tables 7 d e o h 3 l q % d o o / r f d w l r q v d q g ' h v f u l s w l r q v 7 d e o h $ g g u h v v l q j 7 d e o h . h \ 3 d u d p h w h u v 7 d e o h $ e v r o x w h 0 d [ l p x p ' & 5 d w l q j v 7 d e o h 5 h f r p p h q g h g ' & 2 s h u d w l q j & r q g l w l r q v 7 d e o h , q s x w , q s x w 2 x w s x w & d s d f l w d q f h 7 d e o h * h q h u d o , dd 3 d u d p h w h u v 7 d e o h , ' ' 7 l p l q j 3 d w w h u q v % d q n , q w h u o h d y h 5 ( $ ' 2 s h u d w l r q 7 d e o h ' ' 5 , dd 6 s h f l i l f d w l r q v d q g & r q g l w l r q v 7 d e o h $ & 7 l p l q j 6 s h f l i l f d w l r q v 7 d e o h 2 ' 7 ( o h f w u l f d o & k d u d f w h u l v w l f v 7 d e o h , q s x w ' & / r j l f / h y h o v 7 d e o h , q s x w $ & / r j l f / h y h o v 7 d e o h ' l i i h u h q w l d o , q s x w / r j l f / h y h o 7 d e o h ' l i i h u h q w l d o $ & 2 x w s x w 3 d u d p h w h u v 7 d e o h 2 x w s x w ' & & x u u h q w ' u l y h 7 d e o h 2 x w s x w & k d u d f w h u l v w l f v 7 d e o h ) x o o 6 w u h q j w k 3 x o o ' r z q & x u u h q w p $ 7 d e o h ) x o o 6 w u h q j w k 3 x o o 8 s & x u u h q w p $ 7 d e o h 5 h g x f h g 6 w u h q j w k 3 x o o ' r z q & x u u h q w p $ 7 d e o h 5 h g x f h g 6 w u h q j w k 3 x o o 8 s & x u u h q w p $ 7 d e o h , q s x w & o d p s & k d u d f w h u l v w l f v 7 d e o h $ g g u h v v d q g & r q w u r o v 3 l q v 7 d e o h & o r f n ' d w d 6 w u r e h d q g 0 d v n 3 l q v 7 d e o h $ & , q s x w 7 h v w & r q g l w l r q v 7 d e o h ' ' 5 6 h w x s d q g + r o g 7 l p h ' h u d w l q j 9 d o x h v t , 6 t , + 7 d e o h ' ' 5 6 h w x s d q g + r o g 7 l p h ' h u d w l q j 9 d o x h v t , 6 t , + 7 d e o h ' ' 5 t ds, t ' + ' h u d w l q j 9 d o x h v z l w k ' l i i h u h q w l d o 6 w u r e h 7 d e o h ' ' 5 t ds, t ' + ' h u d w l q j 9 d o x h v z l w k ' l i i h u h q w l d o 6 w u r e h 7 d e o h 6 l q j o h ( q g h g ' 4 6 6 o h z 5 d w h ' h u d w l q j 9 d o x h v 8 v l q j t dsb, t dhb 51 7 d e o h 6 l q j o h ( q g h g ' 4 6 6 o h z 5 d w h ) x o o \ ' h u d w h g ' 4 6 ' 4 d w 9 5 ( ) d w ' ' 5 7 d e o h 6 l q j o h ( q g h g ' 4 6 6 o h z 5 d w h ) x o o \ ' h u d w h g ' 4 6 ' 4 d w 9 5 ( ) d w ' ' 5 7 d e o h 6 l q j o h ( q g h g ' 4 6 6 o h z 5 d w h ) x o o \ ' h u d w h g ' 4 6 ' 4 d w 9 5 ( ) d w ' ' 5 7 d e o h 7 u x w k 7 d e o h ' ' 5 & r p p d q g v 7 d e o h 7 u x w k 7 d e o h & x u u h q w 6 w d w h % d q n q & r p p d q g w r % d q n q 7 d e o h 7 u x w k 7 d e o h & x u u h q w 6 w d w h % d q n q & r p p d q g w r % d q n p 7 d e o h 0 l q l p x p ' h o d \ z l w k $ x w r 3 u h f k d u j h ( q d e o h g 7 d e o h % x u v w ' h i l q l w l r q 7 d e o h 5 ( $ ' 8 v l q j & r q f x u u h q w $ x w r 3 u h f k d u j h 7 d e o h : 5 , 7 ( 8 v l q j & r q f x u u h q w $ x w r 3 u h f k d u j h 7 d e o h 7 u x w k 7 d e o h & . ( / 2 * , & ' h y l f h v , q f r u s r u d w h g u h v h u y h v w k h u l j k w w r p d n h f r u u h f w l r q v p r g l i l f d w l r q v h q k d q f h p h q w v l p s u r y h p h q w v d q g r w k h u f k d q j h v w r l w v s u r g x f w v d q g v h u y l f h v d w d q \ w l p h d q g w r g l v f r q w l q x h d q \ s u r g x f w r u v h u y l f h z l w k r x w q r w l f h & x v w r p h u v v k r x o g r e w d l q w k h o d w h v w u h o h y d q w l q i r u p d - w l r q e h i r u h s o d f l q j r u g h u v d q g v k r x o g y h u l i \ w k d w v x f k l q i r u p d w l r q l v f x u u h q w d q g f r p s o h w h / 2 * , & ' h y l f h v g r h v q r w d v v x p h d q \ o l d e l o l w \ d u l v l q j r x w r i w k h d s s o l f d w l r q r u x v h r i d q \ s u r g x f w r u f l u f x l w g h v f u l e h g k h u h l q , q q r h y h q w v k d o o d q \ o l d e l o l w \ h [ f h h g w k h s u r g x f w s x u f k d v h s u l f h / 2 * , & ' h y l f h v e h o l h y h v w k h l q i r u p d w l r q f r q w d l q h g k h u h l q l v d f f x u d w h k r z h y h u l w l v q r w o l d e o h i r u l q d g y h u w h q w h u u r u v , q i r u p d w l r q v x e m h f w w r f k d q j h z l w k r x w q r w l f h / 2 * , & ' h y l f h v d v v x p h v q r o l d e l o l w \ i r u x v h r i l w v s u r g x f w v l q p l v v l r q f u l w l f d o r u o l i h v x s s r u w d s s o l f d w l r q v 3 u r g x f w v r i / 2 * , & ' h y l f h v d u h q r w z d u u d q w h g q r u l q w h q g h g w r e h x v h g i r u p h g l f d o o l i h v x s s r u w o l i h v d y l q j f u l w l f d o f r q w u r o r u v d i h w \ d s s o l f d w l r q v x q o h v v s x u v x d q w w r d q h [ s u h v v z u l w w h q d j u h h p h q w z l w k / 2 * , & ' h y l f h v ) x u w k h u p r u h / 2 * , & ' h y l f h v g r h v q r w d x w k r u l ] h l w v s u r g x f w v i r u x v h d v f u l w l f d o f r p s r q h q w v l q o l i h v x s s r u w v \ v w h p v z k h u h d p d o i x q f w l r q r u i d l o x u h p d \ u h d v r q d e o \ e h h [ s h f w h g w r u h v x o w l q v l j q l i l f d q w l q m x u \ w r w k h x v h u logic devices incorporated www.logicdevices.com september 16, 2013 lds-l9d2xxmxxsbg5 rev e 115 2 - 5.0 gb, ddr2, 32 m [64 m] x 64/72/80 integrated memory module (imod) l9d232m64sbg5 l9d232m72sbg5 L9D232M80SBG5 l9d264m64sbg5 l9d264m72sbg5 l9d264m80sbg5 high performance, integrated memory module product r evision h istory revision engineer issue date description of change $ b c d e , 1 , 7 , $ 7 ( 5 h p r y h g t 3 u h o l p l q d u \ , q i r u p d w l r q u i u r p k h d g l q j & k d q j h g 3 d u w 1 x p e h u $ g g h g / l v w r i 7 d e o h v d q g / l v w r i ) l j x u h v & r u u h f w l r q w r 7 d e o h $ & 7 l p l q j 6 s h f l i l f d w l r q v & r q w l q x h g & r u u h f w l r q w r 7 d e o h 1 r w h v khl khl khl % l o o 9 r o ] % l o o 9 r o ] |
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