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x t april 1999 intel and pentium are registered trademarks of intel corporation. lexmark is a trademark of lexmark international, inc. spread spectrum modulation is licensed under us patent no. 5488627, lexmark international, inc. american microsystems, inc. reserves the right to change the detail specifications as may be requir ed to permit improvements in the design of its products. 4.5.99 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 1.0 features generates clocks required for intel pentium ? ii based systems, including: four enabled 2.5v 100mhz or 66mhz cpu sys- tem bus clock outputs seven enabled 3.3v pci bus clocks and one free-running pci clock three 3.3v ref clocks at 14.318mhz two 2.5v apic clocks at 14.318mhz for apic bus timing two 3.3v 48mhz clocks for 4x universal serial bus (usb) timing non-linear spread spectrum modulation (-0.5% at 31.5khz) selectable 100mhz or 66mhz system bus clock supports intel test mode and tristate output control to facilitate board testing synchronous clocks skew-matched to <175ps on cpu and apic buffers and <250ps on pci buffers separate cpu-enable, pci-enable and power-down inputs with glitch-free stop clock controls on all clocks for clock control and power management all inputs and 3.3v outputs are lvttl-compatible figure 1: block diagram (fs6251) crystal oscillator pll pll 2 48m_0:1 ref_0:2 apic_0:1 sel_0:1 xout cpu_0:3 pci_1:7 xin cpu_stop# pci_stop# pwr_dwn# 2 or 3 delay FS6251-01 vdd_r vss_r vdd_a vss_a vss_c vdd_c vdd_p vss_p vdd_u vss_u (2.5v outputs) sel_100/66# pci_f ss_en# 2.0 description the FS6251-01 is a cmos clock generator ic designed for high-speed motherboard applications. two different frequencies can be selected for the cpu and pci clocks via two sel pins. glitch-free stop clock control of the cpu and pci clocks is provided. a low current power- down mode is available for mobile applications. separate clock buffers provide for a 2.5v voltage range on the cpu_0:3 and apic_0:1 clocks. figure 2: pin configuration (fs6251) 1 48 2 3 4 5 6 7 8 47 46 45 44 43 42 41 ref_0 ref_1 vss_r xin xout pci_1 cpu_1 cpu_0 vss_a ref_2 vdd_a apic_0 vdd_r 9 10 11 12 13 14 15 16 pci_2 vss_p pci_3 pci_4 pci_5 pci_6 vdd_p pci_7 17 18 19 20 21 22 23 vss_p vdd_u 48m_0 48m_1 40 39 38 37 36 35 34 33 vdd cpu_2 cpu_3 vdd_c vss_c 32 31 30 29 28 27 26 sel_0 sel_1 ss_en# pci_stop# cpu_stop# vss 24 vss_u 25 FS6251-01 vss_p pci_f vdd_p vdd vss sel_100/66# pwr_dwn# vss_c vdd_c apic_1 (reserved) (2.5v outputs) 48-pin ssop figure 2: pin configuration (fs6252) 1 28 2 3 4 5 6 7 8 27 26 25 24 23 22 21 xin xout pci_1 cpu_1 cpu_0 ref_2 vss_r vdd_r 9 10 11 12 13 14 pci_2 vdd_p pci_3 pci_4 pci_5 vdd_p vss_p 20 19 18 17 16 15 vdd vss_c sel pci_stop# cpu_stop# vss fs6252-01 vss_p pci_f vdd vss sel_100/66# pwr_dwn# vdd_c (2.5v outputs) 28-pin ssop, soic table 1: cpu/pci frequency selection sel_100/66# sel_1 sel_0 cpu (mhz) pci (mhz) 0 0 0 tristate tristate 00170 35 0 1 0 73.33 36.67 0 1 1 66.67 33.33 1 0 0 xin/2 xin/6 1 0 1 105 35 1 1 0 110 36.67 1 1 1 100 33.33
x t april 1999 4.5.99 2 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 table 2: pin descriptions key: ai = analog input; ao = analog output; di = digital input; di u = input with internal pull-up; di d = input with internal pull-down; dio = digital input/output; di-3 = three-level digital input, do = digital output; p = power/ground; # = active-low pin pin (fs6251) pin (fs6252) type name description 22, 23 - do 48m_0:1 two 48mhz clock outputs for universal serial bus (usb) timing 35, 36, 39, 40 23, 24 do cpu_0:3 four low-skew (<175ps @ 1.25v) 2.5v to 3.3v cpu clock outputs for host frequencies. (two copies of the cpu clock are available in fs6252 version) 30 18 di u cpu_stop# cpu_0:3 clock output enable. asynchronous, active-low disable stops all cpu clocks in the low state. 44, 45 - do apic_0:1 two buffered low-skew (<175ps @ 1.25v) 2.5v/3.3v outputs of the 14.318mhz reference clock for apic bus timing 8, 10, 11, 13, 14, 16, 17 5, 7, 8, 9 do pci_1:7 seven low-skew (<250ps @ 1.5v) 3.3v pci clock outputs. pci clocks are synchronous with cpu clocks but lag the cpu clocks by 1ns to 4ns. (four copies of the pci clock are available in fs6252 version) 7 4 do pci_f one free-running 3.3v pci clock output. 31 19 di u pci_stop# pci_1:7 clock output enable. asynchronous, active-low disable stops all pci clocks in the low state. 29 17 di u pwr_dwn# asynchronous active-low power-down signal shuts down oscillator, all plls, puts all clocks in low state. clock re-enable latency of 3ms. 1, 2, 47 26 do ref_0:2 three buffered outputs of the 14.318mhz reference clock. (one copy of the reference clock is available in fs6252 version) 26, 27 16 di u sel_0:1 two frequency select inputs (both sel pins are tied together in fs6252 version) 25 15 di sel_100/66# selects 100mhz or 66mhz cpu clock frequency (pull-up/pull-down must be provided externally) 28 - di u ss_en# spread spectrum enable. active-low enable turns on the spread spectrum feature; a logic-high turns off the spread spectrum modulation. 19, 33 13, 21 p vdd 3.3v 10% 46 - p vdd_a power supply for 2.5v apic_0:1 clock outputs 37, 41 25 p vdd_c power supply for 2.5v cpu_0:3 clock outputs 9, 15 9, 12 p vdd_p power supply for 3.3v pci_1:7 and pci_f clock outputs 48 27 p vdd_r power supply for 3.3v ref_0:2 clock outputs 21 - p vdd_u power supply for 3.3v 48m_0:1 clock outputs 20, 32 14, 20 p vss ground 43 - p vss_a ground for apic_0:1 clock outputs 34, 38 22 p vss_c ground for cpu_0:3 clock outputs 6, 12, 18 3, 12 p vss_p ground for pci_1:7 and pci_f clock outputs 3 28 p vss_r ground for ref_0:2 clock outputs 24 - p vss_u ground for 48m_0:1 clock outputs 4 1 ai xin 14.318mhz crystal oscillator feedback 5 2 ao xout 14.318mhz crystal oscillator drive 42 - - (reserved) reserved
x t april 1999 4.5.99 3 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 table 3: actual clock frequencies note: spread spectrum is disabled clock target (mhz) actual (mhz) deviation (ppm) 100.00 99.9963 -37 cpu_0:3 66.67 66.6536 -196 33.33 (with cpu = 100) 33.3321 -37 pci_1:7, pci_f 33.33 (with cpu = 66.67) 33.3268 -196 48m_0:1 (1) 48.00 48.0080 +167 (1) 48mhz usb clock is required to be 167ppm off from 48.000mhz to conform to usb requirements. 3.0 programming information table 4: function/clock enable configuration control inputs clock outputs (mhz) sel_ 100/66# sel_1 sel_0 pwr_ dwn# cpu_ stop# pci_ stop# ref_0:2 cpu_0:3 pci_f pci_1:7 apic_ 0:1 48m_0:1 0 0 0 1 x x tristate tristate tristate tristate tristate tristate 0 0 1 1 1 1 14.318 70 35 35 14.318 48 0 1 0 1 1 1 14.318 73.33 36.67 36.67 14.318 48 0 1 1 1 1 1 14.318 66.67 33.33 33.33 14.318 48 100111xin xin2 xin6 xin6 xin xin2 1 0 1 1 1 1 14.318 105 35 35 14.318 48 1 1 0 1 1 1 14.318 110 36.67 36.67 14.318 48 1 1 1 1 1 1 14.318 100 33.33 33.33 14.318 48 x x x 0 x x low low low low low low 1 0 0 14.318 low running low 14.318 48 1 0 1 14.318 low running running 14.318 48 1 1 0 14.318 running running low 14.318 48 sel_0:1 and sel_100/66# 1 0 1 1 1 14.318 running running running 14.318 48 3.1 frequency selection output frequencies may be selected via three pins: sel_100/66#, sel_1 and sel_0. all three pins should be fixed at a logic state before power-up occurs. table 4 provides a guide to pin operation. 3.1.1 sel_1, sel_0 pins these two pins either tristate the output drivers, select the test mode frequency, or choose the cpu and pci frequencies. both the sel_1 and sel_0 pins have pull- ups that default the cpu output frequency to either 66mhz or 100mhz, depending on the state of the sel_100/66# pin. both 5% and 10% overclocking fre- quencies are available for system testing. both pins are bonded together on the fs6252 as the sel pin. 3.1.2 sel_100/66# pin this pin is an active-low lvttl input that switches be- tween a 100mhz or a 66mhz system (cpu) clock. a pull- up or pull-down must be provided externally.
x t april 1999 4.5.99 4 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 3.2 stop clock control three pins control the clock outputs: cpu_stop#, pci_stop# and pwr_dwn#. 3.2.1 cpu-enable, pci-enable the cpu_stop# pin is an active-low lvttl input pin that disables the cpu_0:3 clocks for low power opera- tion. cpu_stop# can be asserted asynchronously, and the stop clock control is glitch-free, in that the cpu clock must complete a full cycle before the clock is stopped low. the pci_stop# pin is an active-low lvttl input pin that disables the pci_1:7 clocks for low power operation, ex- cept for the pci_f clock. the pci_f is a free-running clock, and will continue to run even if all other pci clocks have stopped. pci_stop# can be asserted asynchro- nously, and the stop-clock control is glitch-free, in that the pci clock must complete a full cycle before the clock is stopped low. 3.2.2 power down the pwr_dwn# signal is an asynchronous, active-low lvttl input that puts the device in a low power inactive state without removing power from the device. all internal clocks are turned off, and all clock outputs are held low. powering down occurs in less than two pci clocks from the falling edge of pwr_dwn# to when all clock outputs are forced low. 4.0 clock latency all clock outputs are stopped in the low state, and are started so that the first high pulse is a full pulse width. all clocks complete a full period on transitions between run- ning (enabled) and stopped (disabled) to ensure glitch- free stop clock control. all enabled clocks will continue to run while disabled clocks are stopped. the clock enable signals are as- sumed to be asynchronous inputs relative to clock out- puts. enable signals are synchronized to their respective clocks by this device. the cpu and pci clocks will tran- sition between running and stopped according to table 5. 4.1 power-up latency power-up latency is defined as the time from the moment when pwr_dwn# goes inactive (a rising edge) to when the first valid clocks are driven from the device. upon re- lease of pwr_dwn#, external circuitry should allow a minimum of 3ms for the plls to lock before enabling any clocks. 4.2 clock enable latency clock enable latency is defined in the number of rising edges of free-running cpu clocks between when the en- able signal becomes active (a rising edge) to when the first valid clock is driven from the device. figure 2: cpu_stop# timing cpu clock (internal) pci clock (internal) cpu_stop# cpu_0:3
x t april 1999 4.5.99 5 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 figure 3: pci_stop# timing cpu clock (internal) pci clock (internal) pci_stop# pci_1:7 figure 4: pwr_dwn# timing cpu clock (internal) pci clock (internal) pwr_dwn# pci_1:7 cpu_0:3 vco crystal oscillator shaded regions in the crystal oscillator and vco waveforms indicate that the clock is valid and the crystal oscillator and vco are active. table 5: latency table cpu clock enable latency (number of rising edges of the cpu clock) signal signal state min. max. pci clock enable latency (number of rising edges of the pci clock) 0 disabled 2 3 1 cpu_stop# 1 enabled 2 3 1 0 disabled 2 3 1 pci_stop# 1 enabled 2 3 1 0 power off 1 4 2 (max.) pwr_dwn# 1 power on 3ms 3ms 3ms
x t april 1999 4.5.99 6 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 5.0 spread spectrum modulation to limit peak emi emissions, high-speed motherboard designs now require the reduction of the peak harmonic energy contained in the system bus frequencies. a re- duction in the peak energy of a specific frequency can be accomplished by spreading the energy over a limited range of frequencies through a technique known as spread spectrum clocking. in this technique, a generated clock frequency is dithered in a tightly controlled sweep near the clock frequency using a predetermined modula- tion profile and period. figure 5: spectral energy distribution spread- spectrum clock non-spread clock d e (1- d )f nom f nom the amount of emi reduction is directly related to three parameters: the modulation percentage, the frequency of the modulation, and the modulation profile. 5.1 modulation percentage the modulation percentage d , is typically 0.5% of the center frequency (denoted here as f nom ). the modulation percentage determines the range of frequencies the spectral energy is distributed over. for a 100mhz clock frequency, a 0.5% modulation sweeps the clock fre- quency between 99.5mhz and 100.5mhz. if the sweep is symmetrical around the center frequency, the technique is known as center-spread modulation. however, a circuit that is designed for a 100mhz reference may not have enough timing margin to support a clock greater then 100mhz. the clock frequency can instead be modulated between f nom , and (1- d ) f nom, ; the technique is known as down-spread modulation. for a d of C0.5%, the clock will sweep between 99.5mhz and 100mhz. a small degrada- tion in circuit performance may be noticed, as the clock frequency now averages 99.75mhz. 5.2 modulation frequency the frequency of modulation, noted as f m , describes how fast the center frequency sweeps between f nom , and (1- d ) f nom, . typical modulation frequencies must be greater than 30khz (above the audio band) but small enough to not upset system timing. since a tracking pll cannot instantaneously update the output clock to match a modulated input clock, any accumulation of the difference in phase between the modulated input clock and a track- ing pll output clock is called tracking skew. the result- ing phase error will decrease the timing margins in any successive circuitry. 5.3 modulation profile the modulation profile determines the shape of the spectral energy distribution by defining the time that the clock spends at a specific frequency. the longer a clock remains at a specific frequency, the larger the energy concentration at that frequency. a sinusoidal modulation spends a large portion of time between f nom , and (1- d ) f nom , resulting in large energy peaks at the edges of the spectral energy distribution. a linear modulation, such as a triangle profile, improves the spectral distribution but also exhibits energy peaking at the edges. a non-linear modulation profile, known as the hershey kiss profile and patented by lexmark international, inc., offers the best distribution of spectral energy. figure 6: modulation profiles time (1- d )f nom f nom 1/f m time (1- d )f nom f nom 1/f m the type of modulation profile used will also impact tracking skew. the maximum frequency change occurs at the profile limits where the modulation changes the slew rate polarity. to track the sudden reversal in clock fre- quency, the downstream pll must have a large loop bandwidth.
x t april 1999 4.5.99 7 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 compared to the profile limits the modulation slew rate is relatively slow between the limits, allowing the down- stream pll a chance to reduce the tracking skew. the ability of the downstream pll to catch up is determined by the loop transfer function phase angle. spread spectrum clocking can be shown to have a negli- gible effect on cycle-to-cycle jitter performance. any in- crease in jitter is less than 1ps when d <1% and f m <50khz. careful design of downstream plls can en- sure that tracking skew is minimized. to have less than 100ps of tracking skew, a downstream pll should have a loop bandwidth greater than 1mhz, and a phase angle less than 0.1 . figure 7 shows the tracking skew of a downstream pll with a loop bandwidth of 1.5mhz and a phase angle of 0.26 following a non-linear profile-modulated 100mhz input clock with a d =-0.5% and an f m =31.2khz. figure 7: pll tracking skew 100 80 60 40 20 0 20 40 60 80 100 pll tracking skew time [us] skew [ps] 5.4 spread spectrum enable the active-low lvttl ss_en# input pin enables spread spectrum modulation of the cpu and pci clocks. when ss_en# is a logic-high, the spread spectrum modulation of these clocks is disabled. if ss_en# is a logic-low, spread spectrum modulation is enabled. a pull-up on this pin disables spread spectrum modula- tion by default. figure 8: actual modulation profile 65 60 55 50 45 40 35 30 25 20 15 10 5 0 99.6 99.5 99.7 99.8 99.9 100 frequency (mhz) 1/f m (s)
x t april 1999 4.5.99 8 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 6.0 electrical specifications table 6: absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. exposure to maximum rati ng conditions for extended conditions may affect device performance, functionality, and reliability. parameter symbol min. max. units supply voltage (v ss = ground) v dd v ss -0.5 7 v input voltage, dc v i v ss -0.5 v dd +0.5 v output voltage, dc v o v ss -0.5 v dd +0.5 v input clamp current, dc (v i < 0 or v i > v dd )i ik -50 50 ma output clamp current, dc (v i < 0 or v i > v dd )i ok -50 50 ma storage temperature range (non-condensing) t s -65 150 c ambient temperature range, under bias t a -55 125 c junction temperature t j 125 c lead temperature (soldering, 10s) 260 c input static discharge voltage protection (mil-std 883e, method 3015.7) 2 kv caution: electrostatic sensitive device permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy ele c- trostatic discharge. table 7: operating conditions parameter symbol conditions/description min. typ. max. units core (vdd) @ 3.3v 5% 3.135 3.3 3.465 clock buffers (vdd_p, vdd_r, vdd_u) @ 3.3v 5% 3.135 3.3 3.465 supply voltage v dd clock buffers (vdd_a,, vdd_c) @ 2.5v 5% 2.375 2.5 2.625 v operating temperature range t a 070 c crystal resonator frequency f xtal 14.316 14.318 14.32 mhz crystal resonator load capacitance c xl xin, xout pins 13.5 18 22.5 pf 48m_0:1 10 20 apic_0:1 10 20 cpu_0:3 10 20 pci_f, pci_1:7 15 30 load capacitance c l ref_0:2 10 20 pf
x t april 1999 4.5.99 9 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 table 8: dc electrical specifications unless otherwise stated, all power supplies = 3.3v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. negative currents indicate current flows out of the device. parameter symbol conditions/description min. typ. max. units overall f cpu = 100mhz; vdd_a = vdd_c = 3.465v 170 f cpu = 100mhz; vdd_a = vdd_c = 2.625v 100 f cpu = 66.67mhz; vdd_a = vdd_c = 3.465v 170 supply current, dynamic, with loaded outputs i dd f cpu = 66.67mhz; vdd_a = vdd_c = 2.625v 72 ma pwr_dwn# low; vdd_a = vdd_c = 3.465v 48 500 supply current, static i dds pwr_dwn# low; vdd_a = vdd_c = 2.625v 45 100 m a digital inputs (cpu_stop#, pci_stop#, pwr_dwn#, sel_0:1, ss_en#) high-level input voltage v ih 2.0 v dd +0.3 v low-level input voltage v il v ss -0.3 0.8 v high-level input current i ih -1 1 m a low-level input current (pull-up) i pu v il = 0.4v 15 38 50 m a digital input (sel_100/66#) high-level input voltage v ih 2.0 v dd +0.3 v low-level input voltage v il v ss -0.3 0.8 v input leakage current i il -1 1 m a crystal oscillator feedback (xin) threshold bias voltage v th 1.0 1.49 2.0 v high-level input current i ih v ih = 3.3v 34 m a low-level input current i il v il = 0v -50 -34 -15 m a crystal loading capacitance * c l(xtal) as seen by an external crystal connected to xin and xout 13.5 18 22.5 pf input loading capacitance * c l(xin) as seen by an external clock driver on xout; xin unconnected 36 pf crystal oscillator drive (xout) high level output source current i oh v o = 0v -15 -3.0 ma low level output sink current i ol v o = 3.3v 3.0 15 ma cpu_0:3 clock outputs (2.5v type 1 clock buffer) i oh min vdd_c = 2.375v, v o = 1.0v -27 -43 high level output source current i oh max vdd_c = 2.625v, v o = 2.375v -14 -27 ma i ol min vdd_c = 2.375v, v o = 1.2v 27 47 low level output sink current i ol max vdd_c = 2.625v, v o = 0.3v 20 30 ma z ol measured at 1.25v, output driving low 13.5 24 45 output impedance z oh measured at 1.25v, output driving high 13.5 25 45 w tristate output current i oz -10 10 m a short circuit output source current * i sch v o = 0v; shorted for 30s, max. -56 ma short circuit output sink current * i scl v o = 2.5v; shorted for 30s, max. 58 ma
x t april 1999 4.5.99 10 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 table 8: dc electrical specifications, continued unless otherwise stated, all power supplies = 3.3v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. negative currents indicate current flows out of the device. parameter symbol conditions/description min. typ. max. units apic_0:1 clock output (2.5v type 2 clock buffer) i oh min vdd_a = 2.375v, v o = 1.4v -36 -47 high-level output source current i oh max vdd_a = 2.625v, v o = 2.5v -10 -21 ma i ol min vdd_a = 2.375v, v o = 1.0v 36 85 low-level output sink current i ol max vdd_a = 2.625v, v o = 0.2v 21 31 ma z ol measured at 1.25v, output driving low 9 12 30 output impedance z oh measured at 1.25v, output driving high 9 21 30 w tristate output current i oz -10 10 m a short circuit output source current * i osh v o = 0v; shorted for 30s, max. -66 ma short circuit output sink current * i osl v o = 2.5v; shorted for 30s, max. 131 ma ref_0:2, 48m_0:1 clock outputs (3.3v type 3 clock buffer) i oh min vdd_r, vdd_u = 3.135v, v o = 1.0v -29 -34 high-level output source current i oh max vdd_r, vdd_u = 3.465v, v o = 3.135v -12 -23 ma i ol min vdd_r, vdd_u = 3.135v, v o = 1.95v 29 35 low-level output sink current i ol max vdd_r, vdd_u = 3.465v, v o = 0.4v 14 27 ma z ol measured at 1.65v, output driving low 20 41 60 output impedance z oh measured at 1.65v, output driving high 20 42 60 w tristate output current i oz -10 10 m a short circuit output source current * i osh v o = 0v; shorted for 30s, max. -41 ma short circuit output sink current * i osl v o = 3.3v; shorted for 30s, max. 40 ma pci_1:7, pci_f clock outputs (3.3v type 5 clock buffer) i oh min vdd_p = 3.135v, v o = 1.0v -33 -43 high level output source current i oh max vdd_p = 3.465v, v o = 3.135v -15 -33 ma i ol min vdd_p = 3.135v, v o = 1.95v 30 54 low level output sink current i ol max vdd_p = 3.465v, v o = 0.4v 19 38 ma z ol measured at 1.65v, output driving low 12 27 55 output impedance z oh measured at 1.65v, output driving high 12 33 55 w tristate output current i oz -10 10 m a short circuit output source current * i osh v o = 0v; shorted for 30s, max. -51 ma short circuit output sink current * i osl v o = 3.3v; shorted for 30s, max. 62 ma
x t april 1999 4.5.99 11 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 table 9: ac timing specifications unless otherwise stated, all power supplies = 3.3v 5%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. negative currents indicate current flows out of the device. spread spectrum modulation is disabled except for rise/fall time measurements. 100mhz 66.67mhz parameter symbol conditions/description min. typ. max. min. typ. max. units overall spread spectrum modulation frequency * f m ss_en# low 31.5 31.5 khz spread spectrum modulation profile * ss_en# low lexmark lexmark spread spectrum modulation index * d m ss_en# low -0.5 -0.5 % cpu to cpu @ 1.25v, c l =20pf 66 175 50 175 apic to apic @ 1.25v, c l =20pf 32 175 24 175 clock skew * t skw pci to pci @ 1.5v, c l =30pf 48 500 48 500 ps clock offset * t pd cpu @ 1.25v, c l = 20pf to pci @ 1.5v, c l = 30pf 1.5 1.73 4.0 1.5 1.88 4.0 ns tristate enable delay * t dzl, t dzh sel_0:1 and sel_100/66# = 0 1.0 8.0 1.0 8.0 ns tristate disable delay * t dzl, t dzh sel_0:1 and sel_100/66# = 0 1.0 8.0 1.0 8.0 ns clock stabilization (on power-up) * t stb via pwr_dwn# 1.5 3.0 1.6 3.0 ms cpu_0:3 clock outputs (2.5v type 1 clock buffer) duty cycle * ratio of high pulse width, as measured from rising edge to next falling edge at 1.25v, to one clock period 45 55 45 55 % jitter, long term ( s y ( t )) * t j(lt) on rising edges 500 m s apart at 1.25v relative to an ideal clock, c l =20pf, all plls active 295 296 ps jitter, period (peak-peak) * t j( d p) from rising edge to next rising edge at 1.25v, c l =20pf, all plls active 145 250 182 250 ps t r min measured @ 0.4v C 2.0v; c l = 10pf 0.4 0.8 0.4 0.8 rise time * t r max measured @ 0.4v C 2.0v; c l = 20pf 1.1 1.6 1.1 1.6 ns t f min measured @ 2.0v C 0.4v; c l = 10pf 0.4 1.0 0.4 1.0 fall time * t f max measured @ 2.0v C 0.4v; c l = 20pf 1.1 1.6 1.1 1.6 ns enable delay * t dlh via cpu_stop# 7 38 11 42 ns disable delay * t dhl via cpu_stop# 2 33 3 34 ns apic_0:1 clock output (2.5v type 2 clock buffer) duty cycle * ratio of high pulse width, as measured from rising edge to next falling edge at 1.25v, to one clock period 45 55 45 55 % jitter, long term ( s y ( t )) * t j(lt) on rising edges 500 m s apart at 1.25v relative to an ideal clock, c l =20pf, all plls active 50 35 ps jitter, period (peak-peak) * t j( d p) from rising edge to next rising edge at 1.25v, c l =20pf, all plls active 215 237 ps t r min measured @ 0.4v C 2.0v; c l = 10pf 0.4 1.1 0.4 1.1 rise time * t r max measured @ 0.4v C 2.0v; c l = 20pf 1.3 1.6 1.3 1.6 ns t f min measured @ 2.0v C 0.4v; c l = 10pf 0.4 0.6 0.4 0.6 fall time * t f max measured @ 2.0v C 0.4v; c l = 20pf 0.8 1.6 0.8 1.6 ns
x t april 1999 4.5.99 12 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 table 9: ac timing specifications, continued unless otherwise stated, all power supplies = 3.3v %, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal char- acterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. negative currents indicate current flows out of the device. spread spectrum modulation is disabled except for rise/fall time measurements. 100mhz 66.67mhz parameter symbol conditions/description min. typ. max. min. typ. max. units ref_0:2, 48m_0:1 clock outputs (3.3v type 3 clock buffer) duty cycle * ratio of high pulse width, as measured from rising edge to next falling edge at 1.5v, to one clock period 45 55 45 55 % jitter, long term ( s y ( t )) * t j(lt) on rising edges 500 m s apart at 1.5v relative to an ideal clock, c l =20pf, all plls active 51 54 ps jitter, period (peak-peak) * t j( d p) from rising edge to next rising edge at 1.5v, c l =20pf, all plls active 199 252 ps t r min measured @ 0.4v C 2.4v; c l = 10pf 1.0 1.3 1.0 1.3 rise time * t r max measured @ 0.4v C 2.4v; c l = 20pf 2.0 4.0 2.0 4.0 ns t f min measured @ 2.4v C 0.4v; c l = 10pf 1.0 1.6 1.0 1.6 fall time * t f max measured @ 2.4v C 0.4v; c l = 20pf 2.0 4.0 2.0 4.0 ns pci_1:7, pci_f clock outputs (3.3v type 5 clock buffer) duty cycle * ratio of high pulse width, as measured from rising edge to next falling edge at 1.5v, to one clock period 45 55 45 55 % jitter, long term ( s y ( t )) * t j(lt) on rising edges 500 m s apart at 1.5v relative to an ideal clock, c l =30pf, all plls active 293 263 ps jitter, period (peak-peak) * t j( d p) from rising edge to next rising edge at 1.5v, c l =30pf, all plls active 148 500 146 500 ps t r min measured @ 0.4v C 2.4v; c l = 15pf 0.5 1.0 0.5 1.0 rise time * t r max measured @ 0.4v C 2.4v; c l = 30pf 1.4 2.0 1.4 2.0 ns t f min measured @ 2.4v C 0.4v; c l = 15pf 0.5 1.1 0.5 1.1 fall time * t f max measured @ 2.4v C 0.4v; c l = 30pf 1.5 2.0 1.5 2.0 ns enable delay * t dlh via pci_stop# 30 60 30 60 ns disable delay * t dhl via pci_stop# 15 45 15 45 ns
x t april 1999 4.5.99 13 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 figure 9: cpu_0:3 clock outputs (2.5v type 1 clock buffer) high drive current (ma) low drive current (ma) voltage (v) min. typ. max. voltage (v) min. typ. max. 0 0 0 0 0 -28 -61 -107 0.1 3 7 11 0.4 -28 -61 -107 0.2 6 13 21 0.6 -28 -61 -107 0.3 9 19 30 0.8 -28 -61 -107 0.4 12 24 40 1 -27 -60 -105 0.5 15 30 48 1.2 -26 -58 -101 0.6 173556 1.4 -24-53-94 0.7 193963 1.6 -21-48-85 0.8 214370 1.8 -17-40-73 0.9 234777 1.9 -15-36-67 1 245083 2 -12-31-59 1.1 255388 2.1 -9-25-51 1.2 275693 2.2 -6-20-43 1.3 275897 2.3 -3-14-34 1.4 28 60 100 2.375 0 -9 -27 1.6 29 62 106 2.5 0 -14 1.8 29 63 110 2.625 0 2.2 29 63 111 2.375 29 63 111 2.5 63 111 2.625 111 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 2xwsxw9rowdjh9 2 x w s x w & x u u h q w p $ min. typ. max. 40 w 60 w 80 w figure 10: apic_0:1 clock output (2.5v type 2 clock buffer) high drive current (ma) low drive current (ma) voltage (v) min. typ. max. voltage (v) min. typ. max. 0 0 0 0 0 -42 -90 -159 0.1 5 10 16 0.4 -42 -90 -159 0.2 10 19 31 0.6 -42 -90 -159 0.3 14 28 45 0.8 -42 -90 -159 0.4 18 36 59 1 -41 -88 -157 0.5 22 44 72 1.2 -39 -85 -150 0.6 25 51 84 1.4 -36 -78 -140 0.7 29 57 95 1.6 -32 -70 -127 0.8 31 63 105 1.8 -25 -59 -109 0.9 34 69 114 1.9 -22 -52 -99 1 36 73 123 2 -18 -45 -89 1.1 38 78 131 2.1 -14 -37 -77 1.2 40 82 138 2.2 -9 -29 -64 1.3 41 85 144 2.3 -4 -20 -50 1.4 42 88 150 2.375 0 -13 -40 1.6 43 91 158 2.5 0 -21 1.8 43 93 163 2.625 0 2.2 43 93 165 2.375 43 93 165 2.5 93 165 2.625 165 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 00.511.522.53 2xwsxw9rowdjh9 2 x w s x w & x u u h q w p $ min. typ. max. 40 w 60 w 80 w
x t april 1999 4.5.99 14 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 figure 11: ref_0:2, 48m_0:1 clock outputs (3.3v type 3 clock buffer) high drive current (ma) low drive current (ma) voltage (v) min. typ. max. voltage (v) min. typ. max. 0 0 0 0 0 -29 -46 -99 0.4 9 13 27 1 -29 -46 -99 0.65 14 21 41 1.4 -27 -44 -94 0.85 17 26 52 1.5 -27 -43 -92 1 202959 1.65-25-41-89 1.4 253776 1.8 -24-39-85 1.5 263979 2 -22-36-79 1.65 27 41 84 2.4 -16 -28 -63 1.8 284388 2.6 -12-22-53 1.95 29 45 92 3.135 0 -6 -23 3.135 29 45 102 3.3 0 -12 3.6 45 102 3.465 0 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 00.511.522.533.54 2xwsxw9rowdjh9 2 x w s x w & x u u h q w p $ min. typ. max. 30 w 50 w 90 w figure 12: pci_1:7, pci_f clock outputs (3.3v type 5 clock buffer) high drive current (ma) low drive current (ma) voltage (v) min. typ. max. voltage (v) min. typ. max. 0 0 0 0 0 -34 -59 -195 0.4 9.4 18 38 1 -33 -58 -194 0.65 14 30 64 1.4 -31 -55 -189 0.85 17.7 38 84 1.5 -30 -54 -184 1 20 43 100 1.65 -28 -52 -172 1.4 26.5 53 139 1.8 -25.5 -50 -159 1.5 28 55 148 2 -22 -46 -140 1.65 29 56 163 2.4 -14.5 -35 -100 1.8 30 57 175 2.6 -11 -28 -83 1.95 30 58 178 3.135 0 -6 -33 3.135 31 59 187 3.3 0 -19 3.6 32 59 188 3.465 0 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 00.511.522.533.54 2xwsxw9rowdjh9 2 x w s x w & x u u h q w p $ min. typ. max. 40 w 60 w 80 w
x t april 1999 4.5.99 15 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 figure 13: dc measurement points v ih 3.3 = 2.0v v il 3.3 = 0.8v v ol 3.3 = 0.4v v oh 3.3 = 2.4v 1.5v 3.3v v ih 2.5 = 1.7v v il 2.5 = 0.7v 2.5v v ol 2.5 = 0.4v v oh 2.5 = 2.0v 1.25v a. 3.3v clock interface b. 2.5v clock interface (device interface) (system interface) (device interface) (system interface) figure 14: clock skew diagrams t cp skw t cc skw t pp skw 3.3v 2.5v 1.25v 1.5v 2.5v 2.5v 1.25v 1.25v 3.3v 3.3v 1.5v 1.5v t ri skw 3.3v 1.5v 2.5v 1.25v 2.5v to 3.3v clock offset 2.5v to 2.5v clock skew 3.3v to 3.3v clock skew 3.3v to 2.5v clock offset cpu pci cpu cpu pci pci ref ioapic figure 15: timing diagrams t kh t r duty cycle t kl t kp 2.0v 1.25v 0.4v t f t kh t r duty cycle t kl t kp 2.4v 1.5v 0.4v t f a. 3.3v clock interface b. 2.5v clock interface
x t april 1999 4.5.99 16 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 7.0 package information table 10: 48-pin ssop (7.5mm/0.300") package dimensions dimensions inches millimeters min. max. min. max. a 0.095 0.110 2.41 2.79 a 1 0.008 0.016 0.203 0.406 a 2 0.088 0.092 2.24 2.34 b 0.008 0.0135 0.203 0.343 c 0.005 0.010 0.127 0.254 d 0.620 0.630 15.75 16.00 e 0.292 0.299 7.42 7.59 e 0.025 bsc 0.64 bsc h 0.400 0.410 10.16 10.41 l 0.024 0.040 0.610 1.02 q 0 8 0 8 be d a 1 seating plane base plane a 2 a h e 48 1 all radii: 0.005" to 0.01" x t c l 7 typ. q table 11: 48-pin ssop (7.5mm/0.300") package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air q ja air flow = 0 m/s 93 c/w lead inductance, self l 11 center lead 3.3 nh lead inductance, mutual l 12 center lead to any adjacent lead 1.6 nh lead capacitance, bulk c 11 center lead to v ss 0.6 pf lead capacitance, mutual c 12 center lead to any adjacent lead 0.2 pf
x t april 1999 4.5.99 17 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 table 12: 28-pin ssop package dimensions dimensions inches millimeters min. max. min. max. a 0.068 0.078 1.73 2.00 a 1 0.002 0.008 0.05 0.21 a 2 0.066 0.07 1.68 1.78 b 0.01 0.015 0.25 0.38 c 0.005 0.008 0.13 0.20 d 0.396 0.407 10.07 10.33 e 0.205 0.212 5.20 5.38 e 0.028 bsc 0.65 bsc h 0.301 0.311 7.65 7.90 l 0.022 0.037 0.55 0.95 q 0 8 0 8 h e all radii: 0.005" to 0.01" x t 1 28 be d a 1 seating plane base plane a 2 a c l 7 typ. q table 13: 28-pin ssop package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air q ja air flow = 0 m/s 97 c/w lead inductance, self l 11 center lead 2.24 nh lead inductance, mutual l 12 center lead to any adjacent lead 0.95 nh lead capacitance, bulk c 11 center lead to v ss 0.25 pf lead capacitance, mutual c 12 center lead to any adjacent lead 0.07 pf
x t april 1999 4.5.99 18 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 table 14: 28-pin soic (0.300") package dimensions dimensions inches millimeters min. max. min. max. a 0.093 0.104 2.35 2.65 a 1 0.004 0.012 0.10 0.30 a 2 0.08 0.100 2.05 2.55 b 0.013 0.013 0.33 0.51 c 0.009 0.009 0.23 0.32 d 0.697 0.713 17.70 18.10 e 0.291 0.299 7.40 7.60 e 0.05 bsc 1.27 bsc h 0.393 0.419 10.00 10.65 h 0.010 0.030 0.25 0.75 l 0.016 0.05 0.40 1.27 q 0 8 0 8 be d a 1 seating plane base plane a 2 a h e 28 1 all radii: 0.005" to 0.01" x t c l 7 typ. q h x 45 table 15: 28-pin soic (0.300") package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air q ja air flow = 0 m/s 80 c/w lead inductance, self l 11 center lead 2.53 nh lead inductance, mutual l 12 center lead to any adjacent lead 0.85 nh lead capacitance, bulk c 11 center lead to v ss 0.42 pf lead capacitance, mutual c 12 center lead to any adjacent lead 0.08 pf
x t april 1999 4.5.99 19 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 8.0 ordering information device number font ordering code package type operating temperature range shipping configuration fs6251 -01 11525-801 48-pin (7.5mm/0.300) ssop (shrink small outline package) 0 c to 70 c (commercial) tape and reel 11525-802 28-pin (7.5mm/0.300) soic (small outline package) 0 c to 70 c (commercial) tape and reel fs6252 -01 11525-803 28-pin (5.3mm/0.209) ssop (shrink small outline package) 0 c to 70 c (commercial) tape and reel copyright ? 1998, 1999 american microsystems, inc. devices sold by ami are covered by the warranty and patent indemnification provisions appearing in its terms of sale only. ami makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the fr eedom of the described devices from patent infringement. ami makes no warranty of merchantability or fitness for any purposes. ami re - serves the right to discontinue production and change specifications and prices at any time and without notice. amis products are intended for use in commercial applications. applications requiring extended temperature range, unusual environmental require- ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom- mended without additional processing by ami for such applications. american microsystems, inc., 2300 buckskin rd., pocatello, id 83201, (208) 233-4690, fax (208) 234-6796, www address: http://www.amis.com e-mail: tgp@amis.com
x t april 1999 4.5.99 20 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 8.1 pll tracking skew time-domain pll simulator for ssc tracking michael t. zhang intel corp. platform architecture lab. 2111 ne 25th ave., m/s: jf2-54 hillsboro, or 97124-5961 email: michael.t.zhang@intel.com phone: (503)-264-2301 fax: (503)-264-6053 dan clementi american microsystems, inc. timing generator products 768 n. bethlehem pike ambler, pa 19002-2659 email: dclement@focus.amis.com phone: (215)-654-1719 fax: (215)-654-9791 rev 1.0 april 20, 1998 information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or u se of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any pat- ent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life s ustaining ap- plications. intel may make changes to specifications and product descriptions at any time, without notice. patent royalty payments if applicable are not the responsibility of intel. third-party brands and names are the property of their respective owners. copyright 1998, intel corporation, all rights reserved. this application note is a mathcad simulation of downstream pll track- ing skew on a spread spectrum clock with a lexmark profile. the mathcad 7.0 document, along with three different modulation pro- files, may be obtained from intels web site at http://www.intel.com or from amis web site at http://www.amis.com . if either docu- ment is unavailable, contact your lo- cal ami sales representative to obtain a copy. this document is supplied as applica- tion information only, and in no way is intended to imply acceptance of this or any other device by intel.
x t april 1999 4.5.99 21 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 note: inputs are needed for highlighted equations (with yellow background color). read in the modulation profile: (use the .prn file name as the argument of the readprn function. the file names of the three example modulation profiles are: lexmark.prn, triangle.prn, and sin.prn) f readprn "lexmark.prn" ()hz . wavepoints rows f () i 0 wavepoints 1 .. f carrier mean f () f carrier 99.75 mhz = <--the center frequency of the clock d max f ( ) min f () max f () d 0.5 % = <--the spread amount m i if f i min f () i , 1 , n i if f i max f () i , 1 , f m f carrier max m () maxn () 2 . f m 31.17 kh z = <--the modulation frequency input modulation amount (peak to peak in percentage, d_ mod) d _mod 0.5 % . f_mod f carrier max f () dd _mod 2 . ff carrier d _mod d . display the profiles 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 9.94 10 7 9.95 10 7 9.96 10 7 9.98 10 7 9.99 10 7 1 10 8 modulation profile frequency [hz] build up a simulation. the general methodology that we will use here is: compute the phase of the source waveform (the one that is applied to the tracking pll) at a series of points in time. iteratively compute the phase of the tracking pll clock at successive points in the series, take the error between the two cloc ks and adjust the frequency of the tracking pll to suit. note that the spacing of the points is regular. n an actual pll, the cor rec- tions to the loop are applied only on zero crossings of the signals. this deviation from actual practice can be demonstrated t o have a very small effect on the resulting performance of the loop (assuming that no cycle slips are occurring). the simulation time step will be set to the average clock period: t step 1 f carrier set up the range variables for simulation: i 0 wavepoints 1 () .. i1 1 wavepoints 1 () ..
x t april 1999 4.5.99 22 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 compute the accumulated phase of each source clock at each point in the simulation: f 0 0 f i1 f i1 1 2 p . f_mod i1 . t step . define the parameters of the tracking pll: g vco 400 mhz volt . <--the vco gain (not including any feedback divider) n fb 2 <--the modulus of the feedback divider r 9750 ohm . <--the loop filter resistor c 1 11 10 12 . farad . <--the loop filter capacitors c 2 356 10 12 . farad . i cp 710 6 . amp . <--the charge pump current calculate the effective series capacitance (used later): c s c 1 c 2 . c 1 c 2 c s 10.67 pf = find out the loop bandwidth and the phase angle of the transfer function: h o s () g vco i cp . n fb c 1 . 1 s 2 . s 1 rc 2 . s 1 rc s . . hs () h o s () 1h o s () x10 5 hz . f b root h o xi . () 1 x , 2 p . f b 1.504 10 6 hz = q arg h 2 p . f m . i . q 0.262 deg =
x t april 1999 4.5.99 23 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 display a bode plot of tracking pll closed loop response: w min 2 p . 1000 . hz . w max 2 p . 10 . mhz . rln w max w min bpts 50 0 j 1 bpts .. w j w min e j bpts r . . 1 10 3 1 10 4 1 10 5 1 10 6 1 10 7 10 5 0 5 input-to-output transfer function db remove dimensions to speed iterative calculations: c 1 c 1 farad c 2 c 2 farad r r ohm g vco g vco sec . volt . t step t step sec f carrier f carrier sec . i cp i cp amp c s c s farad
x t april 1999 4.5.99 24 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 the functions to calculate the voltage on c1 and c2 after some time (t), with an applied current (i), with initial voltages on the capacitors (v1 0 and v2 0 , respectively): v 1 tv1 0 , v2 0 , i , c 1 v1 0 v2 0 c 1 c 2 ir . c 2 . c 1 c 2 2 . e t rc s . . c 1 c 2 . v1 0 v2 0 ir . . c 1 c 2 i . t . c 2 2 v1 0 . c 1 2 v2 0 . c 1 c 2 2 + ... v 2 tv1 0 , v2 0 , i , c 2 v2 0 v1 0 c 1 c 2 ir . c 2 . c 1 c 2 2 . e t rc s . . c 1 c 2 . v1 0 v2 0 . c 1 c 2 i . t . c 2 2 v1 0 . c 1 2 v2 0 . ic 2 2 . r . c 1 c 2 2 + ... the function used to compute the area under the loop filter voltage curve (this will be used twice: once for the time the charg e pump is on and a second time when it is off): atv1 0 , v2 0 , i , 1 2 2c s . r . c 2 . v1 0 v2 0 c 1 c 2 . ir . c 2 . . c 1 c 2 2 . e t rc s . . 1 2 tti . c 1 c 2 . 2c 1 . c 2 . v1 0 v2 0 . 2c 2 2 . v1 0 ir . . 2c 1 2 . v2 0 . . c 1 c 2 2 . + ... rc s . c 2 . v2 0 v1 0 c 1 c 2 . ir . c 2 . c 1 c 2 2 . + .. sgn x () ifx0 < 1 , 1 , ()
x t april 1999 4.5.99 25 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 define a function to accept an array of incoming phase vs. time data and simulate the response of the pll: initialize tracking pll phase initialize c1 voltage initialize c2 voltage sample the phase error calculate the pulse width make the correct polarity of charge pump current compute the voltage on c1 and c2 at the end of the current pulse compute the voltage on c1 and c2 at the end of the sampling period compute the total volt-seconds under the loop filter voltage curve (in two parts) total phase accumulated in this step running total phase accumulated by vco trackpll f _src () f _trk 0 0 v1 0 f carrier n fb . g vco v2 0 f carrier n fb . g vco f err f _src k1 f _trk k1 t f err 2 p . f carrier . t if t t step > t step ,t , ii cp sgn f err . v1 t v 1 t v1 k1 , v2 k1 , i , v2 t v 2 t v1 k1 , v2 k1 , i , v1 k v 1 t step t v1 t , v2 t , 0 , v2 k v 2 t step t v1 t , v2 t , 0 , a1 a t v1 k1 , v2 k1 , i , a2 a t step t v1 t , v2 t , 0 , aa1a2 f incr 2 p . a . g vco n fb . f _trk k f _trk k1 f incr k 1 wavepoints 1 () .. ? for f _trk return saved data use the function above to compute the response of the pll to the pre-calculated source phase sequences: i 300 wavepoints 1 .. simdata trackpll f () skew i simdata i f i 2 p . 1 f carrier hz . . translate to time-domain
x t april 1999 4.5.99 26 )6)6 &orfn*hqhudwru,&iru,qwho3hqwlxp ? ,,%;3&6\vwhpv ,62 display the resulting skew vs. time plots: max skew ( ) 99 ps = min skew () 99 ps = 0 10 20 30 40 50 60 70 80 90 100 100 80 60 40 20 0 20 40 60 80 100 pll tracking skew skew [ps]

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