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1 www.pericom.com 02/27/15 features ? ? compliant with vesa displayport 1.2 specifcation for hbr2, hbr, rbr rate (5.4/2.7/1.62gbps) ? ? dual mode displayport outputs by providing ddc signals across the aux sink pin ? ? built-in aux interception circuit only listen to the link training, but does not afect link training ? ? sink request auto test mode through aux channels ? ? dynamic eq through aux confguration register programming for deterministic jitter reduction ? ? cable detection pins, toggle between dp and tmds mode ? ? automatic power down state when hpd signal is low ? ? low insertion loss across the aux signal path ? ? dedicated pin control mode for equalization setting control ? ? internally biased ac coupled in aux channel ? ? single power supply: 3.3v ? ? integrated esd protection ? ? package : 48-pin tqfn, 7mm x 7mm dp++ source device dp redriver connector dp mux 5-10? trace length recommended typical application description pi3eqxdp1201 provides the ability to reduce signal jitter by transmission line efects to enable longer cable length on the 5.4gbps displayport1.2 signals. integrated aux decoder can support displayport link training. it can decipher the link training message and auto - matically confgure displayport diferential signal outputs with the best pre-emphasis and output swing level settings. input equalization, output level swing and pre-emphasis are controlled by either aux link snooping or pin confgu - ration. decoding of the aux command happens during link training. built-in sync request auto test mode enables users to com - plete displayport link status through aux channels in min - utes. pi3eqxdp1201 is intended for use in any systems, dp sig - nal compliance is required, including notebook pc and docking stations, graphic cards and digital video systems. applications ? ? notebook and dock station ? ? pc system boards ? ? digital video systems company confidential hpd_src enable cntrl cad_src aux_src scl/sda aux_snk cad_snk hpd_snk out0p/n out1p/n out2p/n out3p/n in0p/n in1p/n in2p/n in3p/n equalizer pre-emphasis control logic & con?guraton registers aux listener, aux pass-through, ddc pass-through blocks functional block diagram pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode 15-0021
2 www.pericom.com 02/27/15 package pinout v3p3 dnc oc_1 op_0 op_1 v3p3 cntrl cad_src hpd_src cad_snk hpd_snk v3p3 24 1 2 3 4 5 6 7 8 9 10 11 12 23 22 21 20 19 18 17 16 15 14 13 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 gnd out0p out0n dnc out1p out1n gnd out2p out2n dnc out3p out3n v3p3 auto_eq sda_ddc scl_ddc v3p3 gnd aux_srcp aux_srcn aux_snkp aux_snkn enable v3p3 dnc in0p in0n eq in1p in1n dnc in2p in2n oc_0 in3p in3n gnd pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
3 www.pericom.com 02/27/15 continued > pin description pin # pin name pin ty pe description 1 v3p3 power 3.3v +/10% power rail 2 dnc nc do not connect; leave pin foating 3 oc_1 input swing control bit 1. pulled-up internally with 100kohm see truth tables for functionality 4 op_0 input pre-emphasis control bit 1. internally pulled-up with 100kohm see truth tables for functionality 5 op_1 input pre-emphasis control bit 0. internally pulled-up with 100kohm see truth tables for functionality 6 v3p3 power 3.3v +/-10% power rail 7 cntrl input confgure output voltage swing and pre-emphasis (see truth table for functionality) 8 cad_src output cable adapter detection from dp connector cad_src = "0" : no cable adapter; enable dp redriver mode with aux listening and link training active cad_src = "1" & installed cable adapter; enable tmds redriver mode and disable aux interception 9 hpd_src output hot plug detect to system dp source. 3.3v cmos output. 10 cad_snk input cable detect from sink side. 11 hpd_snk input hot plug detect from the sink side 200kohm pull-down 12 v3p3 power 3.3v +/- 10% power rail 13 out3n output lane 3 data negative output 14 out3p output lane 3 data positive output 15 dnc nc do not connect 16 out2n output lane 2 data negative output 17 out2p output lane 2 data positive output 18 gnd power ground 19 out1n output lane 1 data negative output 20 out1p output lane 1 data positive output 21 dnc nc do not connect 22 out0n output lane 0 data negative output 23 out0p output lane 0 data positive output 24 gnd power ground 25 v3p3 power 3.3v +/10% power rail 26 enable input external power down pin "1"=enable ; "0"=disable ; pulled-up internally with 100kohm 27 aux_snkn i/o aux negative channel connected to dp sink device 28 aux_snkp i/o aux positive channel connected to dp sink device pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
4 www.pericom.com 02/27/15 pin # pin name pin ty pe description 29 aux_srcn i/o aux negative channel connected to dp source device 30 aux_srcp i/o aux positive channel connected to dp source device 31 gnd power ground 32 v3p3 power 3.3v +/10% power rail 33 scl_ddc i/o ddc clock channel from source side when cad_snk=1 34 sda_ddc i/o ddc data channel from source side when cad_snk=1 35 auto_eq input auto eq control pin. enable = 1, disable = 0. tis pin is internally pulled up through 100kohm. eq-pin (pin 40) can control auto eq mode 0, 1 and 2. 36 v3p3 power 3.3v +/10% power rail 37 dnc nc do not connect 38 in0p input lane 0 data positive input 39 in0n input lane 0 data negative input 40 eq input be able to confgure fixed eq setting, when disable auto-eq mode (auto_eq pin =0). tis pin is internally biased to 50% of v3p3. 41 in1p input lane 1 data positive input 42 in1n input lane 1 data negative input 43 dnc nc do not connect 44 in2p input lane 2 data positive input 45 in2n input lane 2 data negative input 46 oc_0 input output control pin. see output control truth table for functionality internally pulled-high with 100kohm 47 in3p input lane 3 data positive input 48 in3n input lane 3 data negative input pin description pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
mode control pins output swing pre-emphasis eq setting cntrl cad sink oc_1, oc_0 op_1, op_0 normal mode 0 1 x x x x 80 0mv 0db follow auto eq & fixed eq table 0 0 x, x x,x follow listener follow listener follow auto eq & fixed eq table test mode 1 x 0 0 1 1 40 0mv 0db` pin control 1 x 0 0 0 0 40 0mv 3.5db pin control 1 x 0 0 0 1 40 0mv 6db pin control 1 x 0 0 1 0 40 0mv 9.5db pin control 1 x 0 1 1 1 60 0mv 0db pin control 1 x 0 1 0 0 60 0mv 3.5db pin control 1 x 0 1 0 1 / 1 0 60 0mv 6db pin control 1 x 1 1 1 1 80 0mv 0db pin control 1 x 1 1 0 x / 1 0 80 0mv 3.5db pin control 1 x 1 0 xx 120 0mv 0db pin control normal mode normal mode auto eq mode 0 auto eq mode 1 auto eq mode 2 fixed eq. 2.5db @ 2.7ghz fixed eq. 5.1db @ 2.7ghz fixed eq. 7.2db @ 2.7ghz notes eq l m h l m h eq pin is internally biased to ~50% of v3p3 at "m(middle)" or foating statue. measured gains 1.62g 2.7g 5.4g unit l -1.42 -2.01 -2.79 db m 2.41 3.9 5.16 db h 6.96 9.28 10.8 db auto eq h h h l l l auto eq pin has a internal pull-up. eq setting in auto eq mode pre-emphasis_set bit[4:3] in dpcd registers auto eq mode 0 auto eq mode 1 auto eq mode 2 unit 1.62g 2.7g 5.4g 1.62g 2.7g 5.4g 1.62g 2.7g 5.4g 0 0 2.26 2.74 2.49 3.97 5.92 7.3 3.97 7.27 8.69 db 0 1 0.34 0.57 0.22 1.44 2.5 3.41 3.21 5.1 6.42 db 1 0 -1.42 -2.01 -2.79 0.34 0.57 0.22 1.44 2.5 3.41 db 1 1 -2.39 -3.62 -4.71 -1.42 -2.01 -2.79 0.34 0.57 0.22 db control pin functional tables 5 www.pericom.com 02/27/15 pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
6 www.pericom.com 02/27/15 functional description intelligent power management pericoms block based design and intelligent detection scheme allow portions, or all of the ic, to be disabled for power sav - ings. for example, in dp mode, if only one or two lanes are active, the other lanes will be automatically powered of. if there is no input video signal the entire ic will be powered down. if there is no monitor detected, pericoms pi3eqxdp1201 can also automatically power down the ic. tis intelligent power management concept not only saves system power, but also stops the device from outputting useless data or noise when no signal is present at the input of the ic. te power-down mode can also be entered using hard pin en - able, or through dpcd register (aux link training) displayport aux listener pi3eqxdp1201 integrates an aux listener(decoder), which enables the device to receive and deci - pher all aux link training data and use this ex - tracted information for its own confguration. te intercepted dpcd data is used to adjust the active lane count, output swing level, output pre-emphasis level, and to manage the devices d3 power saving state. aux listener specifcation dp aux listener will support native aux ch syntax. mapping of i 2 c onto aux ch syntax is not supported. aux listener monitors aux channel from requester and replier for transactions and stored aux command from requester and reply command from sinks that are related to the link settings. aux listener recovered the clock from aux data input by cycle counting the synchronization pulse at the beginning of the aux cycle. in a aux write request cycle, the aux address compare the addresses with the following registers address, data is extracted and stored into the respective registers when the addresses matches. tese registers are set during link training se - quence following hot plug detection. 00100h data rate register 00101h lane_count_set 00103h training_lane0_set 00104h training_lane1_set 00105h training_lane2_set 00106h training_lane3_set 00260h sink test request response 00600h power down te aux listener support sink request test sequence. afer hpd irq event and dp source read 00201h aux register and if bit 1 is high, the dp source will enter a sink request test mode and initiate a sequence of aux read request cycle. during the read cycle, data matching the fol - lowing registers address are stored in the listener. 00206h adjust_request_lane0_1 00207h adjust_request_lane2_3 00218h test request 00219h test link rate 00220h test lane count afer the read request cycle, the dp source will write 1 to bit 0 register 00260h if the dp source enters sink request mode, or 1 to bit 1 of register 00260h if the source declined the sink test request. te data stored in registers 002xx above will override the value set in 00101h to 00106h reg - isters when the sink entered the sink test mode. sink test request acknowledgement 00260h mode bufer confguration outputs xxxxxx00b no action 00100 : 00106h xxxxxx01b sink test mode 00206h,00207h,00219h,00220h override 00100,1,3,4,5,6h register settings xxxxxx10b sink test mode declined 00100h : 00106h xxxxxx11b not legal code 00100h : 00106h pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
7 www.pericom.com 02/27/15 a complete two way aux transaction is defned as one of the following 1. aux write and sink issue ack reply from source sync start/start pattern 4-bit cmd 1000 20-bit address 8-bit length data stop from sink ack sync start bit 00000000 stop 2. aux write and sink issue nack reply for write transaction: a data byte m must follow aux nack, m indi - cates the number of data bytes successfully written. when a source device is writing a dpcd address not supported by the sink device, the sink device shall reply with aux nack and m equal to zero. from source sync start bit 4-bit cmd 1000 20-bit adr 8-bit length data stop from sink nack sync start bit 00010000 8-bit data byte m stop 3. aux read and sink issue ack reply for read transaction: ready to reply to read request with data following. displayport receiver may assert a stop condition before transmitting the total number of requested data bytes when not all the bytes are available. from source sync start bit 4-bit cmd 1001 20-bit ad - dress 8-bit length stop from sink ack sync start bit 00000000 data stop 4. aux read and sink issue nack reply for read transaction: a sink device receiving a native aux ch read request for an unsupported dpcd address must reply with an aux ack and read data set equal to zero instead of replying with aux nack. from source sync start bit 4-bit cmd 1001 20-bit address 8-bit length stop from sink nack sync start bit 00001000 data = 0 stop typical aux test request handshake se - quences with hpd_irq aux listener stores the last transaction in the register to identify the current transaction type. s in k s id e s o u r c e s id e a u x r e p l y 0 0 2 1 8h a u x a c k 0 0 2 1 8 h to 0027fh a u x r e a d 0 0 2 1 8 h to 0027fh a u x w r i te 0 0 2 6 0h a u x w r i te 0 0 2 6 0h e n a b le t e s t r e g is te r s i f b it0 = 1 , d o n o th in g i f b it1 = 1 . a u x r e p l y 0 0 2 0 1h a u x a c k 0 0 2 0 1 h . . a u x a c k 0 0 2 0 1h pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
8 www.pericom.com 02/27/15 start up sequence and hot plug detect (hpd) usage afer power on, hpd_snk control state machine goes to low power state 1 and then state 2, and then monitor hpd_ snk. at power on reset state, low power state 1 and low power state 2, all outputs are hiz, equalizer is powered down, hpd _src is hiz. at lower power mode state 2, if hpd_snk is asserted, it will turn output signals active. if output port is active and hpd_snk = 0, then it will go to a debounce timer and wait for 300ms, if hpd_snk is still =0, the controller will return to low power mode wait state 2. if hpd_snk is 1 then the controller will return to output port active state. hpd_snk will pass through hpd _src. low power mode 2 hpda=1 port a active port a wait hpd a=0 power on reset low power mode 1 hpda=1 hpda=0 wait 2ms hpd detection & control circuit state diagram pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
9 www.pericom.com 02/27/15 dc electrical characteristics symbol parameters condition min. ty p. max. units v3p3 3.3v power supply 3.0 3.3 3.6 v control pin enable v ih lvttl input high voltage 2.4 v3p3 v v il lvttl input low voltage gnd 0.8 v i ih input high-level current v ih =2v to v3p3 -5 5 ua i il input low-level current v il =gnd to 0.8v -50 -15 ua hpd_src and hpd_snk pins v ih lvttl input high voltage 2.4 v3p3 v v il lvttl input low voltage 1/3*v3p3 2/3*v3p3 v i ih input high-level current gnd ? 0.6 ua i il input low-level current ?20 40 ua v oh lvttl high level output voltage i oh =-8ma 2.4 v v ol lvttl low level output voltage i ol = 8ma 0.4 v auxp/n, scl/sda when confgure scl/sda pins i ih input high-level current ?vih=v3p3 -1 ? 1 ua i il input low-level current ?vil=0 -1 ? 1 ua when confgure as aux pins vcom common mode voltage ? 0 ? 2.0 v v aux-pp peak to peak diferential voltage 0.19 ? 1.26 v r on on resistance vin = -0.3v to +0.4v ion=-40ma ? 11 20 bw 3db bandwidth 1 db storage temperature.......................................................... C65c to +150c v3p3 i/o supply voltage to ground potential ...................... -0.5v to 4.0v dc signal voltage ....................................................... -0.5v to v3p3 +0.5v current output .................................................................. -25ma to+25ma power dissipation continous .......................................................... 500mw operating temperature ........................................................... -40 to +85c esd protection 2 all pins, hbm ................................................................................. 2kv note: 1) stresses greater than those listed under maximum rat - ings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. 2) esd results are for single supply mode only maximum ratings (1) (above which useful life may be impaired. for user guidelines, not tested.) pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
10 www.pericom.com 02/27/15 symbol parameters condition min. ty p. max. units dp diferential input v id peak to peak diferential input voltage 400 ? 1200 mv v odo diferential overshoot voltage ? ? 15%*v3p3 v3p3 v odu diferential undershoot voltage ? ? 25%*v3p3 v3p3 iof single end standby current ? ? 10 ua isc output short current ? ? 60 ma dp diferential output vtx dif-lev1 diferential pk-pk level 1 340 400 460 mv vtx dif-lev2 diferential pk-pk level 2 510 600 680 mv vtx dif-lev3 diferential pk-pk level 3 690 800 920 mv vtx dif-lev4 diferential pk-pk level 4 1020 1200 1380 mv pre-emphasis level 0db vtx dif = 0.8v 0 0 0 db 3.5db (1.5x) vtx dif = 0.8v 2.8 3.5 4.2 db 6db (2x) vtx dif = 0.8v 4.8 6 7.2 db 9.5db (3x) vtx dif = 0.8v 7.6 9.5 11.4 db dp diferential output cml driver ac switching characteristics trise / tfall rise and fall time 20% to 80 % 80 115 150 ps tsk(d) intrapair diferential skew 50 ps tsk(o) intrapair diferential skew 50 ps power consumption symbol condition min ty p max units icc _v3p3 enable = high, hpd_snk = high 4 dp lanes active, pre-emphasis = 0db, output swing = 400mv 5.4gbps 340 ma 2.7gbps 310 1.62gbps 300 icc _v3p3_ sb enable = low 1.4 5 ma iccq_v3p3 enable = high, hpd_snk = low 4 20 ma powerdown_v3p3 aux reg 600h = 02h, enable= high, hpd_snk = high, cntrl = low 5 ma dc electrical characteristics pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
swing=400mv, preemph=0db swing=600mv, preemph=0db swing=800mv, preemph=0db swing=1200mv, preemph=0db swing=400mv, preemph=3.5db swing=600mv, preemph=3.5db swing=800mv, preemph=3.5db swing=400mv, preemphasis=6db swing=600mv, preemph=6db swing=400mv, preemphasis=9.5db measured output waveforms as following is shown the actual measured output waveforms on the condition of 5.4gbps with prbs27-1 pattern. auto eq=high; cad_snk=0; hpd=high; oc_1=high; oc_0=op_0=low; op_1=low; input level is 0.6v diferential peak- peak with 12-in fr4 length and 36-in output coaxial cable 11 www.pericom.com 02/27/15 pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
12 www.pericom.com 02/27/15 packaging mechanical: 48-contact tqfn (zbe) 1 notes: 2012 date: 03/25/10 description: 48-pin, thin fine pitch quad flat no-lead (tqfn) package code: zb48 document control #: pd-2080-t revision: a ordering information ordering code package code pack age ty pe PI3EQXDP1201ZBE zb pb-free & green, 48-pin tqfn 1. termal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e = pb-free and green 3. adding an x sufx = tape/reel note: for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
13 www.pericom.com 02/27/15 related products part number product description pi3hdx1204-b hdmi2.0 6gbps redriver & level shifer pi3dpx1203 dp1.3 8gbps redriver pi3hdx511d/e/f 3.4g hdmi1.4 redriver for source application, supporting dual mode displayport pi3hdx412bd 1:2 active 3.4gbps hdmi1.4 compliant splitter/demux/redriver pi3hdx414 1:4 active 3.4gbps hdmi1.4 compliant splitter/demux/redriver pi3hdx621 2:1 3.4gbps hdmi1.4 switch/re-driver with arc and fast switching support for sink ap - plication pi3pcie3242 pcie 3.0, 1-lane (2-channel), diferential 2-lane exchange (2x2 matrix) switch. 3.3v for type-c connector pi3wvr12412 wide voltage range displayport? & hdmi video switch pi3vdp12412 4-lane displayport1.2 compliant switch reference information document description an pi3eqxdp1201 design guideline for displayport source application note pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
14 www.pericom.com 02/27/15 appendix: 1. displayport compliance test report notebook application example notebook docking application example pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
15 www.pericom.com 02/27/15 2. reference schematics dual-mode dp source application diagram with combined aux and ddc channels from source dual-mode dp source application diagram with separate aux and ddc channels from source pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021
revision history version changes 2015/2/4 removed 3.3/1.5v power supply and smbus option for new design. please contact pericom if you need this func - tion support. 16 www.pericom.com 02/27/15 pi3eqxdp1201 3.3v, 4-ch displayport 1.2 redriver with aux listener/autotest mode company confidential 15-0021

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