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for communications equipment overview the MN86072 enhances image quality by applying various imaging processing techniques to the analog signal from an image sensor. it reproduces halftone images with 64-gradation using two-dimensional mtf correction and a user-programmable gamma curve. features image processing that yields top image quality ? white and black shading correction using overall pixel correction ? error dispersion processing that reproduces halftone images with 64-gradation user-programmable gamma curve ? multivalue smoothing for diagonal lines to eliminate unsightly "jaggies," artifacts resulting from enlargement or line density conversion ? enlargement/reduction (line density conversion) with a user-specified scaling factor without introducing moire patterns high-speed processing of only 1 ms per line for an a3 page at 400 dpi with an image processing frequency of 6 mhz built-in analog processing circuits: offset correction circuit, gain correction circuit, and analog-to-digital converter MN86072 image processing lsi drive signal generator for ccds, ciss, and other memory interfaces that cover a wide variety of applications ? standard g3 operation (l mode) (200 dpi, 3 ms/line) b4 readout: 64-kbit sram 1 a3 readout: 256-kbit pseudo-sram 1 ? high-speed g3 operation (m mode) (200 dpi, 1 ms/line) b4 and a3 readout: 64-kbit sram 2 ? high-resolution g3 operation (m mode) (400 dpi, 2 ms/line) b4 readout: 64-kbit sram 2 a3 readout: 256-kbit sram 2 +sram (16-kbit) 2 or 256-kbit sram 2 ? ultra-high-speed g4 (h mode) (400 dpi, 1 ms/line) b4 and a3 readout: 64-kbit sram 4 + 5k 8-bit fifo 1 applications facsimile equipment maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86072 for communications equipment brief specifications image processing speed: ? 0.1 to 6 million pixels per second pixels per line: ? max. 16,384 pixels in the primary scanning direction offset correction: ? negative feedback preamplifier the chip controls the feedback voltage using a/d conversion data from black pixel sections built-in circuits: feedback voltage control circuit + source follower circuit 2 (support for channel-separated ccds included) gain control: ? analog control using an external operational amplifier and the built-in field effect transistor (fet) an external resistor determines the control range. (the standard range is from +6 db to C12 db.) built-in circuits: gain control circuit + fet 2 (support for channel-separated ccds included) a/d converter: ? half flash converter number of bits: 8 conversion speed: 0.1 to 6 mhz input range: min. 3 v p-p input channels: support for odd/even separation white shading correction: ? overall pixel correction distortion correction level: max. 75% (or max. 50%) of a/d converter's input range black shading correction: ? overall pixel correction distortion correction level: 25% of a/d converter's input range mtf correction: ? laplacian transforms (processing for text images) reference to five pixels, max. coefficient of C1.875 support for edge direction-specific processing and processing from preceding history halftone processing: ? error dispersion processing: reproduction of 64-gradation using 6-bit proces sing ? dither pattern: mesh (4 4 or 8 8 pixels) bayer (4 4 pixels) gamma correction: ? user-definable by loading a conversion curve conversion levels: 7 bits to 6 binary coded: ? fixed slice slice level: user-specified 5-bit value enlargement/reduction (line density conversion): ? decimation with image clock or line enable scaling factor in primary scanning direction: 0.78% to 200% (in 0.78% increments) scaling factor in subscanning direction: 0.39% to 200% (in 0.39% increments) enlargement/reduction (line density conversion) correction: ? multivalue smoothing (for enlargement in primary direction or line density enchancement) ? black pixel preservation (for reduction in primary or subscanning direction or line density reduction) ? or processing (for line density conversion in subscanning direction from 7.7 line/mm to 3.85) sensor interfaces: ? ccd sensor supports both channel-composite and channel-separated ccds. generates the following drive signals using user settings: fsg (sh), fck1, fck2 (?1 and ?2), fr1, fr2 (rs1 and rs2) ? contacting bipolar image sensor generates sclk and st signals. maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
for communications equipment MN86072 ? cds sensor generates sclk and stpl signals. memory interfaces: ? l mode (max. 1 mhz) : 256-kbit pseudo-sram 1 or 256-kbit sram 1 or, if enlargement and black shading are disabled and the lines are not more than 2048 pixels long, 64-kbit sram 1 ? m mode(max.3mhz) : 64-kbit sram 2 or, if there is enlargement or black shading 64-kbit sram 3 ? h mode (max. 6 mhz) : 64-kbit sram 4 + 5k 8-bit fifo 1 ? shading memory function (common in l, m, and h modes)" : support for fixed rom shading : support for automatic data transfers between shading memory and eerom : shading memory accessible from microprocessor for read/ write operations image bus interface: ? parallel mode (dma slave operation) : 8-bit mode : 16-bit mode (requires external circuitry) ? serial mode with request (vreq) input and enable (vsen), clock (vsck), and data (vsda) outputs scanning modes: ? free scan ? cycle scan (normal drive) ? cycle scan (trapezoidal drive) ? trigger scan system interface: ? interface to 8-bit microprocessors (choice of intel or motorola formats) video data register readout function: ? image data after a/d conversion or shading correction : maximum value for abc interval : minimum value for offset correction interval : data at user's choice of position image data i/o function: ? image data output after shading correction (8 bits) ? image data output after multivalue smoothing (7 bits) ? image data input sent from external a/d converter (8 bits) output ports: ? 16 pins (memory interface for l mode) ? 3 pins (memory interface for m mode) power supply: ? digital circuits dv dd : 5.0v ? analog circuits av dd : 5.0v ? a/d converter reference voltages v refh : 5.0 to 3.0 v v refl : 0.0 to 2.0 v maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86072 for communications equipment pin assignment qfh128-p-1818 (top view) hswr hfwe hrstr hrstw hrck hmwe hcwr hbwr hwck hmid7 hmid6 hmid5 hmid4 hmid3 hmid2 hmid1 hmid0 hmcd6 hmcd5 hmcd4 hmcd3 hmcd2 hmcd1 hmcd0 hmad6 hmad5 hmad4 hmad3 hmad2 hmad1 hmad0 dv dd mma8 mmoe mmlwe mmfwe mmewe mma12 mma11 mma10 msa1 msid7 msid6 msid5 msid4 msid3 msid2 msid1 msid0 mmld6 mmld5 mmld4 mmld3 mmld2 mmld1 mmld0 mmfd6 mmfd5 mmfd4 mmfd3 mmfd2 mmfd1 mmfd0 lma8 lroe lmoe lmwe lmce lma12 lma11 lma10 lma14 lsid7 lsid6 lsid5 lsid4 lsid3 lsid2 lsid1 lsid0 lra12 lra11 lra10 lbp7 lbp6 lbp5 lap6 lap5 lap4 lap3 lap2 lap1 lap0 dv dd cs rd wr reset vpd0 vpd1 vpd2 vpd3 vpd4 vpd5 vpd6 vpd7 vsda vsck dreq dack vreq abc clamp peak1 peak2 vinig1 agdr1 agur1 agout1 fetg1 fets1 fetd1 vrefl vrefh av ss hmkd0 hmkd1 hmkd2 hmkd3 hmkd4 hrstk hmkw hrocs vsda vsck vsen vreq 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 hawr hmod0 hmod1 hmod2 hmod3 hmod4 hmod5 hmod6 hmod7 mast mcm0 mcm1 fsg fck1 fck2 fr1 fr2 sentim sync mclki d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 c80_68 dv ss dv ss hrsta mack hmbd6 hmbd5 hmbd4 hmbd3 hmbd2 hmbd1 hmbd0 hmsd7 hmsd6 hmsd5 hmsd4 hmsd3 hmsd2 hmsd1 hmsd0 ofout1 ofhc1 ofout2 ofhc2 vinig2 agdr2 agur2 agout2 fetg2 fets2 fetd2 av dd adin2 adin1 msa0 mrwe mroe ma13 mbp2 mbp1 mbp0 mmfd7 mmed7 mmed6 mmed5 mmed4 mmed3 mmed2 mmed1 mmed0 lma13 lrwe lbp4 lbp3 lbp2 lbp1 lbp0 lap7 lmxd7 lmxd6 lmxd5 lmxd4 lmxd3 lmxd2 lmxd1 lmxd0 mma9 mma0 mma1 mma2 mma3 mma4 mma5 mma6 mma7 stpl sclk sclk mclko lma9 lma0 lma1 lma2 lma3 lma4 lma5 lma6 lma7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
for communications equipment MN86072 pin function chart hswr hawr hbwr hcwr hmwe hrsta hwck hrck hrstw hrstr hfwe mack 128pin qfh vreq dack dreq vsck vsda vreq dack vsen vsck vsda hmkd0 hmkd1 hmkd2 hmkd3 hmkd4 hrstk hmkw hrocs vpd0 vpd1 vpd2 vpd3 vpd4 vpd5 vpd6 vpd7 vscd0 vscd1 vscd2 vscd3 vscd4 vscd5 vscd6 vscd7 vgsd0 vgsd1 vgsd2 vgsd3 vgsd4 vgsd5 vgsd6 ckvg vadd0 vadd1 vadd2 vadd3 vadd4 vadd5 vadd6 vadd7 hmsd0 hmsd1 hmsd2 hmsd3 hmsd4 hmsd5 hmsd6 hmsd7 mmed0 mmed1 mmed2 mmed3 mmed4 mmed5 mmed6 mmed7 lmxd0 lmxd1 lmxd2 lmxd3 lmxd4 lmxd5 lmxd6 lmxd7 hmad0 hmad1 hmad2 hmad3 hmad4 hmad5 hmad6 mmfd0 mmfd1 mmfd2 mmfd3 mmfd4 mmfd5 mmfd6 lap0 lap1 lap2 lap3 lap4 lap5 lap6 hmbd0 hmbd1 hmbd2 hmbd3 hmbd4 hmbd5 hmbd6 mmfd7 mbp0 mbp1 mbp2 ma13 mroe mrwe lap7 lbp0 lbp1 lbp2 lbp3 lbp4 lrwe hmcd0 hmcd1 hmcd2 hmcd3 hmcd4 hmcd5 hmcd6 mmld0 mmld1 mmld2 mmld3 mmld4 mmld5 mmld6 lbp5 lbp6 lbp7 lra10 lra11 lra12 hmid0 hmid1 hmid2 hmid3 hmid4 hmid5 hmid6 hmid7 msid0 msid1 msid2 msid3 msid4 msid5 msid6 msid7 lsid0 lsid1 lsid2 lsid3 lsid4 lsid5 lsid6 lsid7 hmod0 hmod1 hmod2 hmod3 hmod4 hmod5 hmod6 hmod7 mma0 mma1 mma2 mma3 mma4 mma5 mma6 mma7 lma0 lma1 lma2 lma3 lma4 lma5 lma6 lma7 mma8 mma9 mma10 mma11 mma12 msa0 msa1 mmewe mmfwe mmlwe mmoe lma8 lma9 lma10 lma11 lma12 lma13 lma14 lmce lmwe lmoe lroe mast mcm0 mcm1 d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 cs wr(ds) rd(r/w) c80_68 mclki sync mclko fck2 fck1 fr1 fr2 fsg sentim sclk sclk stpl peak1 peak2 clamp abc ofout1 ofhc1 adin1 fets1 fetd1 fetg1 agout1 agur1 agdr1 vinig1 vinig2 agdr2 agur2 agout2 fetg2 fetd2 fets2 adin2 ofhc2 ofout2 vrefh vrefl av dd av ss dv dd dv dd dv ss dv ss MN86072 mode selection (3) system interface (15) clock (2) sensor interface (6) analog cnt (4) analog pins (20) power supply (8) image bus interface (5) parallel i/o (8) memory interface (5) reset maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86072 for communications equipment 87 mast o clock synchronization selection h: master mode. the chip synchronizes operation with its internal sync signal and feeds this signal to the sync pin. l: slave mode. the chip synchronizes operation with the external sync signal from the sync pin. 86 mcm0 i memory interface mode selection these inputs select the mode for the memory interface pins, which determine the multiplier applied to master clock frequency (from the 85 mcm1 i mclki pin). mast mcm1 mcm0 memory interface mode clock mode l l l l mode slave f ckvd 16 l l h m mode slave f ckvd 8 l h l h mode slave f ckvd 2 l h h t mode slave f ckvd 2 h l l l mode master f ckvd 16 h l h m mode master f ckvd 8 h h l h mode master f ckvd 2 h h h dctest 1. mode selection pins pin no. symbol i/o function description pin descriptions l mode (low-speed mode) 256-kbit pseudo-sram 1 or 256-kbit sram 1 recommended image signal frequency (f ckvd ): max. 1 mhz master clock frequency (f mclki ): f ckvd 16 m mode (medium-speed mode) 64-kbit sram 3 if enlargement and black shading are disabled 64-kbit sram 2 recommended image signal frequency (f ckvd ): max. 3 mhz master clock frequency (f mclki ): f ckvd 8 h mode (high-speed mode) 64-kbit sram 4 + 5k 8-bit fifo 1 recommended image signal frequency (f ckvd ): max. 6 mhz master clock frequency (f mclki ): f ckvd 2 maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
for communications equipment MN86072 t mode (test data input mode) this mode is for testing internal functions. master clock frequency (f mclki ): f ckvd 2 dctest mode this mode configures the output and i/o pins for dc testing. hmid0 hmid1 dc test function 0 output high-impedance test 1 0 "l" level output test 1 1 "h" level output test 1. mode selection pins (continued) pin no. symbol i/o function description pin descriptions (continued) 76 to 69 d0 to d7 i/o microprocessor data i/o bus 68, 67 a0, a1 i microprocessor address input 63 cs i microprocessor chip select input 61 wr(ds) i microprocessor data write input (set c80_68 pin at "h" level) microprocessor data strobe input (set c80_68 pin at "l" level) 62 rd(r/w) i microprocessor data read input (set c80_68 pin at "h" level) microprocessor data read/write input (set c80_68 pin at "l" level) 66 c80 68 i microprocessor selection input l: motorola h: intel 60 reset i system reset input 2. system interface pins pin no. symbol i/o function description maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86072 for communications equipment internal master clock output. mclko o this pin provides the internal master clock, the signal from the mclki pin. mast sysl remarks (tim2 reg) h 0 mclk output 77 mclki i master clock input clock frequency: image signal frequency 2 (h mode memory interface) image signal frequency 8 (m mode memory interface) image signal frequency 16 (l mode memory interface) clock duty: 50% clock synchronization signal i/o sync i/o start timing pulse for individual lines mast sysl remarks (tim2 reg) l sync input h 1 sync output 3. clock pins pin no. symbol i/o function description pin descriptions (continued) 78 mclki sync(0) sync(1) maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
for communications equipment MN86072 fck1 o ccd: 1 (tim 1 reg) reduced ccd sensor. ?1 clock: ckvd/2. 83 sclk o ccd: 0 (tim 1 reg) cds or bipolar image sensor. sclk clock: ckvd fck2 o ccd: 1 (tim 1 reg) 82 reduced ccd sensor. ?2 clock: ckvd/2. sclk o ccd: 0 (tim 1 reg) cds or bipolar image sensor. sclk clock: ckvd fsg o ccd: 1, conta: (tim 1 reg) reduced ccd sensor. ?sg 84 st o ccd: 0, conta: 0 (tim 1 reg) bipolar image sensor. st = start puls stpl o ccd: 0, conta: 0 (tim 1 reg) cds sensor. stpl = start pulse 81 fr1 o frm2: 0 reduced ccd sensor. ?r1 clock (parallel mode) frm2: 1 reduced ccd sensor. ?r clock (serial mode) 80 fr2 o frm2: 0 reduced ccd sensor. ?r2 clock (parallel mode) frm2: 1 reduced ccd sensor. ?sp clock (serial mode) 79 sentim o sensor timing output pin stm1 stm0 setim output signal (tim2 reg) (tim2 reg) 0 0 offset enable 0 1 abc enable 1 0 user-defined timing (for all lines read) 1 1 user-defined timing (for valid lines only) 4. sensor interface pins pin no. symbol i/o function description pin descriptions (continued) maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86072 for communications equipment 44 peak1 o gain control signal 1 (overflow 1) "l" level: reduce gain. "h" level: increase gain. 43 peak2 o gain control signal 2 (overflow 2) "l" level: reduce gain. "h" level: increase gain. 45 clamp o clamp (offset correction) interval signal. "l" level: hold. "h" level: sample (offset adjustment operation). 46 abc o abc effective interval signal. "l" level: hold gain. "h" level: adjust gain. 5. sensor drive pins pin no. symbol i/o function description pin descriptions (continued) maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
for communications equipment MN86072 47 vreq i video request. this pin accepts image data transfer requests from the controlled device. "l" level: transfer request enable. "h" level: transfer request disable. in the trigger scan mode, pulling this pin to "l" level forces the sensor start (stpl) pin to "l" level to start sensor readout. after image-processing a line of data, the image data are outputted at the vsda pin. in the cycle scan mode, pulling this pin to "l" level enables the next readout line. after image-processing a line of data, the image data are outputted at the vsda pin. in the free scan mode, the chip ignores this pin, sensor readout starts at the interval specified with the timing settings, and the image data are outputted at the vsda pin after processing each line of data. parallel mode (ipara (ibcnt regi): 1) dreq o parallel data transfer request. "l" level: transfer request enable. 49 "h" level: transfer request disable. serial mode (ipara (ibcnt regi): 0) vsen o video enable "l" level: image data enable. "h" level: image data disable. 48 dack i parallel data acknowledge. data transfer acknowledge signal in response to dreq. "l" level: data transfer enable. "h" level: data transfer disable. 6. image bus interface pins pin no. symbol i/o function description pin descriptions (continued) maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86072 for communications equipment 50 vsck o parallel mode (ipara (ibcnt regi): 1) video serial clock (signal for external circuitry). timing for reading vsda data. vsck o serial mode (ipara (ibcnt regi): 0) video serial clock. timing for reading vsda data. 51 vsda o parallel mode (ipara (ibcnt regi): 1) video serial data. (signal for external circuitry). binary image data output. "l" level: black. "h" level: white. vsda o serial mode (ipara (ibcnt regi): 0) video serial data. binary image data output. "l" level: black. "h" level: white. 6. image bus interface pins (continued) pin no. symbol i/o function description pin descriptions (continued) maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
for communications equipment MN86072 7. parallel i/o pins pin no. symbol i/o function description pin descriptions (continued) 52 vadd7 i psd2: 0, psd1: 0, psd0: (ibcnt regi) external a/d converter signal input hrocs o psd2: 0, psd1: 1, psd0: (ibcnt regi) shading rom chip select vpd7 o/hi-z psd2: 1, psd1: 0, psd0: 0 (ibcnt regi) binary parallel image output (parallel interface) dack: l output. dack: h high-impedance. vscd7 o psd2: 1, psd1: 0, psd0: 1 (ibcnt regi) output pin for image signal after shading correction ckvg o psd2: 1, psd1: 1, psd0: 0 (ibcnt regi) multivalue image signal synchronization clock output sbus7 o psd2: 1, psd1: 1, psd0: 1 (ibcnt regi) internal dbus data output 53 vadd6 i psd2: 0, psd1: 0, pdsd0: (ibcnt regi) external a/d converter input hkwr o psd2: 0, psd1: 1, psd0: (ibcnt regi) hmkd write/read output vpd6 o/hi-z psd2: 1, psd1: 0, psd0: 0 (ibcnt regi) binary parallel image output (parallel interface) dack: l output. dack: h high-impedance. vscd6 o psd2: 1, psd1: 0, psd0: 1 (ibcnt regi) output pin for image signal after shading correction vgsd6 o psd2: 1, psd1: 1, psd0: 0 (ibcnt regi) multivalue image signal output sbus6 o psd2: 1, psd1: 1, psd0: 1(ibcnt regi) internal dbus data output 54 vadd5 i psd2: 0, psd1: 0, psd0: (ibcnt regi) external a/d converter input hrstk o psd2: 0, psd1: 1, psd0: (ibcnt regi) external address control clear for black shading vpd5 o/hi-z psd2: 1, psd1: 0, psd0: 0 (ibcnt regi) binary parallel image output (parallel interface) dack: l output. dack: h high-impedance. vscd5 o psd2: 1, psd1: 0, psd0: 1 (ibcnt regi) output pin for image signal after shading correction maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86072 for communications equipment 7. parallel i/o pins (continued) pin no. symbol i/o function dscription pin descriptions (continued) 54 vgsd5 o psd2: 1, psd1: 1, psd0: 0 (ibcnt regi) multivalue image signal output sbus5 o psd2: 1, psd1: 1, psd0: 1 (ibcnt regi) internal dbus data output 55 to 59 vadd4 i psd2: 0, psd1: 0, psd0: (ibcnt regi) vadd0 external a/d converter output hmkd4 i/o psd2: 0, psd1: 1, psd0: (ibcnt regi) to hmkd0 black shading correction data i/o. hkwr: l input. hkwr: h high-impedance. vpd4 o/hi-z psd2: 1, psd1: 0, psd0: 0 (ibcnt regi) to vpd0 binary parallel image signal output (parallel interface) dack: l output. dack: h high-impedance. vscd4 o psd2: 1, psd1: 0, psd0: 1 (ibcnt regi) to vscd0 shading correction data i/o. vgsd4 o psd2: 1, psd1: 1, psd0: 0 (ibcnt regi) to vgsd0 multivalue image signal output sbus4 o psd2: 1, psd1: 1, psd0: 1(ibcnt regi) to sbus0 internal dbus data output *1 vpd0 to 7 1: black data direction: msb first 0: white *2 vpd0 to 7 x'ff' to x'00': "white" to "black" *3 vgsd 0 to 6 x'7f' to x'00': "white" to "black" *4 vadd0 to 7 x'ff' to x'00': "white" to "black" maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
for communications equipment MN86072 image signal frequency: 00 l max. 625khz to 1mhz memory selection bit, stk. lll 01 lll 0: sram or psram 1: psram 1 0 fixed in rom exscd * 1 0: internal scd processing. fixed 1: external scd input. 11 in rom ll image signal frequency: 0C lll max. 3 mhz exscd * 1 0: internal scd processing. m l h 1: external scd input. fixed stk:C 11 ll disabling black correction and in rom enlargement reduces memory requirements to two srams. image signal frequency: max. 6 mhz hhl C C lll exscd * 1 fixed 0: internal scd processing. in rom 1: external scd input. stk:C 8. memory interface pins pin descriptions (continued) function is selected by the memory control register (mecr) and mode pins of mcmo (pin no. 86) and of mcm1 (pin no. 85). mode pins mecr image processing functions mode mcm1 mcm0 rsh mag shading enlarge- notes ment white correc- tion black correc- tion note* 1: scd is the data after shading correction. maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86072 for communications equipment 18 lmxd0 ram data i/o bus. to to i/o i/o data bus for white shading data, black shading data, error 11 lmxd7 dispersion processing error data, and 2-line image data." 95 lma0 ram address to to 88 lma7 97 lma8 96 lma9 o 104 lma10 103 lma11 102 lma12 2 lma13 105 lma14 99 lmoe o ram oe control 100 lmwe o ram we control 101 lmce o pseudo-sram chip select control 103 lsid0 i white shading rom data input. input for data after external shading to to correction. 106 lsid7 98 lroe o white shading rom oe control. 4 lrwe o eerom we control 116 lra10 o upper address of eerom to to (the lower bits use lma0Clma9.) 114 lra12 127 lap0 o output port a (8 bits) to to 121 lap6 10 lap7 9 lbp0 o output port b (8 bits) to to 5 lbp4 120 lbp5 119 lbp6 118 lbp7 8.1 l mode pin no. symbol i/o function description pin descriptions (continued) maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
for communications equipment MN86072 18 mmed0 ram data i/o. to to i/o white shading data and error dispersion processing error data. 11 mmed7 127 mmfd0 ram data i/o. to to i/o black shading data and error dispersion processing error data (for use 121 mmfd6 in enlargement). 10 mmfd7 120 mmld0 ram data i/o. to to i/o 2-line image data. 114 mmld6 113 msid0 white shading rom data input, or to to i input for data after external shading correction. 106 msid7 95 mma0 ram address to to 88 mma7 97 mma8 96 mma9 o 104 mma10 to to 102 mma12 6 mma13 2 msa0 o upper address of ram 105 msa1 101 mmewe ram we control 100 mmfwe o 99 mmlwe 98 mmoe o ram oe control 5 mroe o white shading rom and eerom oe control 4 mrwe o eerom we control 9 mbp0 output port b (3 bits) to to o 7 mbp2 8.2 m mode pin no. symbol i/o function description pin descriptions (continued) maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86072 for communications equipment 18 hmsd0 ram data i/o. to to i/o white shading data. 11 hmsd7 127 mmad0 ram data i/o. to to i/o one-line image data. 121 mmad6 10 mmbd0 ram data i/o. to to i/o one-line image data. 4 mmbd6 120 mmcd0 ram data i/o. to to i/o one-line image data. 114 mmcd6 113 hmid0 fifo data input. to to i error dispersion processing error data. 106 hmid7 95 hmod0 fifo data input. to to o error dispersion processing error data. 88 hmod7 97 hmswr ram oe control 96 hmawr o 104 hmbwr 103 hmcwr 102 hmwe o ram we control (needs nand gate) 105 hwck o fifo wck 101 hrck o fifo rck 100 hrstw o fifo rstw 99 hrstr o fifo rstr 98 hfwe o fifo we 3 mack o ram address counter clock 2 hrsta o ram address counter clear 8.3 h mode pin no. symboll i/o funcrion description pin descriptions (continued) maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
for communications equipment MN86072 application circuit example (1) h mode white correction (without sma mode) with no black correction memory configuration: 64-kbit sram 4 5k 8-bit fifo 1 sram(64k) sram(64k) i/o0 to 7 a0 to 12 oe we i/o0 to 6 a0 to 12 oe oe we sram(64k) sram(64k) i/o0 to 6 i/o0 to 6 a0 to 12 a0 to12 we oe we 13 cl ck q f163 4 din wck rstw we rstr rck dout fifo(5k 8) MN86072 hmsd0 to 7 swr hmad0 to 6 hmbd0 to 6 bwr hmcd0 to 6 cwr hmwe hrsta hmod0 to 7 mack hwck hrstw hrck hmid0 to 7 awr hrstr hfwe maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
MN86072 for communications equipment application circuit example (2) h mode white correction (without sma mode) with black correction memory configuration: 64-kbit sram 4 5k 8-bit fifo 1 sram(64k) sram(64k) i/o0 to 4 a0 to 12 oe we i/o0 to 6 a0 to 12 oe oe we sram(64k) i/o0 to 7 a0 to 12 oe we sram(64k) sram(64k) i/o0 to 6 i/o0 to 6 a0 to 12 a0 to 12 we oe we 13 13 cl ck q f163 4 cl ck q f163 4 din wck rstw we rstr rck dout fifo(5k 8) MN86072 hmkd0 to 4 hmsd0 to 7 swr hkwr hrstk hmad0 to 6 hmbd0 to 6 bwr hmcd0 to 6 cwr hmwe hrsta hmod0 to 7 mack hwck hrstw hrck hmid0 to 7 awr hrstr hfwe maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
for communications equipment MN86072 package dimensions (unit: mm) qfh128-p-1818 0.2 ?.1 0.5 ?.2 (1.25) (1.25) 33 128 97 18.0 ?.2 18.0 ?.2 0.1 ?.1 20.0 ?.2 20.0 ?.2 0 to 10 1.0 ?.2 64 3.4 ?.3 3.3 ?.2 96 65 132 0.5 0.1 seating plane 0.15 +0.10 ?.05 maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/
request for your special attention and precautions in using the technical information and semiconductors described in this book (1) if any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) the technical information described in this book is intended only to show the main characteristics and application circuit examples of the products, and no license is granted under any intellectual property right or other right owned by our company or any other company. therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) the products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). consult our sales staff in advance for information on the following applications: ? special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the prod- ucts may directly jeopardize life or harm the human body. ? any applications other than the standard applications intended. (4) the products and product specifications described in this book are subject to change without notice for modification and/or im- provement. at the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date product standards in advance to make sure that the latest specifications satisfy your requirements. (5) when designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. otherwise, we will not be liable for any defect which may arise later in your equipment. even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (esd, eos, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. when using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) this book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of matsushita electric industrial co., ltd. maintenance/ discontinued maintenance/discontinued includes following four product lifecycle stage. planed maintenance type maintenance type planed discontinued typed discontinued type please visit following url about latest information. http://www.semicon.panasonic.co.jp/en/

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