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standard power data sheet rev. 1.11, 2015-01-30 ifx1763 v50 wide input range low noise 500ma 5v ldo IFX1763XEJV50 ifx1763ldv50
type package marking IFX1763XEJV50 pg-dso-8 exposed pad 1763ev50 ifx1763ldv50 pg-tson-10 176lv50 pg-dso-8 exposed pad pg-tson-10 data sheet 2 rev. 1.11, 2015-01-30 wide input range low noise 500ma 5v ldo IFX1763XEJV50 ifx1763ldv50 1overview features ? low noise down to 42 v rms (bw = 10 hz to 100 khz) ? 500ma current capability ? low quiescent current: 30 a ? wide input voltage range up to 20 v ? internal circuitry working down to 1.8 v ? 2.5% output voltage accuracy (over full temperature and load range) ? low dropout voltage: 350 mv ? very low shutdown current: < 1 a ? no protection diodes needed ? fixed output voltage: 5.0 v ? stable with 3.3 f output capacitor ? stable with aluminium, tantalum or ceramic capacitors ? reverse battery protection ? no reverse current ? overcurrent and overtemperature protected ? pg-dso-8 exposed pad and tson-10 exposed pad packages ? green product (rohs compliant) applications ? microcontroller supply ? battery-powered systems ? noise sensitive instruments ? radar applications ? image sensors the ifx1763 v50 is not qualified and manufactured acco rding to the requirements of infineon technologies with regards to automotive and/or transportation applications. for automotive applications please refer to the infineon tlx (tle, tls, tlf.....) vo ltage regulator products.
IFX1763XEJV50 ifx1763ldv50 overview data sheet 3 rev. 1.11, 2015-01-30 the ifx1763 v50 is a micropower, low noise, low dropou t 5 v voltage regulator. the device is capable of supplying an output current of 500 ma with a dropout vo ltage of 350 mv. designed for use in battery-powered systems, the low quiesce nt current of 30 a makes it an ideal choice. one feature of the ifx1763 v50 is its low output noise: by adding an external 0.01 f bypass capacitor output noise values down to 42 v rms over a 10 hz to 100 khz bandwidth can be reached. the ifx1763 v50 voltage regulator is stable with output capaci tors as small as 3.3 f. small ceramic capacitors can be used without the series resistance required by many other regulators. its internal protection circuitry includes reverse battery protection, current limiting and revers e current protection. the ifx1763 v50 is available in a pg-dso-8 exposed pad and as well as in a tson10 exposed pad package.
data sheet 4 rev. 1.11, 2015-01-30 IFX1763XEJV50 ifx1763ldv50 block diagram 2 block diagram note: pin numbers in the block diagram refer to the dso-8 ep package type. figure 1 block diagram ifx1763 v50 bias voltage reference saturation control temperature protection over current protection ifx1763 in en gnd byp out sense error amplifier 1 2 4 5 8 6
IFX1763XEJV50 ifx1763ldv50 pin configuration data sheet 5 rev. 1.11, 2015-01-30 3 pin configuration 3.1 pin assignment figure 2 pin configuration of IFX1763XEJV50 in pg-dso-8 exposed pad figure 3 pin configuration of ifx1763ldv50 in pg-tson10 in nc gnd out sense nc byp en 1 3 2 8 7 6 45 ifx1763 xej v50 9 1 2 3 4 5 10 9 8 7 6 out out nc sense byp in in nc en gnd 11 ifx1763ld v50
data sheet 6 rev. 1.11, 2015-01-30 IFX1763XEJV50 ifx1763ldv50 pin configuration 3.2 pin definitions and functions pin symbol function 1 (dso-8 ep) 1,2 (tson-10) out output . supplies power to the load. for this pin a minimum output capacitor of 3.3 f is required to preven t oscillations. larger ou tput capacitors may be required for applications wit h large transient loads in order to limit peak voltage transients or when the regulator is appli ed in conjunction with a bypass capacitor. for more details please refer to th e section ?application information? on page 19 . 2 (dso-8 ep) 4 (tson-10) sense output sense. the sense pin is the input to the error amplifier. this allows to achieve an optimized regulation performa nce in case of small voltage drops r p that occur between regulator and load. in applications where such drops are relevant they can be eliminated by connect ing the sense pin directly at the load. in standard configurations the sense pi n can be connected directly to the out pin. for further details please refer to the section ?kelvin sense connection? on page 19 . 3, 7 (dso-8 ep) 3, 8 (tson-10) nc no connect. the nc pins have no connection to any internal circuitry. connect either to gnd or leave open. 4 (dso-8) 5 (tson-10) byp bypass. the byp pin is used to bypass the reference of the ifx1763 v50 to achieve low noise performanc e. the byp-pin is clamped in ternally to 0.6 v (i.e. one v be ). a small capacitor fr om the output to th e byp pin will bypass the reference to lower the output voltage noise 1) . if not used this pin must be left unconnected. 1) a maximum value of 10 nf can be used for reducing output voltage noise over the bandwidth from 10 hz to 100 khz. 5 (dso-8 ep) 7 (tson-10) en enable. with the en pin the ifx1763 v50 can be put into a low power shutdown state. the output will be off wh en the en is pulled low. the en pin can be driven by 5v logic or open-collector logic with pull-up resistor. the pull-up resistor is required to supply the pull-up current of the open-collector gate 2) and the en pin current 3) . please note that if the en pin is not used it must be connected to v in . it must not be left floating. 2) normally several microamperes. 3) typical value is 1 a. 6 (dso-8 ep) 6,(tson-10) gnd ground. 8 (dso-8 ep) 9, 10 (tson-10) in input. via the input pin in the power is supplied to the device. a capacitor at the input pin is required if the device is more than 6 inches away from the main input filter capacitor or if bigger indu ctance is present at the in pin 4) . the ifx1763 v50 is designed to withstand reverse voltages on the input pin with respect to gnd and output. in the case of reverse input (e.g. due to a wrongly attached battery) the device will act as if there is a diode in series with its input. in this way there will be no reverse current flow ing into the regu lator and no reverse voltage will appear at the load. hence, the device will prot ect both - the device itself and the load. 4) in general the output impedance of a battery rises with frequen cy, so it is advisable to incl ude a bypass capacitor in batter y- powered circuits. depending on actual conditions an i nput capacitor in the range of 1 to 10 f is sufficient. 9 (dso-8 ep) 11 (tson-10) tab exposed pad. to ensure proper thermal performance, solder pin 11 (exposed pad) of tson10 to the pcb ground and tie directly to pin 6. in the case of dso- 8 ep as well solder pin 9 (exposed pad) to the pcb ground and tie directly to pin 6.
IFX1763XEJV50 ifx1763ldv50 general product characteristics data sheet 7 rev. 1.11, 2015-01-30 4 general product characteristics 4.1 absolute maximum ratings notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. table 1 absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to gr ound, positive current flowing into pin (unless otherwise specified) 1) not subject to production test, specified by design. parameter symbol va lues unit note / test condition number min. typ. max. input voltage voltage v in -20 ? 20 v ? p_4.1.1 output voltage voltage v out -20 ? 20 v ? p_4.1.2 input to output differential voltage v in -v out -20 ? 20 v ? p_4.1.3 sense pin voltage v sense -20 ? 20 v ? p_4.1.4 byp pin voltage v byp -0.6 ? 0.6 v p_4.1.5 enable pin voltage v en -20 ? 20 v ? p_4.1.6 temperatures junction temperature t j -40 ? 150 c ? p_4.1.7 storage temperature t stg -55 ? 150 c ? p_4.1.8 esd susceptibility all pins v esd -2 ? 2 kv hbm 2) 2) esd susceptibility, hbm accordin g to ansi/esda/jedec js001 (1.5k ? , 100 pf) p_4.1.9 all pins v esd -1 ? 1 kv cdm 3) 3) esd susceptibility, charged device model ?cdm? according jedec jesd22-c101 p_4.1.10
data sheet 8 rev. 1.11, 2015-01-30 IFX1763XEJV50 ifx1763ldv50 general product characteristics 4.2 functional range note: within the functional or operating range, the ic operat es as described in the circuit description. the electrical characteristics are specif ied within the conditions given in th e electrical char acteristics table. 4.3 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . table 2 functional range parameter symbol values unit note / test condition number min. typ. max. input voltage range v in 5.5 ? 20 v ? p_4.2.1 operating junction temperature t j -40 ? 125 c ? p_4.2.2 table 3 thermal resistance 1) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. ifx1763x ej (pg-dso-8 exposed pad) junction to case r thjc ? 7.0 ? k/w ? p_4.3.1 junction to ambient r thja ?39?k/w? 2) 2) specified r thja value is according to jedec jesd51-2,-5,-7 at na tural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm boar d with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. p_4.3.2 junction to ambient r thja ? 155 ? k/w footprint only 3) 3) specified r thja value is according to jedec jesd 51-3 at natural convection on fr4 1s0p board; the product (chip+package) was simulated on a 76.2 114.3 1.5 mm 3 board with 1 copper layer (1 x 70m cu). p_4.3.3 junction to ambient r thja ?66?k/w300 mm 2 heatsink area on pcb 3) p_4.3.4 junction to ambient r thja ?52?k/w600 mm 2 heatsink area on pcb 3) p_4.3.5 ifx1763 ld (pg-tson10) junction to case r thjc ? 6.4 ? k/w ? p_4.3.6 junction to ambient r thja ?53?k/w? 2) p_4.3.7 junction to ambient r thja ? 183 ? k/w footprint only 3) p_4.3.8 junction to ambient r thja ?69?k/w300 mm 2 heatsink area on pcb 3) p_4.3.9 junction to ambient r thja ?57?k/w600 mm 2 heatsink area on pcb 3) p_4.3.10
IFX1763XEJV50 ifx1763ldv50 electrical characteristics data sheet 9 rev. 1.11, 2015-01-30 5 electrical characteristics 5.1 electrical characteristics table table 4 electrical characteristics -40 c < t j < 125 c; all voltages with respect to ground; positive current defined flowing out of pin; unless otherwise specified. parameter symbol values unit note / test condition number min. typ. max. minimum operating voltage 1) minimum operating voltage v in,min ?1.82.3v i out = 500 ma p_5.1.1 output voltage 2) output voltage v out 4.875 5.00 5.125 v 1 ma < i out < 500 ma; 6v< v in <20v p_5.1.2 line regulation line regulation ? v out ?125mv ? v in = 5.5 v to 20 v; i out =1ma p_5.1.3 load regulation load regulation ? v out ?1632mv t j =25c; v in =6.0v; ? i out =1 to 500ma p_5.1.4 load regulation ? v out ??57mv v in =6.0v; ? i out =1 to 500ma p_5.1.5 dropout voltage 3) dropout voltage v dr ? 110 140 mv i out =10ma; v in = v out,nom ; t j =25c p_5.1.6 dropout voltage v dr ? ? 190 mv i out =10ma; v in = v out,nom p_5.1.7 dropout voltage v dr ? 170 200 mv i out =50ma; v in = v out,nom ; t j =25c p_5.1.8 dropout voltage v dr ? ? 250 mv i out =50ma; v in = v out,nom p_5.1.9 dropout voltage v dr ? 200 230 mv i out =100ma; v in = v out,nom ; t j =25c p_5.1.10 dropout voltage v dr ? ? 300 mv i out =100ma; v in = v out,nom p_5.1.11 dropout voltage v dr ? 350 380 mv i out =500ma; v in = v out,nom ; t j =25c p_5.1.12 dropout voltage v dr ? ? 480 mv i out =500ma; v in = v out,nom p_5.1.13 gnd pin current 4) gnd pin current i gnd ?3060a v in = v out,nom; i out =0ma p_5.1.14 gnd pin current i gnd ? 50 100 a v in = v out,nom; i out =1ma p_5.1.15
data sheet 10 rev. 1.11, 2015-01-30 IFX1763XEJV50 ifx1763ldv50 electrical characteristics gnd pin current i gnd ? 300 850 a v in = v out,nom; i out =50ma p_5.1.16 gnd pin current i gnd ?0.72.2ma v in = v out,nom; i out =100ma p_5.1.17 gnd pin current i gnd ?38ma v in = v out,nom; i out =250ma p_5.1.18 gnd pin current i gnd ?1122ma v in = v out,nom; i out =500ma; t j 25c p_5.1.19 gnd pin current i gnd ?1131ma v in = v out,nom; i out =500ma; t j < 25c p_5.1.20 quiescent current in shutdown quiescent current in off-mode (en-pin low) i q ?0.11a v in =6v; v en =0v; t j =25c p_5.1.21 enable enable threshold high v th,en ?0.82.0v v out = off to on p_5.1.22 enable threshold low v tl,en 0.25 0.65 ? v v out = on to off p_5.1.23 en pin current 5) i en ?0.01?a v en =0v; t j = 25c p_5.1.24 en pin current 5) i en ?1?a v en =20v; t j = 25c p_5.1.25 output voltage noise 6) output voltage noise e no ?55? v rms c out = 10 f ceramic; c byp =10nf; i out =500ma; (bw = 10 hz to100 khz) p_5.1.26 output voltage noise e no ?44? v rms c out = 10f ceramic +250m ? resistor in series; c byp =10nf; i out =500ma; (bw = 10 hz to100 khz) p_5.1.27 output voltage noise e no ?42? v rms c out = 22 f ceramic; c byp =10nf; i out =500ma; (bw = 10 hz to100 khz) p_5.1.28 output voltage noise e no ?42? v rms c out = 22 f ceramic +250m ? resistor in series; c byp =10nf; i out =500ma; (bw = 10 hz to100 khz) p_5.1.29 power supply ripple rejection 6) power supply ripple rejection psrr 50 65 ? db v in - v out = 1.5 v (avg); v ripple =0.5vpp; f r =120hz; i out =500ma p_5.1.30 table 4 electrical characteristics (cont?d) -40 c < t j < 125 c; all voltages with respect to ground; positive current defined flowing out of pin; unless otherwise specified. parameter symbol values unit note / test condition number min. typ. max.
IFX1763XEJV50 ifx1763ldv50 electrical characteristics data sheet 11 rev. 1.11, 2015-01-30 note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specified mean valu es expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25c and the given supply voltage. output current limitation output current limit i out,limit 520 ? ? ma v in =7v; v out = 0 v p_5.1.31 output current limit i out,limit 520 ? ? ma v in = v out,nom +1v ? v out =-0.1v p_5.1.32 input reverse leakage current input reverse leakage i leak,rev ??1ma v in =-20v; v out = 0 v p_5.1.33 reverse output current 7) reverse outp ut current i reverse ?1020a v out = v out,nom ; v in < v out,nom ; t j = 25c p_5.1.34 output capacitor 6) output capacitance c out 3.3 ? ? f c byp = 0 nf p_5.1.35 esr esr ? 8) ?3 ? ? p_5.1.36 1) this parameter defines the minimum input voltage for whic h the device is powered up and provides the maximum nominal output current of 500 ma. under this minimum input voltage condition the ifx1763 v50 starts to be in tracking mode and the output voltage will typically be in the r ange of around 1 v while providing the 500 ma. 2) the operation conditions are limited by the maximum junction temperature. the regulated out put voltage spec ification will only apply for conditions where the limit of the maximum juncti on temperature is fulfilled. it will therefore not apply for all possible combinations of input voltage and output curren t. when operating at maximum in put voltage, the output current must be limited for thermal reasons. the same holds true when operating at maximum output current where the input voltage range must be limited for thermal reasons. 3) the dropout voltage is the minimum inpu t to output voltage differential needed to maintain regulation at a specified output current. in dropout, the output voltage will be equal to v in - v dr . 4) gnd-pin current is tested with v in = v out,nom and a current source load. this means that this parameter is tested while being in dropout condition and thus reflects a worst case condition. the gnd-pin current will in mo st cases decrease slightly at higher input voltages - please also refer to the corresponding typical performance graphs. 5) the en pin current flows into en pin. 6) not subject to production test, specified by design. 7) reverse output current is tested with the in pin grounded and th e out pin forced to the rated output voltage. this current flows into the out pin and out of the gnd pin. 8) c byp =0nf, c out 3.3 f; please note that for cases where a bypass capacitor at byp is used - depending on the actual applied capacitance of c out and c byp - a minimum requirement for esr may apply. for further details please also refer to the corresponding typical performance graph. table 4 electrical characteristics (cont?d) -40 c < t j < 125 c; all voltages with respect to ground; positive current defined flowing out of pin; unless otherwise specified. parameter symbol values unit note / test condition number min. typ. max.
data sheet 12 rev. 1.11, 2015-01-30 IFX1763XEJV50 ifx1763ldv50 typical performanc e characteristics 6 typical performance characteristics dropout voltage v dr versus output current i out guaranteed dropout voltage v dr versus output current i out dropout voltage v dr versus junction temperature t j quiescent current versus junction temperature t j 0 100 200 300 400 500 0 50 100 150 200 250 300 350 400 450 500 i out [a] v dr [mv] t j = ?40 c t j = 25 c t j = 125 c 0 100 200 300 400 500 0 50 100 150 200 250 300 350 400 450 500 i out [a] v dr [mv] = guaranteed limits t j 25 c t j 125 c ?50 0 50 100 0 50 100 150 200 250 300 350 400 450 500 t j [ c] v dr [mv] i out = 10 ma i out = 50 ma i out = 100 ma i out = 500 ma ?50 0 50 100 0 5 10 15 20 25 30 35 40 45 50 t j [ c] i q [a] v in = 6 v i out = 0 ma . v en = v in
IFX1763XEJV50 ifx1763ldv50 typical performanc e characteristics data sheet 13 rev. 1.11, 2015-01-30 output voltage v out versus junction temperature t j quiescent current i q versus input voltage v in gnd current i gnd versus input voltage v in gnd current i gnd versus input voltage v in ?50 0 50 100 4.9 4.92 4.94 4.96 4.98 5 5.02 5.04 5.06 5.08 t j [ c] v out [v] i out = 1 ma 0 2 4 6 8 10 0 100 200 300 400 500 600 700 800 v in [v] i gnd [a] v out,nom = 5.0 v i out,nom = 0 ma v en = v in t j = 25 c 0 2 4 6 8 10 0 200 400 600 800 1000 1200 1400 1600 v in [v] i gnd [a] [* for v out = 5.0 v] t j = 25 c r load = 5.0 k / i out = 1 ma* r load = 100 / i out = 50 ma* 0 2 4 6 8 10 0 2 4 6 8 10 12 14 16 v in [v] i gnd [ma] [* for v out = 5.0 v] t j = 25 c r load = 50.0 / i out = 100 ma* r load = 16.7 / i out = 300 ma* r load = 10.0 / i out = 500 ma *.
data sheet 14 rev. 1.11, 2015-01-30 IFX1763XEJV50 ifx1763ldv50 typical performanc e characteristics gnd current i gnd versus output current i out en pin threshold (on-to-off) versus junction temperature t j en pin threshold (off-to-on) versus junction temperature t j en pin current i en versus en pin voltage v en 0 100 200 300 400 500 0 2 4 6 8 10 12 i out [ma] i gnd [ma] v in = 6 v t j = 25 c ?50 0 50 100 0 0.2 0.4 0.6 0.8 1 1.2 t j [ c] v en,th [v] 1 ma 500 ma ?50 0 50 100 0 0.2 0.4 0.6 0.8 1 1.2 t j [ c] v en,th [v] 1 ma 500 ma 0 5 10 15 20 0 0.2 0.4 0.6 0.8 1 1.2 1.4 v en [v] i en [a] t j = 25 c v in = 20 v
IFX1763XEJV50 ifx1763ldv50 typical performanc e characteristics data sheet 15 rev. 1.11, 2015-01-30 en pin current versus junction temperature t j current limit versus input voltage v in current limit versus junction temperature t j reverse output current versus output voltage v out ?50 0 50 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 t j [ c] i en [a] v en = 20 v 0 1 2 3 4 5 6 7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 v in [v] i out,max [a] v out = 0 v t j = 25 c ?50 0 50 100 0 0.2 0.4 0.6 0.8 1 1.2 t j [ c] i out,max [a] v in = 7 v v out = 0 v 0 2 4 6 8 10 0 10 20 30 40 50 60 70 80 90 v out [v] i out,rev [a] v in = 0 v t j = 25 c v out.nom = 5.0 v (v50)
data sheet 16 rev. 1.11, 2015-01-30 IFX1763XEJV50 ifx1763ldv50 typical performanc e characteristics reverse output current versus junction temperature t j minimum input voltage 1) versus junction temperature t j 1) v in ,min is referred here as the minimum input volt age for which the requested current is provided and v out reaches 1 v. load regulation versus junction temperature t j ?50 0 50 100 0 2 4 6 8 10 12 14 16 18 20 22 t j [ c] i out,rev [a] v in = 0 v v out.nom = 5.0 v (v50) ?50 0 50 100 0 0.5 1 1.5 2 2.5 t j [ c] v in,min [v] i out = 100 ma i out = 500 ma ?50 0 50 100 ?30 ?25 ?20 ?15 ?10 ?5 0 t j [ c] v load [mv] i load = 1 ma to 500 ma v in = 6.0 v; v out.nom = 5.0 v
IFX1763XEJV50 ifx1763ldv50 typical performanc e characteristics data sheet 17 rev. 1.11, 2015-01-30 esr stability versus output current i out (for c out =3.3f) esr( c out ) with c byp = 10 nf versus output capacitance c out input ripple rejection psrr versus frequency f input ripple rejection psrr versus junction temperature t j esr max c byp = 0 nf esr min c byp = 0 nf esr max c byp = 10 nf esr min c byp = 10 nf 0 100 200 300 400 500 10 ?1 10 0 10 1 i out [ma] esr(c out ) [ ] c out = 3.3 f (0.06 is measurement limit) 2 3 4 5 6 7 0 0.5 1 1.5 2 2.5 3 c out [f] esr(c out ) [ ] stable region above blue line c byp = 10 nf measurement limit i out =500ma c byp =0 nf i out =500ma c byp =10nf i out =50ma c byp =0 nf i out =50ma c byp =10nf 10 100 1k 10k 100k 0 10 20 30 40 50 60 70 80 90 100 f [hz] psrr [db] v in = v outnom + 1.5 v v ripple = 0.5 v pp c out = 10 f ?50 0 50 100 50 52 54 56 58 60 62 64 66 68 t j [ c] psrr [db] v in = v outnom + 1.5 v v ripple = 0.5 v pp f ripple = 120 hz c out = 10 f i out =500ma c byp =0 nf i out =500ma c byp =10nf
data sheet 18 rev. 1.11, 2015-01-30 IFX1763XEJV50 ifx1763ldv50 typical performanc e characteristics output noise spectral density versus frequency ( c out = 10f, i out =50ma 1) ) 1) load condition 50ma is representing a worst case co ndition with regard to output voltage noise performance. output noise spectral density versus frequency ( c out = 22f, i out =50ma 1) ) transient response c byp = 0nf transient response c byp = 10nf c byp = 0 nf; esr(c out )=0 c byp = 10 nf; esr(c out )=0 c byp = 10 nf; esr(c out )=250m 10 1 10 2 10 3 10 4 10 5 10 ?2 10 ?1 10 0 10 1 f [hz] output spectral noise density v/ hz c out = 10 f i out = 50 ma c byp = 0 nf; esr(c out )=0 c byp = 10 nf; esr(c out )=0 c byp = 10 nf; esr(c out )=250m output spectral noise density v/ hz c out = 22 f i out = 50 ma -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0 100 200 300 400 500 600 700 800 900 1000 v out deviation / [v] time ( s) c out = 10 f c byp = 0 nf v in = 6v 0 100 200 300 400 500 600 0 100 200 300 400 500 600 700 800 900 1000 load step / [ma] time ( s) i out : 100 to 500ma -0,2 -0,15 -0,1 -0,05 0 0,05 0,1 0,15 0,2 0 20406080100120140160180200 v out deviation / [v] time / [ s] c out = 10 f c byp = 10 nf v in = 6v 0 100 200 300 400 500 600 0 20406080100120140160180200 load step / [ma] time / [ s] i out : 100 to 500ma
IFX1763XEJV50 ifx1763ldv50 application information data sheet 19 rev. 1.11, 2015-01-30 7 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 4 typical application circuit ifx1763 v50 note: this is a very simplified example of an applicatio n circuit. the function must be verified in the real application 1)2) . the ifx1763 v50 is a 500 ma low dropout regulator with very low quiescent current and enable-functionality. the device is capable of supplying 500 m a at a dropout voltage of 350 mv. ou tput voltage noise numbers down to 42 v rms can be achieved over a 10 hz to 100 khz bandwi dth with the addition of a 10 nf reference bypass capacitor. the usage of a re ference bypass capacitor will additionally im prove transient respon se of the regulator, lowering the settling time for transient load conditions. the device has a low operating quiescent current of typical 30 a that drops to less than 1 a in shutdown (en-pin pulle d to low level). the device also incorporates several protection features which makes it idea l for battery-powered systems. it is protected against bo th reverse input and reverse output voltages. in battery backup applications where the output can be held up by a backup battery when the input is pulled to ground the device behaves li ke it has a diode in series with its output and prevents reverse current flow. 7.1 kelvin sense connection the sense pin of the ifx1763 v50 is th e input to the error amplifier. an optimum regulation will be obtained at the point where the sense pin is connected to the out pin of the regulator. in critical applications however small voltage drops can be caused by the resistance r p of the pc-traces and thus may lo wer the resulting voltage at the load. this effect may be eliminated by connecting the sense pin to the output as close as possible at the load 1) please note that in case a non-negligible inductance at in pin is present, e.g. due to long cables, traces, parasitics, etc, a bigger input capacitor c in may be required to filter its influence. as a rule of thumb if the in pin is more than six inches away from the main input filter capac itor an input capacitor value of c in = 10 f is recommended. 2) for specific needs a small optional resistor may be placed in series to very low esr output capacitors c out for enhanced noise performance (for details please see ?bypass capacitance and low noise performance? on page 20 ). r load c byp c out c in in gnd out en sense byp ifx1763 v in gnd 10nf 10f 1f v out
data sheet 20 rev. 1.11, 2015-01-30 IFX1763XEJV50 ifx1763ldv50 application information (see figure 5 ). please note that the voltage drop across the external pc trac e will add up to th e dropout voltage of the regulator. figure 5 kelvin sense connection 7.2 bypass capacitance and low noise performance the ifx1763 v50 regulator may be used in combinatio n with a bypass capacitor connecting the out pin to the byp pin in order to minimize output voltage noise 1) .this capacitor will bypass the reference of the regulator, providing a low frequ ency noise pole. the noise pole provided by such a bypass capacitor will lower the output voltage noise in the considered bandwidth. for a given outp ut voltage actual numbers of the output voltage noise will - next to the bypass capacitor itself - be dependent on the ca pacitance of the applied ou tput capacitor and its esr: in case of applying the ifx1763 v50 with a bypass capacitor of 10 nf in combination with a (low esr) ceramic c out of 10 f will result in output vo ltage noise numbers of typical 55 v rms . this output noise level can be reduced to typical 44 v rms under the same conditions by adding a small resistance of ~250 m ? in series to the 10 f ceramic output capacitor acti ng as additional esr. a reduction of the output voltage noise can also be achieved by increasing capacitance of the output capacitor. for c out = 22 f (ceramic low esr) the output voltage noise will be typical 42 v rms . for output capacitor values of 22 f or bigger adding resistance in series to c out does not further lower output noise numbers significant ly anymore. for further details please also see ?output voltage noise6)? on page 10 ,, of the electrical characteristics. please note that next to reducing the output voltage noise level the usage of a bypass capaci tor has the additional benefit of improving transient response which will be also ex plained in the next chapter. however one needs to take into consideration that on the other hand the regulator start-up time is proportional to the size of the bypass capacitor and slows down to values around 15 ms when using a 10 nf bypass capacitor in combination with a 10 f c out output capacitor. 7.3 output capacitance requirements and transient response the ifx1763 v50 is designed to be stable with a wide range of output capacitors. the esr of the output capacitor is an essential parameter wit h regard to stability, most notably with small capacitors . a minimum output capacitor of 3.3 f with an esr of 3 ? or less is recommended to prevent oscillati ons. like in general for ldo?s the output transient response of the ifx1763 v50 will be a function of the out put capacitance. larg er values of output capacitance decrease peak deviations and thus improv e transient response for larger load current changes. 1) a good quality low leakage capacitor is recommended. c in in gnd out en sense byp ifx1763 v in r load c out r p r p
IFX1763XEJV50 ifx1763ldv50 application information data sheet 21 rev. 1.11, 2015-01-30 bypass capacitors, used to decouple individual components powered by the ifx1763 v50 will increase the effective output capacitor value. please note that with the usage of larger bypass capacitors for low noise operation either larger values of output capacitors are needed or a minimum esr requirement of c out may have to be considered (see also figure ?esr(cout) with cbyp = 10 nf versus output capacitance cout? on page 17 as example). in conjunction with the usage of a 10 nf bypass capacitor an output capacitor c out 6.8 f is recommended. the benefit of a bypass capacito r to the transient response performance is impressive and illustrated as one example in figure 6 where the transient response of the ifx1763 v50 to one and the same load step from 100 ma to 500 ma is shown with and withou t a 10 nf bypass capacitor: for the given configuration of c out = 10 f with no bypass capa citor the load step will se ttle in the range of le ss than 200 s while for c out = 10 f in conjunction with a 10 nf bypa ss capacitor the same load step will settle in the range of 20 s. due to the shorter reaction time of the regulator by adding the bypass capacitor not only the settling time improves but also output voltage deviations due to load steps are sharply reduced. figure 6 influence of c byp : example of transient response to one and the same load step with and without c byp of 10 nf ( i out 100ma to 500ma) 7.4 protection features the ifx1763 v50 regulators incorporate several protection features which make them ideal for usage in battery- powered circuits. in addition to normal protection features associated with mo nolithic regulators like current limiting and thermal limiting the device is protected against reve rse input voltage, reverse output voltage and reverse voltages from out put to input. current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. for normal oper ation the junction temperat ure must not exceed 125c. the input of the device will withstand reverse voltages of 20 v. current fl owing into the device will be limited to less than 1 ma (typically less than 100 a) and no negative voltage will appear at th e output. the device will protect both itself and the load. this provides pr otection against batteries being plugged backwards. the output of the ifx1763 v50 can be pulled below ground without damaging the device. if the input is left open- circuit or grounded, the output can be pulled below ground by 20 v. under such condit ions the out pin by itself will act like an open circuit with practica lly no current flowing out of the pin 1) . in more application relevant cases where the output pin out is connected to the sense pin ther e will be a small current of typically less than 100 a present from this origin. if the input is powered by a voltage source th e output will sour ce the short-ci rcuit current of the device and will protect itself by thermal limiting. in this case grounding the en pin will turn off the device and stop the output from sourcing the short-circuit current. in circuits where a backup battery is required, several different input/output conditions can occur. the output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open-circuit. current flow ba ck into the outp ut will follow the curve as shown in figure 7 below. 1) typically < 1 a for the mentioned conditions, v out being pulled below ground with other pins either grounded or open. -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0 100 200 300 400 500 600 700 800 900 1000 v out deviation / [v] time ( s) c_byp = 0nf c_byp = 10nf c out = 10 f c byp = 0 vs 10nf v in = 6 v
data sheet 22 rev. 1.11, 2015-01-30 IFX1763XEJV50 ifx1763ldv50 application information when the in pin of the ifx1763 v50 is forced below the out pin, or the out pin is pulled above the in pin, the input current will typically drop to less than 2 a. this can happen if the input of the device is connected to a discharged battery and the output is held up by either a ba ckup battery or a second re gulator circuit. the state of the en pin will have no effect on the reverse outp ut current when the output is pulled above the input. figure 7 reverse output current 0 2 4 6 8 10 0 10 20 30 40 50 60 70 80 90 v out [v] i out,rev [a] v in = 0 v t j = 25 c v out.nom = 5.0 v (v50)
IFX1763XEJV50 ifx1763ldv50 package outlines data sheet 23 rev. 1.11, 2015-01-30 8 package outlines figure 8 pg-dso-8 exposed pad package outlines figure 9 pg-tson-10 package outlines green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). pg-dso-8-27-po v01 14 85 8 14 5 8x 0.41 0.0 9 2) m 0.2 d c a-b 1.27 c stand off +0 -0.1 0.1 (1.45) 1.7 max. 0.08 seating plane c a b 4. 9 0.1 1) a-b c 0.1 2x 3 ) jedec reference ms-012 variation ba 1) does not include plastic or metal protrusion of 0.15 max. per side 2) dambar protrusion shall be maximum 0.1 mm total in excess of lead width bottom view 0.2 3 0.2 2.65 0.2 0.2 d 6 m d 8x 0.64 0.25 3. 9 0.1 1) 0.1 0.35 x 45? cd2x +0.06 0.1 9 8 ? max. index marking pin 1 m a rking pin 1 m a rking pg-t s on-10-2-po v02 0.1 0.2 0.1 0.25 0.1 0.55 0.96 0.1 2.5 8 0.1 0 +0.05 0.1 0.1 0. 3 6 0.1 0.5 3 0.1 0.1 0.25 0.5 0.1 3 . 3 0.1 3 . 3 0.1 1 0.1 0.71 0.1 1.6 3 0.1 1.4 8 0.1 z 0.05 0.07 min. z (4:1) for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm
data sheet 24 rev. 1.11, 2015-01-30 IFX1763XEJV50 ifx1763ldv50 revision history 9 revision history revision date changes 1.11 2015-01-30 ? editorial changes - figure title of tson-10 package figure in product overview corrected. 1.1 2014-10-30 updated data sheet includin g additional package type pg-tson-10: ? pg-tson-10 package variants added: product overview, pin configuration thermal resistance, wording, etc added / updated accordingly. ? editorial changes throughout the document. 1.0 2014-05-16 data sheet - initial release
edition 2015-01-30 published by infineon technologies ag 81726 munich, germany ? 2015 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. the infineon technologies component descr ibed in this data sheet may be used in life-support devices or systems and/or automotive, aviation and aero space applications or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life- support automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that device or system. life support devices or syste ms are intended to be implanted in th e human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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