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| 1/3 january 2002 AN1426 application note design guide psdsoft express and psd4135 contents (see next page)
page 1 contents 1 introduction .................................................................................................................. ..................................... 2 2 physical connection ............................................................................................................ .............................. 5 3 first design exampleisp capable system........................................................................................... ....... 5 3.1 psdsoft express design entry ................................................................................................... ............... 7 3.1.1 invoke psdsoft express and open a new project................................................................................ 7 3.1.2 mcu and psd selection........................................................................................................ ............... 8 3.1.3 pin definitions ............................................................................................................ .......................... 8 3.1.4 chip select equations ....................................................................................................... .................. 10 3.1.5 design flow ................................................................................................................ ........................ 12 3.1.6 additional psd settings ..................................................................................................... ................ 12 3.1.7 psd-specific c code generation ............................................................................................... ........ 12 3.1.8 merge mcu firmware with psd ................................................................................................... .... 13 3.1.9 programming the psd......................................................................................................... ................ 15 4 enhanced design example ......................................................................................................... .................... 17 5 conclusion.................................................................................................................... .................................... 17 6 references .................................................................................................................... .................................... 17 page 2 1 introduction flash psd4x35 devices are members of a family of flash-based peripherals for use with embedded microcontrollers (mcus). these programmable system devices (psds) consist of memory, logic, and i/o. when coupled with a low-cost 16-bit mcu/mpu, the psd forms a complete embedded flash system that is 100% in-system programmable (isp) and in- application programmable (iap). there are many features in the psd silicon and in the psdsoft development software that make using the psd easy, regardless of how much embedded design experience you have. this document offers two designs using a psd4135g2 and a infineon c167cr mcu. note that a variety of 16-bit mcu/mpus can be used in place of the infineon part. although the specifics of this document are based on the c167cr, this document can be used as a guide for other mcu/mpu applications. the first design is a simple system to get up and running quickly for basic applications, or to check out your prototype c167cr hardware. the second design illustrates the use of enhanced features of psd in-system programming (isp) as applied to the c167cr. you can start with the first design and migrate to the second as your functional requirements grow. there are other members of the psd4x35 family, including the psd4235g2. the psd4235g2 has an on-chip complex pld (cpld) that replaces the gpld of the psd4135g2. see the psd4x35 data sheets for details. this application note is applicable to all psd4x35 family members. in-system programming and in-application re-programming our industry uses the term in-system programming (isp) in a general sense. isp is applicable to programmable logic, as well as programmable non-volatile memory (nvm). however, an additional term will be used in this document: in-application programming (iap). there are subtle yet significant differences between isp and iap when microcontrollers are involved. isp of memory means that the mcu is off-line and not involved while memory is being programmed. for iap, the mcu participates in programming the memory, which is important for systems that must be online while updating firmware. often, isp is well suited for manufacturing, while iap is appropriate for field updates. psd4x35 devices are capable of both isp and iap. keep in mind that iap can only program the memory sections of the psd and not the configuration and programmable logic portions. with isp, the entire psd can be erased or programmed. the iap problem typically, a host computer downloads firmware into an embedded flash system through a communication channel that is controlled by the mcu. this channel is usually a uart, but any communication channel that the c167cr supports will do. the c167cr must execute the code that controls the iap process from an independent memory array that is not being erased or programmed. otherwise, boot code and flash programming algorithms (iap loader code) will be unavailable to the c167cr. it is absolutely necessary to use an alternate memory array (an independent memory that is not being programmed) to store the iap loader code. a system designer must choose the type of alternate memory to store iap loader code (rom, sram, flash, or eeprom); each type has advantages and disadvantages. this alternate page 3 memory may reside external to the mcu or on-chip. a top-level view of an embedded iap flash system with external memory is shown in figure 1. communication channel alternate memory for iap loader code main flash memory 512 kbytes embedded system host computer system sram 8kbytes system i/o 16-bit mcu/mpu pld figure 1 embedded flash system capable of iap (5 devices) a common solution without a psd device, implementing iap with the c167cr and most other 16-bit mcus can be difficult and time consuming. for iap, some c167cr designers will use the fixed boot-loader feature of the c167cr uart to download executable code into sram. then c167cr execution jumps to the sram to execute the remainder of the download process for programming the main flash memory. this can be a cumbersome and error prone exercise using re-locatable code in volatile memory, which is difficult to debug, vulnerable to power outages, and not supported by all emulators. additionally, this method restricts the designer to using a uart to implement iap. a better, integrated solution previously, iap required mcu participation to exercise a communication channel to implement a download to the main flash memory. however, the psd4x35 offers an alternative to iap. this methodispuses a built-in ieee-1149.1 jtag interface, which requires no mcu participation. this means that a completely blank psd can be soldered into place, and the entire chip can be programmed in-system using st's flashlink ? jtag cable ($59 us) and psdsoft express? development software, available for free at www. st. com /psm . figure 2 (next page) shows a two-chip solution using a flash psd. this system has ample main flash memory, a secondary flash memory, and sram. all three of these memories can operate independently and concurrently; meaning the mcu can operate from one memory while erasing/writing the other. the system has programmable logic, expanded i/o, and design security. since the psd4x35 family is 100% isp, a blank psd4x35 can be connected to a rom-less mcu/mpu and initially programmed through the jtag port. therefore, no iap firmware needs to be written up front. just plug in the flashlink ? cable and begin programming memory, logic, and configuration. this powerful new feature of the psd4x35 allows immediate development of application code in your lab, smart manufacturing techniques, and easy field updates. page 4 communication channel embedded system host computer system i/o psd4x35 * 512 kbyte main flash * 32 kbyte secondary flash * 8 kbyte sram * programmable logic * i/o jtag 16-bit mcu/mpu figure 2 C embedded flash system capable of iap (2 devices) lets take a quick look inside the flash psd4x35, as shown in figure 3. you can see the three independent memory arrays, which are selected on a segment basis when the proper mcu address is decoded in the decode pld. the page register participates in memory decoding, which greatly simplifies paging. the mcu address, data, and control signals are routed throughout the chip and can be used within the general-purpose pld. the gpld has 24 combinatorial logic outputs for external device chip-selects or general logic. there are 52 i/o pins that can be individually configured for many different functions. a power management scheme can selectively shut down parts of the chip and tailor special power saving mechanisms on-the-fly. the security feature can block access to all areas of the chip from a device programmer/reader. finally, the self-contained jtag-isp controller allows programming of all areas of the chip. 512 kbyte primary flash 8segments 32 kbyte second flash 4segments 8 kbyte sram decode pld page reg. gpld--24 combinatorial outputs power mgmt. jtag controller mcu address/data/control bus pld bus i/o bus psd4135g2 i/o port e i/o port f i/o port g i/o port d i/o port a i/o port c i/o port b device security mcu control mcu addr/data figure 3top level block diagram of psd4x35 page 5 2 physical connection connect your c167cr to the psd4x35 as shown in figure 4. an 80-pin package is shown in the example. the same connections can be used for all of the members of the psd4x35 family. the jtag programming channel, lcd module, latched address output, and mcu i/o signals are all optional. this example design is similar to st s dk4000-c167 development kit, available for purchase ($149 us) on the web: www. st. com /psm . there are 11 unused psd i/o pins in this example. unused pins should be pulled to vcc with a 100k resistor or tied to gnd. see application note 54 for more information on the jtag port. tdo tstat ad1 tms ad2 ad6 terr\ ad3 ad0 ad7 ad4 tdi ad5 tck rd_wr mcuio2 mcuio3 reset\ mcuio1 mcuio0 a0 ad12 wr\ ad9 ad8 ad14 ad10 ad11 ad15 rd\ ad13 ale a16 a17 a18 a19 a20 a21 a22 a23 mcuio4 mcuio5 mcuio6 mcuio7 lcd_e bhe\ a1 a2 a3 a4 a5 a6 a8 a9 a10 a11 a12 a13 a14 a15 a7 u1 ea xtal1 xtal2 rstin ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 rd ale txd rxd wr/wrl a16 a17 a18 a19 a20 a21 a22 a23 wrh/bhe u2 ??????????? 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 20 48 47 46 45 44 43 42 41 47 50 49 79 80 1 48 2 71 72 73 74 75 76 77 78 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 adio15 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 cntl0 cntl1 cntl2 pd0 pd1 pd2 reset pd3 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 reset\ la_out[15..0] data bus 2 x 16 lcd module jtag-isp connector r/w xx mhz uart port ? ? ad7-ad0 e mcu i/o signals rs figure 4 C physical connections, c167cr and psd4x35 3 first design exampleisp capable system the first design example is only capable of isp and not iap. it outlines the steps required to get a flash c167cr system up and running quickly. basically, the psds secondary flash will be page 6 programmed with the jtag-isp channel with code that will execute basic system tests and display some messages on the lcd. the second design example takes advantage of concurrent memory operation and iap, using the main flash in addition to the secondary flash. you should become familiar with this first design before using the second. a psd4135g2 was used for this example. however, other members of the flash f amily may be used instead, with minor changes to the sample design. see the psd4x35 series data sheets for a comparison of family members. for this simple design, we used a psd4135g2 with the following memories: 512 kbytes main flash memory, broken into eight 64 kbyte segments denoted fs i(i=0-7) 32 kbytes secondary flash, broken into four 8 kbyte segments denoted csboot j(j=0-3) . 8 kbyte sram (rs0) 256-byte psd4135 configuration register (csiop). note: the psd memory segments are defined using psdsoft express?. well use the psds secondary flash memory to hold the boot code, c167 interrupt vectors, and common firmware functions. for this example, well execute from the psds secondary flash memory only and not use the psds main flash memory. lets examine the sample memory map in figure 5, below. notes: 0x0 0x4000 0x8000 0xc000 0xffff psd secondary flash for boot code (csboot0-1) 8k x 16 c167 registers psd sram (rs0) 4k x 16 xram 0xc000 0xe800 0xf000 0xe000 0xd000 unmapped 1. only c167 page 0 is used for this demonstration(no segmentation, 64k max) boot configuration lcd chip sel. (lcd_e) psd control reg (csiop) 2. syscon and buscon0 used for memory access except for csiop and lce_e, which use buscon1. unmapped unmapped 0xffff 0xde00 0xdf00 figure 5memory map: simple c167cr/psd4x35 design page 7 note the following about the sample memory map shown in figure 5: this simple example only requires 16 address bits only half (16 kbytes) of the secondary flash is used the middle 32 kbytes of the memory map is unused the upper 16 kbytes is allocated for the psd sram (rs0), the psd control register (csiop), the lcd module, and the c167cr registers and ram. the boot memory holds the following information: c167cr reset vector and initialization routines c167cr interrupt vectors and service routines i/o management. since figure 5 is a sample memory map, you may wish to change it. to do so, simply edit the chip select equations for the desired segments using the design assistant. 3.1 psdsoft express design entry highlights of design entry will be given here. this section is meant to show you just the essentials to get you going. here are the steps: 3.1.1 invoke psdsoft express and open a new project start psdsoft express. create a new project. select your project folder and name the project (in this example, name the project easyc167 in the folder psdexpress\my_project). select an mcu. in this example, were using an infineon c167cr. select /wr, /rd, /bhe for the control signals. select the psd4000 series for the psd family. select a psd4135g2 and use the 80-pin tqfp package (u package). based on the above selections, the bus width will be set to 16-bits automatically. select the bus mode to be multiplexed and the ale/as level will automatically be set to high. now you have your project established, based on a psd4135g2 and a c167cr. however, there are many other mcu/mpus you could have chosen in place of the c167cr and still have use of this document. the main reason for selecting the c167cr is that it is used in our dk4000 development kit. page 8 3.1.2 mcu and psd selection this is what the screen should look like after youve made the selections: click ok . now you will be asked if you want to use the design assistant or a pre-defined template. choose design assistant. this exercise in the design assistant will help you become familiar with the design flow. in the future, you may choose to use a template, which will make many of the choices for you, based on your selection of mcu and psd. 3.1.3 pin definitions you are immediately taken to the pin definitions screen, which allows you to define each psd pin function on a point and click basis. notice that some of the psd pins that connect to the c167cr are already defined for you because their function is set. you need only define the remaining pins. we want to define the remaining pins based on the functional requirements presented in the schematic. define the pins as follows: set all the pins of port a to mcu i/o mode and label them mcuio0 to mcuio7. define pb0 and pb1 as external active-high chip selects. name pb0 lcd_e and pb1 rd_wr. set all the pins on port c to address input and give them the label a16 to a23. the port e pins pe0 to pe5 should be assigned to dedicated jtag signals. define the port f and port g pins to be latched address out and give them the labels la_out0 to la_out15, where la_out0 is assigned to pf0 and la_out15 to pg7. page 9 your pin definition screen should now look like the screen capture below: you can view a summary of your pin definitions by clicking the view button. when you are satisfied that you have defined all the pins correctly, click the next>> button to be taken to the page register definition screen. since we are not using paging in this example, you can immediately click on the chip select equations tab. it is on this screen that you define your memory map for internal and external chip-select equations. page 10 3.1.4 chip select equations your screen should be similar to the capture below: lets start by defining the chip-select for the internal sram (rs0). looking at the memory map of figure 5, we see that 4 kwords (8 kbytes) of address space needs to be allocated to the psds internal sram. so, we enter the hex start address of c000 and the hex end address of cfff. here is a snapshot of what your screen should look like after you have entered the equations: now, click on csiop and enter the equations according to figure 5. note: the csiop is x 8 access. page 11 the boot code is stored in the secondary flash in the lower 8 kwords of address space from 0h to 3fffh in csboot0 and csboot1. the equation for csboot0 should be entered as follows: enter the information for csboot1 in a similar fashion where csboot1 will be valid from 2000h to 3fffh. enter the external chip-select equation for the lcd module (x 8 access): note that since the lcd is external, we must now include the _wr and _rd control signals in the chip select equation, where this was taken care of automatically for internal chip-selects. since the _wr and _rd signals are active-low, the ! symbol is required. also notice how, after you have finished typing in the equation for the chip select, the end result appears at the bottom of the screen if you select that signal again. lastly, click on the rd_wr signal and type gnd in the last column to keep the signal low at all times. if the desire was to keep the signal high at all times, you would have typed vcc instead. you can click the view button at any time to see a design assistant summary. once you are satisfied with the results, click the done button. clicking done starts a preliminary resource check of the information you have entered to ensure that there are no overlapping memory segments, among other tests. any errors encountered will be indicated. page 12 3.1.5 design flow once you have clicked on done , you are taken to the design flow window. use this window as your main navigational tool for psdsoft express?. clicking on individual boxes within the flow diagram will invoke a process. a box shadowed in red identifies the next process that needs to be completed. the first three steps have been completed to this point. if you invoke a process that invalidates other processes downstream, the gray boxes indicate which processes must be invoked again and the red shadow indicates which process to invoke first. the design flow should be in the following state: 3.1.6 additional psd settings click on the additional psd settings box. this is where you may choose to set the security bit to prevent a device programmer from examining or copying the contents of the psd. you can also click through the other sheets on this screen to set the jtag usercode value and set sector protection on psd non-volatile memory segments as desired. 3.1.7 psd-specific c code generation you can take advantage of the provided low-level c code drivers for accessing memory elements within the psd by clicking on the generate c code specific to psd box in the design flow window. ansi c code functions and headers are generated for you to paste into your c compiler environment. simply tailor the code to meet your system needs and compile. c code generation can be performed anytime after a project is opened. to generate ansi c functions and headers, simply specify the folder(s) in which you want the header files and the c source file to be written, and name the c source file. select the categories page 13 of functions that you would like to include, then click generate . three files will be written to your specified folder(s): page 14 click on merge mcu firmware in the main flow diagram. first you will notice that psdsoft express? will fit your psd configuration to the silicon architecture of the psd. after the fitting process is complete, the merging of mcu firmware with psd screen appears. in the left column are individual psd memory segment chip-selects (fs0, fs1, and so on). the next column shows the logic equations for selection of each internal psd memory segment. these equations reflect the choices that you made while defining psd internal chip-select equations in an earlier step. in the middle of the screen are hexadecimal start and stop addresses that psdsoft express has filled in for you based on your chip-select equations. on the right are fields to enter (browse) the mcu firmware files. select intel hex record for record type as shown. scroll all the way down to the bottom to get to the secondary flash memory. now, click on the browse button for csboot0 and csboot1 and select the firmware file, psdexpress\examples\tim.h86. once you have filled in the file names, your screen should look like the one below: this specification places firmware in psd secondary flash memory segments csboot0 and csboot1. psdsoft express will extract any firmware that lies inside the file tim.h86 between mcu addresses 0000 and 3fff and place it in psd memory segment csboot0-1. click ok to generate the composite object file, easyc167.obj. note: the file tim.h86 will run on the dk4000-c167 development board from st, and display some messages on the lcd screen to indicate a successful isp session. for your own prototype project, create a simple firmware file that configures your system hardware and performs rudimentary tasks to check out your new hardware. after your new hardware is proven, you can add more code for advanced tasks, including iap of the psd flash memories. scroll to the bottom to get to the secondary flash. page 15 3.1.9 programming the psd the easyc167.obj file can be programmed into the psd by one of three ways: the st flashlink tm jtag cable, which connects to the pc parallel port. the st psdpro device programmer, which also uses the pc parallel port. third-party programmers, from stag, needhams, and others. see our website at www. st. com for compatible third-party programmers. 3.1.9.1 programming with flashlink tm connect the flashlink tm jtag-isp cable to your pc parallel port. click the jtag-isp box in the design flow window. you will be asked how many devices are in your jtag chain. for this example, select only one. you would only select more than one if you had more than one isp device in your jtag chain. after you make your selection and clicked ok , you should see the following screen: this window enables you to perform jtag-isp operations and also offers a loop back test for your flashlink tm cable. if this is your first use, test your flashlink tm cable and pc parallel port by clicking the hw setup button, then click looptest button and follow the directions. now lets define our jtag-isp environment. psdsoft express should have filled in the folder and filename of the object file to program, the psd device, and the jtag-isp operation, as shown in the screen above. for this design example, we have chosen to use all six jtag-isp pins (instead of four). be sure to indicate 6 pins as shown above to achieve minimum jtag- isp programming times. (refer to application note 54 for details on six pins versus four.) to begin programming, connect the jtag cable to the target system, power-up the target system, and click execute on the jtag screen. the log window at the bottom of the jtag screen shows the progress. page 16 there are optional choices available when the properties button is clicked. one choice includes setting the state of all non-jtag psd i/o pins during jtag-isp operations (make them inputs or outputs). the default state of all non-jtag psd i/o pins is input, which is fine for this design example. the other choice allows you to specify a usercode value to compare before any jtag-isp operation starts. this is typically used in a manufacturing environment. (see the on-screen description for details.) after jtag-isp operations have completed, you can save the jtag setup for this programming session to a file for later use. to do so, click on the save button in step 3. to restore the setup of a previous session, click the browse button in step 3. 3.1.9.2 programming with psdpro connect the psdpro device programmer to your pc parallel port per the installation instructions. click on the st conventional programmers box in the design flow window. you will see this: if this is the first use of the psdpro, youll need to designate the psdpro as the device connected to your parallel port. to do this, click the set h icon button at the top of the conventional programming screen and choose the psdpro. then click on the h test icon to perform a test of the psdpro and the pc parallel port. after testing, place a psd4135g2 into the socket of the psdproandclickonthe program icon. (the easyc167.obj file is automatically loaded when this process is invoked.) the messaging of psdsoft will inform you when programming is complete. note: this window is also helpful even if you do not have a psdpro device programmer. use this window to see where the merge mcu firmware utility has placed c167cr firmware within physical memory of the psd. for this design example, click on the secondary psd flash memory icon fb in the tool bar to see the c167cr vector at absolute mcu addresses 0001h and 0002h, which translates to direct physical psd addresses 80001h and 80002h, respectively. to see how page 17 all of your c167cr absolute addresses translated into direct physical psd memory addresses, view the report that psdsoft generates under reports from the main toolbar, then select address translation report. within the report, the start and stop addresses are the absolute mcu system addresses that you have specified. the addresses shown in square brackets are the direct physical addresses used by a device programmer to access the memory elements of the psd in a linear fashion (a special device programming mode that the mcu cannot access). 4 enhanced design example this section should be available in june, 2000. it will detail how to use the psds memories concurrently to perform iap. if you have any questions on this in the mean time, contact an applications engineer at app s.psd @ st. com . 5 conclusion these examples are just two of an endless number of ways to configure the flash psd for your system. concurrent memories with a built-in programmable decoder at the segment level offer excellent flexibility. the ability to expand your system does not require any physical connection changes, as everything is configured internal to the psd. and finally, the jtag channel can be used for isp anytime, and anywhere, with no participation from the mcu. all of these features are crosschecked under the psdsoft express? development environment to minimize your effort to design a flash-based system capable of isp and iap. 6 references 1) psd4000 family data sheet 2) application note 54 jtag informationpsd8xxf for detailed use of the jtag channel 3) dk4000 user manual for information on the c167cr/psd4135g2 development kit. AN1426 - application note 2/3 table 1. document revision history date rev. description of revision apr-2000 1.0 document written (an069) in the wsi format 03-jan-2002 1.1 front page, and back two pages, in st format, added to the pdf file 3/3 AN1426 - application note for current information on psd products, please consult our pages on the world wide web: www.st.com/psm if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.psd@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com |
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