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rev. 0 ad8369 45 db digitally controlled vga lf to 600 mhz information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2002 analog devices, inc. all rights reserved. functional block diagram bias gain code decode filt vpos pwup senb denb bit3 bit0 bit2 bit1 ophi oplo cmdc comm comm inlo inhi gm cells 3db step features digitally controlled variable gain in 3 db steps ? db to +40 db (r l = 1 k ) ?0 db to +35 db (r l = 200 ) less than 0.2 db flatness over a +20 mhz bandwidth up to 380 mhz 4-bit parallel or 3-wire serial interface differential 200 input and output impedance single 3.0 v?.5 v supply draws 37 ma at 5 v power-down <1 ma maximum applications cellular/pcs base stations if sampling receivers fixed wireless access wireline modems instrumentation ophi and oplo. the overall gain depends upon the source and load impedances due to the resistive nature of the input and output ports. digital control of the ad8369 is achieved using either a serial or a parallel interface. the mode of digital control is selected by connecting a single pin (senb) to ground or the positive sup- ply. digital control pins can be driven with standard cmos logic levels. the ad8369 may be powered on or off by a logic level applied to the pwup pin. for a logic high, the chip powers up rapidly to its nominal quiescent current of 37 ma at 25?. when low, the total dissipation drops to less than a few milliwatts. the ad8369 is fabricated on an analog devices proprietary, high performance 25 ghz silicon bipolar ic process and is available in a 16-lead tssop package for the industrial temperature range of ?0 c to +85 c. a populated evaluation board is available. product description the ad8369 is a high performance digitally controlled variable gain amplifier (vga) for use from low frequencies to a ? db frequency of 600 mhz at all gain codes. the ad 8369 delivers excellent distortion performance: the two-tone, third-order intermodulation distortion is ?9 dbc at 70 mhz for a 1 v p-p composite output into a 1 k w load. the ad8369 has a nominal noise figure of 7 db w hen at maximum gain, then increases with decreasing gain. output ip3 is +19.5 dbm at 70 mhz into a 1 k w load and remains fairly constant over the gain range. the signal input is applied to pins inhi and inlo. variable gain is achieved via two methods. the 6 db gain steps are implemented using a discrete x-amp structure, in which the input signal is progressively attenuated by a 200 w r-2r ladder network that also sets the input impedance; the 3 db steps are implemented at the output of the amplifier. this combination provides very accurate 3 db gain steps over a span of 45 db. the output imped- ance is set by on-chip resistors across the differential output pins,
rev. 0 ? ad8369?pecifications (v s = 5 v, t = 25 c, r s = 200 , r l = 1000 , frequency = 70 mhz, at maximum gain, unless otherwise noted.) parameter conditions min typ max unit overall function frequency range 3 db bandwidth lf * 600 mhz gain control interface voltage gain span 45 db maximum gain all bits high (1 1 1 1) 40 db minimum gain all bits low (0 0 0 0) ? db gain step size 3db gain step accuracy over entire gain range, with respect to 3 db step 0.05 db gain step response time step = 3 db, settling to 10% of final value 30 ns input stage input resistance from inhi to inlo 200 w from inhi to comm, from inlo to comm 100 w input capacitance from inhi to inlo 0.1 pf from inhi to comm, from inlo to comm 1.1 pf input noise spectral density 2 nv/ hz input common-mode dc voltage m easured at pin cmdc 1.7 v maximum linear input |v inhi ?v inlo | at minimum gain 2.2 v output stage output resistance from ophi to oplo 200 w from ophi to comm, from oplo to comm 100 w output capacitance from ophi to oplo 0.25 pf from ophi to comm, from oplo to comm 1.5 pf common-mode dc voltage no input signal v s /2 v slew rate output step = 1 v 1200 v/ m s power interface supply voltage 3.0 5.5 v quiescent current pwup high 37 42 ma vs. temperature ?0 c t a 85 c52ma disable current pwup low 400 750 m a vs. temperature ?0 c t a 85 c1ma power up interface pin pwup enable threshold 1.0 v disable threshold 2.2 v response time time delay following low to high transition 7 m s on pwup until output settles to within 10% of final value input bias current pwup = 5 v 160 m a digital interface pins senb, bit0, bit1, bit2, bit3, and denb low condition 2.0 v high condition 3.0 v input bias current low input 150 m a frequency = 10 mhz voltage gain 40.5 db gain flatness within 10 mhz of 10 mhz +0.05 * db noise figure 7.0 db output ip3 f1 = 9.945 mhz, f2 = 10.550 mhz +22 dbv rms +22 dbm imd 3 f1 = 9.945 mhz, f2 = 10.550 mhz v ophi ?v oplo = 1 v p-p composite ?4 dbc harmonic distortion second-order, v ophi ?v oplo = 1 v p-p ?2 dbc third-order, v ophi ?v oplo = 1 v p-p ?1 dbc p1db for 1d b deviation from linear gain +3 dbv rms +3 dbm * the low frequency high-pass corner is determined by the capacitor on pin filt, c filt . see the theory of operation section for details.
rev. 0 ad8369 ? parameter conditions min typ max unit frequency = 70 mhz voltage gain 40.5 db gain flatness within 20 mhz of 70 mhz 0.1 db noise figure 7.0 db output ip3 f1 = 69.3 mhz, f2 = 70.7 mhz +19.5 dbv rms +19.5 dbm imd 3 f1 = 69.3 mhz, f2 = 70.7 mhz v ophi ?v oplo = 1 v p-p composite ?9 dbc harmonic distortion second-order, v ophi ?v oplo = 1 v p-p ?8 dbc third-order, v ophi ?v oplo = 1 v p-p ?4 dbc p1db for 1d b deviation from linear gain +3 dbv rms +3 dbm frequency = 140 mhz voltage gain 40.0 db gain flatness within 20 mhz of 140 mhz 0.10 db noise figure 7.0 db output ip3 f1 = 139.55 mhz, f2 = 140.45 mhz +17 dbv rms +17 dbm imd 3 f1 = 139.55 mhz, f2 = 140.45 mhz v ophi ?v oplo = 1 v p-p composite ?4 dbc harmonic distortion second-order, v ophi ?v oplo = 1 v p-p ?3 dbc third-order, v ophi ?v oplo = 1 v p-p ?5 dbc p1db for 1 db deviation from linear gain +3 dbv rms +3 dbm frequency = 190 mhz voltage gain 39.7 db gain flatness within 20 mhz of 190 mhz 0.1 db noise figure 7.2 db output ip3 f1 = 189.55 mhz, f2 = 190.45 mhz +15.5 dbv rms +15.5 dbm imd 3 f1 = 189.55 mhz, f2 = 190.45 mhz v ophi ?v oplo = 1 v p-p composite ?1 dbc harmonic distortion second-order, v ophi ?v oplo = 1 v p-p ?7 dbc third-order, v ophi ?v oplo = 1 v p-p ?1 dbc p1db for 1d b deviation from linear gain +2 dbv rms +2 dbm frequency = 240 mhz voltage gain 39.3 db gain flatness within 20 mhz of 240 mhz 0.1 db noise figure 7.2 db output ip3 f1 = 239.55 mhz, f2 = 240.45 mhz +14 dbv rms +14 dbm imd 3 f1 = 239.55 mhz, f2 = 240.45 mhz v ophi ?v oplo = 1 v p-p composite ?8 dbc harmonic distortion second-order, v ophi ?v oplo = 1 v p-p ?0 dbc third-order, v ophi ?v oplo = 1 v p-p ?9 dbc p1db for 1 db deviation from linear gain +1.5 dbv rms +1.5 dbm frequency = 320 mhz voltage gain 39.0 db gain flatness within 20 mhz of 320 mhz 0.15 db noise figure 7.4 db output ip3 f1 = 319.55 mhz, f2 = 320.45 mhz +11.5 dbv rms +11.5 dbm imd 3 f1 = 319.55 mhz, f2 = 320.45 mhz v ophi ?v oplo = 1 v p-p composite ?3 dbc harmonic distortion second-order, v ophi ?v oplo = 1 v p-p ?7 dbc third-order, v ophi ?v oplo = 1 v p-p ?9 dbc p1db for 1 db deviation from linear gain +1.0 dbv rms +1.0 dbm specifications (continued)
rev. 0 ? ad8369 parameter conditions min typ max unit frequency = 380 mhz voltage gain 38.5 db gain flatness within 20 mhz of 380 mhz 0.15 db noise figure 7.8 db output ip3 f1 = 379.55 mhz, f2 = 380.45 mhz +8.5 dbv rms +8.5 dbm imd 3 f1 = 379.55 mhz, f2 = 380.45 mhz, v ophi ?v oplo = 1 v p-p composite ?7 dbc harmonic distortion second-order, v ophi ?v oplo = 1 v p-p ?5 dbc third-order, v ophi ?v oplo = 1 v p-p ?9 dbc p1db for 1 db deviation from linear gain +0.5 dbv rms +0.5 dbm specifications subject to change without notice. specifications (continued) timing specifications serial programming timing requirements (v s = 5 v, t = 25 c) parameter typ unit minimum clock pulsewidth (t pw )10ns minimum clock period (t ck )20ns minimum setup time data vs. clock (t ds )2ns minimum setup time data enable vs. clock (t es )2 ns minimum hold time clock vs. data enable (t eh )2 ns minimum hold time data vs. clock (t dh )4ns t ck t pw t eh t es clock disabled clock disabled clock enabled data is latched on low-to-high transition of denb (not to scale) t dh t ds msb msb? msb? lsb clock (bit 1) data (bit 0) data enable (denb) serial programming timing parallel programming timing requirements (v s = 5 v, t = 25 c) parameter typ unit minimum setup time data enable vs. data (t es )2 ns minimum hold time data enable vs. data (t eh )2 ns minimum data enable width (t pw )4ns msb ( bit3) da ta is latched on high-to-low transition of denb denb t es t eh t pw lsb ( bit0) msb? ( bit1) msb? ( bit2) (not to scale) parallel programming timing
rev. 0 ad8369 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8369 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * supply voltage v s , vpos . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v pwup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s + 200 mv bit0, bit1, bit2, bit3, denb, senb . . . . . . v s + 200 mv input voltage, v inhi ?v inlo . . . . . . . . . . . . . . . . . . . . . . . . 4 v input voltage, v inhi or v inlo with respect to comm . . 4.5 v input voltage, v inhi ?v inlo with respect to comm ................................ comm ?200 mv internal power dissipation . . . . . . . . . . . . . . . . . . . . . 265 mw ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c/w maximum junction temperature . . . . . . . . . . . . . . . . . 125 c operating temperature range . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . . ?5 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . to 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide model temperature range package description package option ad8369aru ?0? to +85? tube, 16-lead tssop ru-16 ad8369aru-reel7 ?0? to +85? 7" tape and reel ad8369eval evaluation board table i. typical voltage gain vs. gain code (v s = 5 v, f = 70 mhz) typical typical gain gain (db) gain (db) code bit3 bit2 bit1 bit0 r l = 1 k r l = 200 00 0005 10 10 0012 7 20 0101 4 30 0114 1 40 1007 2 50 10110 5 60 11013 8 70 11116 11 81 00019 14 91 00122 17 10 1 01025 20 11 1 01128 23 12 1 10031 26 13 1 10134 29 14 1 11037 32 15 1 11140 35
rev. 0 ? ad8369 pin configuration 1 2 3 4 5 6 7 8 16 15 12 11 9 10 14 ad8369 inlo comm bit0 bit1 bit2 bit3 denb oplo ophi cmdc filt senb vpos pwup comm inhi 13 top view (not to scale) pin function descriptions pin no. mnemonic function 1 inlo balanced differential input. internally biased, should be ac-coupled. 2 comm device common. connect to low impedance ground. 3 bit0 gain selection least significant bit. used as data input signal when in serial mode of operation. 4 bit1 gain selection control bit. used as clock input pin when in serial mode of operation. 5 bit2 gain selection control bit. inactive when in serial mode of operation. 6 bit3 gain selection most significant bit. inactive when in serial mode of operation. 7 denb data enable pin. writes data to register. see timing specifications for details. 8 oplo balanced differential output. biased to midsupply, should be ac-coupled. 9 ophi balanced differential output. biased to midsupply, should be ac-coupled. 10 cmdc common-mode decoupling pin. connect bypass capacitor to ground for additional common-mode supply decoupling beyond the existing internal decoupling. 11 filt high-pass filter connection. used to set high-pass corner frequency. 12 senb serial or parallel interface select. connect senb to vpos for serial operation. connect senb to comm for parallel operation. 13 vpos positive supply voltage, v s = +3 v to +5.5 v. 14 pw up power-up pin. connect pwup to vpos to power up the device. connect pwup to comm to power-down. 15 comm device common. connect to a low impedance ground. 16 inhi balanced differential input. internally biased, should be ac-coupled.
rev. 0 ? t ypical performance characteristics?d8369 gain code 50 10 01 gain ?db 23456 78 910 40 30 0 10 20 11 12 13 14 15 20 r l = 1k r l = 200 tpc 1. gain vs. gain code at 70 mhz frequency ?mhz 43 10 gain ?db 100 1000 41 39 37 35 33 31 29 27 25 v s = 3v, r l = 200 v s = 5v, r l = 200 v s = 5v, r l = 1k v s = 3v, r l = 1k tpc 2. maximum gain vs. frequency by r l and supply voltage gain code 01 output ip3 ?dbm 23456 78 910 20 11 12 13 14 15 14 16 18 22 24 26 28 13 7 9 11 15 17 19 21 output ip3 ?dbv rms tpc 3. output ip3 vs. gain code at 70 mhz, v s = 5 v, r l = 200 w frequency ?mhz 50 10 gain ?db 100 1000 40 30 20 10 0 10 20 gain code 15 gain code 0 tpc 4. gain vs. frequency by gain code, r l = 1 k w frequency ?mhz 50 10 gain ?db 100 1000 40 30 20 10 0 10 20 gain code 15 gain code 0 tpc 5. gain vs. frequency by gain code, r l = 200 w frequency ?mhz 10 output ip3 ?dbm 100 1000 35 30 25 20 10 0 15 5 output ip3 ?dbv rms 28 23 18 13 3 ? 8 ? tpc 6. output ip3 vs. frequency, v s = 5 v, r l = 200 w maximum gain (v s = 5 v, t = 25 c, r s = 200 , maximum gain , unless otherwise noted.)
rev. 0 ? ad8369 gain code 0 output imd ?dbc 4 ?9 3 2 15678 ?0 ?8 ?7 ?6 ?5 ?4 ?3 910111 2131415 tpc 7. two-tone, imd 3 vs. gain code at 70 mhz, v ophi ?v oplo = 1 v p-p, v s = 5 v, r l = 1 k w frequency ?mhz 050 harmonic distortion ?dbc 40 55 60 70 100 150 200 250 300 350 400 hd 3 75 45 50 65 hd 2 tpc 8. harmonic distortion at v ophi ?v oplo = 1 v p-p vs. frequency, v s = 5 v, r l = 1 k w , maximum gain gain code 50 10 01 noise figure ?db 23456 78 910 40 30 0 20 11 12 13 14 15 tpc 9. noise figure vs. gain code at 70 mhz, v s = 5 v, r l = 200 w frequency ?mhz 0 output imd ?dbc 200 ?0 150 100 50 250 300 350 400 ?0 ?0 ?0 ?0 ?0 ?0 450 500 550 600 tpc 10. two-tone imd 3 vs. frequency v ophi ?v oplo = 1 v p-p, v s = 5 v, r l = 1 k w , maximum gain hd 2 frequency ?mhz 050 harmonic distortion ?dbc 55 60 65 70 100 150 200 250 300 350 400 35 40 50 hd 3 45 tpc 11. harmonic distortion at v ophi ?v oplo = 1 v p-p vs. frequency, v s = 5 v, r l = 200 w , maximum gain 5v r l = 1k frequency ?mhz 050 noise figure ?db 7.8 100 150 200 250 300 350 400 8.0 7.6 7.4 7.2 7.0 6.8 6.6 3v r l = 200 tpc 12. noise figure vs. frequency by r l and supply voltage at maximum gain
rev. 0 ad8369 ? gain code 01 p1db ?dbm 23456 78 910 11 12 13 14 15 4.0 5.0 6.0 7.0 8.0 9.0 8.5 7.5 6.5 5.5 4.5 ?.0 ?.0 ?.0 0 1.0 2.0 1.5 0.5 ?.5 ?.5 ?.5 p1db ?dbv rms tpc 13. output p1db vs. gain code at 70 mhz, v s = 5 v, r l = 200 w frequency ?mhz 10 cmrr ?db 100 1000 80 30 20 10 0 40 50 60 70 tpc 14. common-mode rejection ratio vs. frequency at maximum gain, v s = 5 v, r l = 200 w (refer to appendix for definition) frequency ?mhz 10 resistance ? 100 100 150 200 250 1000 r c capacitance ?pf 0 0.25 0.50 0.75 inlo inhi tpc 15. equivalent input resistance and capacitance vs. frequency at maximum gain frequency ?mhz 10 p1db ?dbm 100 1000 0 1 2 3 4 5 6 7 8 9 p1db ?dbv rms ? ? ? ? ? ? ? 0 1 2 tpc 16. output p1db vs. frequency, v s = 5 v, r l = 200 w , maximum gain frequency ?mhz 40 10 reverse isolation ?db 100 1000 50 60 70 80 90 100 tpc 17. reverse isolation vs. frequency at maximum gain, v s = 5 v, r l = 200 w (refer to appendix for definition) oplo ophi frequency ?mhz 10 resistance ? 100 100 150 200 250 1000 r c capacitance ?pf 0 0.25 0.50 0.75 tpc 18. equivalent output resistance and capacitance vs. frequency at maximum gain
rev. 0 ?0 ad8369 750mhz 500mhz 0 330 300 270 240 210 180 150 120 90 60 30 380mhz 10mhz gain code 15 gain codes 0, 1, and 9 tpc 19. differential input reflection coefficient, s 11 , z o = 50 w differential, selected gain codes a verage of 128 samples time ?20ns/div gnd bit 0 2v/vertical division differential output 250mv/vertical division zero tpc 20. gain step time domain response, 3 db step, v s = 5 v, r l = 1 k w , parallel transparent mode time ?2 s/div differential output 70mhz, 750mv/div pwup 2v/vertical division gnd zero tpc 21. pwup time domain response, maximum gain, v s = 5 v, r l = 1 k w 750mhz 500mhz 0 330 300 270 240 210 180 150 120 90 60 30 380mhz 10mhz gain code 15 gain codes 0, 1, and 9 tpc 22. differential output reflection coefficient, s 22 , z o = 50 w differential, selected gain codes time ?1 s/div gnd output 1v/vertical division bit 3 2v/vertical division input = 250mv p-p, 10mhz o verdrive recovery zero tpc 23. overdrive recovery, maximum gain, v s = 5 v, r l = 1 k w , parallel transparent mode time ?20 s/div gnd zero input 2mv/div differential output 200mv/div tpc 24. pulse response, maximum gain, v s = 5 v, r l = 1 k w
rev. 0 ad8369 ?1 frequency ?mhz 10 gain error ?db 100 1000 0.5 0 1.0 1.5 2.0 0.5 1.0 1.5 2.0 40 c 85 c gain error at 40 c and 85 c with respect to 25 c. data based on 45 parts from two batch lots. tpc 25. gain error due to temp erature change vs. frequency, 3 sigma to either side of mean, v s = 5 v, r l = 1 k w , maximum gain 40 c frequency ?mhz 10 gain error ?db 100 1000 0.5 0 1.0 1.5 2.0 0.5 1.0 1.5 2.0 gain error at 40 c and 85 c with respect to 25 c. data based on 45 parts from two batch lots. 85 c tpc 26. gain error due to temperature change vs. frequency, 3 sigma to either side of mean, v s = 3 v, r l = 1 k w , maximum gain frequency ?mhz 10 output ip3 ?dbm 20 100 25 30 35 1000 output ip3 ?dbv rms 5 10 15 0 13 18 23 28 ? 3 8 ? ?0 c +85 c +25 c tpc 27. ip3 vs. frequency by temperature, v s = 5 v, r l = 200 w , maximum gain frequency ?mhz 10 gain error ?db 100 1000 0.5 0 1.0 1.5 2.0 0.5 1.0 1.5 2.0 40 c 85 c gain error at 40 c and 85 c with respect to 25 c. data based on 45 parts from two batch lots. tpc 28. gain error due to temperature change vs. frequency, 3 sigma to either side of mean, v s = 5 v, r l = 200 w , maximum gain frequency ?mhz 10 gain error ?db 100 1000 0.5 0 1.0 1.5 2.0 0.5 1.0 1.5 2.0 gain error at 40 c and 85 c with respect to 25 c. data based on 45 parts from two batch lots. 40 c 85 c tpc 29. gain error due to temperature change vs. frequency, 3 sigma to either side of mean, v s = 3 v, r l = 200 w , maximum gain frequency ?mhz 10 p1db ?dbm 100 1000 0 6 10 ? 2 4 8 85 c 40 c 25 c p1db ?dbv rms ? ? 3 ? ? ? 1 tpc 30. output p1db vs. frequency by temperature, v s = 5 v, r l = 200 w , maximum gain
rev. 0 ?2 ad8369 sample from one batch lot gain step size ?db/code pa rt count 3.08 30 0 20 10 3.10 3.12 3.14 3.06 40 50 60 tpc 31. distribution of gain step size, 70 mhz, v s = 5 v imd ?dbc pa rt count ?4 16 12 0 2 10 14 4 6 8 18 ?3 ?2 ?1 ?0 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 sample from two batch lots tpc 32. distribution of imd 3 , 70 mhz, r l = 1 k w , v ophi ?v oplo = 1 v p-p composite, v s = 5 v, maximum gain frequency ?mhz 0 group delay ?ps 400 500 300 200 100 500 600 700 800 0 1000 1500 2000 2500 3000 3v, r l = 1k 5v, r l = 1k 3v, r l = 200 5v, r l = 200 tpc 33. group delay vs. frequency by r l and supply voltage at maximum gain sample from one batch lot gain step size ?db/code 15 pa rt count 3.16 40 30 0 20 5 10 25 35 3.18 3.20 3.22 tpc 34. distribution of gain step size, 320 mhz, v s = 5 v imd ?dbc pa rt count ?8 16 12 0 2 10 14 4 6 8 18 ?7 ?6 ?3 ?2 ?5 ?4 ?1 ?0 ?9 ?8 20 22 24 26 sample from two batch lots tpc 35. distribution of imd 3 , 320 mhz, r l = 1 k w , v ophi ?v oplo = 1 v p-p composite, v s = 5 v, maximum gain frequency ?mhz 0 group delay ?ps 400 600 800 1000 1200 1400 1600 100 200 300 400 500 600 700 800 all gain codes represented tpc 36. group delay vs. frequency by gain code, v s = 5 v, r l = 1 k w , maximum gain
rev. 0 ad8369 ?3 gm cells gain step selection digital 3db switched a ttenuator bias fixed gain inlo cmdc inhi 20pf 22pf oplo ophi v s v s v s /2 v s /2 100 100 ~ v s 2 ?0.7 figure 1. general block diagram, control and signal paths are differential theory of operation the ad8369 is a digitally controlled fully differential vga based on a variation of analog devices?patented x-amp archi- tecture (figure 1). it provides accurate gain control over a 45 db span with a constant ? db bandwidth of 600 mhz. the 3 db gain steps can be controlled by a user-selectable parallel- or serial-mode digital interface. a single pin (senb) selects the mode. the ad8369 is designed for optimal operation when used in a fully differential system, although single-ended operation is also possible. its nominal input and output impedances are 200 w . input attenuator and output 3 db step the ad8369 is comprised of a seven-stage r-2r ladder net- work (eight taps) and a selected gm stage followed by a fixed-gain differential amplifier. the ladder provides a total attenuation of 42 db in 6 db steps. the full signal is applied to the amplifier using the first tap; at the second tap, the signal is 6 db lower and so on. a further 3d b interpolating gain step is introduced at the output of the fixed gain amplifier, providing the full 45 db of gain span. fixed gain amplifier the fixed gain amplifier is driven by the tap point of the r-2r ladder network via the selected gm cell. the output stage is a complementary pair of current sources, loaded with internal 100 w resistors to ac ground which provides a 200 w differential out put impedance. the low frequency gain of the ad8369 can be approximated by the equation: v v in out l l n r r = + ? ? ? ? ? ? ? - () 06 200 200 1 2 15 . where r l is the external load resistor in ohms and n is the gain code; 0 is the minimum gain code and 15 is the maximum gain code. the external load, which is in parallel combination with the internal 200 w output resistor, affects the overall gain and peak output swing. note that the external load has no effect on the gain step size. input and output interfaces the dc working points of the differential input and output inter- faces of the ad8369 are internally biased. the inputs inhi and inlo are biased to a diode drop below v s /2 (~1.7 v for a 5 v positive supply) to meet isolation and headroom constraints, while the outputs ophi and oplo are centered on the supply midpoint, v s /2, to provide the maximum output swing. the internal v s /2 reference and the cmdc reference are buff- ered and decoupled to ground via internal capacitors. the input bias voltage, derived from this v s /2 reference, is brought frequency ?khz 100 10 pssr ?db 100 1000 90 80 70 60 50 40 30 20 10 0 10000 tpc 37. power supply rejection ratio, v s = 5 v, r l = 1 k w , maximum gain
rev. 0 ?4 ad8369 out to pin cmdc for decoupling to ground. an external capacitor from cmdc to comm of 0.01 m f or more is recommended to lower the input common-mode impedance of the ad8369 and improve single-ended operation. signals must be ac-coupled at the input, either via a pair of capacitors or a transformer. these may not be needed when the source has no dc path to ground, such as a saw filter. the output may need dc blocking capacitors when driving dc- grounded loads, but it can be directly coupled to an adc, provided that the common-mode levels are compatible. the input and output resistances form a high-pass filter in com- bination with any external ac-coupling capacitors that should be chosen to minimize signal roll-off at low frequencies. for example, using input-coupling capacitors of 0.1 m f, each driving a 100 w input node (200 w differential), the ? db high-pass corner frequency is at: 1 210 100 16 7 p ()() = khz it is important to note that the input and output resistances are subject to process variations of up to 20%. this will affect the high-pass corner frequencies and the overall gain when driven fr om, or lo ad ed b y, a fin ite i mpe da nc e (s ee th e reduc ing gain sensitivity to input and output impedance variation section). noise and distortion it is a common aspect of this style of vgas, however imple- mented, that the effective noise figure worsens as the gain is reduced. the ad8369 uses a fixed gain amplifier, having a certain invariant noise spectral density, preceded by an attenuator. thus, the noise figure increases simply by 6 db per tap point, from a starting point of 7 db at full gain. however, unlike voltage-controlled amplifiers that must neces- sarily invoke nonlinear elements in the signal path, the distortion in a step-gain amplifier can be very low and is essentially indepen- dent of the gain setting. note that the postamplifier 3 db step does not affect the noise performance, but it has some bearing on the output third-order intercept (oip3). see tpcs 3 and 9. offset control loop the ad8369 uses a control loop to null offsets at the input. if left uncorrected, these offsets, in conjunction with the gain of the ad8369, would reduce the available voltage swing at the output. the control loop samples the differential output volt- age error and feeds nulling currents back into the input stage. the nominal high-pass corner frequency of this loop is inter- nally set to 520 khz, but it is subject to process variations of up to 20%. this corner frequency can be reduced by adding an external capacitor from the filt pin to ground, in parallel to an internal 30 pf capacitor. for example, an external capaci- tor of 0.1 m f would lower the high-pass corner by a factor of 30/100,030, to approximately 156 hz. this frequency should be chosen to be at least one decade below the lowest compo- nent of interest in the input spectrum. digital control the gain of the ad8369 is controlled via a serial or parallel interface, as shown in figure 2. serial or parallel operation is selected via the senb pin. setting senb to a logic low (< v s /2) selects parallel operation, while a logic high on senb (> v s /2) s elects serial operation. the ad8369 has two control registers, the gain control register and the shift register. the gain control register is a latch that holds the data that sets the amplifier gain. the shift registers are composed of four flip-flops that accept the serial data stream. denb senb b a mux b a mux b a mux b a mux shift register a/ b shift register shift register shift register bit0 (data) bit1 (clock) bit2 bit3 gain control register (latch) to gain control section bit0 bit1 bit2 bit3 t/ h figure 2. digital interface block diagram in parallel operation, the 4-bit parallel data is placed on pins bit3 through bit0 and passed along to the gain control register via the mux. data is latched into the gain control register on the falling edge of the input to denb, subject to meeting the speci- fied setup and hold times. if this pin is held high (> v s /2), any changes in the parallel data will result in a change in the gain, after propagation delays. this is referred to as the transparent mode of operation. if denb is held low, the last 4-bit word in the gain control register will remain latched regardless of the signals at the data inputs. in serial operation, the bit0 pin is used for data input while the bit1 pin is the clock input. data is loaded into the serial shift registers on the rising edge of the clock when denb is low. given the required setup and hold times are observed, four rising edge transitions of the clock will fully load the shift register. on the rising edge of denb, the 4-bit word in the shift register is passed into the gain control register. while this pin is held high, the clock input to the shift registers is turned off. once denb is taken low, the shift register clock is again enabled and the last 4-bit word prior to enabling the clock will be latched into the gain control registers. this enables the loading of a new 4-bit gain control word without interruption of the signal path. only when denb goes high is data transferred from the shift registers to the gain control registers. if no connections are made to the digital control pins, internal 40 k w resistors pull these pins to levels that set the ad8369 to its minimum gain condition. at power-up or chip enable, if the ad8369 is in parallel mode and denb is held low, the gain control register will come up in an indeterminate state. to avoid this, denb should be held high with valid data present during power-up when operating in the parallel mode. in serial mode, the data in the gain control interface powers up with a random gain code independent of the denb pin. serial mode operation requires at least four clock cycles and the transition of denb from low to high for valid data to be present at the gain control register.
rev. 0 ad8369 ?5 0.1 f r l 0.1 f 0.1 f r l 0.1 f control interface 9 10 11 12 13 14 15 16 pwup vpos senb filt cmdc ophi inhi comm inlo denb comm bit0 bit1 bit2 bit3 ad8369 oplo 0.1 f 8 7 6 5 4 3 2 1 0.1 f 0.1 f 3v to 5.5v tc4-1w 50 tx line in v s figure 3. basic connections basic connections figure 3 shows the minimum connections required for basic operation of the ad8369. supply voltages of between +3 v and +5.5 v are permissible. the supply to the vpos pin should be decoupled with at least one low inductance surface-mount ceramic capacitor of 0.1 m f placed as close as possible to the device. more effective decoupling is provided by placing a 100 pf capacitor in parallel and including a 4.7 w resistor in series with the supply. attention should be paid to voltage drops. a ferrite bead is a better choice than the resistor where a smaller drop is required. input-output interface a broadband 50 w input termination can be achieved by using a 1:2 turns-ratio transformer, as shown in figure 3. this also can be used to convert a single-ended input signal to a balanced differential form at the inputs of the ad8369. as in all high frequency applications, the trace impedance should be maintained right up to the input pins by careful design of the pc board traces, as described in the pcb layout considerations section. reducing gain sensitivity to input and output impedance variation the lot-to-lot variations in gain mentioned previously can, in principle, be eliminated by adjustments to the source and load. define a term as a function of the input and output resistances of the ad8369 and the source and load resistances presented to it: rr rr source input output load = () = () a a for a 50 w source, = 0.25. then the load resistance for zero sensitivity to variations must be 800 w . put more simply: rrrr source load input output ()() = ()( ) = 200 2 in general, there is a loss factor, 1/(1+ ), at each interface so the overall gain reduction due to source and output loading is 40 log 10 (1 + ). in this case, the input and output loss factors are 0.8 (1.94 db) at each interface so the overall gain is reduced by 3.88 db. operation from a single-sided source while there are distinct benefits of driving the ad8369 with a well-balanced input, in terms of distortion and gain conform- ance at high frequencies, satisfactory operation will often be possible when a single-sided source is ac-coupled directly to pin inhi, and pin inlo is ac-grounded via a second capacitor. this mode of operation takes advantage of the good hf common-mode rejection of the input system. the capacitor values are, as always, selected to ensure adequate transmission at low frequencies. 0.1 f r l 0.1 f control interface source 9 10 11 12 13 14 15 16 pwup vpos senb filt cmdc ophi inhi comm inlo denb comm bit0 bit1 bit2 bit3 ad8369 oplo 0.1 f 0.1 f v s 8 7 6 5 4 3 2 1 0.1 f 50 0.1 f 0.1 f figure 4. single-ended-to-differential application example
rev. 0 ?6 ad8369 for example, suppose the input signal in figure 4 is a 140 mhz sinusoid from a ground-referenced 50 w source. the 0.1 m f coupling capacitors present a very low reactance at this frequency (11 m w ) so that essentially all of the ac voltage is delivered to the differential inputs of the ad8369. it will be apparent that, in addition to the use of adequate coupling capacitance, the external capacitor used to extend the low frequency range of the offset control loop, c filt , must also be large enough to prevent the offset control loop from attempting to track the ac signal fluctuations. interfacing to an adc the ad8369 can be used to effectively increase the dynamic range of an adc in a direct if sampling receiver application. figure 5 provides an example of an interface to an adc designed for an if of 70 mhz. it comprises a low-pass filter that attenu ates harmonics while providing an impedance transformation from 200 w to 1 k w . this impedance transformation allows the ad8369 to operate much below its peak output swing in the pass band, which significantly reduces distortion. 0.1 f control interface 9 10 11 12 13 14 15 16 pwup vpos senb filt cmdc ophi inhi comm inlo denb comm bit0 bit1 bit2 bit3 ad8369 oplo 0.1 f v s 8 7 6 5 4 3 2 1 0.1 f 0.1 f 0.1 f 6.8pf 15pf 1k 270nh 270nh adc figure 5. ad8369 to adc interface adc output frequency ?mhz 0 ?0 0 p out ?dbfs ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 510152 02530 70mhz ?1dbfs hd2 = ?3dbc hd3 = ?0dbc snr = 51db figure 6. single-tone 70 mhz, ? dbfs adc output frequency ?mhz 0 ?0 0 p out ?dbfs ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 510152 02530 ?2.5dbfs ?dbfs figure 7. two-tone, 70 mhz, 70.3 mhz, ? dbfs a high performance 14-bit adc, the ad6645, is used for illus- trative purposes and is sampling at 64 msps with a full-scale input of 2.2 v p-p. typically, an snr of 51 db and an sfdr of almost ?0 dbfs are realized by this configuration. figure 6 shows an fft of the ad8369 delivering a single tone at ? dbfs (that is, 2 v p-p) at the input of the adc with an hd2 of ?3 dbc and hd3 of ?0 dbc. figure 7 shows that the two-tone, third-order intermodulation distortion level is ?5.5 dbc. pcb layout considerations each input and output pin of the ad8369 presents 100 w rela tive to their respective ac grounds. to ensure that signal integrity is not seriously impaired by the printed circuit board, the relevant connection traces should provide a characteristic impedance of 100 w to the ground plane. this can be achieved through proper layout. figure 8 shows the cross section of a pc board and table ii shows the dimensions that will provide a 100 w line impedance. table ii. dimensions required for 100 w characteristic impedance microstrip line in fr-4 r ( fr-4) 4.6 w22 mils h53 mils t 2.1 mils
rev. 0 ad8369 ?7 31012 49 8 7 611 5 2 13 1 15 22 24 16 21 20 19 18 23 17 14 25 d-sub 25 pin male 1nf r l 1nf 1nf 1nf 9 10 11 12 13 14 15 16 pwup vpos senb filt cmdc ophi inhi comm inlo denb comm bit0 bit1 bit2 bit3 ad8369 oplo c7 0.1 f 8 7 6 5 4 3 2 1 c5 0.1 f in j1 in j2 tc4-1w r1 0 t1 r2 0 c4 c3 out j6 out j7 tc4-1w r12 0 r11 0 t2 c8 1nf r5 open v s pwup sw 2 pwdn 2 1 3 c8 1nf r6 0 r7 0 r8 0 r9 0 r10 0 v s v s a b 1 14 sw3 sw4 r3 1k r13 1k latch clock data r4 1k c9 open 3467 10 912 25 8 11 28 4 sw1 1 2 3 c1 c2 figure 9. evaluation board schematic key considerations when laying out an rf trace with a controlled impedance include: space the ground plane to either side of the signal trace at least 3 line-widths away to ensure that a microstrip (vertical dielec- tric) line is formed, rather than a coplanar (lateral dielectric) waveguide. ensure that the width of the microstrip line is constant and that there are as few discontinuations (component pads, etc.) as possible along the length of the line. width variations cause impedance discontinuities in the line and may result in unwanted reflections. do not use silkscreen over the signal line; this will alter the line impedance. keep the length of the input and output connection lines as short as possible. 3w 3w w h t r figure 8. cross-sectional view of a pc board the ad8369 contains both digital and analog sections. care should be taken to ensure that the digital and analog sections are adequately isolated on the pc board. the use of separate ground planes for each section connected at only one point via a ferrite bead inductor will ensure that the digital pulses do not adversely affect the analog section of the ad8369.
rev. 0 ?8 ad8369 evaluation board the evaluation board allows for quick testing of the ad8369 using standard 50 w test equipment. the schematic is shown in figure 9. transformers t1 and t2 are used to transform 50 w source and load impedances to the desired 200 w reference level. this allows for broadband operation of the device without the need to pay close attention to impedance matching (see table iii). figure 10. evaluation board layout evaluation board software the evaluation board comes with the ad8369 control software that allows for serial gain control from most computers. the evaluation board is connected via a cable to the parallel port of the computer. by simply adjusting the slider bar in the control software, the gain code is automatically updated to the ad8369. on some older pcs, it may be necessary to use 5 k w pull-up resistors to vpos on data, clock, and latch depending upon the capabilities of the port transceiver. it is necessary to set sw3 on the evaluation board to ?er?for the control software to function normally. a screen shot of the evaluation software interface is shown in figure 11. figure 11. evaluation software interface
rev. 0 ad8369 ?9 table iii. ad8369 evaluation board configuration options component function default condition vpos, gnd supply and ground vector pins not applicable sw1 data enable: set to position a when in serial mode of operation, set to position b not applicable when in parallel mode of operation. sw2 device enable: when in the pwdn position, the pwup pin will be connected to not applicable ground and the ad8369 will be disabled. the device is enabled when the switch is in the pwup position, connecting the pwup pin to vpos. sw3, r5 serial/parallel selection. the device will respond to serial control inputs from not applicable connector p1 when the switch is in the ser position. parallel operation is achieved r5 = open (size 0603) when in the par position. device can be hardwired for parallel mode of operation by placing the 0 w resistor in position r5. sw4 parallel interface control. used to hardwire bit0 through bit3 to the desired gain not a pplicable code when in parallel mode of operation. the switch functions as a hexadecimal to binary encoder (gain code 0 = 0000, gain code 15 = 1111). j1, j2, j6, j7 input and output signal connectors. these sma connectors provide a convenient not applicable way to interface the evaluation board with 50 w test equipment. c1, c2, c3, c4 ac-coupling capacitors. provides ac-coupling of the input and output signals. c1, c2, c3, c4 = 1 nf (size 0603) t1, t2 impedance transformers. used to transform the 200 w input and output t1, t2 = tc4-1w impedance to 50 w . (minicircuits) r1, r2, r11, r12 single-ended or differential. r2 and r11 are used to ground the center tap of r1, r2, r11, r12 the secondary windings on transformers t1 and t2. r1 and r12 should be used = 0 w (size 0603) to ground j2 and j7 when used in single-ended applications. r1 and r12 should be removed for differential operation. r6, r7, r8, r9, r10 control interface resistors. simple series resistors for each control interface signal. r6, r7, r8, r9, r10 = 0 w (size 0603) c 5, c 6, c8 power supply decoupling. nominal supply decoupling consists of a 0.1 m f capacitor c5 = 0.1 m f (size 0603) to ground followed by a 1 nf capacitor to ground positioned as close to the device c6 = c8 = 1 nf as possible. c8 provides additional decoupling of the input common-mode voltage. (size 0603) c7 high-pass filter capacitor. used to set high-pass corner frequency of output. c7 = 0.1 m f (size 0603) c9 clock filter capacitor. may be required with some printer ports to minimize overshoot. c9 = open (size 0603) the clock waveform may be smoothed using a simple filter network established by r7 and c9. some experimentation may be necessary to determine optimum values.
rev. 0 ?0 ad8369 appendix characterization equipment two sets of automated characterization equipment were used to obtain the majority of the information contained in this data sheet. an agilent n4441a balanced measurement system was used to obtain the gain, phase, group delay, reverse isolation, cmrr, and s-parameter information. except for the s-parameter informa- tion, t-attenuator pads were used to match the 50 w impedance of the ports of this instrument to the ad8369. an anritsu ms4623b ?corpion?vector network analyzer was used to obtain nonlinear measurements imd 3 , ip3, and p1db through matching baluns and attenuator networks. definitions of selected parameters common-mode rejection ratio (tpc 14) has been defined for this characterization effort as: differential mode forwardgain common mode forwardgain - - , , where the numerator is the gain into a differential load at the output due to a differential source at the input and the denomina- tor is the gain into a common-mode load at the output due to a common-mode source at the input. in terms of mixed-mode s-parameters, this equates to: sdd scc 21 21 reverse isolation (tpc 17) is defined as sdd12. more information on mixed-mode s-parameters can be obtained in the a reference by bockelman, d.e. and eisenstadt, w.r., combined differential and common-mode scattering parameters: theory and simulation . ieee transactions on microwave theory and techniques, v 43, n 7, 1530 (july 1995). composite waveform assumption the nonlinear two-tone measurements made for this data sheet, i.e., imd 3 and ip3, are based on the assumption of a fixed value composite waveform at the output, generally 1 v p-p. the fre- quencies of interest dictate the use of rf test equipment and because this equipment is generally not designed to work in units of volts, but rather watts and dbm, an assumption was made to simplify equipment setup and operation. two sinusoidal tones can be represented as: vft 11 2 = () sin p vft 22 2 = () sin p the average voltage of one tone is: 11 2 0 1 2 t vdt t () = where t is the period of the waveform. the average voltage of the two-tone composite signal is: 1 1 0 12 2 t vvdt t + () = so each tone contributes 1/ 2 to the average composite ampli- tude in terms of voltage. it can be shown that the average power of this composite waveform is two times greater, or 3db, than that of the single tone. this principle can be used to set correct input amplitudes from generators scaled in dbm and is correct if the two tones are of equal amplitude and are not farther than 1 percent apart in frequency. r l r1 10nf control interface 9 10 11 12 13 14 15 16 pwup vpos senb filt cmdc ophi inhi comm inlo denb comm bit0 bit1 bit2 bit3 ad8369 oplo 0.1 f 8 7 6 5 4 3 2 1 v s port1 port2 port3 port4 a gilent n4441a (all ports 50 ) r1 10nf r2 r2 10nf 10nf 69.8 69.8 69.8 69.8 10nf 0.1 f 1nf r l = 200 differential: r1 = 69.8 , r2 = 69.8 r l = 1000 differential: r1 = 475 , r2 = 52.3 figure 12. balanced measurement system setup
rev. 0 ad8369 ?1 r l control interface 9 10 11 12 13 14 15 16 pwup vpos senb filt cmdc ophi inhi comm inlo denb comm bit0 bit1 bit2 bit3 ad8369 oplo 0.1 f 8 7 6 5 4 3 2 1 v s source output receiver input anritsu ms4623b vna 10nf 10nf 10nf 0.1 f 1nf mini-circuits tc4-1w mini-circuits tc4-1w 10nf 10nf figure 13. vector network analyzer setup (200 w ) control interface 9 10 11 12 13 14 15 16 pwup vpos senb filt cmdc ophi inhi comm inlo denb comm bit0 bit1 bit2 bit3 ad8369 oplo 0.1 f 8 7 6 5 4 3 2 1 v s source output receiver input anritsu ms4623b vna 10nf 10nf 10nf 0.1 f 1nf mini-circuits tc4-1w mini-circuits tc4-1w 10nf 10nf 604 604 237 4120 figure 14. vector network analyzer setup (1 k w )
rev. 0 ?2 ad8369 9 10 11 12 13 14 15 16 pwup vpos senb filt cmdc ophi inhi comm inlo denb comm bit0 bit1 bit2 bit3 ad8369 oplo 0.1 f 8 7 6 5 4 3 2 1 v s 5.0v 100nf 100nf 1nf 0.1 f 1nf 100nf 100nf r l v s 113 113 162 162 191 191 100nf 100nf ad8351 100nf 100nf macom etc1-1-13 tek p6248 diff probe tek 1103 probe power supply r & s fsea30 spectrum analyzer ?9db ?2db lpf rf out r & s smt-03 signal generator figure 15. harmonic distortion setup r l 9 10 11 12 13 14 15 16 pwup vpos senb filt cmdc ophi inhi comm inlo denb comm bit0 bit1 bit2 bit3 ad8369 oplo 0.1 f 8 7 6 5 4 3 2 1 v s 5.0v mini-circuits tc4-1w 10nf 1nf 0.1 f 1nf 10nf v s 10nf 604 604 237 4120 10nf r & s smt-03 signal generator mini-circuits tc4-1w ?4dbm at 70mhz picosecond pulse labs pulse generator 50 rf out a gilent infinium dso figure 16. gain step response setup
rev. 0 ad8369 ?3 9 10 11 12 13 14 15 16 pwup vpos senb filt cmdc ophi inhi comm inlo denb comm bit0 bit1 bit2 bit3 ad8369 oplo 0.1 f 8 7 6 5 4 3 2 1 v s 5.0v 100nf 2 f10 f 1nf 100nf 1000 v s tek p6248 diff probe tek 1103 probe power supply tek tds 5104 dso 10nf 10nf 0 r & s smt-03 signal generator 0 rf out mini-circuits tc4-1w pulse in splitter a gilent 8112a pulse generator c2 figure 17. pulse response setup r l 9 10 11 12 13 14 15 16 pwup vpos senb filt cmdc ophi inhi comm inlo denb comm bit0 bit1 bit2 bit3 ad8369 oplo 0.1 f 8 7 6 5 4 3 2 1 v s 5.0v a gilent infinium dso mini-circuits tc4-1w 10nf 1nf 0.1 f 1nf 10nf v s 10nf 604 604 237 4120 10nf r & s smt-03 signal generator mini-circuits tc4-1w ?0dbm at 10mhz picosecond pulse labs pulse generator 50 rf out figure 18. overdrive response setup
rev. 0 c03029??1/02(0) printed in u.s.a. ?4 ad8369 outline dimensions 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab

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