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february 2015 docid023944 rev 4 1/34 1 AN4206 application note getting started with stm32f3 series hardware development introduction this application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, clock management, reset control, boot mode settings and debug management. it explains how to use the stm32f3xx product lines and describes the minimum hardware resources required to develop an application based on stm32f3 series. the stm32f3x8 line devices with their disabled embedded regulator share many features/peripherals with the stm32f301, stm32f302, stm32f303 and stm32f334 line devices, which embedded regulator is enabled, with some differences. a summary of the differences between the product lines is provided in section 6 . a detailed reference design schematic is also c ontained in this document with descriptions of the main components, interfaces and modes. www.st.com
contents AN4206 2/34 docid023944 rev 4 contents 1 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 independent analog power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1.2 sigma delta supply voltages (only on f37x) . . . . . . . . . . . . . . . . . . . . . 11 1.1.3 battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.4 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2 reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.2 power on reset (por) / power down reset (pdr) . . . . . . . . . . . . . . . . . 14 1.2.3 programmable voltage detector (pvd) . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 high speed external clock signal (hse) osc clock . . . . . . . . . . . . . . . . . 16 2.2 lse clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 hsi clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 lsi clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 swj debug port (serial wire and jtag) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.1 swj debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3.2 flexible swj-dp pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3.3 internal pull-up and pull-down resistors on jtag pins . . . . . . . . . . . . . . 22 4.3.4 swj debug port connection with standard jtag connector . . . . . . . . . 23 5 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 ground and power supply (v ss , v dd, v ssa , v dda, v sssd , v ddsd ) . . . . . 24
docid023944 rev 4 3/34 AN4206 contents 3 5.4 decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5 other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6 unused i/os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 stm32f3x8 vs stm32f30x/f373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.1 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.3 boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.4 swj interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.6 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2 component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
list of tables AN4206 4/34 docid023944 rev 4 list of tables table 1. boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 2. debug port pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 3. swj i/o pin availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 4. stm32f30x/f373 versus stm32f3x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 6. optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
docid023944 rev 4 5/34 AN4206 list of figures 5 list of figures figure 1. stm32f303/302xb/c power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. stm32f302xd/e/stm32f303xd/e power supply sche me . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. stm32f373 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. stm32f334/303/302/301x6/8 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. schottky diode connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. power on reset/power down rese t waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. pvd thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. hse/ lse clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. host-to-board connectio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. jtag connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. typical layout for v dd /v ss pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 13. stm32f30x microcontroller reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 14. stm32f373 microcontroller reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
power supplies AN4206 6/34 docid023944 rev 4 1 power supplies 1.1 power supply schemes there are a variety of power supply schemes: ? v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. ? provided externally through v dd pins. ? v dda = 2.0 to 3.6 v: external analog power supply for adc/dac, comparators, reset blocks, rcs and pll (in all stm32f3 seri es devices except stm32f373 line, the minimum voltage to be applied to v dda is 2.4 v when the opamp and dac are used. in stm32f373, minimum voltage to be applied to v dda is 2.4 v when the adc and dac are used). ? the v dda voltage level must always be greater than or equal to the v dd voltage level and must be provided first. ? v bat = 1.65 to 3.6 v: power supply for rt c, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. ? v ddsd12 = 2.2 to 3.6 v: external power supply for sdadc1/2, pb2, pb10, and pe7 to pe15 i/o pins (i/o pin ground is internally connected to vss). v ddsd12 must always be kept lower or equal to v dda . if v ddsd12 is not used, it must be connected to v dda . ? v ddsd3 = 2.2 to 3.6 v: external power supply for sdadc3, pb14 to pb15 and pd8 to pd15 i/o pins (i/o pin ground is internally con nected to vss). v ddsd3 must always be kept lower or equal to v dda . if v ddsd3 is not used, it must be connected to v dda . note: v ddsd12 and v ddsd3 are available on stm32f373 only.
docid023944 rev 4 7/34 AN4206 power supplies 33 figure 1. stm32f303/302xb/c power supply scheme 069 3r zhuvzl wfk 9 %$7 *3 ,2 v 287 ,1 .huqhoorjlf &38 'ljlwdo 0hprulhv %dfnxsflufxlwu\ /6(57& %dfnxsuhjlvwhuv :dnhxsorjlf q) ? ?) 9 5hjxodwru 9 ''$ 9 66$ $'& '$& /hyhovkliwhu ,2 /rjlf 9 '' q) ?) 9 ''$ 9 5() 9 5() 9 '' 9 66 ? ? 9 5() q) ?) ? !nalog2#s0,, comparators/0!-0
power supplies AN4206 8/34 docid023944 rev 4 figure 2. stm32f302xd/e/stm32f303xd/e power supply scheme 069 /hyhovkliwhu $qdorj5&v 3//frpsdudwruv23$03 3rzhu vzlwfk $'&'$& .huqhoorjlf &38 gljlwdo phprulhv ,2orjlf %dfnxsflufxlwu\ /6(57& :dnhxsorjlf %dfnxsuhjlvwhuv 9 %$7 9 *3,2v 9 '' 287 ,1 5hjxodwru [9 '' [9 66 9 ''$ 9 ''$ 9 5() 9 5() 9 66$ [q) [?) q) ?) q) ?) 9 5()
docid023944 rev 4 9/34 AN4206 power supplies 33 figure 3. stm32f373 power supply scheme 069 $qdorj 5&v3//&203 3r zhu vzl wfk 9 %$7 *3 ,2 v 287 ,1 .huqhoorjlf &38 'ljlwdo 0hprulhv %dfnxsflufxlwu\ /6(57& %dfnxsuhjlvwhuv :dnhxsorjlf ?q) ? ?) 9 5hjxodwru 9 ''$ 9 66$ $'& '$& /hyhovkliwhu ,2 /rjlf 9 '' q) ?) 9 ''$ 9 5() 9 5() 9 '' 9 66 ? ? 6ljpd 'howd $'&v q) ?) 9''6' 9''6' 9''6' 9''6' 9666' q) ?) 95()6' 95()6' q) ?) 95()6' *3 ,2 v 287 ,1 /hyhovkliwhu ,2 /rjlf *3 ,2 v 287 ,1 /hyhovkliwhu ,2 /rjlf q) ?) 9 5() 5() 9 9 #9 '' #9''6' #9''6'
power supplies AN4206 10/34 docid023944 rev 4 figure 4. stm32f334/303/302/301x6/8 power supply scheme 1.1.1 independent analog power supply to improve conversion accuracy and to extend the supply flexibility, the analog domain has an independent power supply which can be separately filtered and shielded from noise on the pcb. ? the adc and dac voltage supply input is available on a separate v dda pin. ? an isolated supply ground connecti on is provided on pin vssa. the v dda supply can be equal to or higher than v dd . this allows v dd to stay low while still providing the full performance for the analog blocks. when a single supply is used, v dda can be externally connected to v dd , through the external filtering circuit in order to ensure a noise free v dda . when v dda is different from v dd , v dda must be always higher or equal to v dd . to keep safe potential difference between v dda and v dd during power-up/power-down, an external schottky diode may be used between v dd and v dda . refer to the dat asheet for the maximum allowed difference. 069 3r zhuvzl wfk 9 %$7 *3 ,2 v 287 ,1 .huqhoorjlf &38 'ljlwdo 0hprulhv %dfnxsflufxlwu\ /6(57& %dfnxsuhjlvwhuv :dnhxsorjlf q) ? ?) 9 5hjxodwru 9 ''$ 9 66$ $'& '$& /hyhovkliwhu ,2 /rjlf 9 '' q) ?) 9 ''$ 9 5() 9 5() 9 '' 9 66 ? ? 9 5() q) ?) ? !nalog2#s0,, comparators/0!-0
docid023944 rev 4 11/34 AN4206 power supplies 33 figure 5. schottky diode connection 1.1.2 sigma delta supply voltages (only on f37x) to improve sigma delta adc (sdadc) peripherals performance the device implements two independent power supplies used to power sdadc peripherals. there are two power supply pins with common ground pin (v ddsd12 , v ddsd3 , v sssd ). those power supply sources also defines voltage levels on digital gpio pins which are sharing sdadc analog inputs for given sdadc peripheral. refer to device datasheet which gpio pins are powered from v ddsd12 and which from v ddsd3 . sigma delta power supplies must be always less or equal to the analog supply: v ddsdx < v dda but they can be lower or higher than v dd . if no sdadc is used in application then v ddsdx must be connected externally to v dd . v sssd must be always connected to v ss . there are some next important restrictions to v ddsd12 and v ddsd3 with relation to the reference voltage used for the sdadcs: ? if the v refsd+ pin is selected as the external reference voltage for the sdadcs: ? if sdadc1 or sdadc2 are enabled in the pwr controller (ensd1, ensd2 bits) then: v ddsd12 > v refsd+ , v ddsd3 > v refsd+ ? if sdadc1 and sdadc2 are disabled in the pwr controller then: v ddsd3 > v vrefsd+ ? if the v ddsdx power supply is selected as the reference voltage for the sdadcs: ? if sdadc1 or sdadc2 are enabled in pwr controller (ensd1, ensd2 bits) then: v ddsd12 = v ddsd3 ? if sdadc1 and sdadc2 are disabled and sd adc3 is enabled in the pwr controller (ensd1, ensd2, ensd3 bits) then: v ddsd12 <= v ddsd3 . 1.1.3 battery backup to retain the content of the backup registers when v dd is turned off, the v bat pin can be connected to an optional standby voltage supplied by a battery or another source. the v bat pin also powers the rtc unit, allowing the rtc to operate even when the main digital supply (v dd ) is turned off. 069 9'' 9''$ 9 '' 9 ''$ 6fkrwwn\glrgh
power supplies AN4206 12/34 docid023944 rev 4 the switch to the v bat supply is controlled by the power down reset (pdr) circuitry embedded in the reset block. if no external battery is used in the applicat ion, it is highly recommended to connect v bat externally to v dd . 1.1.4 voltage regulator the voltage regulator is always enabled after reset. it works in three different modes depending on the application modes: ? run mode: the regulator supplies full power to the 1.8 v domain (core, memories and digital peripherals) ? stop mode: the regulator supplies low power to the 1.8 v domain, preserving the contents of the registers and sram. in stop mode, the voltage regulator can be configured in low power mode in order to further reduce the consumption. ? standby mode: the regulator is powered off. the contents of the registers and sram are lost except for the standby circuitry and the backup domain. this includes the following features which can be selected by programming individual control bits: ? independent watchdog (iwdg): the iwdg is started by writing to its key register or by a hardware option. once started it cannot be stopped except by a reset. ? real-time clock (rtc): configured by the rtcen bit in the backup domain control register (rcc_bdcr). ? internal rc oscillato r (lsi): configured by the ls ion bit in the control/status register (rcc_csr). ? external 32.768 khz oscilla tor (lse): configured by th e lseon bit in the backup domain control register (rcc_bdcr).
docid023944 rev 4 13/34 AN4206 power supplies 33 1.2 reset and power supply supervisor 1.2.1 reset there are three types of reset, defined as: system reset, power reset and backup domain reset. system reset a system reset sets all registers to their rese t values, except the reset flags in the clock controller csr register and the registers in th e backup domain. a system reset is generated when one of the following events occurs: 1. a low level on the nrst pin (external reset). 2. system window watchdog event (wwdg reset). 3. independent watchdog event (iwdg reset). 4. a software reset (sw reset). 5. low-power management reset. 6. option byte loader reset. 7. power reset the reset source can be identified by checking the reset flags in the control/status register, rcc_csr). the reset service routine vector is fixed at address 0x0000_0004 in the memory map. the system reset signal provided to the device is output on the nrst pin. the pulse generator guarantees a minimum reset pulse duration of 20 s for each in ternal reset source. in the case of an external reset, t he reset pulse is generated while the nrst pin is asserted low. figure 6. simplified diagram of the reset circuit for more details, please refer to the stm32f3xx reference manuals (rm0316, rm0313, rm0365 and rm0366). .234 2 05 6 $$ 77$'reset )7$' reset 0ulse generator 0owerreset %xternal reset min?s 3ystemreset &ilter 3oftwarereset ,ow powermanagementreset /ptionbyteloaderreset -36
power supplies AN4206 14/34 docid023944 rev 4 power reset a power reset is generated when one of the following events occurs: 1. power-on/power-down reset (por/pdr reset) 2. when exiting standby mode backup domain reset the backup domain has two specific resets that affect only the backup domain. a backup domain reset is generated when one of the following events occurs: 1. software reset, triggered by setting the bdrst bit in the backup domain control register (rcc_bdcr). 2. v dd or v bat power on, if both supplies have previously been powered off. 1.2.2 power on reset (por ) / power down reset (pdr) the device has an integrated power-on reset (por) and power-down reset (pdr) circuits which are always active and ensure pr oper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. ? the por monitors only the v dd supply voltage. during the startup phase v dda must arrive first and be greater than or equal to v dd. ? the pdr monitors both the v dd and v dda supply voltages. however, the v dda power supply supervisor can be disabled (by programming a dedicated option bit v dda_monitor ) to reduce the power consumption if the application design ensures that v dda is higher than or equal to v dd . for more details on the power on / power down reset threshold, refe r to the electrical characteristics section in the datasheet. figure 7. power on reset/power down reset waveform 069 ''''$ 5hvhw 325 3'5 p9 k\vwhuhvlv 7hpsrul]dwlrq 5677(032 99 w
docid023944 rev 4 15/34 AN4206 power supplies 33 1.2.3 programmable volt age detector (pvd) you can use the pvd to monitor the v dd power supply by comparing it to a threshold selected by the pls[2:0] bits in the power control register (pwr_cr). the pvd is enabled by setting the pvde bit. a pvdo flag is available, in the power control/ status register (pwr_csr), to indicate if v dd is higher or lower than the pvd threshold. ? this event is internally connected to the exti line16 and can generate an interrupt if enabled through the exti registers. ? the pvd output interrupt can be generated when v dd drops below the pvd threshold and/or when v dd rises above the pvd threshold depending on exti line16 rising/falling edge configurat ion. as an example the se rvice routine could perform emergency shutdown tasks. figure 8. pvd thresholds '' 39'wkuhvkrog 39'rxwsxw p9 k\vwhuhvlv 069 9
clocks AN4206 16/34 docid023944 rev 4 2 clocks three different clock sour ces can be used to drive the system clock (sysclk): ? hsi 8 mhz rc oscillator clock (hig h-speed internal clock signal) ? hse oscillator clock (high-sp eed external clock signal) ? pll clock the devices have other secondary clock sources: ? 40 khz low-speed internal rc (lsi rc) th at drives the independent watchdog and, optionally, the rtc used for auto-wakeup from the stop/standby modes. ? 32.768 khz low-speed external crystal (lse crystal) that optionally drives the real-time clock (rtcclk) each clock source can be switched on or off independently when it is not used, to optimize the power consumption. refer to the stm32f3xx reference manuals (rm0316, rm0313, rm0364, rm0365 and rm0366) for a description of the clock tree. 2.1 high speed external cl ock signal (hse) osc clock the high speed external clock signal can be generated from two possible clock sources: ? hse external crystal/ceramic resonator ? hse user external clock the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. the loading capacitance values must be adjust ed according to the selected oscillator. figure 9. hse/ lse clock sources clock source hardware configuration external clock crystal/ceramic resonators osc_out external source gpio osc_in osc_in osc_out load capacitors c l2 c l1
docid023944 rev 4 17/34 AN4206 clocks 33 external crystal/ceramic resonator (hse crystal) the 4 to 32 mhz external oscillator has the adva ntage of producing a ve ry accurate rate on the main clock. re fer to the electrical characteristic s section of the datasheet for more details about the associated hardware configuration. the hserdy flag in the clock control register (rcc_cr) indicates if the hse oscillator is stable or not. at startup, the clock is not re leased until this bit is set by hardware. an interrupt can be generated if enabled in the clock interrup t register (rcc_cir). the hse crystal can be switched on and off using the hseon bit in the clock control register (rcc_cr). external source (hse bypass) in this mode, an external cloc k source must be provided. it can have a frequency of up to 32 mhz. you select th is mode by setting the hsebyp and hseon bits in the clock control register (rcc_cr) . the external clock signal (square, sinus or triangle) with ~40-60% duty cycle depending on the frequency (refer to the datasheet) has to drive the osc_in pin while the osc_out pin can be used a gpio. see figure 9 . 2.2 lse clock the lse crystal is a 32.768 khz low speed external crystal or ceramic resonator. it has the advantage of providing a low-power but highly accurate clock source to the real-time clock peripheral (rtc) for clock/calendar or other timing functions. the lse crystal is switched on and off using the lseon bit in backup domain control register (rcc_bdcr). the crys tal oscillator driving strength can be changed at runtime using the lsedrv[1:0] bits in the backup domain control register (rcc_bdcr) to obtain the best compromise between robustness and short start-up time on the one hand and low power consumption on the other. the lserdy flag in the backup domain cont rol register (rcc_bdcr) indicates whether the lse crystal is stable or not. at startup, the lse crystal output clock signal is not released until this bit is set by hardware. an interrupt can be generated if enabled in the clock interrupt regist er (rcc_cir). external source (lse bypass) in this mode, an external cloc k source must be provided. it can have a frequency of up to 1 mhz. you select this mode by setting the lsebyp and lseon bits in the backup domain control register (rcc_bdcr). the external cl ock signal (square, sinus or triangle) with ~50% duty cycle has to drive the osc32_in pi n while the osc32_out pin can be used as gpio. see figure 9 . 2.3 hsi clock the hsi clock signal is genera ted from an internal 8 mhz rc oscillator and can be used directly as a system clock or divided by 2 to be used as pll input. the hsi rc oscillator has the advantage of providing a clock source at low cost (no external components). it also has a faster startup time than the hse crystal oscillator however, ev en with calibration, the frequency is less accurate th an an external crystal osc illator or ceramic resonator.
clocks AN4206 18/34 docid023944 rev 4 calibration rc oscillator frequencies can vary from one chip to another due to m anufacturing process variations, this is why each device is fact ory calibrated by st for 1% accuracy at t a = 25 c. furthermore, it is possible to route the hsi clock to the mco mu ltiplexer. the clock can then be the input to timer 16 in all stm32f3 series devices (except the stm32f373 line where the clock is the input to timer 14) to a llow the user to calib rate the oscillator. 2.4 lsi clock the lsi rc acts as an low-power clock source that can be kept running in stop and standby mode for the independent watchdog (iwdg) and rtc. the clock frequency is around 40 khz (between 30 khz and 60 khz). for more details, refer to the electrical characteristics sectio n of the datasheets. 2.5 clock securi ty system (css) the clock security system can be activated by software. in this case, the clock detector is enabled after the hse oscillator startup delay, a nd disabled when this oscillator is stopped. ? if a failure is detected on the hse oscilla tor clock, the oscillator is automatically disabled. ? a clock failure event is sent to the break inputs of: ? - tim1/8/15/16/17 in the stm32f303xb/c and stm32f358 devices. ? - tim1/8/20/15/16/17 in the stm32f303xd/e and stm32f398 devices. ? - tim1/15/16/17 in the stm32f301/302/303x6/8, stm32f302xb/c/d/e, stm32f334, stm323f318 and stm32f328 devices. ? an interrupt is generated to inform the software about the failure (clock security system interrupt cssi), allowing the mcu to perform recovery operations. ? cssi is linked to the cortex ? -m4 nmi (non-maskable inte rrupt) exception vector. ? if the hse oscillator is used directly or indi rectly as the system clock (indirectly means that it is used as the pll input clock, and the pll clock is used as the system clock), a detected failure causes a switch of the system clock to the hsi oscillator and the disabling of the external hse oscillator. if the hse oscillato r clock (divided or not) is the clock entry of the pll that is being used as a system clock when the failure occurs, the pll is disabled too. for details, see the stm32f3 reference manuals (rm0316, rm0313, rm0364, rm0365 and rm0366) available from stmicroelectronics website www.st.com .
docid023944 rev 4 19/34 AN4206 boot configuration 33 3 boot configuration in the stm32f3xx, three different boot modes can be selected through the boot0 pin and nboot1 option bit, as shown in table 1 . the values on both boot0 pin and nboot1 bit are latched on the 4th rising edge of sysclk after a reset. the user must set nboo t1 and boot0 to sele ct the required boot mode. the boot0 pin and nboot1 bit are also re-sampled when exiting from standby mode. consequently they must be kept in the required boot mode configuration in standby mode. after the startup delay has elapsed, the cpu fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004. depending on the selected boot mode, main flash memory, system memory or sram is accessible as follows: ? boot from main flash memory: the main flash memory is aliased in the boot memory space (0x0000 0000), but is still access ible from its original memory space (0x0800 0000). in other words, the flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000. ? boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but is still accessible from its original memory space (0x 1fff ec00 ). ? boot from embedded sram: the sram is aliased in the boot memory space (0x0000 0000), but is still accessible from its original memory space (0x2000 0000). note: in the stm32f3 series devices embedding a ccm ram is not possible to boot from the ccm sram mapped at 0x1000 0000. the embedded boot loader is located in the system memory, programmed by st during production. it is used to reprogram the flash memory using one of the following interfaces: ? usart1(pa9/pa10), usart2(pd5/pd6) or usb(pa11/pa12) on stm32f302/303xb/c devices, ? usart1(pa9/pa10), usart2(pa2/pa3) or usb(pa11/pa12) on stm32f301/302x6/8 and stm32f302/303xd/e devices, ? usart1 (pa9/pa10), usart2 (pa2/pa3), i2c1 (pb6/pb7) on stm32f303x6/8 and stm32f334 devices. ? usart1 (pa9/pa10), usart2 (pa2/pa3), i2c1 (pb6/pb7), i2 c3 (pa8/pb5) on stm32f398 and f318 devices. for additional information, refer to application note an2606. table 1. boot modes boot mode selection boot mode aliasing boot1 (1) 1. the boot1 value is the opposite of the nboot1 option bit. boot0 x 0 main flash memory main flash memory is selected as boot space 0 1 system memory system memory is selected as boot space 1 1 embedded sram embedded sram is selected as boot space
debug management AN4206 20/34 docid023944 rev 4 4 debug management 4.1 introduction the host/target interface is the hardware equipment that connects the host to the application board. this interface is made of three components: a hardware debug tool, a jtag or swd connector and a cable connecting the host to the debug tool. figure 10 shows the connection of the host to the stm32f3xx evaluation board. figure 10. host-to-board connection 4.2 swj debug port ( serial wire and jtag) the stm32f3 series core integrates the serial wire / jtag debug port (swj-dp). it is an arm ? standard coresight? debug port that combines a jtag-dp (5-pin) interface and a sw-dp (2-pin) interface. ? the jtag debug port (jtag-dp) provides a 5-pin standard jtag interface to the ahp- ap port ? the serial wire debug port (sw-dp) provides a 2-pin (clock + data) interface to the ahp-ap port in the swj-dp, the two jtag pins of the sw-dp are multiplexed with some of the five jtag pins of the jtag-dp. 4.3 pinout and debug port pins the stm32f3 series mcu is offered in vari ous packages with different numbers of available pins. as a result, some functionality related to the pi n availability ma y differ from one package to another. (ydoxdwlrqerdug +rvw3& 3rzhuvxsso\ 6:'frqqhfwru 'hexjwrro dlf
docid023944 rev 4 21/34 AN4206 debug management 33 4.3.1 swj debug port pins five pins are used as outputs for the swj-dp as alternate functions of general-purpose i/os (gpios). these pins, shown in table 2 , are available on all packages. 4.3.2 flexible swj-dp pin assignment after reset (sysresetn or por esetn), all five pins used fo r the swj-dp are assigned as dedicated pins immediately usable by the debu gger host (note that the trace outputs are not assigned except if explicitly programmed by the debugger host). however, some of the jtag pins shown in table 3 can be configured to an alternate function through the gpiox_afrx registers. table 3 shows the different possibilit ies to free some pins to be configured alternate functions. for more details, see the corresponding st m32f3xx reference manual (rm0316, rm0313, rm0365 and rm0366) available from the stmicroelectronics website www.st.com . table 2. debug port pin assignment swj-dp pin name jtag debug port sw debug port pin assignment type description type debug assignment jtms/swdio i jtag test mode selection i/o serial wire data input/output pa13 jtck/swclk i jtag test clock i serial wire clock pa14 jtdi i jtag test data input - - pa15 jtdo/traceswo o jtag test data output - traceswo if async trace is enabled pb3 jntrst i jtag test nreset - - pb4 table 3. swj i/o pin availability available debug ports swj i/o pin assigned pa13 / jtms/ swdio pa14 / jtck/ swclk pa15 / jtdi pb3 / jtdo pb4/ jntrst full swj (jtag-dp + sw-dp) - reset state x x x x x full swj (jtag-dp + sw-dp) but without jntrst xxxx jtag-dp disabled and sw-dp enabled x x jtag-dp disabled and sw-dp disabled free to be configured as alternate functions
debug management AN4206 22/34 docid023944 rev 4 4.3.3 internal pull-up and pu ll-down resistors on jtag pins the jtag input pins must not be floating since they are direct ly connected to flip-flops to control the debug mode features. special care must be taken with the swclk/tck pin that is directly connected to the cloc k of some of these flip-flops. to avoid any uncontrolled i/o levels, the stm 32f3xx embeds internal pull-up and pull-down resistors on jtag input pins: ? jntrst: internal pull-up ? jtdi: internal pull-up ? jtms/swdio: internal pull-up ? tck/swclk: inte rnal pull-down once a jtag i/o is released by the user soft ware, the gpio controller takes control again. the reset states of the gpio control regist ers put the i/os in the equivalent state: ? jntrst: input pull-up ? jtdi: input pull-up ? jtms/swdio: input pull-up ? jtck/swclk: input pull-down ? jtdo: input floating the software can then use these i/os as standard gpios. note: the jtag ieee standard re commends to add pull-up resistors on td i, tms and ntrst but there is no special recommendatio n for tck. however, for the stm32f3xx , an integrated pull-down resistor is used for jtck. having embedded pull-up and pull-down resistors removes the need to add external resistors.
docid023944 rev 4 23/34 AN4206 debug management 33 4.3.4 swj debug port connection wi th standard jtag connector figure 11 shows the connection between the stm32f3xx and a standard jtag connector. figure 11. jtag connector implementation 069 9 '' 9 '' 670)[[ q-7567 -7', -6706:',2 -7&.6:&/. -7'2 q567,1 975() q7567 7', 706 7&. 57&. 7'2 q6567 '%*54 '%*$&. nrkp 9 66 &rqqhfwru? -7$*frqqhfwru nrkp nrkp
recommendations AN4206 24/34 docid023944 rev 4 5 recommendations 5.1 printed circuit board for technical reasons, it is best to use a multilayer printed circuit board (pcb) with a separate layer dedicated to ground (v ss ) and another dedicated to the v dd supply. this provides good decoupling and a good shielding effect. for many applications, economic reasons prohibit the use of this type of boar d. in this case, the ma jor requirement is to ensure a good structure for ground and for the power supply. 5.2 component position a preliminary layout of the pcb must make separate circuits: ? high-current circuits ? low-voltage circuits ? digital component circuits ? circuits separated according to their emi contribution. th is will reduce cross-coupling on the pcb that introduces noise 5.3 ground and power supply (v ss , v dd, v ssa , v dda, v sssd , v ddsd ) all blocks such as, for example noisy, low-le vel sensitive and digital should be grounded individually and all ground returns should be to a single point. loops must be avoided or have a minimum area. the power supply should be implemented close to the ground line to minimize the area of the supply loop. this is due to the fact that the supply loop acts as an antenna, and is therefore the main transmitter and receiver of emi. all component-free pcb areas must be filled with additi onal grounding to cr eate a kind of shie lding (especially when using single-layer pcbs). 5.4 decoupling all power supply and ground pins must be prop erly connected to the power supplies. these connections, including pads, tracks and vias sh ould have as low an impedance as possible. this is typically achieved with thick track widt hs and, preferably, the use of dedicated power supply planes in multilayer pcbs. in addition, each power supply pair should be decoupled with 100 nf filtering ceramic capacitors and a chemical capacitor of about 4.7 f connected between the supply pins of the stm32f3xx device. these capacitors need to be placed as close as possible to, or below, the appropriate pins on the underside of the pcb. typical values are 10 nf to 100 nf, but exact values depend on the application needs. figure 12 shows the typical layout of such a v dd /v ss pair.
docid023944 rev 4 25/34 AN4206 recommendations 33 figure 12. typical layout for v dd /v ss pair 5.5 other signals when designing an application, the emc perfor mance can be improved by closely studying: ? signals for which a temporary disturbance affects the running process permanently (such as interrupts and handshaking str obe signals, but not led commands). for these signals, a surrounding ground trace, shorter lengths and the absence of noisy and sensitive traces nearby (crosstalk effect) improve emc performance. ? digital signals: the best possible electrical margin must be reached for the two logical states and slow schmitt triggers are re commended to eliminate parasitic states. ? noisy signals (clock, etc.) ? sensitive signals (high impedance, etc.) 5.6 unused i/os and features all microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the mcu resources. to increase emc performance and avoid extra power consumption, unused clocks, counters or i/os, should not be left free. i/os should be connected to a fixed logic level of 0 or 1 by an external or internal pull-up or pull- down on the unused i/o pin. the other option is to configure gpio as output mode using softwa re. unused features should be frozen or disabled, which is their default value. 9ldwr9'' 9ldwr966 9''966 &ds 069 670)[[ &ds
stm32f3x8 vs stm32f30x/f373 AN4206 26/34 docid023944 rev 4 6 stm32f3x8 vs stm32f30x/f373 the previous sections are also valid for stm32f3x8 devices (where the internal voltage regulator is bypassed), howeve r the following differences in comparison with stm32f30x and stm32f373 devices need to be taken into account. ? stm32f3x8 devices require a 1.8 v +/- 8% operating voltage supply (v dd ) and 1.65 v - 3.6 v analog voltage supply (v dda ). the embedded regulator is off and v dd directly supplies the regulator output. the voltage regulator is bypassed and the microcontroller must be powered from a nominal v dd = 1.8 v 8% voltage. ? in stm32f3x8 devices, the pb2 i/o (or pb7 i/o, depending on the product and package) is not available and is replaced by the npor functionality used for power-on reset. to guarantee a proper power-on reset, the npor pin must be held low when v dda is applied. when v dd is stable, the reset state can be exited by putting the npor pin in high impedance. the npor pin has an internal pull-up which holds this input to v dda . ? in stm32f3x8 devices, the por, pdr and pvd features are not available. ? in stm32f3x8 devices, standby mode is not available. stop mode is still available but it is meaningless to distinguish between voltage regulator in low power mode and voltage regulator in run mode because the regulator is not used and v dd is applied externally to the regulator output. ? in stm32f3x8 devices usb is not available. ? in stm32f3x8 devices, the bootloader interfac es are different from the ones in devices with internal regulator on. please refer to the table 5 for details. the table below summarizes the differences between the f30x/f37x and f3x8. table 4. stm32f30x/f373 versus stm32f3x8 feature stm32f30x/f373 stm32f3x8 digital supply vdd 2 - 3.6v 1.8v +/- 8% analog supply vdda 2 - 3.6v 1.65 - 3.6v internal regulator status enabled. used to supply the internal 1.8v digital power. disabled. vdd directly supplies the regulator output. por/pdr/pvd available not available standby mode available not available vdda and vddsd (1) monitoring available not available stop mode with voltage regulator in low power mode or run mode. it is meaningless to distinguish between voltage regulator in low power mode and voltage regulator in run mode because the regulator is not used and vdd is applied externally to the regulator output. usb available not available
docid023944 rev 4 27/34 AN4206 stm32f3x8 vs stm32f30x/f373 33 pb2 gpio (or pb7 gpio depending on the product and package) available not available. it is replaced by the npor functionality used for power- on reset. bootloader com interfaces f30xb/c and f37x: usart1 (pa9/pa10), usart2 (pd5/pd6) or usb (pa11/pa12) through dfu (device firmware upgrade). f30xx6/8/d/e:usart1 (pa9/pa10), usart2 (pa2/pa3) or usb (pa11/pa12) through dfu (device firmware upgrade). f303x6/8 and f334x6/8:usart1 (pa9/pa10), usart2 (pa2/pa3) or i2c1 (pb6/pb7). f358xx and f378xx: usart1 (pa9/pa10), usart2 (pd5/pd6) or i2c1 (pb6/pb7) f328xx:usart1 (pa9/pa10), usart2 (pa2/pa3) or i2c1 (pb6/pb7) f318xx/f398xx:usart1 (pa9/pa10), usart2 (pa2/pa3) or i2c1 (pb6/pb7) or i2c3 (pa8,pb5) 1. vddsd on stm32f373 only. table 4. stm32f30x/f373 versus stm32f3x8 (continued) feature stm32f30x/f373 stm32f3x8
reference design AN4206 28/34 docid023944 rev 4 7 reference design 7.1 description the reference design shown in figure 13 , is based on the stm32f3xx, a highly integrated microcontroller running at 72 mhz, that combines the cortex ? -m4 fpu 32-bit risc cpu core with embedded flash and sram memories. this reference design can be tailored to any other stm32f3xx device with a different package, using the pins correspondence given in the corresponding datasheet. 7.1.1 clock two clock sources are used by the microcontroller: ? lse: x1? 32.768 khz crystal for the embedded rtc ? hse: x2? 8 mhz crystal for th e stm32f3xx microcontroller refer to section 2: clocks on page 16 . 7.1.2 reset the reset signal in figure 13 is active low. the reset sources include: ? reset button (b1) ? debugging tools via the connector cn1. refer to section 1.2: reset and power supply supervisor on page 13 . 7.1.3 boot mode the boot option is configured by setting switch sw1 (boot 0) and option bit nboot1. refer to section 3: boot configuration on page 19 . 7.1.4 swj interface the reference design shows the connection between the stm32f3xx and a standard jtag connector. refer to section 4: debug management on page 20 . note: it is recommended to connect the reset pins so as to be able to re set the application from the development tools. 7.1.5 power supply refer to section 1: power supplies on page 6 . 7.1.6 pinouts and pin descriptions please refer the corresponding stm32f3xx datasheet available on ww.st.com for the pinout and pin description.
docid023944 rev 4 29/34 AN4206 reference design 33 7.2 component references table 5. mandatory components component value reference quantity comments microcontroller - stm32f303vct/ stm32f358vct6 stm32f373vct6/ stm32f378vct6 1 100-pin package capacitor 100 nf c3/c5/c7/c9 4 for stm32f303 3 for stm32f373 3 for stm32f378 ceramic capacitors (decoupling capacitors) capacitor 4.7 f c1 1 ceramic capacitor (decoupling capacitor) capacitor 1 f c2/c11 2 used for vdda and vref+ capacitor 10 nf c4/c13 2 ceramic capacitor (decoupling capacitor) capacitor 10 nf c8/c12/c13 3 ceramic capacitors for vddsdx and vrefsd+ (stm32f373 only) capacitor 1 f c6/c10/c19 3 used for vddsdx and vrefsd+ (stm32f373 only) table 6. optional components component value reference quantity comments resistor 390 ?? r4 1 used for hse: the value depends on the crystal characteristics. this value is given only as a typical example. resistor 0 ? r6 1 used for lse: the value depends on the crystal characteristics. this resistor value is given only as a typical example. resistor 10 k ? r5/r12/r13/r14 4 pull up and pull down for jtag and boot mode. capacitor 100 nf c16 1 ceramic ca pacitors for reset button. capacitor 10 pf c17/c18 2 used for lse: the value depends on the crystal characteristics. capacitor 20 pf c14/c15 2 used for hse: the value depends on the crystal characteristics. quartz 8 mhz x1 1 used for hse quartz 32 khz x2 1 used for lse battery 3v3 bt1 1 if no external battery is us ed in the application, it is recommended to connect v bat externally to v dd switch - sw1 1 used to select the correct boot mode.
reference design AN4206 30/34 docid023944 rev 4 push-button - b1 1 used as reset button jtag connector - cn1 1 used for mcu programming/debugging table 6. optional components (continued) component value reference quantity comments
docid023944 rev 4 31/34 AN4206 reference design 33 figure 13. stm32f30x microcontroller reference schematic 1. on stm32f30x, if no external battery is used in t he application and in stm32f3x8 in all cases, it is recommended to connect v bat externally to v dd . 2. on stm32f3x8, gpio port pb2 is replaced by the npor function. '5$)7 9''b q) q) x)
reference design AN4206 32/34 docid023944 rev 4 figure 14. stm32f373 microcontroller reference schematic 1. on stm32f373, if no external battery is used in the application and in stm32f378 in all cases, it is recommended to connect v bat externally to v dd . 2. on stm32f378, gpio port pb2 is replaced by the npor function. 1 1 2 2 3 3 4 4 d d c c b b a a stmic r oelectronics ti t l e: number: rev: sheet of b.2 date: 11 / 20 / 2012 1 4 3 2 b1 reset button c16 100nf c15 20pf c14 20pf x1 8mhz 4 1 3 2 x2 32.768k hz c17 10pf c16 10pf a n11 stm32f373 reference schematic pb 5 pb 6 pb 7 p a 4 p a 5 p a 6 p a 7 r5 10k 2 3 1 sw1 p a 11 p a 12 pe0 pd 0 pd 1 p a 9 p a 10 pd 3 pd 4 pd 5 pd 6 pc1 0 pc11 pb 1 4 pb 1 5 pb 1 0 pc1 2 pe 14 reset # pb 8 pc5 p a 0 pb 9 pc1 3 pd 8 pd 9 pd 1 0 pd 11 pd 1 2 pc6 pc7 pc8 pc9 pe 15 pe9 pe8 pe 11 pe 10 pe 12 pe 13 p a 1 pc1 pc2 pc3 pd 1 3 pd 2 pe1 pb 1 pb 2 p a 15 pb 3 pd 1 4 pb 0 pc4 pe2 pe3 pe4 pe5 pe6 p a 3 p a 13 p a 14 pb 4 pc0 p a 2 p a 8 pd 7 pd 1 5 pe7 pc1 4 pc1 5 boot0 tm s / sw d i o tc k / swc l k tdi tdo / sw o tr st vss a / vref- 20 vdd a 21 vref+ 22 vsssd 49 vss _ 3 74 vss _ 1 99 vb a t 6 vdd _ 2 28 vddsd12 50 vdd _ 3 75 vdd _ 1 100 vrefsd- 48 vddsd3 51 vrefsd+ 52 u1b stm 32f373vct6 pf2 pf4 pf6 pf9 pf10 pf0 pf1 r4 390 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 cn1 jt a g vdd r13 10k r14 10k r12 10k jt a g connecto r tdi reset # tr st tm s / sw d i o tc k / swcl k tdo / sw o vdd vdd a vrefsd+ bt1 cr1220 1 2 3 jp3 vdd pf0-osc_i n 12 pf1-osc_out 13 nrst 14 p a 0 23 p a 1 24 p a 2 25 p a 3 26 p a 4 29 p a 5 30 p a 6 31 p a 7 32 pb 0 35 pb 1 36 pb 2 37 pb 1 0 47 pb 1 4 53 pb 1 5 54 p a 8 67 p a 9 68 p a 10 69 p a 11 70 p a 12 71 p a 13 72 pf6 73 p a 14 76 p a 15 77 pb 3 89 pb 4 90 pb 5 91 pb 6 92 pb 7 93 boot0 94 pb 8 95 pb 9 96 pe2 1 pe3 2 pe4 3 pe5 4 pe6- wkup3 5 pc13-wkup2 7 pc14-osc32_in 8 pc15-osc32_o ut 9 pc0 15 pc1 16 pc2 17 pc3 18 pc4 33 pc5 34 pe7 38 pe8 39 pe9 40 pe 10 41 pe 11 42 pe 12 43 pe 13 44 pe 14 45 pe 15 46 pd 8 55 pd 9 56 pd 1 0 57 pd 11 58 pd 1 2 59 pd 1 3 60 pd 1 4 61 pd 1 5 62 pc6 63 pc7 64 pc8 65 pc9 66 pc1 0 78 pc11 79 pc1 2 80 pd 0 81 pd 1 82 pd 2 83 pd 3 84 pd 4 85 pd 5 86 pd 6 87 pd 7 88 pe0 97 pe1 98 pf9 10 pf10 11 pf2 19 pf4 27 u1 a stm 32f373vct6 vref+ c11 1uf vdd a c13 10 nf c5 100nf c3 100nf c7 vdd c6 1uf c8 vrefsd+ c2 1uf c4 vref+ c1 4.7uf vddsd12 c10 1uf c12 vddsd12 mcu supply 0 vddsd3 1uf c13 10 nf vddsd3 note 1 10 nf 100 nf 10 nf 10 nf r6 c19
docid023944 rev 4 33/34 AN4206 revision history 33 8 revision history table 7. document revision history date revision changes 11-dec-2012 1 initial release. 27-mar-2014 2 modified introduction . modified the list of applicable products in table 1 on the cover page. added figure 4 . modified chapter 6 and section 7.1 . 14-apr-2014 3 removed any reference to stm32f301x4, stm32f302x4, stm32f303x4 (i.e. part numbers with 16kbytes of flash). modified section 6 . modified table 4 . 25-feb-2015 4 extended the applicability to st m32f303xd/e, stm32f302xd/e and stm32f398ve devices. removed the table 1 on the cover page ?list of applicable products? as the document applies to the whole stm32f3 series. updated:, ? section 1.1: power supply schemes , ? section 2.3: hsi clock , ? section 2.5: clock security system (css) , ? section 3: boot configuration , ? section 6: stm32f3x8 vs stm32f30x/f373 , ? section 7.2: component references , ? figure 13: stm32f30x microcontroller reference schematic , ? figure 14: stm32f373 microcont roller reference schematic .
AN4206 34/34 docid023944 rev 4 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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