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synchronous buck pwm, step-down, dc-to-dc controller adp1828 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2010 analog devices, inc. all rights reserved. features wide bias voltage range 3.0 v to 20 v wide power stage input range 1 v to 24 v wide output voltage range: 0.6 v to 85% of input voltage 0.85% accuracy at 0 o c to 70 o c all n-channel mosfet design for low cost fixed-frequency operation at 300 khz, 600 khz, or resistor adjustable 300 khz to 600 khz clock output for synchronizing other controllers no current sense resistor required internal linear regulator voltage tracking for sequencing soft start and thermal overload protection overvoltage and undervoltage power-good indicator 15 a shutdown supply current available in a 20-lead qsop and 20-lead, 4mm 4 mm lfcsp applications telecom and networking systems base station power set-top boxes, game consoles printers and copiers medical imaging systems dsp and microprocessor core power supplies ddr termination general description the adp1828 is a versatile and synchronous pwm voltage mode buck controller. it drives an all n-channel power stage to regulate an output voltage as low as 0.6 v to 85% of the input voltage and is sized to handle large mosfets for point-of-load regulators. the adp1828 is ideal for a wide range of high power applications, such as dsp and processor core i/o power, and general-purpose power in telecommunications, medical imaging, pc, gaming, and industrial applications. it operates from input bias voltages of 3 v to 20 v with an internal ldo that generates a 5 v output for input bias voltages greater than 5.5 v. the adp1828 operates at a pin-selectable, fixed switching frequency of either 300 khz or 600 khz, or at any frequency between 300 khz and 600 khz with a resistor. the switching frequency can also be synchronized to an external clock up to 2 the parts nominal oscillator frequency. the clock output can be used for synchronizing additional adp1828s (or the adp1829 controllers), thus eliminating the need for an external clock source. the adp1828 includes soft start protection to limit any inrush current from the input supply during startup, reverse current protection during soft start for a precharged output, as well as a unique adjustable lossless current-limit scheme utilizing external mosfet r dson sensing. for applications requiring power-supply sequencing, the adp1828 provides a tracking input that allows the output voltage to track during startup, shutdown, and faults. the additional supervisory and control features include thermal overload, undervoltage lockout, and power good. the adp1828 operates over the ?40c to +125c junction temperature range and is available in a 20-lead qsop and 20-lead, 4mm 4mm lfcsp. in vreg en freq sync pgood comp ss c ss 200nf l1 = 0.82h m1 m2 2 c in 180f 2 20v dh bst sw csl dl pgnd clkout clkset fb c4 0.47f pv trk adp1828 r cl 1.8k ? v in = 10v to 18v output 1.8v, 20a c6 1f r8 20k ? c3 5.6nf pgnd agnd c2 33pf r1 20k ? r3 7.5k ? r2 10k ? d1 c out1 47f x5r 6.3v c out2 1000f 2 c1 680pf r6 100k ? c7 1f c5 1f gnd agnd d1: bat54 m1: infineon, bsc080n03ls m2: infineon, 2 bsc030n03ls f sw = 300khz c in : sanyo, oscon 20sp180m c out2 : sanyo, poscap 2r5tpd1000m5 l1: wurth elektronic, 0.82h, 744355182 06865-001 figure 1. typical application circuit with 20 a output
adp1828 rev. c | page 2 of 36 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 6 ? esd caution.................................................................................. 6 ? simplified block diagram ............................................................... 7 ? pin configurations and function descriptions ........................... 8 ? typical performance characteristics ........................................... 10 ? theory of operation ...................................................................... 15 ? input power ................................................................................. 15 ? internal linear regulator .......................................................... 15 ? soft start ...................................................................................... 15 ? error amplifier ........................................................................... 16 ? current-limit scheme............................................................... 16 ? mosfet drivers........................................................................ 16 ? setting the output voltage ........................................................ 17 ? switching frequency control and synchronization.............. 17 ? compensation............................................................................. 18 ? power-good indicator ............................................................... 18 ? thermal shutdown..................................................................... 18 ? shutdown control...................................................................... 18 ? tracking ....................................................................................... 18 ? application information................................................................ 19 ? selecting the input capacitor ................................................... 19 ? output lc filter ......................................................................... 19 ? selecting the mosfets ............................................................. 20 ? setting the current limit .......................................................... 21 ? accurate current-limit sensing .............................................. 21 ? feedback voltage divider ......................................................... 21 ? compensating the voltage mode buck regulator................. 21 ? soft start ...................................................................................... 25 ? switching noise and overshoot reduction............................ 25 ? voltage tracking......................................................................... 25 ? coincident tracking .................................................................. 26 ? ratiometric tracking ................................................................. 26 ? thermal considerations............................................................ 28 ? pcb layout guideline ................................................................... 29 ? recommended component manufacturers........................... 30 ? application circuits ....................................................................... 31 ? outline dimensions ....................................................................... 33 ? ordering guide .......................................................................... 34 ? revision history 11/10rev. b to rev. c added 20-lead lfcsp_wq .............................................universal changes to features and general description sections.............. 1 changes to table 2............................................................................ 6 added figure 4; renumbered sequentially .................................. 8 changes to table 3............................................................................ 8 updated outline dimensions ....................................................... 33 added figure 59; renumbered sequentially .............................. 33 changes to ordering guide .......................................................... 34 6/09rev. a to rev. b changes to figure 40...................................................................... 24 4/09rev. 0 to rev. a changes to features section and general description section..1 changes to in input voltage parameter and en input impedance to 5 v zener parameter, table 1..................................3 changes to table 2.............................................................................6 changes to table 3.............................................................................8 changes to theory of operation section and input power section.............................................................................................. 14 changes to mosfet drivers section ......................................... 15 updated outline dimensions....................................................... 32 changes to ordering guide .......................................................... 32 9/07revision 0: initial version
adp1828 rev. c | page 3 of 36 specifications in = 12 v, pv = v en = v trk = 5 v, sync = gnd, unless otherwise specified. all limits at temperature extremes are guaranteed via corre- lation using standard statistical quality control (sqc). t j = ?40c to +125c, unless otherwise specified. typical values are at t a = 25c. table 1. parameter conditions min typ max unit power supply in input voltage pv is tied to vreg, in is not tied to vreg (using internal regulator) 5.5 20 v in input voltage in = pv = vreg, in is tied to vreg (not using internal regulator) 3.0 5.5 v in quiescent current not switching, i vreg = 0 ma 1.5 3.0 ma in shutdown current en = gnd 5 15 a vreg-to-gnd shutdown impedance en = gnd, in is not tied to vreg 1.6 m vreg undervoltage lockout thresh old vreg rising 2.4 2.7 3.0 v vreg undervoltage lockout hyst eresis vreg falling 0.125 v error amplifer fb regulation voltage t a = 25c, trk > 700 mv 597 600 603 mv t a = 0c to +70c, trk > 700 mv 595 605 mv t j = ?40c to +125c, trk > 700 mv 591 609 mv fb input bias current 5 100 na open-loop voltage gain 70 db gain-bandwidth product 20 mhz comp sink current 600 a comp source current 120 a comp clamp high voltage in = vreg = 3 v 2.4 v in = 12 v 3.6 v comp clamp low voltage 0.75 v linear regulator vreg output voltage in = 5 v+ dropout voltage to18 v, i vreg =100 ma t j = ?40c to +125c 4.75 5.0 5.25 v vreg load regulation i vreg = 0 ma to 100 ma, in = 5.25 v to 18 v ?10 mv vreg line regulation in = 5 v+ dropout voltage to 18 v, no load 1 mv vreg current limit vreg drops to 4 v 220 ma vreg short-circuit current vreg drops to 0.4 v 60 140 200 ma in to vreg dropout voltage 1 i vreg = 100 ma, in < 5 v 0.6 1.0 v vreg minimum output capacitance 1 f pwm controller vramp peak-to-peak voltage 2 0.7 1.0 1.45 v dh maximum duty cycle freq = gnd (300 khz) 91 93 % dh minimum on time any frequency 100 ns dl minimum on time any frequency 200 ns soft start ss pull-up resistance ss = gnd 90 k ss pull-down resistance ss = 0.6 v 6 k ss to fb offset voltage ss = 0 mv to 500 mv ?45 mv ss pull-up voltage 0.8 v tracking trk common-mode input voltage range 0 600 mv trk to fb offset voltage trk = 0 mv to 500 mv ?5.5 +5 mv trk input bias current 100 na
adp1828 rev. c | page 4 of 36 parameter conditions min typ max unit oscillator oscillator frequency sync = freq = gnd 240 300 360 khz sync = gnd, freq = vreg 480 600 720 khz r freq = 57.6 k 240 300 360 khz r freq = 35.7 k 370 450 530 khz r freq = 24.9 k 480 600 720 khz sync synchronization range freq = gnd 300 600 khz freq = vreg 600 1200 khz sync input pulse width 200 ns sync pin capacitance 5 pf current sense csl threshold voltage relative to pgnd ?17 ?38 ?58 mv csl output current csl = pgnd 42 50 56 a current sense blanking period 100 ns gate drivers dh rise time c dh = 3 nf, v bst ? v sw = 5 v 15 ns dh fall time c dh = 3 nf, v bst ? v sw = 5 v 10 ns dl rise time c dl = 3 nf 15 ns dl fall time c dl = 3 nf 10 ns dh or dl driver r on , sourcing current 3 , 4 sourcing 1.5 a with a 0.1 s pulse 2 dh or dl driver r on , sinking current 3 , 4 sinking 1.5 a with a 0.1 s pulse 1.5 dh or dl driver r on , sourcing current in = vreg = 3 v; sourcing 1 a with a 0.1 s pulse 2.3 dh or dl driver r on , sinking current in = vreg = 3 v; sinking 1 a with a 0.1 s pulse 2 dh to dl, dl to dh dead time 40 ns clock out clockout pulse width 360 ns clkout rise or fall time c clkout = 47 pf 10 ns sync to clkout propagation delay, t pd c clkout = 47 pf, c sync = 5 pf 40 ns sync to clkout propagation delay, t pd c clkout = 47 pf, c sync = 5 pf, in < 5 v 52 ns logic thresholds sync, clkset, freq logic high 1.8 v sync, clkset logic low 0.4 v freq logic low 0.25 v clkset, sync, freq input leakage current clkset, sync, freq = 0 v or vreg 1 a en input threshold 1.1 1.5 1.8 v en input threshold hysteresis 0.2 v en current source en = 0 v to 3.0 v ?0.1 ?0.6 ?1.5 a en input impedance to 5 v zener en = 5.5 v to 20 v 100 k thermal shutdown thermal shutdown threshold 4 145 c thermal shutdown hysteresis 4 15 c
adp1828 rev. c | page 5 of 36 parameter conditions min typ max unit power good fb overvoltage threshold v fb rising 700 750 810 mv fb overvoltage hysteresis 50 mv fb undervoltage threshold v fb falling 500 550 585 mv fb undervoltage hysteresis 50 mv pgood propagation delay 8 s pgood off leakage current v pgood = 5.5 v 1 a pgood output low voltage i pgood = 10 ma 150 500 mv 1 connect in to vreg when in < 5.5 v. for applications with in < 5.5v and in not connected to vreg, keep in mind that vreg = v in C dropout. vreg needs to be 3 v for proper operation. 2 v ramp = 1.0 v f osc /f sw , where f osc is the natural oscillator frequency and f sw is the actual switching frequency. if sync is not used, then f osc = f sw . if sync is used, then f sw = f sync . 3 with a 5 v drive, the peak source or sink current could be up to 2.5 a and 3.3 a, respectively, when driving external power mo sfets. the duration of the peak current pulse is generally in the order of 10 ns. 4 guaranteed by design and characterization. not subject to production test.
adp1828 rev. c | page 6 of 36 absolute maximum ratings table 2. parameter rating in ?0.3 v to +20.5 v en ?0.3 v < in + 0.3 v pv, sync, freq, comp, ss, fb, pgood, clkset, clkout, vreg, trk ?0.3 v to +6 v bst-to-gnd, sw-to-gnd ?0.3 v to +30 v bst-to-sw ?0.3 v to +6 v bst-to-gnd, sw-to-gnd, 50 ns transients +38 v sw-to-gnd, 30 ns negative transients ?7 v csl-to-gnd ?1 v to +30 v dh-to-gnd (sw ? 0.3 v) to (bst + 0.3 v) dl-to-pgnd ?0.3 v to (pv + 0.3 v) pgnd-to-gnd 2 v ja , 20-lead qsop on a multilayer pcb (natural convection) 1 83c/w ja , 20-lead lfcsp on a multilayer pcb (natural convection) 1 35.6c/w operating junction temperature 2 ?40c to +125c storage temperature ?65c to +150c maximum soldering lead temperature 260c 1 junction-to-ambient thermal resistance ( ja ) of the package was calculated or simulated on a multilayer pcb. 2 the junction temperature, t j , of the device is dependent on the ambient temperature, t a , the power dissipation of the device, p d , and the junction to ambient thermal resistance of the package, ja . maximum junction temperature is calculated from the ambient temper ature and power dissipation using the formula t j = t a + p d ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified all other voltages are referenced to gnd. esd caution
adp1828 rev. c | page 7 of 36 simplified block diagram qs r pwm q thermal shutdown uvlo linear reg logic ref clkout driver oscillator error amplifier 0.6v 0.55v 0.75v vreg in 100k ? adp1828 0.6v 0.8v 0.75v 0.55v clk ramp pwm comparator 0.8v fault 90k ? 6k ? ilim 50a vreg en clkout clkset freq sync comp fb trk ss gnd fault in bst dh sw pv dl pgnd csl pgood 06865-003 figure 2. simplified block diagram
adp1828 rev. c | page 8 of 36 pin configurations and function descriptions 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 sync en in comp gnd vreg freq clkset bst dh pgnd csl sw ss trk fb pgood pv dl clkout top view (not to scale) adp1828 06865-004 figure 3. 20-lead qs op pin configuration 06865-059 14 13 12 1 3 4 sw 15 dh csl pgnd 11 dl en vreg 2 in gnd 5 comp 7 trk 6 fb 8 ss 9 pgood 10 pv 19 freq 20 sync 18 clkou t 17 clkset 16 bst top view adp1828 (not to scale) notes 1. connect the bottom exposed pad of the lfcsp package to system agnd plane. figure 4. 20-lead lfcsp pin configuration table 3. pin function descriptions op pin o. lcp pin o. neonic description 1 19 freq frequency control input. low for 300 khz, high for 600 khz, or connect a resistor from freq to gnd to set the free-running frequency between 300 khz and 600 khz. 2 20 sync frequency synchronization input. accepts external signals between 300 khz and 600 khz if freq is set to low, or between 600 khz and 1.2 mhz if freq is set to high. if f osc is set by r freq , then the synchronization frequency range is from f osc up to 600 khz. if sync is not used, connect sync to gnd or vreg. v sync can be driven up to 6 v even when v in is less than 6 v. 3 1 en enable input. drive en high or tristate en to turn on the adp1828 controller, and drive it low to turn off. connect en to in for automatic startup. 4 2 in input supply to the internal linear regulator. dr ive in with 5.5 v to 20 v to power the adp1828 from ldo, vreg; tie pv to vreg. for input voltages between 3 v and 5.5 v, tie in, pv, and vreg together. 5 3 vreg output of the internal linear regulator (ldo). the in ternal circuitry and gate drivers are powered from vreg. bypass vreg to agnd plane with 1 f ceramic capacitor for stable operation, for example, a 10 v x5r 1 f ceramic capacitor is sufficient. the vreg o utput is 5 v when in = 5 v + dropout. connect in to vreg and pv when in = 3 v to 5.5 v. for applications with in < 5.5 v and in not connected to vreg, keep in mind that vreg = vin C dropout. vreg needs to be 3 v for proper operation. 6 4 gnd ground for internal circuits. tie the bot tom of the feedback dividers to this gnd. 7 5 comp error amplifier output. connect an rc ne twork from comp to fb for loop compensation. 8 6 fb voltage feedback. connect a resistor divider from the buck regulator output to gnd and tie the tap to fb to set the output voltage. 9 7 trk tracking input. to track a master voltage, drive trk from a voltage divider from the master voltage. if the tracking function is not used, connect trk to vreg. 10 8 ss soft start control input. connect a capacitor from ss to gnd to set the soft start period. 11 9 pgood open-drain power-good output. sinks current when fb is out of regulation. connect a pull-up resistor from pgood to vreg. 12 10 pv positive input voltage for gate driver dl. when in is 3 v to 5.5 v, connect in to vreg and pv. connect a 1 f bypass capacitor from pv to pgnd. when in = 5.5 v to 20 v, connect pv to vreg. 13 11 dl low-side (synchronous re ctifier) gate driver output. 14 12 pgnd power gnd. ground for gate driver. 15 13 csl current sense comparator inverting input. connect a resistor between csl and sw to set the current- limit offset. 16 14 sw switch node connection. 17 15 dh high-side (switch) gate driver output. 18 16 bst boost capacitor input. powers the high-side gate driver dh. connect a 0.22 f to 0.47 f ceramic capacitor from bst to sw and a schottky diode from pv to bst.
adp1828 rev. c | page 9 of 36 qsop pin no. lscsp pin no. mnemonic description 19 17 clkset clock set input. setting clkset to logic high (co nnect clkset to vreg) sets the clkout to 2 the internal oscillator frequency and is in phase with the oscillator. setting clkset to logic low sets the clkout to 1 the oscillator fr equency and 180 out of phase. 20 18 clkout clock output. the clkout frequency, f clkout , is either 1 or 2 the osci llator frequency. clkout can 0be used to synchronize another ad p1828 or adp1829 controllers. set f clkout to 1 when synchronizing another adp1828, or to 2 when synchron izing the adp1829. if sync is used, f sync = f clkout independent of the clkset voltage. clkout is able to drive a 100 pf load. n/a 1 epad epad exposed pad. connect the bottom exposed pad of the lfcsp package to system agnd plane. 1 n/a means not applicable.
adp1828 rev. c | page 10 of 36 typical performance characteristics 02468101214161820 load (a) 90 80 70 60 50 40 30 efficiency (%) 300khz 600khz v in = 12v v out = 1.8v t a = 25c 06865-002 figure 5. efficiency vs. load current of figure 1 0 5 10 15 20 25 load (a) 95 90 85 80 75 70 65 60 55 efficiency (%) f sw = 300khz v out = 1.8v t a = 25c 06865-005 v in = 5.5v v in = 3.3v v in = 12v v in = 15v figure 6. efficiency vs. load current of figure 1 01 2345 95 90 85 80 75 70 65 60 55 efficiency (%) load (a) f sw = 600khz v in = 3.3v v out = 1.2v t a = 25c 06865-006 figure 7. efficiency vs. load current of figure 54 01 2345 95 90 85 80 75 70 65 60 55 50 efficiency (%) load (a) f sw = 600khz v in = 12v v out = 3.3v t a = 25c 06865-007 figure 8. efficiency vs. load current of figure 55 0 5 10 15 20 25 30 95 90 85 80 75 70 65 60 55 50 45 efficiency (%) load (a) f sw = 300khz v in = 12v v out = 1.8v t a = 25c 06865-008 figure 9. efficiency vs. load current of figure 57 06865-009 5.5 5.0 4.5 4.0 3.5 3.0 vreg output (v) 3.0 3.5 4.0 4.5 5.0 5.5 v in (v) t a = 25c figure 10. vreg in dropout, no load
adp1828 rev. c | page 11 of 36 0 20 40 60 80 100 vreg load current (ma) 5.000 4.995 4.990 4.985 4.980 4.975 4.970 4.965 4.960 4.955 4.950 vreg output (v) 06865-010 v in = 5.5v t a = 25c figure 11. vreg vs. load current ?50 ?25 0 25 50 75 100 125 temperature (c) 5.000 4.995 4.990 4.985 4.980 4.975 4.970 4.965 4.960 4.955 4.950 vreg (v) 06865-011 v in = 7v no load 10ma load 100ma load figure 12. vreg voltage vs. temperature 0 50 100 150 200 250 vreg load current (ma) 5 4 3 2 1 0 vreg output (v) v in = 5.5v t a = 25c 06865-012 figure 13. vreg current-limit foldback 3 5 7 9 11 13 15 17 v in (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 ? f osc (%) 06865-013 300khz 600khz t a = 25c figure 14. f osc vs. v in , referenced at v in = 3 v 06865-014 ch1 5.00v ch2 100mv m 400ns a ch1 3.60v 1 2 v in = 5.5v load = 5a t b w b w sw vreg (ac-coupled) figure 15. vreg output of figure 55 temperature (c) feedback voltage (v) 06865-015 ?40 ?15 10 35 60 85 110 135 0.5990 0.5995 0.6000 0.6005 0.6010 0.6015 0.6020 0.6025 figure 16. feedback voltage vs. temperature, v in = 12 v
adp1828 rev. c | page 12 of 36 ?50 ?25 0 25 50 75 100 125 150 temperature (c) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ? f osc (khz) 06865-016 v in = 3v to 18v f osc = 300khz or 600khz reference point is at 25c figure 17. f osc vs. temperature 2 5 8 11141720 v in (v) 6 5 4 3 2 1 0 quiescent current (ma) 06865-017 t a = 25c figure 18. supply current vs. input voltage 06865-018 ch1 10.0v ch3 50.0mv ch2 5.00v m 1.00s a ch1 6.40v 3 1 2 t b w sw input ripple output ripple b w b w figure 19. input and output ripple of figure 1 , 22 a load 06865-019 ch1 100mv ch4 5.00a ? m 200s a ch4 8.20a 1 4 t b w v out (ac-coupled) step load (5a to 20a) figure 20. load transient response of figure 1 , 5 a to 20 a, v in = 12 v 06865-020 ch1 10.0v ch3 10.0mv ch2 50.0mv m 1.00s a ch1 5.80v 2 1 3 t b w sw input ripple output ripple b w figure 21. input and output ripple of figure 55 , 4 a load 06865-021 ch2 200mv ch3 100mv m 200s a ch4 4.20a 3 t b w input voltage (ac-coupled) output (ac-coupled) 2 4 ch4 5.00a ? b w step load (1a to 5a) figure 22. load transient response of figure 55 , 1 a to 5 a, v in = 12 v
adp1828 rev. c | page 13 of 36 06865-022 ch1 2.00v ch3 50.0mv m 4.00ms a ch1 6.08v 3 t b w v out (ac-coupled) 1 v in = 5v to 9v to 5v figure 23. line transient response of figure 1 , no load 06865-023 ch1 5.00v ch3 1.00v ch2 500mv m 20.0ms a ch3 1.34v 4 1 2 3 b w ss short circuit applied input current b w ch4 5.00a ? short circuit removed v in = 5.5v v out figure 24. output short-circuit response 06865-024 ch1 5.00v ch3 1.00v ch2 1.00v m 4.00ms a ch1 3.000v 3 1 2 b w ss b w v out en t figure 25. soft start and inrush current of figure 1 06865-025 ch1 5.00v ch3 1.00v ch2 500mv m 2.00ms a ch1 4.10v 4 1 2 3 b w ss b w ch4 5.00v v out sw t v in figure 26. power-on response, en tied to v in 06865-026 ch1 200mv ch2 200mv m 20.0ms a ch1 680mv 1 t b w b w fb trk figure 27. tracking, trk from 0 v to 1 v 06865-027 ch1 100mv ch2 100mv m 20.0ms a ch1 352mv 1 t b w b w trk and fb superimposed figure 28. tracking, trk from 0 v to 0.5 v
adp1828 rev. c | page 14 of 36 06865-029 ch3 5.00v ch4 5.00v ch2 10.0v m 1.00s a ch2 4.80v 2 3 4 dh clkout dl t figure 29. clkout, clkset = 0 v 06865-030 ch3 5.00v ch4 5.00v ch2 10.0v m 1.00s a ch2 4.80v 2 3 4 dh clkout dl t figure 30. clkout, clkset = 5 v 06865-031 ch3 5.00v ch4 5.00v ch2 10.0v ch1 5.00v m 1.00s a ch1 3.50v 4 3 2 1 dh clkout dl t sync figure 31. sync 06865-032 ch1 5.00v ch3 200mv ch2 200mv m 4.00ms a ch4 1.12v 2 1 4 b w b w ss b w b w ch4 2.00v v in = 0v to 3v vreg fb t dh figure 32. start into precharged output 06865-033 ch1 5.00v ch3 5.00v ch2 10.0v m 4.00s a ch2 8.20v 2 1 3 b w b w b w en t dh dl figure 33. en, shutdown
adp1828 rev. c | page 15 of 36 theory of operation the adp1828 is a versatile, synchronous-rectified, fixed- frequency, pulse-width modulation (pwm), voltage mode, step-down controller capable of generating an output voltage as low as 0.6 v to 85% of the input voltage. it is ideal for a wide range of applications, such as dsp and processor core i/o supplies, general-purpose power in telecom, medical imaging, gaming, pcs, set-top boxes, and industrial controls. the adp1828 controller operates directly from 3 v to 20 v. it includes fully integrated mosfet gate drivers and a linear regulator for internal and gate drive bias. the adp1828 operates at a pin-selectable, fixed switching frequency of either 300 khz or 600 khz, or operates at any frequency between 300 khz and 600 khz by connecting a resistor between freq and gnd. the switching frequency can also be synchronized to an external clock up to 2 the parts nominal oscillator frequency. the built-in clock output can be used for synchronizing the adp1829 and other adp1828 controllers, thus eliminating the need for an external clock source. the adp1828 also includes clockout, voltage tracking, thermal overload protection, undervoltage lockout, power good, soft start to limit inrush current from the input supply during startup, reverse current protection during soft start for precharged outputs, and an adjustable lossless current-limit scheme utilizing external mosfet r dson sensing. the adp1828 operates over the ?40 c to +125 c junction temperature range and is available in a 20-lead qsop. input power the adp1828 is powered from the in pin from 3.0 v up to 20 v. the internal low dropout linear regulator, regulates the in voltage down to 5 v when in is between 5.5 v and 20 v. the output of the ldo is denoted as vreg. the control circuits, gate drivers, and the external boost capacitor operate from the ldo output for in between 5.5 v and 20 v. pv powers the low-side mosfet gate drive (dl), and in powers the internal control circuitry. bypass pv to pgnd with a 1 f or greater capacitor, and bypass in to gnd with a 0.1 f or greater capacitor. bypass the power input to pgnd with a suitably large capacitor. the vreg output is sensed by the undervoltage lock-out (uvlo) circuit to be certain that enough voltage headroom is available to run the controllers and gate drivers. as vreg rises above about 2.7 v, the controllers are enabled. the in voltage is not directly monitored by the uvlo circuit. if the in voltage is insufficient to allow vreg to be above the uvlo threshold, the controllers are disabled, but the ldo continues to operate. the ldo is enabled and cannot be turned off whenever en is high, even if vreg is below the uvlo threshold. for a supply voltage between 5.5 v and 20 v, connect in to the supply voltage, and tie vreg to pv. for a supply voltage between 3 v and 5.5 v, connect in, pv, and vreg to the supply voltage. in this case, the input supply voltage directly powers the low- side gate driver. while in is limited to 20 v, the switching stage can run from up to 24 v and the bst pin can go to 30 v to support the gate drive. this can provide an advantage, for example, in the case of high frequency operation from high input voltage. power dissipation in the adp1828 can be limited by running in from a low voltage rail while operating the switches from the high voltage rail. internal linear regulator the internal linear regulator has low dropout, meaning it can regulate its output voltage (vreg) close to the input voltage. it powers up the internal control circuitry and provides bias for the gate drivers when vreg is tied to pv. it is guaranteed to have more than 100 ma of output current capability, which is sufficient to handle the gate drive requirements of typical logic threshold mosfets driven at up to 1.2 mhz. bypass vreg to agnd with a 1 f or greater capacitor. because the ldo supplies the gate drive current, the output of vreg is subjected to sharp transient currents as the drivers switch and the boost capacitors recharge during each switching cycle. the ldo has been optimized to handle these transients without overload faults. due to the gate drive loading, using the vreg output for other auxiliary system loads is not recommended. the ldo includes a current limit well above the expected maximum gate drive load. this current limit also includes a short-circuit fold back to further limit the vreg current in the event of a short-circuit fault. soft start the adp1828 employs a programmable soft start that reduces input current transients and prevents output overshoot. ss drives an auxiliary positive input to the error amplifier; thus, the voltage at this pin regulates the voltage at the feedback control pin. program the soft start by connecting a capacitor from ss to gnd. on startup, the capacitor charges from an internal 90 k resistor to 0.8 v. the dc-to-dc converter output voltage rises with the voltage at the soft start pin, allowing the output voltage to rise slowly and reducing the inrush current.
adp1828 rev. c | page 16 of 36 if the output voltage is precharged prior to turn-on, the adp1828 prevents reverse inductor current, which would discharge the output capacitor. once the voltage at ss exceeds the regulation voltage (typically 0.6 v), the reverse current is re-enabled to allow the output voltage regulation to be independent of load current. when a controller is disabled or experiences any form of fault condition, the soft start capacitor is discharged through an internal 6 k resistor, so that at restart or recovery from fault the output voltage soft starts again. error amplifier the adp1828 error amplifier is an operational amplifier. the adp1828 senses the output voltage through an external resistor divider at the fb pin. the fb pin is the inverting input to the error amplifier. the error amplifier compares this feedback voltage to the internal 0.6 v reference, and the output of the error amplifier appears at the comp pin. the comp pin voltage then directly controls the duty cycle of the switching converter. a series/parallel rc network is tied between the fb pin and the comp pin to provide the compensation for the buck converter control loop. a detailed design procedure for compensating the system is provided in the compensating the voltage mode buck regulator section. the error amplifier output is clamped between a lower limit of about 0.75 v and a higher limit of up to about 3.6 v, depending on the vreg voltage. when the comp pin is low, the switching duty cycle goes to 0%, and when the comp pin is high, the switching duty cycle goes to the maximum. the ss and trk pins are auxiliary positive inputs to the error amplifier. whichever voltage is lowest (ss, trk, or the internal 0.6 v reference) controls the fb pin voltage and the output. as a consequence, if two of these inputs are close to each other, a small offset is imposed on the error amplifier. current-limit scheme the adp1828 employs a programmable, cycle-by-cycle lossless current-limit circuit that uses an inexpensive resistor to set the threshold. every switching cycle, the synchronous rectifier turns on for a minimum time and the voltage drop across the mosfet r dson is measured to determine if the current is too high. this measurement is done by an internal current-limit compa- rator and an external current-limit setting resistor. the resistor is connected between the switch node (that is the drain of the rectifier mosfet) and the csl pin. the csl pin, which is the inverting input of the comparator, forces 50 a through the resistor to create an offset voltage drop across it. when the inductor current is flowing in the mosfet rectifier, its drain is forced below pgnd by the voltage drop across its r dson . if the r dson voltage drop exceeds the preset drop on the current-limit resistor, the inverting comparator input is similarly forced below pgnd and an overcurrent fault is flagged. the normal transient ringing on the switch node is ignored for 100 ns after the synchronous rectifier turns on, so the over- current condition must also persist for 100 ns for a fault to be flagged. when the adp1828 senses an overcurrent condition, the next switching cycle is suppressed, the soft start capacitor is discharged through an internal 6 k resistor, and the error amplifier output voltage is pulled down. the adp1828 remains in this mode for as long as the overcurrent condition persists. note that the current-limit scheme in the adp1828 is not the same as a short-circuit protection. the adp1828 does not go into current foldback in the event of a short circuit. the short- circuit output current is the current limit set by the r cl resistor and is monitored cycle by cycle. when the overcurrent condition is removed, operation resumes in soft start mode. mosfet drivers the dh pin drives the high-side switch mosfet. this is a boosted 5 v gate driver that is powered by a bootstrap capacitor circuit. this configuration allows the high-side, n-channel mosfet gate to be driven above the input voltage, allowing full enhancement and a low voltage drop across the mosfet. the bootstrap capacitor is connected from the sw pin to the bst pin. a bootstrap schottky diode connected from the pv pin to the bst pin recharges the boost capacitor every time the sw node goes low. use a bootstrap capacitor value greater than 100 the high-side mosfet input capacitance. in practice, the switch node can run up to 24 v of input voltage, and the boost nodes can operate more than 5 v above this to allow full gate drive. the in pin can be run from 3 v to 20 v. the switching cycle is initiated by the internal clock signal. the high-side mosfet is turned on by the dh driver, and the sw node goes high, pulling up on the inductor. when the internally generated ramp signal crosses the comp pin voltage, the switch mosfet is turned off and the low-side synchronous rectifier mosfet is turned on by the dl driver. active break-before- make circuitry as well as a supplemental fixed dead time are used to prevent cross-conduction in the switches. the dl pin provides the gate drive for the low-side mosfet synchronous rectifier. internal circuitry monitors the external mosfets to ensure break-before-make switching to prevent cross-conduction. an active dead-time reduction circuit reduces the break-before-make time of the switch to limit the losses due to current flowing through the synchronous rectifier body diode.
adp1828 rev. c | page 17 of 36 the pv pin provides power to the low-side drivers. it is limited to 5.5 v maximum input and should have a local decoupling capacitor to pgnd. the synchronous rectifier is turned on for a minimum time of about 200 ns on every switching cycle in order to sense the current. this minimum off-time plus the nonoverlap dead time puts a limit on the maximum high-side switch duty cycle based on the selected switching frequency. typically, this maximum duty cycle is about 90% at 300 khz switching. at 1.2 mhz switching, it reduces to about 70% maximum duty cycle. setting the output voltage the output voltage is set using a resistive voltage divider from the output to fb. the voltage divider splits the output voltage to the 0.6 v fb regulation voltage to set the regulation output voltage. the output voltage can be set to as low as 0.6 v and as high as 85% of the power input voltage. switching frequency control and synchronization the adp1828 has a logic controlled frequency select input, freq, which sets the switching frequency to 300 khz or 600 khz. drive freq low at 300 khz and high at 600 khz. the frequency can also be set to between 300 khz and 600 khz by connecting a resistor between freq and gnd. a 24.9 k sets the frequency to 600 khz, 35.7 k to 450 khz, and 57.6 k to 300 khz. figure 34 shows f osc as a function of r freq . 24000 29000 34000 39000 44000 49000 54000 59000 06865-034 oscillator frequency (khz) r freq ( ? ) 200 250 300 350 400 450 500 550 600 t a = 25c v in = 3v v in = 5v figure 34. f osc vs. r freq the sync input is used to synchronize the converter switching frequency to an external signal. this allows multiple adp1828 converters to be operated at the same frequency to prevent frequency beating or other interactions. the adp1828 has a clock output (clkout), which can be used for synchronizing the adp1829 and other adp1828 controllers, thus eliminating the need for an external clock source. pulling clkset low sets the frequency at clkout to 1 the internal oscillator frequency, f osc , and is 180 out of phase with f osc . the 1 output is suitable for synchronizing other adp1828s. setting clkset high (connect to vreg) sets the frequency to 2 f osc and is in phase with f osc . the 2 output is suitable for synchronizing the dual channel adp1829 controller (see table 4 ). table 4. clkout truth table 1 en clkset sync clkout comment h l h/l 1 f osc 180 out of phase with f osc h h h/l 2 f osc in phase with f osc h x clock in clock clkout in-sync with clock in l x x l clkout is low 1 x: dont care, h: logi c high, l: logic low. to synchronize the adp1828 switching frequency to an external signal, drive the sync input with an external clock or with the clkout signal from another adp1828. the adp1828 can be synchronized to between 1 and 2 the internal oscillator frequency. if f osc is set by r freq , then the synchronization frequency range is from f osc up to 600 khz. driving sync faster than recommended for the freq setting results in a small ramp signal, which could affect the signal-to- noise ratio and the modulator gain and stability. when an external clock is detected at the first sync edge, the internal oscillator is reset and the clock control shifts to sync. the sync edges then trigger subsequent clocking of the pwm outputs. the high-side mosfet turn-on follows the rising edge of the sync input by approximately 320 ns (see figure 35 for an illustration). if the external sync signal disappears during operation, the adp1828 reverts to its internal oscillator and experiences a delay of no more than a single cycle of the internal oscillator. sync dh dl 320ns dt dt (dead time) = 40ns 06865-035 figure 35. synchronization
adp1828 rev. c | page 18 of 36 compensation the control loop is compensated by an external series rc network from comp to fb and sometimes requires a series rc in parallel with the top voltage divider resistor. comp is the output of the internal error amplifier. the internal error amplifier compares the voltage at fb to the internal 0.6 v reference voltage. the difference between the fb voltage and the 0.6 v reference voltage is amplified by the open- loop voltage 1000 volt-to-volt gain of the error amplifier. to optimize the adp1828 for stability and transient response for a given set of external components and input/output voltage conditions, choose the compensation components carefully. for more information on choosing the compensation components, see the compensating the voltage mode buck regulator section. power-good indicator the adp1828 features an open-drain power-good output (pgood) that sinks current when the output voltage drops 8.3% below or rises 25% above the nominal regulation voltage. two comparators measure the voltage at fb to set these thresh- olds. the pgood comparator directly monitors fb, and the threshold is fixed at 0.55 v for undervoltage and 0.75 v for overvoltage. the pgood output also sinks current if an overtemperature or input undervoltage condition is detected and is operational with power-input voltage as low as 1.0 v. use this output as a logical power-good signal by connecting a pull-up resistor from pgood to an appropriate supply voltage. thermal shutdown in most applications, the adp1828 controller itself does not generate a significant amount of heat under normal conditions, even when driving relatively large mosfets. however, the surrounding power components or other circuits on the same pcb could heat up the pcb to an unsafe operating temperature. a thermal shutdown protection circuit on the adp1828 shuts off the ldo and the controllers if the die temperature exceeds approximately 145c, but this is a gross fault protection only and should not be depended on for system reliability. shutdown control the adp1828 dc-to-dc converter features a low power shut- down mode that reduces the quiescent supply current to 20 a, or 40 a when in is tied to vreg. to shut down the adp1828, drive en low. to turn it on, drive en high or tristate en. for automatic startup, connect en to in. tracking the adp1828 features a tracking input, trk that makes the output voltage track another voltage, that is, the master voltage. this feature is especially useful in core and i/o voltage sequencing applications where the output of the adp1828 can be set to track and not exceed another voltage. the internal error amplifier includes three positive inputsthe internal 0.6 v reference voltage, and the ss and trk pins. the error amplifier regulates the fb pin to the lowest of the three inputs. to track a supply voltage, tie the trk pin to a resistor divider from the voltage to be tracked. if the trk function is not used, tie the trk pin to vreg.
adp1828 rev. c | page 19 of 36 application information selecting the input capacitor the input current to a buck converter is a pulse waveform. it is zero when the high-side switch is off and approximately equal to the load current when it is on. the input capacitor carries the input ripple current, allowing the input power source to supply only the dc current. the input capacitor needs sufficient ripple current rating to handle the input ripple as well as an esr that is low enough to mitigate input voltage ripple. for the usual current ranges for these converters, it is good practice to use two parallel capacitors placed close to the drains of the high- side switch mosfets (one bulk capacitor of sufficiently high current rating as calculated in equation 2 along with a 10 f ceramic capacitor). select an input bulk capacitor based on its ripple current rating. first, determine the duty cycle of the output with the larger load current: in out v v d = (1) the input capacitor ripple current is approximately )1( ddii l ripple ? (2) where: i l is the maximum inductor or load current. d is the duty cycle. output lc filter the output lc filter smoothes the switched voltage at sw, making the dc output voltage. choose the output lc filter to achieve the desired output ripple voltage. because the output lc filter is part of the regulator negative-feedback control loop, the choice of the output lc filter components affects the regulation control loop stability. choose an inductor value such that the inductor ripple current is approximately 1/3 of the maximum dc output load current. using a larger value inductor results in a physical size larger than required and using a smaller value results in increased losses in the inductor and/or mosfet switches. choose the inductor value by the following equation: ? ? ? ? ? ? ? ? = in out out l sw v v v if l 1 1 (3) where: l is the inductor value. f sw is the switching frequency. v out is the output voltage. v in is the input voltage. i l is the inductor ripple current, typically 1/3 of the maximum dc load current. choose the output bulk capacitor to set the desired output voltage ripple. the impedance of the output capacitor at the switching frequency multiplied by the ripple current gives the output voltage ripple. the impedance is made up of the capacitive impedance plus the nonideal parasitic characteristics, including the equivalent series resistance (esr) and the equiva- lent series inductance (esl). the output voltage ripple can be approximated with: 2 2 2 )4( 8 1 eslf cf esriv sw out sw l out + ? ? ? ? ? ? ? ? + = (4) where: v out is the output ripple voltage. i l is the inductor ripple current. esr is the equivalent series resistance of the output capacitor (or the parallel combination of esr of all output capacitors). esl is the equivalent series inductance of the output capacitor (or the parallel combination of esl of all capacitors). note that the factors of 8 and 4 in equation 4 would normally be 2 for sinusoidal waveforms, but the ripple current wave- form in this application is triangular. parallel combinations of different types of capacitors, for example, a large aluminum electrolytic in parallel with mlccs, may give different results. usually the impedance is dominated by esr at the switching frequency, as stated in the maximum esr rating on the capaci- tor data sheet, so this equation reduces to v out ? i l esr (5) electrolytic capacitors have significant esl also, on the order of 5 nh to 20 nh, depending on type, size, and geometry, and pcb traces contribute some esr and esl as well. however, using the maximum esr rating from the capacitor data sheet usually provides some margin such that measuring the esl is not usually required. in the case of output capacitors, the impedance of the esr and esl at the switching frequency are small, for instance, where the effective output capacitor is a bank of parallel mlcc capa- citors, the capacitive impedance dominates and the ripple equation reduces to sw out l out fc i v 8 ? (6) make sure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current.
adp1828 rev. c | page 20 of 36 during a load step transient on the output, the output capacitor supplies the load until the control loop has a chance to ramp the inductor current. this initial output voltage deviation, due to a change in load, is dependent on the output capacitor charac- teristics. again, usually the capacitor esr dominates this response, and the v out in equation 6 can be used with the load step current value for i l . selecting the mosfets the choice of mosfet directly affects the dc-to-dc converter performance. the mosfet must have low on resistance to reduce i 2 r losses and low gate charge to reduce transition losses. in addition, the mosfet must have low thermal resistance to ensure that the power dissipated in the mosfet does not result in excessive mosfet die temperature. the high-side mosfet carries the load current during on-time and usually carries most of the transition losses of the converter. typically, the lower the mosfets on resistance, the higher the gate charge and vice versa. therefore, it is important to choose a high-side mosfet that balances the two losses. the conduction loss of the high-side mosfet is determined by the equation ? ? ? ? ? ? ? ? ? in out dson load c v v rip 2 )( (7) where: p c is the conduction power loss. r dson is the mosfet on resistance. the gate charging loss is approximated by the equation swg pv g fqvp ? (8) where: p g is the gate charging loss power. v pv is the gate driver supply voltage. q g is the mosfet total gate charge. f sw is the converter switching frequency. the high-side mosfet transition loss is approximated by the equation 2 )( sw fr load in t fttiv p + = (9) where: p t is the high-side mosfet switching loss power. t r is the mosfet rise time. t f is the mosfet fall time. the total power dissipation of the high-side mosfet is the sum of all the previous losses, or (10) where p hs is the total high-side mosfet power loss. the conduction losses may need an adjustment to account for the mosfet r dson variation with temperature. note that mosfet r dson increases with increasing temperature. the mosfet data sheet should list the thermal resistance of the package, ja , along with a normalized curve of the temperature coefficient of the r dson . for the power dissipation estimated in equation 10, calculate the mosfet junction temperature rise over the ambient temperature of interest: t j = t a + ja p d (11) then, calculate the new r dson from the temperature coefficient curve and the r dson specification at 25c. an alternate method to calculate the mosfet r dson at a second temperature, t j , is r dson @ t j = r dson @ 25c (1 + t c ( t j ? 25c)) (12) where t c is the temperature coefficient of the mosfets r dson , and its typical value is 0.004/c. then the conduction losses can be recalculated and the proce- dure iterated until the junction temperature calculations are relatively consistent. the synchronous rectifier, or low-side mosfet, carries the inductor current when the high-side mosfet is off. the low- sition loss is small and can be neglected in the calculation. for high input voltage and low output voltage, the low-side mosfet carries the current most of the time. therefore, to achieve high efficiency, it is critical to optimize the low-side mosfet for low on resistance. in cases where the power loss exceeds the mosfet ra ting or lower resistance is required than is available in a single mosfet, connect multiple he equation for low-side mosfet power loss is t gchs pppp ++? side mosfet tran low-side mosfets in parallel. t ? ? ? ? ? ? ? ? in out dson load ls v v rip 1)( 2 (13) where: p ls is the total low-side mosfet power loss. r dson is the total on resistance of the low-side mosfet(s). check the gate charge losses of the synchronous rectifier using equation 8 to be sure it is reasonable. if multiple low-side mosfets are used in parallel, then use the parallel combina- tion of the on resistances for determining rdson to solve this equation.
adp1828 rev. c | page 21 of 36 setting the current limit the current-limit comparator measures the voltage across the low-side mosfet to determine the load current. the current limit is set through the current-limit resistor, r cl . the current sense pin, csl, sources 50 a through the external current-limit setting resistor, r cl . this creates an offset voltage of r cl multiplied by the 50 a csl current. when the drop across the low-side mosfet r dson is equal to or greater than this offset voltage, the adp1828 flags a current-limit event. because the csl current and the mosfet r dson vary over process and temperature, the minimum current limit should be set to ensure that the system can handle the maximum desired load current. to do this, use the peak current in the inductor, which is the desired current-limit level plus the ripple current, the maximum r dson of the mosfet at its highest expected temperature, and the minimum csl current: a ri r max dson lpk cl ? = 42 mv38 )( (14) where: i lpk is the peak inductor current. ?38 mv is the csl threshold voltage. because the buck converters are usually running a fairly high current, pcb layout and component placement may affect the current-limit setting. an iteration of the r cl value may be required for a particular board layout and mosfet selection. if alternate mosfets are substituted at some point in production, these resistor values may also need an iteration. accurate current-limit sensing the r dson of the external low-side mosfet can vary by more than 50% over the temperature range. accurate current-limit sensing can be achieved by adding a current sense resistor from the source of the low-side mosfet to pgnd. make sure that the power rating of the current sense resistor is adequate for the application. apply equation 14 to calculate r cl and replace r dson(max) with r sense . adp1828 v in m2 m1 l dh dl csl c out v out r cl r sense 06865-037 figure 36. accurate current-limit sensing feedback voltage divider the output regulation voltage is set through the feedback volt- age divider. the output voltage is divided down through the voltage divider and drives the fb feedback input. the regulation threshold at fb is 0.6 v. the maximum input bias current into fb is 100 na. for a 0.15% degradation in regulation voltage and with 100 na bias current, the low-side resistor, r bot , needs to be less than 9 k, which results in 67 a of divider current. for r bot , use a 1 k to 10 k resistor. a larger value resistor can be used, but results in a reduction in output voltage accuracy due to the input bias current at the fb pin, while lower values cause increased quiescent current consumption. choose r top to set the output voltage by using the following equation: ? ? ? ? ? ? ? ? ? = fb fb out bot top v vv rr (15) where: r top is the high-side voltage divider resistance. r bot is the low-side voltage divider resistance. v out is the regulated output voltage. v fb is the feedback regulation threshold, 0.6 v. compensating the voltage mode buck regulator assuming the lc filter design is complete, the feedback control system can then be compensated. good compensation is critical to proper operation of the regulator. calculate the quantities in equation 16 through equation 44 to derive the compensation values. the goal is to guarantee that the voltage gain of the buck converter crosses unity at a slope that provides adequate phase margin for stable operation. additionally, at frequencies above the crossover frequency (f co ), guaranteeing sufficient gain margin and attenuation of switching noise are important secondary goals. for initial practical designs, a good choice for the crossover frequency is one tenth of the switching frequency, calculate first 10 sw co f f = (16) this gives sufficient frequency range to design a compensation scheme that attenuates switching artifacts, while also giving sufficient control loop bandwidth to provide a good transient response. the output lc filter is a resonant network that inflicts two poles upon the response at a frequency (f lc ). next, calculate lc f lc 2 1 = (17) generally speaking, the lc corner frequency is about two orders of magnitude below the switching frequency, and therefore about one order of magnitude below crossover. to achieve sufficient phase margin at crossover to guarantee stability, the design must compensate for the two poles at the lc corner frequency with two zeros to boost the system phase prior to crossover. the two zeros require an additional pole or two above the crossover frequency to guarantee adequate gain margin and attenuation of switching noise at high frequencies.
adp1828 rev. c | page 22 of 36 depending on component selection, one zero might already be generated by the esr of the output capacitor. calculate this zero corner frequency, f esr , as out esr esr cr f 2 1 = (18) figure 37 shows a typical bode plot of the lc filter by itself. the gain of the lc filter at crossover can be linearly approximated from figure 37 as esr lc filter aaa += ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?= esr co lc esr filter f f f f a logdb20 logdb 40 (19) if f esr f co , then add another 3 db to account for the local difference between the exact solution and the linear approxi- mation in equation 19. 0db gain frequency phase f lc f esr f co f sw a filter ?40db/dec - filter 0 ?90 ?180 ?20db/dec 06865-038 figure 37. lc filter bode plot to compensate the control loop, the gain of the system must be brought back up so that it is 0 db at the desired crossover frequency. some gain is provided by the pwm modulation itself. ? ? ? ? ? ? ? ? = ramp in mod v v a log20 (20) for systems using the internal oscillator, this becomes (21) note that if the converter is being synchronized, the ramp voltage, v ramp , is lower than 1.0 v by the percentage of frequency increase over the nominal setting of the freq pin: ? ? ? ? ? ? ? ? = v0.1 log20 in mod v a ? ? ? ? ? ? ? = freq ramp f v v0.1 ? sync f (22) for example, if freq is grounded or connected to vreg, then f freq is 300 khz or 600 khz, respectively. if the frequency is set by a resistor, then f freq is 300 khz and f sync is the frequency set by the resistor. v ramp is greater than 1.0 v if f sync is less than f freq . the rest of the system gain needs to reach 0 db at cross- over. the total gain of the system, therefore, is given by a t = a mod + a filter + a comp (23) where: a mod is the gain of the pwm modulator. a filter is the gain of the lc filter including the effects of the esr zero. a comp is the gain of the compensated error amplifier. additionally, the phase of the system must be brought back up to guarantee stability. note from the bode plot of the filter that the lc contributes ?180 of phase shift (see figure 37 ). because the error amplifier is an integrator at low frequency, it contributes an initial ?90. therefore, before adding com- pensation or accounting for the esr zero, the system is already down ?270. to avoid loop inversion at crossover, or ?180 phase shift, a good initial practical design is to require a phase margin of 60, which is therefore an overall phase loss of ?120 from the initial low frequency dc phase. the goal of the com- pensation is to boost the phase back up from ?270 to ?120 at crossover. two common compensation schemes are used, which are sometimes referred to as type ii or type iii compensation, depending on whether the compensation design includes two or three poles (see the type ii compensator and type iii compensator sections). dominant-pole compensation, or single-pole compensation, is referred to as type i compensation, but it is not very useful for dealing successfully with switching regulators. if the zero produced by the esr of the output capacitor provides sufficient phase boost at crossover, type ii compensation is adequate. if the phase boost produced by the esr of the output capacitor is not sufficient, another zero is added to the compen- sation network, and thus type iii is used. in figure 38 , the location of the esr zero corner frequency gives a significantly different net phase at the crossover frequency.
adp1828 rev. c | page 23 of 36 use the following guidelines for selecting between type ii and type iii compensators: if 2 co esrz f f , use type ii compensation. if 2 co esrz f f > , use type iii compensation. gain frequency phase phase contribution at crossover of various esr zero corners f sw f co f esr3 f esr2 f esr1 0db f lc ?40db/dec ?20db/dec 0 ?90 ?180 - 1 - 2 - 3 06865-039 figure 38. lc filter bode plot the following equations are used for the calculation of the compensation components as shown in figure 39 and figure 40 : i z z1 cr f = 2 1 (24) ) (2 1 ff top ff z2 rrc f + = (25) hfi hfi z p1 cc cc r f + = 2 1 (26) ffff p2 cr f = 2 1 (27) where: f z1 is the zero produced in the type ii compensation. f z2 is the zero produced in the type iii compensation. f p1 is the pole produced in the type ii compensation. f p2 in the pole produced in the type iii compensation. type ii compensator f z f p c hf c i fb r z r bot r top v out internal vref ea comp ?1 s l o p e ?1 s l o pe phase ?180 ?270 g (db) 06865-040 figure 39. type ii compensation if the output capacitor esr zero frequency is sufficiently low (? of the crossover frequency), use the esr to stabilize the regulator. in this case, use the circuit shown in figure 39 . calculate the compensation resistor, r z , with the following equation: 2 lc in coesr ramp top z fv ffvr r = (28) where: f co is chosen to be 1/10 of f sw. v ramp is 1.0 v. next, choose the compensation capacitor to set the compensa- tion zero, f z1 , to the lesser of ? of the crossover frequency or ? of the lc resonant frequency i z sw co z1 cr ff f === 2 1 404 (29) or i z lc z1 f 22 cr f == 1 (30) solving for c i in equation 29 yields sw z i fr c = 20 (31) solving for c i in equation 30 yields lc z i fr c = 1 (32)
adp1828 rev. c | page 24 of 36 use the larger value of c i from equation 31 or equation 32. because of the finite output current drive of the error amplifier, c i needs to be less than 10 nf. if it is larger than 10 nf, choose a larger r top and recalculate r z and c i until c i is less than 10 nf. next, choose the high frequency pole, f p1 , to be ? of f sw . sw p1 ff 2 1 = (33) because c hf << c i , equation 26 is simplified to hf z p1 cr f = 2 1 (34) combine equation 33 and equation 34, and solve for c hf , z sw hf rf c = 1 (35) type iii compensator g (db) phase ?270 ?90 f z f p c hf c i r z c ff r top r bot v out internal vref fb ea comp r ff ? 1 s l o p e ? 1 s l o p e + 1 s l o p e 06865-041 figure 40. type iii compensation if the output capacitor esr zero frequency is greater than ? of the crossover frequency, use the type iii compensator as shown in figure 40 . set the poles and zeros as follows: sw p2p1 fff 2 1 == (36) i z sw co z2z cr ff ff ==== 2 1 404 1 (37) or i z lc z2z cr f ff === 2 1 2 1 (38) use the lower zero frequency from equation 37 or equation 38. calculate the compensator resistor, r z (39) next, calculate c i , 2 lc in co z1 ramp top z fv ffvr r = z1z i fr c = 2 1 (40) because of the finite output current drive of the error amplifier, c i needs to be less than 10 nf. if it is larger than 10 nf, choose a c i until c i is less than 10 nf. because c hf << c i , combining equation 26 and equation 36 yields larger r top and recalculate r z and z sw hf c = 1 rf (41) next, calculate the feedforward capacitor c ff . assuming r ff << lified to r top , then equation 25 is simp top ff z2 rc f = 2 1 (42) solving c ff in equation 42 yields z2top ff fr c = 2 1 (43) where f z2 is obtained from equation 37 or equation 38. the feedforward resistor, r ff , can be calculated by combining equation 27 and equation 36 sw ff ff fc r = 1 (44) check that the calculated component values are reasonable. for instance, capacitors smaller than about 10 pf should be avoided. in addition, the adp1828 error amplifier has a finite output current drive, so r z values less than 3 k and c i values greater than 10 nf should be avoided. if necessary, recalculate the compen- sation network with a different starting value of r top . if r z is too small or c i is too big, start with a larger value of r top . this com- pensation technique should yield a good working solution. olytic capacitors have high esr, and uate. however, if several aluminum electrolytic capacitors are connected in parallel, and produce a ve esr, then type iii compensation is needed. in addition, ceramic capacitors have very low esr (only a few milliohms) making type iii compensation a better choice. type iii compensation offers better performance than type ii in terms of more low frequency gain and more phase margin and less high frequency gain at the crossover frequency. in general, aluminum electr type ii compensation is adeq low effecti
adp1828 rev. c | page 25 of 36 soft start the adp1828 uses an adjustable soft start to limit the output voltage ramp-up period, limiting the input inrush current. the soft start is selected by setting the capacitor, c ss , from ss to gnd. the adp1828 charges c ss to 0.8 v through an internal 90 k resistor. the voltage on the soft start capacitor while it is charging is ? ? ? ? ? ? ? ? ?= ss c t css e v k 90 1v8. 0 (45) the soft start period ends when the voltage on the soft start pin reaches 0.6 v. substituting 0.6 v for v ss and solving for the soft start time t ss : ? ? ? ? ? ? ? ? ?= ss c t e k 90 1v8.0v6. 0 (46) ss ss rc t 386.1 = (47) because r = 90 k: secf/8 = ssss tc (48) where t ss is the desired soft start time in seconds. switching noise and overshoot reduction in any high speed step-down regulator, high frequency noise (generally in the range of 50 mhz to 100 mhz) and voltage overshoot are always present at the gate, the switch node (sw), and the drains of the external mosfets. the high frequency noise and overshoot are caused by the parasitic capacitance, c gd , of the external mosfet and the parasitic inductance of the gate trace and the packages of the mosfets. when the high current is switched, electromagnetic interference (emi) is generated, which can affect the operation of the surrounding circuits. to reduce voltage ringing at the drain of the mosfet, an rc snubber can be added between sw and pgnd, as illu- strated in figure 41 . in most applications, r snub is about 2 , and c snub about 1.2 nf. r snub and c snub can be calculated using the following equations: oss snub fc r = 2 1 (49) oss snub cc = (50) where: f is the high frequency ringing measured at the sw node. c oss is the total output capacitance of the top-side and low-side mosfets, given in the mosfet data sheet. the size of the rc snubber components need to be chosen correctly to handle the power dissipation. the power dissipated in r snub is: swsnub in snub fcvp 2 = in most applications, a size 0805 component is sufficient. the use of the rc snubber reduces the overall efficiency, generally by an amount in the range of 0.1% to 0.5%. however, the rc snubber cannot reduce the voltage overshoot. a resistor, shown as r rise in figure 41 , at the bst pin could help to reduce overshoot and is generally between 1 and 5 . dh sw csl dl pgnd m2 m1 l v out c out r snub c snub v in r cl adp1828 bst pv r rise 06865-042 figure 41. application circuit with a snubber the adp1828 includes a feature that tracks a master voltage. portant when multiple adp1828s s the adp1829) are powering sepa- rate power supply voltages, such as the core and i/o voltages of a dsp or microcontroller. in these cases, improper sequencing can cause damage to the load. the adp1828 tracking input is an additional positive input to the error amplifier. the feedback voltage is regulated to the lower of the 0.6 v reference, the ss voltage, or the voltage at trk, so a lower voltage on trk limits the output voltage. this feature allows implementation of two different types of tracking: coin- cident tracking, where the output voltage is the same as the master voltage until the master voltage reaches regulation, or ratiometric tracking, where the output voltage is limited to a fraction of the master voltage. in all tracking configurations, the final value of the master voltage should be higher than the slave voltage. note that the soft start time setting of the master voltage should be longer than the soft start of the slave voltage. this forces the e to be imposed on the slave voltage. slave voltage is longer, the slave acking relationship is not l should still have a soft start capacitor to give a small but reasonable soft start time to protect the part in case of restart after a current-limit event. voltage tracking this feature is especially im (or other controllers such a rise time of the master voltag if the soft start setting of the comes up more slowly and the tr seen at the output. the slave channe
adp1828 rev. c | page 26 of 36 comp fb trk ss master voltage r trkt r trkb 0.6v detail view of adp1828 error amplifier v out r top r bot 06865-043 figure 42. voltage tracking coincident tracking the most common application is coincident tracking, used in core vs. i/o voltage sequencing and similar applications. coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. connect the slave trk input to a resistor divider from the master voltage that is the same as the divider used on the slave fb pin. this forces the slave voltage to be the same as the master voltage. for coincident tracking, use the following equation: r trkt = r top and r trkb = r bot where: r top and r bot are the values chosen in the compensating the volt age mo de buck r egu lator section . see figure 43 for an example of a coincident tracking circuit. fb trk ss r trkb 10k ? r trkt 20k ? 1.1v adp1828 or adp1829 fb power components power components adp1828 en en ss r top 20k ? r bot 10k ? c ss 1f c ss 150nf 3.3v v out_master 1.8v v out_slave 0 6865-044 figure 43. example of a coincident tracking circuit time slave voltage master voltage voltage 06865-045 figure 44. coincident tracking ch1 5.00v ch3 1.00v ch2 1.00v m 100ms a ch1 2.60v 1 4 ch4 1.00v v out_master en for both adp1828 v out_slave trk_slave b w b w b w 06865-046 figure 45. coincident tracking of figure 43 as the master voltage rises, the slave voltage also rises in the same pattern. eventually, the slave voltage reaches its regulation voltage, where the internal reference takes over the regulation while the trk input continues to increase and thus removes itself from influencing the output voltage. to ensure that the output voltage accuracy is not compromised by the trk pin being too close in voltage to the 0.6 v reference, make sure that the final value of the master voltage is greater than the slave regulation voltage by at least 10%, or 60 mv as seen at the fb node (the higher, the better). a difference of 60 mv between trk and the 0.6 v reference produces about 3 mv of offset in the error amplifier, or 0.5%, at room temperature, while 100 mv between them produces only 0.6 mv or 0.1% offset. for accurate tracking, set the final voltage at trk to less than or equal to 0.5 v. however, this condition would trip the pgood signal. ratiometric tracking ratiometric tracking limits the output voltage to a fraction of the master voltage. for example, the termination voltage for ddr memories (vtt) is set to half the vddq voltage. time slave voltage master voltage voltage 0 6865-047 figure 46. ratiometric tracking for ratiometric tracking, the simplest configuration is to tie the trk pin of the slave channel to the fb pin of the master channel. the advantage of this is having the fewest components, but the accuracy suffers as the trk pin voltage becomes equal to the internal reference voltage and an offset is imposed on the error amplifier of about ?18 mv at room temperature.
adp1828 rev. c | page 27 of 36 a more accurate solution is to provide a divider from the master voltage that sets the trk pin voltage to be something lower than 0.6 v at regulation, for example, 0.5 v. the slave channel can be viewed as having a 0.5 v external reference supplied by the master voltage. keep in mind that pgood is tripped when the trk voltage is set to less than 0.55 v. once this is complete, the fb divider for the slave voltage is designed as in the compensating the voltage mode buck regulator section except to substitute the 0.5 v reference for the v fb voltage. the ratio of the slave output voltage to the master voltage is a function of the two dividers: ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + = trkb trkt bot top master out r r r r v v 1 1 (51) figure 47 shows an example of ratiometric tracking circuit and figure 48 shows its voltage tracking waveforms. fb trk ss r trkb 10k ? r trkt 49.9k ? 0.55v adp1828 or adp1829 fb power components power components adp1828 en en ss r top 22.6k ? r bot 10k ? c ss 1f c ss 150nf 3.3v v out_master 1.8v v out_slave 0 6865-048 figure 47. an example of a ratiometric tracking circuit ch1 5.00v ch3 1.00v ch2 1.00v m 100ms a ch1 2.60v 1 4 ch4 1.00v v out_master en for both adp1828 v out_slave trk_slave b w b w b w 06865-049 figure 48. ratiometric tracking of figure 47 another option is to add another tap to the divider for the master voltage. split the r bot resistor of the master voltage into two pieces, with the new tap at 0.5 v when the master voltage is in regulation. this saves one resistor, but be aware that type iii compensation on the master voltage causes the feedforward signal of the master voltage to appear at the trk input of the slave channel. figure 49 shows an example of ddr memory termination application circuit, where the ddr memory termination voltage, vtt, is ? of vddq. vtt can sink current during the off cycle of the adp1828. the output waveform in figure 50 shows that vtt changes by one-half of the output change in vddq. fb trk ss r trkb 10k ? r trkt 40.2k ? 0.5v adp1828 or adp1829 fb power components power components adp1828 en en ss r top 15k ? r bot 10k ? c ss 1f c ss 150nf 2.5v vddq 1.25v vtt 06865-050 figure 49. an example of a ddr termination circuit ch1 500mv ch3 500mv ch2 100mv m 200s a ch1 50.0mv 3 2 1 vddq (2.5v 0.25v, ac-coupled) vtt (1.25v 0.125v, ac-coupled) trk b w b w b w t 06865-051 figure 50. ddr terminatio n; output waveforms of figure 49 in addition, by selecting the resistor values in the divider carefully, equation 51 shows that the slave voltage output can be made to have a faster ramp rate than that of the master voltage by setting the trk voltage at the slave larger than 0.6 v and r trkb greater than r trkt . make sure that the master ss period is long enough (that is, use a sufficiently large ss capacitor) such that the input inrush current does not run into the current limit of the power supply during startup. ch1 5.00v ch3 1.00v ch2 1.00v m 100ms a ch1 2.60v 1 4 ch4 1.00v v out_master en for both adp1828 trk_slave b w b w b w v out_slave 0 6865-052 figure 51. ratiometric tracking of figure 47 with r trkt = 5 k
adp1828 rev. c | page 28 of 36 thermal considerations the current required to drive the external mosfets comprises the vast majority of the power dissipation of the adp1828. the on-chip ldo regulates down to 5 v, and this 5 v supplies the drivers. the full gate drive current passes through the ldo and is then dissipated in the gate drivers. the power dissipated in the gate drivers on the adp1828 is ) ( dl dh sw ind qqfvp + = (52) where: v in is the voltage applied to in. f sw is the switching frequency. q numbers are the total gate charge specifications from the selected mosfet data sheets. the power dissipation heats up the adp1828. as the switching frequency, the input voltage, and the mosfet size increase, the power dissipation on the adp1828 increases. care must be taken not to exceed the maximum junction temperature. to calculate the junction temperature from the ambient temperature and power dissipation, use the following formula: ja d a j ptt + = (53) the thermal resistance ( ja ) of the package is 83c/w depending on board layout, and the maximum specified junction temperature ans that at maximum ambient temperature of 85c without airflow, the maximum dissipation allowed is about 1 w. a thermal shutdown protection circuit on the adp1828 shuts off the ldo and the controllers if the die temperature exceeds approximately 145c, but this is a gross fault protection only and should not be depended on for system reliability. is 125c, which me
adp1828 rev. c | page 29 of 36 pcb layout guideline in any switching converter, there are some circuit paths that carry high di/dt, which can create spikes and noise. other circuit paths are sensitive to noise. while other circuits carry high dc current and can produce significant ir voltage drops. the key to proper pcb layout of a switching converter is to identify these critical paths and arrange the components and the copper area accordingly. when designing pcb layouts, be sure to keep high current loops small. in addition, keep compensation and feedback components away from the switch nodes and their associated components. the following is a list of recommended layout practices for the synchronous buck controller arranged by decreasing order of importance: ? the current waveform in the top and bottom fets is a pulse with very high di/dt, so the path to, through, and from each individual fet should be as short as possible and the two paths should be commoned as much as possible. in designs that use a pair of d-pak or a pair of so-8 fets on one side of the pcb, it is best to counter-rotate the two so that the switch node is on one side of the pair and the high-side drain can be bypassed to the low-side source with a suitable ceramic bypass capacitor, placed as close as possible to the fets in order to minimize inductance around this loop through the fets and capacitor. the recom- mended bypass ceramic capacitor values range from 1 f to 22 f depending upon the output current. this bypass capacitor is usually connected to a larger value bulk filter capacitor and should be grounded to the pgnd plane. ? the negative terminals of gnd, in bypass, and a soft start capacitor (as well as the bottom end of the output feedback divider resistors) should be tied to an almost isolated small agnd plane. all of these connections should attach from their respective pins to the agnd plane that are as short as possible. no high current or high di/dt signals should be connected to this agnd plane. the agnd area should be connected through one wide trace to the negative terminal of the output filter capacitors. ? the pgnd pin handles a high di/dt gate drive current returning from the source of the low-side mosfet. the voltage at this pin also establishes the 0 v reference for the overcurrent limit protection function and the csl pin. a pgnd plane should connect the pgnd pin and the pv bypass capacitor, 1 f, through a wide and direct path to the source of the low-side mosfet. the placement of c in is critical for controlling ground bounce. the negative terminal of c in needs to be placed very close to the source of the low-side mosfet. ? avoid long traces or large copper areas at the fb and csl pins, which are low signal level inputs that are sensitive to capacitive and inductive noise pickup. it is best to position any series resistors and capacitors as closely as possible to these pins. avoid running these traces close and/or parallel to high di/dt traces. ? the switch node is the noisiest place in the switcher circuit with large ac and dc voltages and currents. this node should be wide to keep resistive voltage drop down. but, to minimize the generation of capacitively coupled noise, the total area should be small. place the fets and inductor close together on a small copper plane in order to minimize series resistance and keep the copper area small. ? gate drive traces (dh and dl) handle high di/dt and tend to produce noise and ringing. they should be as short and direct as possible. if possible, avoid using feedthrough vias in the gate drive traces. if vias are needed, it is best to use two relatively large ones in parallel to reduce the peak current density and the current in each via. if the overall pcb layout is less than optimal, slowing down the gate drive slightly can be very helpful to reduce noise and ringing. it is occasionally helpful to place small value resistors (such as 5 or10 ) in between the dh and dl pins and their respective mosfet gates. these can be populated with 0 resistors if resistance is not needed. note that the added gate resistance increases the switching rise and fall times as well as switching power loss in the mosfet. ? the negative terminal of the output filter capacitors should be tied closely to the source of the low-side fet. doing this helps to minimize voltage differences between gnd and pgnd. ? all traces should be sized according to the current that is handled as well as their sensitivity in the circuit. standard pcb layout guidelines mainly address the heating effects of a current in a copper conductor. while these are completely valid, they do not fully cover other concerns such as stray inductance or dc voltage drop. any dc voltage differential in connections between adp1828 gnd and the converter power output ground can cause a significant output voltage error, as it affects converter output voltage according to the ratio with the 600 mv feedback reference. for example, a 6 mv offset between ground on the adp1828 and the converter power output causes a 1% error in the converter output voltage.
adp1828 rev. c | page 30 of 36 to achieve an accurate output voltage, proper grounding of the agnd and pgnd planes is needed. for light to medium loads, connecting the agnd plane to the pgnd plane with a trace is adequate in obtaining good output accuracy (see figure 52 ). if the pgnd plane is large enough and under a light to medium load, the voltage drop across the pgnd plane is negligible. however, under a heavy load, such as at 20 a, the voltage drop across the pgnd plane could be significant, thus affecting the accuracy of the output. the agnd plane would then have to be routed directly to the negative terminal of the load and the power supply, as illustrated in figure 53 . the power supply gnd terminal and the load gnd terminal should be placed as close as possible to each other to minimize the voltage drop across these two terminals, thus improving the output accuracy. power supply gnd terminal is connected to pgnd plane. agnd plane pgnd plane v out load power supply gnd terminal 0 6865-053 figure 52. grounding technique for a light to medium load power supply gnd terminal is connected to pgnd plane. agnd plane pgnd plane small agnd trace v out load power supply gnd terminal 0 6865-054 figure 53. proper grounding technique for a heavy load recommended component manufacturers table 5. vendor components avx corporation capacitors central semiconductor corp. diodes coilcraft, inc. inductors diodes, inc. diodes international rectifier diodes, mosfets murata manufacturing co., ltd. capacitors, inductors on semiconductor diodes, mosfets rubycon corporation capacitors sanyo capacitors sumida corporation inductors taiyo yuden, inc. capacitors, inductors toko america, inc. inductors united chemi-con, inc. capacitors vishay siliconix diodes, mosfets, resistors, capacitors wurth elektronic inductors
adp1828 rev. c | page 31 of 36 application circuits in vreg en freq sync pgood comp ss c ss 100nf l1 = 1.0h m1a m1b c in 22f 6.3v 3 dh bst sw csl dl pgnd clkout clkset fb c4 0.22f pv trk adp1828 r4 3k? v in = 3.3 v output 1.2v, 5a c6 1f r8 8.06k ? c3 3.3nf pgnd agnd c2 68pf r1 10k ? r3 210? r2 10k? d1 c out1 100f 6.3v c out2 47f 6.3v c1 1.8nf r6 100k ? c5 1f gnd agnd f sw = 600khz c in : ceramic, 22f/6.3v/x5r/0805 c out1 : ceramic, 100f/6.3v/x5r/1210 c out2 : ceramic, 47f/6.3v/x5r/1206 l1: toko, fdv0630-1r0m d1: bat54 m1a, m1b: vishay, dual-fet si7940dp 06865-055 figure 54. application circuit for v in = 3.3 v, all ceramic solution in vreg en freq sync pgood comp ss c ss 100nf l1 = 1.8h m1a m1b c in 22f 16v dh bst sw csl dl pgnd clkout clkset fb c4 0.22f pv trk adp1828 r4 2.8k ? v in = 10v to 13 v output 3.3v, 4a c6 1f r8 6.04k ? c3 4.7nf gnd pgnd agnd agnd c2 120pf r1 20k? r3 412? r2 4.42k ? d1 c out 100f 6.3v c1 1.0nf r6 100k ? c5 1f c7 1f f sw = 600khz c in : ceramic, 22f/6.3v/x5r/1210 c out : ceramic, 100f/6.3v/x5r/1210 l1: toko, fdv0630-1r8m d1: vishay, bat54 m1a, m1b: vishay, dual-fet si7958dp 06865-056 figure 55. application circuit for v in = 12 v, all ceramic solution
adp1828 rev. c | page 32 of 36 in vreg en freq sync pgood comp ss c ss 100nf l1 = 1h m1 m2 c in 270f 16v 2 dh bst sw csl dl pgnd clkout clkset fb c4 0.47f pv trk adp1828 r4 3.3k ? v in = 2.5v to 8v output 1.0v, 15a c6 1f r8 4.99k ? c3 4.7nf pgnd agnd c2 220pf r1 10k? r3 210 ? r2 15k? d1 c out1 10f 6.3v c out2 820f 2.5v 2 c1 1.8nf r6 100k ? v bias = 5 v c5 1f gnd agnd f sw = 300khz c in : sanyo, oscon 16sp270m c out2 : sanyo, oscon 2r5sepc820m l1: coiltronics, hc7-1r0 m1: infineon bsc080n03ls m2: infineon bsc030n03ls d1: vishay, bat54 0 6865-057 figure 56. application circuit for v in = 2.5 v to 8 v in vreg en freq sync pgood comp ss c ss 200nf l1 = 0.47h m1 2 m2 2 c in 180f 20v 3 dh bst sw csl dl pgnd clkout clkset fb c4 0.47f pv trk adp1828 r4 2.2k ? v in = 10v to 18 v output 1.8v, 27a c6 1f r8 26.1k ? c3 2.7nf pgnd agnd c2 47pf r1 20k? r3 6.49k ? r2 10k? d1 c out1 47f 6.3v c out2 1000f 3 c1 680nf r6 100k ? c7 1f c5 1f gnd agnd d1: vishay, bat54 m1: infineon, 2 bsc080n03ls m2: infineon, 2 bsc030n03ls f sw = 300khz c in : sanyo, oscon 20sp180m c out2 : sanyo, poscap 2r5tpd1000m5 l1: wurth elektronic, 0.47h, 744355147 0 6865-058 figure 57. application circuit with 27 a output
adp1828 rev. c | page 33 of 36 outline dimensions compliant to jedec standards mo-137-ad controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 20 11 10 1 seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.041 (1.04) ref 0.010 (0.25) 0.006 (0.15) 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 8 0 coplanarity 0.004 (0.10) 0.065 (1.65) 0.049 (1.25) 0.069 (1.75) 0.053 (1.35) 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 08-19-2008-a figure 58. 20-lead shrink small outline package [qsop] (rq-20) dimensions shown in inches and (millimeters) 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant to jedec standards mo-220-wggd. 061609-b bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 2.65 2.50 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 figure 59. 20-lead lead frame chip scale package (lfcsp_wq) 4 mm 4 mm body, very very thin quad (cp-20-10) dimensions shown in millimeters
adp1828 rev. c | page 34 of 36 ordering guide model 1 notes temperature range 2 package description package option adp1828yrqz-r7 ?40c to +85c 20-lead sh rink small outline package [qsop] rq-20 adp1828acpz-r7 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-10 adp1828lc-evalz evaluation board (with qsop) with 5 a output adp1828hc-evalz evaluation board (with qsop) with 20 a output adp1828-bl1-evz 3 low current blank evaluation board, qsop (0 a to 20 a) adp1828-bl2-evz 3 high current blank evaluation board, qsop (20 a to 30 a) 1 z = rohs compliant part. 2 operating junction temper ature is C40 c to +125c. 3 users can generate schematic design and build of materials from the analog devices, inc., adisimpower?, at www.analog.com/adisimpower .
adp1828 rev. c | page 35 of 36 notes
adp1828 rev. c | page 36 of 36 notes ?2007C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06865-0-11/10(c)

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