november 2013 ?2013 fairchild semiconductor corporation FDMC86261P rev.c1 www.fairchildsemi.com 1 FDMC86261P p-channel powertrench ? mosfet s s s g d d d d bottom d d d d s s s g top pin 1 mlp 3.3x3.3 FDMC86261P p-channel powertrench ? mosfet -150 v, -9 a, 160 m features ? max r ds(on) = 160 m at v gs = -10 v, i d = -2.4 a ? max r ds(on) = 185 m at v gs = -6 v, i d = -2.2 a ? very low rds-on mid voltage p channel silicon technology optimised for low qg ? this product is optimised for fa st switching applications as well as load switch applications ? 100% uil tested ? rohs compliant general description this p-channel mosfet is produced using fairchild semiconductor?s advanced powertrench ? technology. this very high density process is es pecially tailored to minimize on-state resistance and optimi zed for superior switching performance. applications ? active clamp switch ? load switch mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol paramete r ratings units v ds drain to source voltage -150 v v gs gate to source voltage 25 v i d drain current -continuous t c = 25 c -9 a -continuous t a = 25 c (note 1a) -2.7 -pulsed -20 e as single pulse avalanche energy (note 3) 121 mj p d power dissipation t c = 25 c 40 w power dissipation t a = 25 c (note 1a) 2.3 t j , t stg operating and storage junction temperature range -55 to + 150 c r jc thermal resistance, junction to case 3.1 c/w r ja thermal resistance, junction to ambient (note 1a) 53 device marking device package reel size tape width quantity FDMC86261P FDMC86261P power 33 13?? 12 mm 3000 units
www.fairchildsemi.com 2 ?2013 fairchild semiconductor corporation FDMC86261P rev.c1 FDMC86261P p-channel powertrench ? mosfet electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = -250 a, v gs = 0 v -150 v bv dss t j breakdown voltage temperature coefficient i d = -250 a, referenced to 25 c -132 mv/c i dss zero gate voltage drain current v ds = -120 v, v gs = 0 v -1 a i gss gate to source leakage current v gs = 25 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = -250 a-2-3-4v v gs(th) t j gate to source threshold voltage temperature coefficient i d = -250 a, referenced to 25 c 6 mv/c r ds(on) static drain to source on resistance v gs = -10 v, i d = -2.4 a 130 160 m v gs = -6 v, i d = -2.2 a 141 185 v gs = -10 v, i d = -2.4 a,t j = 125 c 218 269 g fs forward transconductance v ds = -10 v, i d = -2.4 a 9 s c iss input capacitance v ds = -75 v, v gs = 0 v, f = 1 mhz 1021 1360 pf c oss output capacitance 87 120 pf c rss reverse transfer capacitance 4.7 10 pf r g gate resistance 0.1 1.7 3.4 t d(on) turn-on delay time v dd = -75 v, i d = -2.4 a, v gs = -10 v, r gen = 6 11 20 ns t r rise time 2.4 10 ns t d(off) turn-off delay time 18 33 ns t f fall time 9.2 20 ns q g(tot) total gate charge v gs = 0 v to -10 v v dd = -75 v, i d = -2.4 a 17 24 nc q g(tot) total gate charge v gs = 0 v to -6 v 11 16 nc q gs total gate charge 4.2 nc q gd gate to drain ?miller? charge 3.7 nc v sd source to drain diode forward voltage v gs = 0 v, i s = -2.4 a (note 2) -0.81 -1.3 v v gs = 0 v, i s = -1.9 a (note 2) -0.80 -1.2 v t rr reverse recovery time i f = -2.4 a, di/dt = 100 a/ s 81 130 ns q rr reverse recovery charge 197 315 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. starting t j = 25 c; p-ch: l = 3 mh, i as = -9 a, v dd = -150 v, v gs = -10 v. 100% test at l = 0.1 mh, i as = -28 a. a) 53 c/w when mounted on a 1 in 2 p a d o f 2 o z c o p p e r b) 125 c/w when mounted on a minimum pad of 2 oz copper g df ds sf ss g df ds sf ss
www.fairchildsemi.com 3 ?2013 fairchild semiconductor corporation FDMC86261P rev.c1 FDMC86261P p-channel powertrench ? mosfet typical characteristics t j = 25 c unless otherwise noted figure 1. 012345 0 5 10 15 20 v gs = -5.5 v v gs = -5 v v gs = -6 v pulse duration = 80 p s duty cycle = 0.5% max v gs = -4.5 v v gs = -10 v -i d , drain current (a) -v ds , drain to source voltage (v) on region characteristics figure 2. 0 5 10 15 20 0 1 2 3 4 v gs = -5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance -i d , drain current (a) v gs = -5.5 v v gs = -6 v v gs = -4.5 v v gs = -10v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 i d = -2.4 a v gs = -10v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 45678910 0 100 200 300 400 500 t j = 125 o c i d = -2.4 a t j = 25 o c -v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 23456 0 5 10 15 20 t j = 150 o c v ds = -10 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c -i d , drain current (a) -v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 100 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v -i s , reverse drain current (a) -v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
www.fairchildsemi.com 4 ?2013 fairchild semiconductor corporation FDMC86261P rev.c1 FDMC86261P p-channel powertrench ? mosfet figure 7. 048121620 0 2 4 6 8 10 i d = -2.4 a v dd = -100 v v dd = -50 v -v gs , gate to source voltage (v) q g , gate charge (nc) v dd = -75 v gate charge characteristics figure 8. 0.1 1 10 100 1 10 100 1000 10000 f = 1 mhz v gs = 0 v capacitance (pf) -v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 20 1 10 50 t j = 125 o c t j = 25 o c t j = 100 o c t av , time in avalanche (ms) -i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 3 6 9 12 v gs = -6 v limited by package r t jc = 3.1 o c/w v gs = -10 v -i d , drain current (a) t c , case temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs case temperature fi g ure 11 . fo rw ard bi as safe op erating area 0.1 1 10 100 500 0.005 0.01 0.1 1 10 30 1 s curve bent to measured data 100 p s 10 ms dc 10 s 100 ms 1 ms -i d , drain current (a) -v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c f i g u r e 1 2 . s i n g l e p u l s e m a x i m u m power dissipation 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.5 1 10 100 1000 single pulse r t ja = 125 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) typical characteristics t j = 25 c unless otherwise noted
www.fairchildsemi.com 5 ?2013 fairchild semiconductor corporation FDMC86261P rev.c1 FDMC86261P p-channel powertrench ? mosfet figure 13. 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 2 single pulse duty cycle-descending order r(t), normalized effective transient thermal resistance t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: z t ja (t) = r(t) x r t ja r t ja = 125 o c/w duty cycle, d = t 1 / t 2 peak t j = p dm x z t ja (t) + t a junction-to-ambient transient thermal response curve typical characteristics t j = 25 c unless otherwise noted
www.fairchildsemi.com 6 ?2013 fairchild semiconductor corporation FDMC86261P rev.c1 FDMC86261P p-channel powertrench ? mosfet dimensional outline and pad layout b. dimensions are in millimeters. c. dimensions and tolerances per a. does not conform to jedec registration mo-229 asme y14.5m, 1994 0. 10 cab 0. 05 c top view bottom view recommended land pattern 0.10 c 0. 08 c b a 3.30+0.10 3.30+0.10 0.05 0.00 0. 10 c 2x 2x 0.8 max side view seating plane 0.10 c pin #1 ident (0.20) 8 5 1.95 0.65 e. drawing file name : mkt-mlp08srev2 pin#1 quadrant 0.35+0.05 4 1 (8x) d. land pattern recommendation is based on fsc design only 2.27+0.05 0.50+0.05 (4x) (1.15) 0.30+0.05 2.00 +0.05 (0.35) r0.15 (0.79) f. fairchild semiconductor (3x) keep out area (3.40) 2.37 0.45(4x) (1.70) 2.152 (0.648) 0.42(8x) 0.70(4x) 0.65 1.95 (0.402) 4 1 85
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