1. product profile 1.1 general description the blm8g0710s-45ab(g) is a dual secti on, asymmetric, 2-stage power mmic using nxp?s state of the art gen8 ldmos technology. this multiband device is perfectly suited as small cell final stage in doherty configuration, or as general purpose driver in the 700 mhz to 1000 mhz frequency range. available in gull wing or straight lead outline. [1] i dq1 represents driver stage; i dq2 represents final stage. 1.2 features and benefits ? designed for broadband operation (frequency 700 mhz to 1000 mhz) ? high section-to-section isolatio n enabling multip le combinations ? high doherty efficiency thanks to 2 : 1 asymmetry ? integrated temperature compensated bias ? biasing of individual stages is externally accessible ? integrated esd protection ? excellent thermal stability ? high power gain ? on-chip matching for ease of use ? compliant to directive 2002/ 95/ec, regarding restricti on of hazardous substances (rohs) 1.3 applications ? rf power mmic for w-cdma base stations in the 700 mhz to 1000 mhz frequency range. possible circuit topologies are the following as also depicted in section 8.1 : ? asymmetric final stage in doherty configuration ? asymmetric driver for high power doherty amplifier blm8g0710s-45ab; blm8g0710s-45abg ldmos 2-stage power mmic rev. 1 ? 20 august 2015 objective data sheet table 1. performance typical rf performance at t case = 25 ? c. test signal: 3gpp test mo del 1; 64 dpch; par = 9.9 db at 0.01% probability on ccdf; specified in a class-ab production circuit. test signal f i dq1 [1] i dq2 [1] v ds p l(av) g p ? d acpr 5m (mhz) (ma) (ma) (v) (w) (db) (%) (dbc) single carrier w-cdma carrier section 957.5 30 120 28 3 35 27 ? 41.5 peaking section 957.5 60 240 28 6 35.2 24.5 ? 40
blm8g0710s-45ab_s-45abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. objective data sheet rev. 1 ? 20 august 2015 2 of 20 nxp semiconductors blm8g0710s-45ab(g) ldmos 2-stage power mmic 2. pinning information 2.1 pinning 2.2 pin description transparent top view the exposed backside of the package is the ground terminal of the device. fig 1. pin configuration d d d 9 ' 6 $ 9 ' 6 % 9 * 6 $ 9 * 6 % 9 * 6 $ 5 ) b 2 8 7 b $ 9 ' 6 $ 5 ) b 2 8 7 b % 9 ' 6 % 9 * 6 % 5 ) b , 1 b $ 5 ) b , 1 b % q f q f q f q f q f q f s l q l q g h [ table 2. pin description symbol pin description v ds(a1) 1 drain-source voltage of carrier section, driver stage (a1) v gs(a2) 2 gate-source voltage of carrier section, final stage (a2) v gs(a1) 3 gate-source voltage of carrier section, driver stage (a1) rf_in_a 4 rf input ca rrier section (a) n.c. 5 not connected n.c. 6 not connected n.c. 7 not connected n.c. 8 not connected n.c. 9 not connected n.c. 10 not connected rf_in_b 11 rf input peaking section (b) v gs(b1) 12 gate-source voltage of peaking section, driver stage (b1) v gs(b2) 13 gate-source voltage of peaking section, final stage (b2) v ds(b1) 14 drain-source voltage of peaki ng section, driver stage (b1)
blm8g0710s-45ab_s-45abg all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2015 . all rights reserved. objective data sheet rev. 1 ? 20 august 2015 3 of 20 nxp semiconductors blm8g0710s-45ab(g) ldmos 2-stage power mmic 3. ordering information 4. block diagram 5. limiting values [1] continuous use at maximum temperature will affect the re liability. for details refer to the online mtf calculator. rf_out_b/v ds(b2) 15 rf output peaking section (b) / drain-source voltage of peaking section, final stage (b2) rf_out_a/v ds(a2) 16 rf output carrier section (a) / drain-source voltage of carrier section, final stage (a2) gnd flange rf ground table 2. pin description ?continued symbol pin description table 3. ordering information type number package name description version blm8g0710s-45ab hsop16f plastic, heatsink smal l outline package; 16 leads(flat) sot1211-2 blm8g0710s-45abg hsop16 plastic, heatsink small outline package; 16 leads sot1212-2 fig 2. block diagram d d d 9 ' 6 $ 9 ' 6 % 9 * 6 $ 5 ) b 2 8 7 b $ 9 ' 6 $ 5 ) b 2 8 7 b % 9 ' 6 % 9 * 6 % 5 ) b , 1 b $ 5 ) b , 1 b % 7 ( 0 3 ( 5 $ 7 8 5 ( & |