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MP38872 6a, 21v, 600khz step-down converter with synchronizable gate driver MP38872 rev.1.11 www.monolithicpower.com 1 9/21/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. the future of analog ic technology description the MP38872 is a monolithic step-down switch mode converter with a built in high-side internal power mosfet and a gate driver for a low-side external mosfet. it achieves 6a continuous output current over a wide input supply range with excellent load and line regulation. current mode operation provides fast transient response and reliable over-current protection. the MP38872 requires a minimum number of readily available standard external components and is available in a 14-pin qfn 3x4 package with exposed pad. features ? wide 4.5v to 21v operating input range ? 6a output current ? 45m ? internal power mosfet switch ? power good indicator ? synchronizable gate driver delivers up to 95% efficiency ? fixed 600khz frequency ? synchronizable to >1mhz external clock ? cycle-by-cycle over current protection ? thermal shutdown ? output adjustable from 0.8v ? stable with low esr output ceramic capacitors ? available in a thermally enhanced 14-pin qfn 3x4 package applications ? point of load regulator in distributed power system ? digital set top boxes ? personal video recorders ? broadband communications ? flat panel television and monitors for mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application MP38872 sw bg fb bst 8, 9, 10 13 1 14 11 gnd in vcc pg en/sync 4, 5, 6 12 3 v out 3.3v c4 1uf 16v m2 v in 2 power good off on c1 22uf 25v c3 1uf 16v l1 2.2uh r1 40.2k r3 100k r2 13k c2 100uf 6.3v v out =3.3v v in =12v v in =20v 100 95 90 85 80 75 70 65 60 55 50 efficiency (%) 0123456 output current (a) efficiency vs output current
MP38872 ? 6a, 21v, 600khz step-down with synchronizable gate driver MP38872 rev.1.11 www.monolithicpower.com 2 9/21/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. ordering information part number* package top marking free air temperature (t a ) MP38872dl qfn14 (3x4) 38872 ?40 c to +85 c * for tape & reel, add suffix ?z (e.g. MP38872dl?z); for rohs compliant packaging, add suffix ?lf (e.g. MP38872dl?lf?z) package reference absolute maxi mum ratings (1) supply voltage v in ....................................... 23v v sw ........................-0.3v (-5v for < 10ns) to 24v v bs - v sw ......................................................... 6v all other pins .................................?0.3v to +6v continuous power dissipation (t a = +25c) (2) qfn14l (3mm x 4mm) .............................. 2.6w junction temperature ...............................150 c lead temperature ....................................260 c storage temperature.............. ?65 c to +150 c recommended operating conditions (3) supply voltage v in ...........................4.5v to 21v output voltage v out .........................0.8v to 15v maximum junction temp. (t j ). ...............+125 c thermal resistance (4) ja jc qfn14l (3mm x 4mm) ........... 48 ...... 11... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max)- t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd5 1-7, 4-layer pcb. pin 1 id exposed pad on backside 14 13 12 11 10 9 8 gnd bg vcc bst sw sw sw fb pg en/sync in in in n/c 1 2 3 4 5 6 7 top view
MP38872 ? 6a, 21v, 600khz step-down with synchronizable gate driver MP38872 rev.1.11 www.monolithicpower.com 3 9/21/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. electrical characteristics v in = 12v, t a = +25 c, unless otherwise noted. parameters symbol condition min typ max units feedback voltage v fb 4.5v v in 23v 0.795 0.808 0.821 v feedback current i fb v fb = 0.8v 10 na switch on resistance (5) r ds(on) 45 m ? switch leakage v en = 0v, v sw = 0v 0 10 a current limit (5) 7.5 8.0 a oscillator frequency f sw v fb = 0.6v 600 khz fold-back frequency v fb = 0v 150 khz maximum duty cycle v fb = 0.6v 85 90 % minimum on time (5) t on 100 ns under voltage lockout threshold rising v cc_uvlo 3.9 4.1 4.3 v under voltage lockout threshold hysteresis 880 mv en input low voltage 0.4 v en input high voltage 1.2 v v en = 2v 2 en input current v en = 0v 0 a sync frequency range (low) f syncl 300 khz sync frequency range (high) f synch 1.5 mhz enable turnoff delay t off 5.0 us supply current (shutdown) v en = 0v 1 10 a supply current (quiescent) v en = 2v, v fb = 1v 0.9 ma thermal shutdown t j 150 c thermal shutdown hysteresis 10 c bg driver bias supply voltage v cc 4.5 5 v gate driver sink impedance (5) r sink 1 ? gate driver source impedance (5) r source 4 ? gate drive current sense trip threshold 20 mv power good control power good threshold rising 0.69 0.74 0.79 v power good threshold hysteresis 40 mv pg pin level v pg pg sink 4ma 0.4 v note: 5) guaranteed by design.
MP38872 ? 6a, 21v, 600khz step-down with synchronizable gate driver MP38872 rev.1.11 www.monolithicpower.com 4 9/21/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. pin functions pin # name description 1 fb feedback. an external resistor divider from the output to gnd, tapped to the fb pin sets the output voltage. to prevent current limit run away during a short circuit fault condition the frequency foldback comparator lowers the oscillator frequency when the fb voltage is below 250mv. 2 pg power good indicator. the output of this pin is low if the output voltage is 10% less than the nominal voltage; otherwise it is an open drain. 3 en/sync on/off control and external frequency synchronization input. 4, 5, 6 in supply voltage. the MP38872 operates from a +4.5v to +21v unregulated input. c1 is needed to prevent large voltage spikes from appearing at the input. 7 n/c no connect 8, 9, 10 sw switch output. 11 bst bootstrap. this capacitor is needed to dr ive the power switch?s gate above the supply voltage. it is connected between sw and bs pins to form a floating supply across the power switch driver. a 1f capacitor is recommended for use. 12 vcc bg driver bias supply. decouple with a 1f ceramic capacitor. x7r or x5r grade dielectric ceramic capacitors are recommended for t heir stable temperature characteristics. 13 bg gate driver output. connect this pi n to the gate of the synchronous mosfet. 14 gnd ground. this pin is the voltage reference for the regulated output voltage. for this reason care must be taken in its layout. this node should be placed outside of the m2 to c1 ground path to prevent switching current spikes from inducing voltage noise into the part.
MP38872 ? 6a, 21v, 600khz step-down with synchronizable gate driver MP38872 rev.1.11 www.monolithicpower.com 5 9/21/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. typical performanc e characteristics v in = 12v, v out = 2.5v, l = 2.2h, t a = +25oc, unless otherwise noted.
MP38872 ? 6a, 21v, 600khz step-down with synchronizable gate driver MP38872 rev.1.11 www.monolithicpower.com 6 9/21/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. typical performanc e characteristics (continued) v in = 12v, v out = 2.5v, l = 2.2h, t a = +25oc, unless otherwise noted. enabled supply current vs. input voltage 1100 1050 1000 950 900 0 5 10 15 20 25 input voltage (v) 55 50 45 40 35 30 case temperature ( o c) 12 34 6 5 output current (a) 100 10 1 0.1 output voltage (v) 0 5 10 15 20 25 input voltage (v) normalized output voltage(v) load current (a) case temperature vs. output current 10 8 6 4 2 0 peak current(a) 10 70 30 90 50 duty cycle (%) peak current vs. duty cycle operating range disabled supply current vs. input voltage 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 input voltage (v) v cc regulator line regulation (i cc = 10ma) 4.9 4.7 4.5 4.3 4.1 3.9 3.7 3.5 v cc (v) 45 4.5 5.5 6 6.5 7 input voltage (v) v in =12v v in =20v load regulation 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995 normalized output voltage 579 13 19 11 15 17 21 i load =6a line regulation 1mhz 1.4mhz 600khz v fb_min d max limit 0.995 0.996 0.997 0.998 0.999 1 1.001 1.002 0123456 input voltage(v)
MP38872 ? 6a, 21v, 600khz step-down with synchronizable gate driver MP38872 rev.1.11 www.monolithicpower.com 7 9/21/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. operation in en/sync fb sw vcc bg gnd pg bst regulator oscillator 600khz driver current sense amplifier error amplifier comp current limit comparator pwm comparator driver d regulator power good reference -- + -- + -- + s r r q q -- + 54pf 1pf v cc 0.74v v cc figure 1?functional block diagram the MP38872 is a fixed frequency, synchronous, step-down switching regulator with an integrated high-side power mosfet and a gate driver for a low-side external mosfet. it achieves 6a continuous output current over a wide input supply range with excellent load and line regulation. it provides a single highly efficient solution with current mode control for fast loop response and easy compensation. the MP38872 operates in a fixed frequency, peak current control mode to regulate the output voltage. a pwm cycle is initiated by the internal clock. the integrated high-side power mosfet is turned on and remains on until its current reaches the value set by the comp voltage. when the power switch is off, it remains off until the next clock cycle starts. if, in 90% of one pwm period, the current in the power mosfet does not reach the comp set current value, the power mosfet will be forced to turn off. error amplifier the error amplifier compares the fb pin voltage with the internal 0.8v reference (ref) and outputs a current proportional to the difference between the two. this output current is then used to charge or discharge the internal compensation network to form the comp voltage, which is used to control the power mosfet current. the optimized internal compensation network minimizes the external component counts and simplifies the control loop design. internal regulator most of the internal circuitries are powered from the 5v internal regulator. this regulator takes the vin input and operates in the full vin range. when vin is greater than 5.0v, the output of the regulator is in full regulation. when vin is lower than 5.0v, the output decreases. since this internal regulator provides the bias current for the bottom gate driver that requires significant amount of current depending upon the external mosfet selection, a 1uf ceramic capacitor for decoupling purpose is required.
MP38872 ? 6a, 21v, 600khz step-down with synchronizable gate driver MP38872 rev.1.11 www.monolithicpower.com 8 9/21/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. enable/synch control the MP38872 has a dedicated enable/synch control pin (en/sync). by pulling it high or low, the ic can be enabled and disabled by en. tie en to vin for automatic start up. to disable the part, en must be pulled low for at least 5s. the MP38872 can be synchronized to external clock range from 300khz up to 1.4mhz through the en/sync pin. the internal clock rising edge is synchronized to the external clock rising edge. under-voltage lockout (uvlo) under-voltage lockout (uvlo) is implemented to protect the chip from operating at insufficient supply voltage. the MP38872 uvlo comparator monitors the output voltage of the internal regulator, vcc. the uvlo rising threshold is about 4.0v while its falling threshold is a consistent 3.6v. internal soft-start the soft-start is implemented to prevent the converter output voltage from overshooting during startup. when the chip starts, the internal circuitry generates a soft-start voltage (ss) ramping up from 0v to 1.2v. when it is lower than the internal reference (ref), ss overrides ref so the error amplifier uses ss as the reference. when ss is higher than ref, ref regains control. over-current-protection and hiccup the MP38872 has cycle-by-cycle over current limit when the inductor current peak value exceeds the set current limit threshold. meanwhile, output voltage starts to drop until fb is below the under-voltage(uv) threshold, typically 30% below the reference. once a uv is triggered, the MP38872 enters hiccup mode to periodically restart the part. this protection mode is especially useful when the output is dead-short to ground. the average short circuit current is greatly reduced to alleviate the thermal issue and to protect the regulator. the MP38872 exits the hiccup mode once the over current condition is removed. thermal shutdown thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. when the silicon die temperature is higher than 150 c, it shuts down the whole chip. when the temperature is lower than its lower threshold, typically 140 c, the chip is enabled again. floating driver and bootstrap charging the floating power mosfet driver is powered by an external bootstrap capacitor. this floating driver has its own uvlo protection. this uvlo?s rising threshold is 2.2v with a hysteresis of 150mv. the bootstrap capacitor voltage is regulated internally (figure 2). even at no load condition, as long as v in is 3v higher than v out , c4 will have enough voltage provided by v in through d1, m1, c4, l1 and c2. if (v in -v sw ) is more than 5v, u2 will regulate m1 to maintain a 5v bst voltage across c1. -- + -- + v in 5v u2 d1 m1 bst sw c4 c2 l1 v out figure 2 ? internal bootstrap charging circuit startup and shutdown if both vin and en are higher than their appropriate thresholds, the chip starts. the reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. the regulator provides stable supply for the remaining circuitries. three events can shut down the chip: en low, vin low and thermal shutdown. in the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. the comp voltage and the internal supply rail are then pulled down. the floating driver is not subject to this shutdown command.
MP38872 ? 6a, 21v, 600khz step-down with synchronizable gate driver MP38872 rev.1.11 www.monolithicpower.com 9 9/21/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. application information the schematic on the front page shows a typical MP38872 application. the ic can provide up to 6a output current at a nominal output voltage of 3.3v. for proper thermal performance, the exposed pad of the device must be soldered down to the printed circuit board. setting the output voltage the external resistor divider is used to set the output voltage (see the schematic on front page). the feedback resistor r1 also sets the feedback loop bandwidth with the internal compensation capacitor (see figure 1). choose r1 to be around 40.2k ? for optimal transient response. r2 is then given by: 1 v 8 . 0 v 1 r 2 r out ? = table 1?resistor selection for common output voltages v out (v) r1 (k ? ) r2 (k ? ) 1.8 40.2 (1%) 32.4 (1%) 2.5 40.2 (1%) 19.1 (1%) 3.3 40.2 (1%) 13 (1%) 5 40.2 (1%) 7.68 (1%) selecting the inductor a 1h to 10h inductor with a dc current rating of at least 25% percent higher than the maximum load current is recommended for most applications. for highest efficiency, the inductor dc resistance should be less than 15m ? . for most designs, the inductance value can be derived from the following equation. osc l in out in out f i v ) v v ( v l ? = where i l is the inductor ripple current. choose inductor current to be approximately 30% of the maximum load current, 6a. the maximum inductor peak current is: 2 i i i l load ) max ( l + = under light load conditions below 100ma, larger inductance is recommended for improved efficiency. synchronous mosfet the external synchronous mosfet is used to supply current to the inductor when the internal high-side switch is off. it significantly reduces the power loss when compared against a schottky rectifier. table 2 lists example synchronous mosfets and manufacturers. table 2?synchronous mosfet selection guide part no. manufacture fds6670as fairchild irf7821 international rectifier am4874 analog power selecting the input capacitor the input capacitor (c1) reduces the surge current drawn from the input and the switching noise from the device. the input capacitor impedance at the switching frequency should be less than the input source impedance to prevent high frequency switching current from passing to the input. ceramic capacitors with x5r or x7r dielectrics are highly recommended because of their low esr and small temperature coefficients. for 6a output applications, a 22f capacitor is sufficient. selecting the output capacitor the output capacitor (c2) keeps output voltage small and ensures regulation loop stability. the output capacitor impedance should be low at the switching frequency. ceramic capacitors with x5r or x7r dielectrics are recommended. pc board layout the high current paths (gnd, in and sw) should be placed very close to the device with short, direct and wide traces. the input capacitor needs to be as close as possible to the in and gnd pins. the external feedback resistors should be placed next to the fb pin. keep the switching node sw short and away from the feedback network. keep the en trace away from the feedback network, and also an isolation with ground trace between the en and fb pins (highly recommended).
MP38872 ? 6a, 21v, 600khz step-down with synchronizable gate driver MP38872 rev.1.11 www.monolithicpower.com 10 9/21/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. external bootstrap diode an external bootstrap diode may enhance the efficiency of the regulator, the applicable conditions of external bst diode is: z duty cycle is high: d= in out v v >65% in these cases, an external bst diode is recommended from the output of the voltage regulator to bst pin, as shown in fig.3 MP38872 sw bst c l bst c out external bst diode in4148 vcc figure 3?add optional external bootstrap diode to enhance efficiency the recommended external bst diode is in4148, and the bst cap is 0.1~1f.
MP38872 ? 6a, 21v, 600khz step-down with synchronizable gate driver notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP38872 rev.1.11 www.monolithicpower.com 11 9/21/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. package information qfn14l w/exposed pad (3mm x 4mm) side view top view 1 14 8 7 bottom view 2.90 3.10 1.60 1.80 3.90 4.10 3.20 3.40 0.50 bsc 0.18 0.30 0.80 1.00 0.00 0.05 0.20 ref pin 1 id marking 1.70 0.50 0.25 recommended land pattern 2.90 note: 1) all dimensions are in millimeters. 2) exposed paddle size does not include mold flash. 3) lead coplanarity shall be 0.10 millimeter max. 4) drawing conforms to jedec mo-229, variation veed-5. 5) drawing is not to scale. pin 1 id see detail a 3.30 0.70 pin 1 id option b r0.20 typ. pin 1 id option a 0.30x45 o typ. detail a 0.30 0.50 pin 1 id index area

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