features eroflex circuit technology C risc turboengines for the future ? scd5231 rev 1 12/22/98 block diagram n full militarized qed rm5231 microprocessor n pinout compatible with popular rm5230 with split power sup plies (2.5v and 3.3v) n dual issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle l 133, 150 and 200 mhz operating frequencies C consult factory for latest speeds l 325 dhrystone2.1 mips l specint95 5.0, specfp95 5.25 n system interface optimized for embedded applications l 32-bit system interface lowers total system cost l high performance write protocols maximize uncached write bandwidth with 600 mb per second peak throughput l operates at processor clock divisors 2, 2.5, 3, 3.5,4, 4.5, 5, 6, 7, 8, 9 l ieee 1149.1 jtag boundary scan n integrated on-chip caches l 32kb instruction and 32kb data - 2 way set associative and per set locking l virtually indexed, physically tagged l write-back and write-through on per page basis l pipeline restart on first double for data cache misses n integrated memory management unit l fully associative joint tlb (shared by i and d translations) l 48 dual entries map 96 pages l variable page size (4kb to 16mb in 4x increments) n high-performance floating point unit l 532 mflops single-precision performance l single cycle repeat rate for common single precision opera-tions and some double precision operations l two cycle repeat rate for double precision multiply and double precision combined multiply-add operations l single cycle repeat rate for single precision combined multiply- add operation n mips iv instruction set l floating point multiply-add instruction increases performance in signal processing and graphics applications l conditional moves to reduce branch frequency l index address modes (register + register) n embedded application enhancements l specialized dsp integer multiply-accumulate instruction and 3 operand multiply instruction l i and d cache locking by set l optional dedicated exception vector for interrupts n fully static cmos design with power down logic l standby reduced power mode with wait instruction l 2.7 w typical power @ 200mhz l 2.5v core with 3.3v ios n 128-pin power quad-4 package (f22), consult factory for package configuration preliminary 32-bit superscaler microprocessor act5231
aeroflex circuit technology scd5231 rev 1 12/22/98 plainview ny (516) 694-6700 2 description the act5231 is a highly integrated superscalar microprocessor that implements a superset of the mips iv instruction set architecture(isa). it has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative tlb, a 32kb 2-way set associative instruction cache, a 32kb 2-way set associative data cache, and an efficient 32-bit system interface. the act5231 can issue both an integer and a floating point instruction in the same cycle. the act5231 is ideally suited for high-end embedded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-d visualization. hardware overview the act5231 offers a high-level of integration targeted at high-performance embedded applications. the key elements of the act5231 are briefly described below. superscalar dispatch the act5231 has an efficient asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. with respect to superscalar issue, integer instructions include alu, branch, load/store, and floating-point load/ store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. in combination with its high throughput fully pipelined floating-point execution unit, the superscalar capability of the act5231 provides unparalleled price/performance in computationally intensive embedded applications. cpu registers like all mips isa processors, the act5231 cpu has a simple, clean user visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. pipeline for integer operations, loads, stores, and other non-floating-point operations, the act5231 uses the simple 5-stage pipeline also found in the act52xx family, r4600, r4700, and r5000. in addition to this standard pipeline, the act5231 uses an extended seven stage pipeline for floating-point operations. the act5231 does virtual to physical translation in parallel with cache access. integer unit the act5231 implements the mips iv instruction set architecture, and is therefore fully upward compatible with applications that run on processors implementing the earlier generation mips i-iii instruction sets. additionally, the act5231 includes two implementation specific instructions not found in the baseline mips iv isa but that are useful in the embedded market place. described in detail in the qed rm5231 datasheet, these instructions are integer multiply-accumulate and 3-operand integer multiply. the act5231 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle alu operations (add, sub, logical, shift) and an autonomous multiply/ divide unit. additional register resources include: the hi/lo result registers for the two-operand integer multiply/divide operations, and the program counter(pc). register file the act5231 has thirty-two general purpose registers with register location 0 hard wired to zero. these registersich allo are used for scalar integer operations and address calculation. the register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. alu the act5231 alu consists of the integer adder/ subtractor, the logic unit, and the shifter. the adder performs address calculations in addition to arithmetic operations, the logic unit performs all logical and zero shift data moves, and the shifter performs shifts and store alignment operations. each of these units is optimized to perform all tions in a single processor cycle. for additional detail information regarding the operation of the quantum effect design (qed) riscmark ? rm 5231 ? , 32-bit superscalar microprocessor see the latest qed datasheet.
aeroflex circuit technology scd5231 rev 1 12/22/98 plainview ny (516) 694-6700 3 act5231 microprocessor pquad pinouts (pinouts subject to change C contact factory) pin # function pin # function pin # function pin # function 1 vcc 53 nc 105 vcc 157 nc 2 nc 54 nc 106 nmi* 158 nc 3 nc 55 nc 107 extrqst* 159 nc 4 vcc 56 vcc 108 reset* 160 nc 5 vss 57 vss 109 coldreset* 161 vcc 6 sysad4 58 modein 110 vccok 162 vss 7 sysad36 59 rdrdy* 111 bigendian 163 sysad28 8 sysad5 60 wrrdy* 112 vcc 164 sysad60 9 sysad37 61 validin* 113 vss 165 sysad29 10 vcc? 62 validout* 114 sysad16 166 sysad61 11 vss 63 release* 115 sysad48 167 vcc? 12 sysad6 64 vccp 116 vcc? 168 vss 13 sysad38 65 vssp 117 vss 169 sysad30 14 vcc 66 sysclock 118 sysad17 170 sysad62 15 vss 67 vcc? 119 sysad49 171 vcc 16 sysad7 68 vss 120 sysad18 172 vss 17 sysad39 69 vcc 121 sysad50 173 sysad31 18 sysad8 70 vss 122 vcc 174 sysad63 19 sysad40 71 vcc? 123 vss 175 sysadc2 20 vcc? 72 vss 124 sysad19 176 sysadc6 21 vss 73 syscmd0 125 sysad51 177 vcc? 22 sysad9 74 syscmd1 126 vcc? 178 vss 23 sysad41 75 syscmd2 127 vss 179 sysadc3 24 vcc 76 syscmd3 128 sysad20 180 sysadc7 25 vss 77 vcc 129 sysad52 181 vcc 26 sysad10 78 vss 130 sysad21 182 vss 27 sysad42 79 syscmd4 131 sysad53 183 sysadc0 28 sysad11 80 syscmd5 132 vcc 184 sysadc4 29 sysad43 81 vcc 133 vss 185 vcc? 30 vcc? 82 vss 134 sysad22 186 vss 31 vss 83 syscmd6 135 sysad54 187 sysadc1 32 sysad12 84 syscmd7 136 vcc? 188 sysadc5 33 sysad44 85 syscmd8 137 vss 189 sysad0 34 vcc 86 syscmdp 138 sysad23 190 sysad32 35 vss 87 vcc? 139 sysad55 191 vcc 36 sysad13 88 vss 140 sysad24 192 vss 37 sysad45 89 vcc? 141 sysad56 193 sysad1 38 sysad14 90 vss 142 vcc 194 sysad33 39 sysad46 91 vcc 143 vss 195 vcc? 40 vcc? 92 vss 144 sysad25 196 vss 41 vss 93 int0* 145 sysad57 197 sysad2 42 sysad15 94 int1* 146 vcc? 198 sysad34 43 sysad47 95 int2* 147 vss 199 sysad3 44 vcc 96 int3* 148 sysad26 200 sysad35 45 vss 97 int4* 149 sysad58 201 vcc 46 modeclock 98 int5* 150 sysad27 202 vss 47 jtdo 99 vcc 151 sysad59 203 nc 48 jtdi 100 vss 152 vcc 204 nc 49 jtck 101 nc 153 vss 205 nc 50 jtms 102 nc 154 nc 206 nc 51 vcc 103 nc 155 nc 207 vcc 52 vss 104 nc 156 vss 208 vss ? these v cc pins may be 2.5v in future higher performance devices ( p a ck a g e & p i n o u t s s u b j e c t t o c h a n g e C c o n ta c t f a c to r y )
aeroflex circuit technology scd5231 rev 1 12/22/98 plainview ny (516) 694-6700 4 sample ordering information part number screening speed (mhz) package ACT-5231PC-133F22C commercial temperature 133 128 lead pquad act-5231pc-150f22t military temperature 150 128 lead pquad act-5231pc-200f22m military screening 200 128 lead pquad aeroflex circuit technology 35 south service road plainview new york 11803 telephone: (516) 694-6700 fax: (516) 694-6715 toll free inquiries: (800) 843-1553 www.aeroflex.com/act1.htm e-mail: sales-act@aeroflex.com specifications subject to change without notice. circuit technology part number breakdown actC 5231 pc C 200 f22 m aeroflex circuit technology base processor type 133 = 150mhz 150 = 150mhz 200 = 200mhz cache style package type & size c = commercial temp, 0c to +70c i = industrial temp, -40c to +85c t = military temp, -55c to +125c m = military temp, -55c to +125c, screened * q = mil-prf-38534 compliant/smd if applicable screening * screened to the individual test methods of mil-std-883 pc = primary cache maximum pipeline freq. surface mount package f22 = 1.10" sq 128 lead pquad
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