? semiconductor components industries, llc, 2013 september, 2013 ? rev. 0 1 publication order number: NCV896530/d NCV896530 2.1 mhz low voltage dual output buck converter the NCV896530 dual step ? down dc ? dc converter is a monolithic integrated circuit dedicated to automotive driver information systems from a downstream voltage rail. both channels are externally adjustable from 0.9 v to 3.3 v and can source totally up to 1600 ma. converters are running at 2.1 mhz switching frequency above the sensitive am band and operate 180 out of phase to reduce large amounts of current demand on the rail. synchronous rectification offers improved system efficiency. the NCV896530 provides additional features expected in automotive power systems such as integrated soft ? start, cycle ? by ? cycle current limit and thermal shutdown protection. the device can also be synchronized to an external clock signal in the range of 2.1 mhz. the NCV896530 is available in a space saving, 3 x 3 mm 10 ? pin dfn package. features ? synchronous rectification for higher efficiency ? 2.1 mhz switching frequency, 180 out ? of ? phase ? sources up to 1600 ma total and 1 a per channel ? adjustable output voltage from 0.9 v to 3.3 v ? 2.7 v to 5.5 v input voltage range ? thermal limit and short circuit protection ? auto synchronizes with an external clock ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable ? this is a pb ? free device typical applications ? audio ? infotainment ? vision system ? instrumentation ?? ?? 3 ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? figure 1. NCV896530 typical application 2.2 h 2.2 h 10 f 10 f 11 dfn10 case 485c marking diagram pin connections a = assembly location l = wafer lot y = year w = work week = pb ? free device 1 fb1 10 fb2 2 en1 3 sync 4 vin 9 en2 8 por 7 gnd (top view) device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. http://onsemi.com 5 sw1 6 sw2 (*note: microdot may be in either location) NCV896530mwtxg dfn10 (pb ? free) ncv89 6530 alyw 3000 / tape & reel
NCV896530 http://onsemi.com 2 block diagram 4 3 2 1 7 6 5 sync vin sw 1 fb1 en 1 por gnd fb 2 sw 2 en2 8 9 10 pwm control logic control ilimit q1 q2 ea1 pwm control logic control q3 q4 voltage reference ea2 vin ramp generator 0 oscillator ea1 ea2 thermal shutdown uvlo ilimit pvin avin vin vref vref 180 sync sync pvin avin figure 2. simplified block diagram
NCV896530 http://onsemi.com 3 pin function description pin pin name type description 1 fb1 analog input feedback voltage from the output 1. this is the input to the error amplifier. 2 en1 digital input enable for converter 1. this pin is active high (equal or lower analog input voltage) and is turned off by logic low. do not let this pin float. 3 sync digital input oscillator synchronization. this pin can be synchronized to an external clock in the range of 2.1 mhz. if not used, the pin must to be connected to ground. 4 vin analog / power input power supply input for the pfet power stage, analog and digital blocks. the pin must be decoupled to ground by a 10 f ceramic capacitor. 5 sw1 analog output connection from power mosfets of output 1 to the inductor. 6 sw2 analog output connection from power mosfets of output 2 to the inductor. 7 gnd analog ground this pin is the ground reference for the analog section of the ic. the pin must be connected to the system ground. 8 por digital output power on reset. this is an open drain output. this output is shutting down when one of the output voltages are less than 90% (typ) of their nominal values. a pull ? up resist- or around 500 k should be connected between por and vin, vout1 or vout2 depending on the supplied device. 9 en2 digital input enable for converter 2. this pin is active high (equal or lower analog input voltage) and is turned off by logic low. do not let this pin float. 10 fb2 analog input feedback voltage from the output 2. this is the input to the error amplifier. 11 exposed pad power ground this pin is the ground reference for the nfet power stage of the ic. the pin must be connected to the system ground and to both input and output capacitors. maximum ratings rating symbol value unit minimum voltage all pins v min ? 0.3 v maximum voltage all pins v max 6.0 v maximum voltage enx, sync, fbx, , swx, por v max vin+0.3 v thermal resistance junction ? to ? ambient (3x3 dfn) (note 1) r ja 40 c/w storage temperature range t stg ? 55 to 150 c junction operating temperature t j ? 40 to 150 c esd withstand voltage human body model machine model v esd 2.0 200 kv v moisture sensitivity level msl 1 per ipc 1. mounted on 1 sq. in. of a 4 ? layer pcb with 1 oz. copper thickness.
NCV896530 http://onsemi.com 4 electrical characteristics (2.7 v < v in < 5.5 v, min and max values are valid for the temperature range ? 40 c t j +150 c unless noted otherwise, and are guaranteed by test design or statistical correlation, typical values are referenced to t a = +25 c) rating conditions symbol min typ max unit input voltage quiescent current sync = gnd, v fb = 0 v en1 = en2 = 2 v, no switching i q ? 2.0 3.0 ma standby current en1 = en2 = 0 v i stbmax ? 4.0 10 a under voltage lockout v in falling v uvlo 2.2 2.4 2.6 v under voltage hysteresis v uvloh ? 100 150 mv sync sync threshold voltage logic high v ihsync 1.2 ? ? v logic low v ilsync 0.4 sync pin bias current v sync = 5 v i ilsync 2 50 a external synchronization f sync 1.8 2.7 mhz sync pulse duty ratio t sync 50 % en1, en2 enx threshold voltage logic high v ihenx 1.2 ? ? v logic low v ilenx 0.4 enx pin bias current v enx = 5 v i ilenx 2 50 a power on reset power on reset threshold v out falling v port 87% 93% v power on reset hysteresis v porh ? 3% v sink current v por = 0.4 v i sipor 2 ma output performances feedback voltage threshold fb1, fb2 v fb ? 0.6 ? v feedback voltage accuracy t a = 25c v out 1 ? % ? 40 c < t a < 125 c v out ? 2 ? +2 soft ? start time time from en to 90% of output voltage t start 400 ? 1000 s switching frequency en1 = en2 = 1, v in = 5 v f sw 1.8 2.1 2.6 mhz duty cycle d ? ? 100 % power switches high ? side mosfet on ? resistance i rds(on) = 600 ma, v in = 5 v, t a = 25 c r onhs ? 500 820 m low ? side mosfet on ? resistance i rds(on) = 600 ma, v in = 5 v, t a = 25 c r onls ? 450 820 m high ? side mosfet leakage current v in = 5 v, v lx = 0 v, v enx = 0 v i leakhs ? 5 a low ? side mosfet leakage current v lx = 5 v, v enx = 0 v i leakls ? 5 a minimum on time t onmin ? 80 ns protection current limit peak inductor current i pk 1.4 2.0 a thermal shutdown threshold t sd 150 170 190 c thermal shutdown hysteresis t sdh 5 20 c hiccup time % of soft ? start time t hcp,dly 60 %
NCV896530 http://onsemi.com 5 typical characteristics curves v in , input voltage (v) f sw , switching frequency (mhz) figure 3. switching frequency vs. input voltage t j = 25 c, en1 = en2 = 1 v sync , sync voltage (v) i sync , sync pulldown current ( a) figure 4. sync pulldown current vs. sync voltage v enx , enable voltage (v) i enx , enable pulldown current ( a) figure 5. enable pulldown current vs. enable voltage v in , input voltage (v) i stbmax , standby current ( a) figure 6. standby current vs. input voltage t j , junction temperature ( c) i pk , current limit (a) figure 7. current limit vs. temperature v ref , reference voltage (mv) t j , junction temperature ( c) figure 8. reference voltage vs. temperature 2.4 2.35 2.3 2.25 2.2 2.5 5.5 5 4.5 3 3.5 4 t j = 25 c 12 05 4.5 1 0.5 3.5 4 10 8 6 4 2 0 3 1.5 2 2.5 12 06 5 4 3 t j = 25 c 10 8 6 4 2 0 2 1 14 12 10 8 6 4 2 0 2.5 5.5 5 4.5 4 3.5 3 t j = 25 c 2.00 ? 40 110 60 10 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 600.0 ? 40 110 60 10 599.5 599.0 598.5 598.0 597.5 597.0 596.5 596.0
NCV896530 http://onsemi.com 6 typical characteristics curves t j , junction temperature ( c) i enx , enable pulldown current ( a) figure 9. enable pulldown current vs. temperature t j , junction temperature ( c) i sync , sync pulldown current ( a) figure 10. sync pulldown current vs. temperature t j , junction temperature ( c) f sw , switching frequency (mhz) figure 11. switching frequency vs. temperature 12.0 ? 40 140 120 100 ? 20 0 20 v sync = 5 v 12 10 8 6 4 2 0 2.30 v enx = 5 v 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 40 60 80 150 100 50 ? 50 0 14 2.25 2.20 2.15 2.10 2.05 2.00 ? 40 10 60 110 v in = 5 v, en1 = en2 = 1
NCV896530 http://onsemi.com 7 dc/dc operation description pwm operating mode the output voltage of the device is regulated by modulating the on ? time pulse width of the main switch q1 at a fixed 2.1 mhz frequency (figure 12). the switching of the pmos q1 is controlled by a flip ? flop driven by the internal oscillator and a comparator that compares the error signal from an error amplifier with the sum of the sensed current signal and compensation ramp. the driver switches on and off the upper side transistor (q1) and switches the lower side transistor in either on state or in current source mode. at the beginning of each cycle, the main switch q1 is turned on by the rising edge of the internal oscillator clock. the inductor current ramps up until the sum of the current sense signal and compensation ramp becomes higher than the error amplifier?s voltage. once this has occurred, the pwm comparator resets the flip ? flop, q1 is turned off while the synchronous switch q2 is turned in its current source mode. q2 replaces the external schottky diode to reduce the conduction loss and improve the efficiency. to avoid overall power loss, a certain amount of dead time is introduced to ensure q1 is completely turned off before q2 is being turned on. i lx v lx v out figure 12. pwm switching waveforms (v in = 3.6 v, v out = 1.2 v, i out = 600 ma, temp = 25 c) soft ? start the NCV896530 uses soft start to limit the inrush current when the device is initially powered up or enabled. soft start is implemented by gradually increasing the reference voltage until it reaches the full reference voltage. during startup, a pulsed current source charges the internal soft start capacitor to provide gradually increasing reference voltage. when the voltage across the capacitor ramps up to the nominal reference voltage, the pulsed current source will be switched off and the reference voltage will switch to the regular reference voltage. over current hiccup protection when the cur rent through the inductor exceeds the current limit the NCV896530 enters over current hiccup mode. when an over current event is detected the NCV896530 disables the outputs and attempts to re ? enable the outputs after the hiccup time. the part remains off for the hiccup time and then goes through the power on reset procedure. if the excessive load has been removed then the output stage re ? enables and operates normally; however, if the excessive load is still present the cycle begins again. internal heat dissipation is kept to a minimum as current will only flow during the reset time of the protection circuitry. the hiccup mode is continuous until the excessive load is removed. low dropout operation the NCV896530 offers a low input ? to ? output voltage difference. the NCV896530 can operate at 100% duty cycle on both channels. in this mode the pmos (q1) remains completely on. the minimum input voltage to maintain regulation can be calculated as: v in(min) v out(max) i out r ds(on) r inductor) (eq. 1) v out : output voltage i out : max output current r ds (on): p ? channel switch r ds(on) r inductor : inductor resistance (dcr) power on reset the power on reset (por) is pulled low when one of the converter is out of 90% of the regulation. when both outputs are in the range of regulation. if only one channel is active, por stays low. when the inactive regulator becomes enabled, por is kept low until the output reaches its voltage range. a pull ? up resistor is needed to this open drain output. the resistor may be connected to vin or to an output voltage of one regulator if the device supplied can not accept vin on the io. in the case of por is tied to vin, por is high when NCV896530 is off. in the case of por is tied to vout, por is low when NCV896530 is off. leave the por pin unconnected when not used. frequency synchronization the NCV896530 can be synchronized with an external clock signal by using the sync pin (1.8 mhz ? 2.4 mhz). during synchronization, the outputs are in phase. thermal shutdown internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. if the junction temperature exceeds t sd , the device shuts down. in this mode all power transistors and control circuits are turned off. the device restarts in soft start after the temperature drops below 130 c min. this feature is provided to prevent catastrophic failures from accidental device overheating.
NCV896530 http://onsemi.com 8 switching frequency when switcher 2 is enabled and switcher 1 is disabled, the switching frequency is approximately 120 khz higher than when switcher 1 is enabled and switcher 2 is either enabled or disabled. conversion ratio the minimum conversion ratio is dictated by switching frequency and the minimum on time. the minimum achievable output is: v out 0.2 v in maximum output capacitance the maximum output capacitance is determined by the amount the capacitor can be charged during soft start and the effect on the control loop. if more than 100 f is used on an output small signal analysis should be done to make sure that sufficient phase margin is maintained. the maximum allowable due to soft start current limit is given by the following equation: c max i out,startup t start v out (eq. 2) c max : maximum output capacitance (f) i out,startup : output current during soft start (a) t start : soft-start time (s) v out : regulated output voltage (v)
NCV896530 http://onsemi.com 9 package dimensions dfn10, 3x3, 0.5p case 485c issue c 10x seating plane l d e 0.15 c a a1 e d2 e2 b 15 10 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. terminal b may have mold compound material along side edge. mold flashing may not exceed 30 microns onto bottom surface of terminal b. 6. details a and b show optional views for end of terminal lead at edge of package. 7. for device opn containing w option, detail b alternate construction is not applicable. ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 reference 0.10 c 0.08 c (a3) c 10x 10x 0.10 c 0.05 c a b note 3 k 10x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 2.40 2.60 e 3.00 bsc e2 1.70 1.90 e 0.50 bsc l 0.35 0.45 l1 0.00 0.03 detail a k 0.19 typ 2x 2x l1 detail a bottom view (optional) *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.1746 2.6016 1.8508 0.5000 pitch 0.5651 10x 3.3048 0.3008 10x dimensions: millimeters on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCV896530/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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