august 2013 ?2013 fairchild semiconductor corporation FDMS86252L rev.c www.fairchildsemi.com 1 FDMS86252L n-channel shielded gate powertrench ? mosfet FDMS86252L n-channel shielded gate powertrench ? mosfet 150 v, 12 a, 56 m features ? shielded gate mosfet technology ? max r ds(on) = 56 m at v gs = 10 v, i d = 4.4 a ? max r ds(on) = 71 m at v gs = 6 v, i d = 3.8 a ? max r ds(on) = 75 m at v gs = 4.5 v, i d = 3.7 a ? advanced package and silicon combination for low r ds(on) and high efficiency ? next generation enhanced body diode technol - ogy, engineered for soft recovery ? msl1 robust package design ? 100% uil tested ? rohs compliant general description this n-channel mosfet is produced using fairchild semiconductor?s advanced powertrench ? process that incorporates shielded gate technology. this process has been optimized for the on-state resistance and yet maintain superior switching performance. applications ? oringfet / load switching ? synchronous rectification ? dc-dc conversion power 56 d d d d g s s s pin 1 bottom top d d d d s s s g pin 1 mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 150 v v gs gate to source voltage 20 v i d drain current -continuous t c = 25 c 12 a -continuous t a = 25 c (note 1a) 4.4 -pulsed (note 4) 30 e as single pulse avalanche energy (note 3) 73 mj p d power dissipation t c = 25 c 50 w power dissipation t a = 25 c (note 1a) 2.5 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case 2.5 c/w r ja thermal resistance, junction to ambient (note 1a) 50 device marking device package reel size tape width quantity FDMS86252L FDMS86252L power 56 13 ?? 12 mm 3000 units
www.fairchildsemi.com 2 ?2013 fairchild semiconductor corporation FDMS86252L rev.c FDMS86252L n-channel shielded gate powertrench ? mosfet electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v150 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 104 mv/c i dss zero gate voltage drain current v ds = 120 v, v gs = 0 v1 a i gss gate to source leakage current v gs = 20 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a11.53v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -6 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 4.4 a 46 56 m v gs = 6 v, i d = 3.8 a4871 v gs = 4.5 v, i d = 3.7 a5275 v gs = 10 v, i d = 4.4 a, t j = 125 c 90 110 g fs forward transconductance v ds = 5 v, i d = 4.4 a21s c iss input capacitance v ds = 75 v, v gs = 0 v, f = 1 mhz 952 1335 pf c oss output capacitance 74 105 pf c rss reverse transfer capacitance 3 5 pf r g gate resistance 0.1 0.6 1.8 t d(on) turn-on delay time v dd = 75 v, i d = 4.4 a, v gs = 10 v, r gen = 6 6.8 14 ns t r rise time 1.4 10 ns t d(off) turn-off delay time 19 34 ns t f fall time 2.9 10 ns q g total gate charge v gs = 0 v to 10 v v dd = 75 v, i d = 4.4 a 15 21 nc q g total gate charge v gs = 0 v to 4.5 v7.611nc q gs gate to source charge 2.1 nc q gd gate to drain ?miller? charge 2.3 nc v sd source-drain diode forward voltage v gs = 0 v, i s = 1.9 a (note 2) 0.7 1.2 v v gs = 0 v, i s = 4.4 a (note 2) 0.8 1.3 t rr reverse recovery time i f = 4.4 a, di/dt = 100 a/ s 53 85 ns q rr reverse recovery charge 51 82 nc notes : 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. e as of 73 mj is based on starting t j = 25 c, l = 3 mh, i as = 7 a, v dd = 150 v, v gs = 10 v. 100% tested at l =0.1 mh, i as = 24 a. 4. pulsed id limited by junction temperature, td<=100 s, please refer to soa curve for more details. g df ds sf ss 50 c/w when mounted on a 1 in 2 pad of 2 oz copper a. g df ds sf ss 125 c/w when mounted on a minimum pad of 2 oz copper. b.
www.fairchildsemi.com 3 ?2013 fairchild semiconductor corporation FDMS86252L rev.c FDMS86252L n-channel shielded gate powertrench ? mosfet typical characteristics t j = 25 c unless otherwise noted figure 1. 012345 0 6 12 18 24 30 v gs = 4.5 v v gs = 3.5 v v gs = 3 v v gs = 6 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 2.5 v v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 6 12 18 24 30 0.5 1.0 1.5 2.0 2.5 3.0 v gs = 4.5 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 6 v v gs = 3 v v gs = 10 v v gs = 2.5 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.4 0.8 1.2 1.6 2.0 2.4 i d = 4.4 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 30 60 90 120 150 t j = 125 o c i d = 4.4 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 1234 0 6 12 18 24 30 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 30 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
www.fairchildsemi.com 4 ?2013 fairchild semiconductor corporation FDMS86252L rev.c FDMS86252L n-channel shielded gate powertrench ? mosfet figure 7. 0 4 8 12 16 0 2 4 6 8 10 i d = 4.4 a v dd = 100 v v dd = 75 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 50 v gate charge characteristics figure 8. 0.1 1 10 100 1 10 100 1000 10000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 1 10 30 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 6 12 18 24 v gs = 4.5 v limited by package r t jc = 2.5 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 1 1 . f o r w a r d b i a s s a f e op erating area 0.01 0.1 1 10 100 800 0.001 0.01 0.1 1 10 50 10 s curve bent to measured data 100 p s 10 ms dc 1 s 100 ms 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c figure 12. 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.1 1 10 100 1000 2000 single pulse r t ja = 125 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics t j = 25 c unless otherwise noted
www.fairchildsemi.com 5 ?2013 fairchild semiconductor corporation FDMS86252L rev.c FDMS86252L n-channel shielded gate powertrench ? mosfet figure 13. 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.0001 0.001 0.01 0.1 1 2 single pulse r t ja = 125 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transient thermal response curve typical characteristics t j = 25 c unless otherwise noted
www.fairchildsemi.com 6 ?2013 fairchild semiconductor corporation FDMS86252L rev.c FDMS86252L n-channel shielded gate powertrench ? mosfet dimensional outline and pad layout c l l c pkg pkg 5.10 4.90 6.25 5.90 c 1.27 3.81 3.86 3.61 0.71 0.44 chamf er corner as pin #1 ident may appear as optional top view side view bottom view 1.27 3.81 1.27 6.61 3.91 4.52 1.27 1234 85 6 7 1 4 8 5 land pattern recommendation 12 34 876 0.10 c a b 0.46 0.36 (8x) 4.29 4.09 5 0.71 0.44 0.77 a b (0.39) 0.61 notes: unless otherwise specified a) package standard reference: jedec mo-240, issue a, var. aa, dated october 2002. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. mold flash or burrs does not exceed 0.10mm. d) dimensioning and tolerancing per asme y14.5m-1994. e) it is recommended to have no traces or vias within the keep out area. f) drawing file name: pqfn08arev6. see detail a detail a scale: 2:1 0.05 0.00 0.30 0.20 0.08 c 6.25 5.90 5.85 5.65 5.10 4.90 6 optional draft angle may appear on four sides of the package pin #1 ident may appear as optional seating plane 0.10 c 1.10 0.90 option - a (sawn type) option - b (punched type) keep out area (1.19) (1.81) (0.50) (3.40) (0.52) 0.15 max (2x) 5.10 3.75
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