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mpc2f35 low-speed usb micro-controller this document contains information on a new product under dev elopment by megawin. megawin reserves the right to change or discontinue this product without notice. ? megawin technology co., ltd. 2008 all rights reserved. 2008/12 version a4 megawin general description the mpc2f35 is a 65c02 mcu with an embedde d 8k bytes flash rom, a 256 bytes ram, a watch-dog timer, a usb and ps/2 combo interfaces, can be implemented via the usb bus line, d+ and d- pins, by the user?s program. the usb feat ures fully meets the low-speed usb specification version 1.1. it will be very suitable for the low-cost keyboard, joystick, i-toy, and some products like the hand-held devices, which need to download/ upload data through the pc system. features ? 8-bit 65c02 micro-controller with 6 mhz external crystal or ceramic resonator ? operation voltage: 4.35v to 5.5v ? memory: ? 8k bytes flash rom ? 256 bytes ram ? 34 programmable gpio: ? 4 led direct sink pins shar ed with port0 (led0/1/2/3) ? 2 external interrupt pins (int0, int1) ? port3 provides the pin interrupt ? 26 bi-directional i/o pins for port1/ 2/3/4 ? one 8-bit programmable timer ? built-in power-on reset ? one watchdog timer ? low-speed usb specification version 1.1 compliance ? supports 4 endpoints, where ep0 is control endpoint, and ep1/2/3 are data endpoints ? integrated usb transceiver, and 3.3v regul ated output for usb pull-up resistor ? provides remote wake-up ? built-in low-voltage detector ? usb and ps/2 combo interfaces ? support two power-saving modes: stop and halt mode ? packages: ? 28-ssop: mpc2f35l ? 40-pdip: MPC2F35E2
2 mpc2f35_usb data sheet megawin pad description pin name i/o description p0.0~0.3 i/o bi-directional i/o, and sink led directly p0.4/- int0 i/o bi-directional i/o with external interrupt 1 p0.5/- int1 i/o bi-directional i/o with external interrupt 2 p0.6~0.7 i/o bi-directional i/o p1.0~1.7 i/o bi-directional i/o p2.0~2.7 i/o bi-directional i/o p3.0~3.7 i/o bi-directional i/o p4.0~4.1 i/o bi-directional i/o - rst i reset pin, low active xtal1 i 6mhz crystal or resonator in xtal2 i 6mhz crystal or resonator out d+/sclk i/o usb data + with ps/2 compatible i/o d-/sdata i/o usb data - with ps/2 compatible i/o v cc i voltage supply v ss i ground v3.3 o 3.3v regulated output, a capacitor should be added on this pin
megawin mpc2f35_usb data sheet 3 block diagram 8k bytes flash rom usb and ps/2 engine power controller i/o ports 8-bit cpu 256 bytes ram port 0.0 ~ 0.7 port 1.0 ~ 1.7 port 2.0 ~ 2.7 port 3.0 ~ 3.7 port 4.0 ~ 4.1 xtal2 xtal1 d+, d- v3.3 interrupt controller watch dog timer power-on reset clock generator acess control 8-bit timer dpm control
4 mpc2f35_usb data sheet megawin packages 3 26 4 5 6 7 8 25 24 23 22 21 -rst p3.7 p3.4 p0.0 p0.1 p0.7 p0.2 vcc d + mpc2f35l p0.6 p0.4 xtal2 xtal1 vss 2 d - 1 v3.3 28 27 9 10 11 12 20 19 18 17 p2.7 p2.6 p2.5 p3.0 p2.0 p1.7 p1.5 p1.4 13 14 16 15 p2.3 p2.4 p2.2 p2.1 d +/sclk v3.3 d -/sdata vss xtal1 xtal2 p0.4/-int0 p0.5/-int1 p0.6 p0.7 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 vcc p0.3/led3 p0.2/led2 p0.1/led1 p0.0/led0 -rst p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 MPC2F35E2
megawin mpc2f35_usb data sheet 5 function description registers a y x p pch pcl 1 s accumulator the accumulator is a 8-bit register, which stores t he results of most arithmetic and logic operations. in addition, the accumulator usually contains o ne of two data words used in these operations. index register (x, y) there are two 8-bit index regist ers (x and y), which may be used to count program steps or to provide an index value to be used in generat ing an effective address. when executing an instruction, which specifies indexed addressi ng, the mcu fetches the op code and the base address, and modifies the address by adding the index register to the base address before performing the desired operation. pre- or post-index of index address is possible. processor status register (p) the 8-bit processor status register contains sev en status flags. some flags are controlled by the program , and others may be controlled by both the program and the mcu. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n v 1 b d i z c z n: signed flag, 1 = negative, 0 = positive z v: overflow flag, 1 = true, 0 = false z b: brk interrupt command, 1 = brk, 0 = irqb z d: decimal mode, 1 = true, 0 = false z i: irqb disable flag, 1 = disable, 0 = enable z z: zero flag, 1 = true, 0 = false z c: carry flag, 1 = true, 0 = false program counter (pc) the 16-bit program counter register provides the addresses, which steps mpc2f35 through the sequential program instructions. each time this m cu fetches an instruction from program memory, the lower byte of the program counter (pcl) is placed on the low-order 8 bits of the address bus, and the higher byte of the program counter (pch) is placed on the high-order 8 bits. the counter is incremented each time when an instruction or data is fetched from program memory.
6 mpc2f35_usb data sheet megawin stack pointer (s) the stack pointer is an 8-bit register, which is used to control the addressing of the variable-length stack. the stack pointer is automatically incremented and decremented under the control of the mcu to perform the stack manipulations. the stack allows simple implementation of nested subroutines and multiple level interrupts. the stack pointer is initialized by the user?s firmware. memory map there is a zero page working ram (0000h ~ 007f h), a stack area (0180h ~ 01ffh) and two special function register areas (sfr, 00c0h ~ 00ffh and 0200h ~ 027fh) in mpc2f35. the locations 0100h to 017fh and the locations 0000h to 007fh share the same memory block, so mpc2f35 has a 256 bytes on-chip sram (zero page working ram and st ack area) and an 8k bytes on-chip flash rom, which are addressed from 8000h to 9fffh. the ad dress mapping of mpc2f35 is shown as below. zero page working ram 0000h 007fh memory map 017fh 0100h 0080h~00bfh 00c0h~00ffh 0180h 01ffh stack area 0200h 027fh sfr sfr program 9fffh a000h 7fffh 8000h ~ 800fh ffffh 8010h - - interrupt vector area ram
megawin mpc2f35_usb data sheet 7 special function register (sfr) the address 00c0h to 00ffh and 0200h to 027fh ar e reserved for the special function registers (sfr). mpc2f35 has 36 sfrs to be used to control or store the status of i/o, timers, system clock and other peripherals. symbol address description initial value irq_en 00c1 interrupt request enable x irq_st 00c2 interrupt request status flag 00 irq_clr 00c3 interrupt request clear 00 tm0 00c5 timer 0 00 tm0_ctl 00c6 timer 0 control 00 p0_buf 00d0 port 0 output buffer 00 p1_buf 00d1 port 1 output buffer 00 p2_buf 00d2 port 2 output buffer 00 p3_buf 00d3 port 3 output buffer 00 p4_buf 00d4 port 4 output buffer 00 p0 00d8 port 0 pad value x p1 00d9 port 1 pad value x p2 00da port 2 pad value x p3 00db port 3 pad value x p4 00dc port 4 pad value x wdt_st 00de watchdog timer status flag 00 wdt_clr 00df watchdog clear x usb_ctl 00e0 usb bus control 00 usb_addr 00e1 usb register address 00 usb_di / usb_do 00e2 usb register data buffer 00 dpm_ctl 00e8 usb bus mode control 00 dpmo 00e9 usb bus output for the ps/2 mode 00 dpmi 00ea usb bus value for the ps/2 mode x pwr_ctl 0200 power-saving control 00 fcpu_sr 0201 fcpu selector 00 rlh_en 0202 release the halt mode enable 00 p0_cr 0240 port 0 control register 00 p0_mr 0241 port 0 mode register 00 p1_cr 0244 port 1 control register 00 p1_mr 0245 port 1 mode register 00 p2_cr 0248 port 2 control register 00 p2_mr 0249 port 2 mode register 00 p3_cr 024c port 3 control register 00 p3_mr 024d port 3 mode register 00 p4_cr 0250 port 4 control register 00 p4_mr 0251 port 4 mode register 00
8 mpc2f35_usb data sheet megawin interrupt vectors vector address item priority properties description 8002h, 8003h reset 1 external. initial reset 8006h, 8007h usb 2 internal usb interrupt 8008h, 8009h tm0 3 internal timer 0 overflow interrupt 800ah, 800bh p3 4 external. port 3 interrupt vector 800ch, 800dh int0 5 external. in t0 external interrupt vector 800eh, 800fh int1 6 external. int1 external interrupt vector there are six interrupt sources provided in mpc2f35. the flag irq_en and irq_st are used to control the interrupts. when flag irq_st is set to ?1 ? by the hardware and the corresponding bits of flag irq_en has been set by firmware, an interrupt is ge nerated. when an interrupt occurs, all interrupts are inhibited until the cli or sta irq_en, #i instruct ion is invoked. executing the sei instruction can also disable the interrupts. interrupt process logic irq_en.1 interrupt vector generator logic initial reset sta irq_en, #i enable irq_st.1 initial reset sta irq_clr, #i sei instruction disable usb interrupt signal irq_en.2 s r q s r q irq_st.2 irq_st.5 irq_en.5 s r q . . . cli instruction 8002h, 8003h 8006h, 8007h 8008h, 8009h 800ah, 800bh 800ch, 800dh 800eh, 800fh int1 trigger signal tm0 interrupt signal
megawin mpc2f35_usb data sheet 9 interrupt registers irq enable flag address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00c1h irq_en - - int1 int0 p3 tm0 usb - program can enable (setting to ?1?) or disable (clearin g to ?0?) the ability of triggering irq through this register. z usb: usb finishes rx or tx data z tm0: timer0 underflow z p3: falling edge trigger signal occurs at port 3 input mode z int0, int1: falling edge trigger signal occurs at p0.4 and p0.5 input mode irq status flag address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00c2h irq_st - - int1 int0 p3 tm0 usb - - when irq occurs, program can read this regist er to know which source triggering irq. irq clear flag address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00c3h irq_clr - - int1 int0 p3 tm0 usb - - program can clear the interrupt event by writing ?1? into the corresponding bit. watchdog timer (wdt) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00deh wdt_st rsts - - - bit 3bit 2bit 1 bit 0 - 00dfh wdt_clr clr - - - - - - - - bit 3 ~ bit 0: contents of wdt z rsts: wdt reset status, set by the hardware when wdt overflows, and clear by the firmware or the hardware reset z clr: rsts clear and wdt reset control bit, t he program can clear the rsts bit and reset wdt by writing ?1? into the clr bit 3 the watchdog timer (wdt) is organized as a 4-bit counter , which is designed to prevent the program from unknown errors. if the wdt ov erflows, the wdt reset function w ill be performed. rsts (bit 7 of wdt_st) is set by hardware when the wdt overflows . it also can be cleared by hardware reset or writing 1 to bit 7 of wdt_clr. the interval of wdt to cause reset is around 0.7s at 6mhz external oscillator. programming one into t he bit 7 of wdt_clr register can re set the contents of the wdt. in normal operation, the application program must re set wdt before it overflows. a wdt overflow indicates that operation is not under control and the chip will be reset. the organizati on of the watchdog timer is shown as below 3
10 mpc2f35_usb data sheet megawin overflow signal wdt qw1 qw2 qw4 qw3 rrrr system reset s r q hardware reset wdt_clr.7 wdt_st.7 fosc/2^18 system control registers power saving control address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 0200h pwr_ctl lvdt - - - - - ckc halt - ? z lvdt: low-voltage detector disable bit. 1: disable, 0: enable (default) z ckc: oscillator control bit. 1: disa ble osc, 0: enable osc (default) z halt: fcpu off-line control bit. 1: fcpu off-line, 0: fcpu on-line (default) when the low-voltage detector is enabled, and if it senses the power voltage is lower than 3.3v, then mpc2f35 will be reset automatically. programmer can switch the normal operation mode to the power-saving mode for reducing power consumption through this register. there are two power saving modes in mpc2f35. stop mode: (pwr_ctl. ckc = 1) system clock stops the built-in os cillator if setting the ckc bit in the pwr_ctl sfr. mpc2f35 can be awakened from the stop mode by 4 ways: the port 3 interrupt, the hardware reset, the power-on reset and the usb wake-up. halt mode: (pwr_ctl. halt = 1) setting the halt bit to let the clock source of mpc2 f35 to be in the off-line status, but the oscillator works or not will be depended on the content of the ckc bit in the pwr_ctl sfr. mpc2f35 can be awakened from the halt mode by 3 wa ys: the interrupts (usb, timer 0, port3, int0 and int1) can be assigned by the rlh_en regist er, the hardware reset, or the power-on reset. f cpu selector address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w
megawin mpc2f35_usb data sheet 11 0201h fcpu_sr - - - - - - - cks - at the 6m hz external crystal, the internal clock source of mpc2f35 is 3m hz by the default value. z cks: f cpu clock source select register. 0: fosc/2 (default), 1:fosc release halt mode enable flag address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 0202h rlh_en - - int1 int0 p3 tm0 usb - - programmer can select the interrupt sources to release the halt mode through this register. 0: disable (default), 1: enable 3 after setting rlh_en register, once there is one inte rrupt to release the halt mode, the programmer can check the corresponding bit of the irq_st register to know which interrupt s ource to execute this release process. timer timer 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00c5h tm0 t7 t6 t5 t4 t3 t2 t1 t0 00c6h tm0_ctl - stc rl/s - - tki2 tki1 tki0 z stc: timer clock disable/enable. 0: disable timer clock (def ault), 1: enable timer clock z rl/s: auto-reload disable/enable. 0: enable auto- reload (default), 1: disable auto-reload tki2 tki1 tki0 timer 0 clock source (f tm0ck ) 0 0 0 f osc / 8 0 0 1 f osc / 16 0 1 0 f osc / 32 0 1 1 f osc / 64 1 0 0 f osc / 128 1 0 1 f osc / 256 1 1 0 f osc / 512 1 1 1 f osc / 1024 when timer 0 is used, it starts to pre-load value to this down-counter by setting the stc bit in the tm0_ctl sfr and its underflow frequency (f tm0_uv ) of timer 0 can be calculated by the following equation: f tm0_uv = f tm0ck / (tm0+1), where f tm0ck is selected by tki2, tki1 and tki0 for example: if f osc =6m hz and tki2=0, tki1=1, tki0=0, then f tm0ck = f osc / 32
12 mpc2f35_usb data sheet megawin tm0 f tm0_uv frequency 00h invalid 01h 93.75 khz 02h 62.5 khz ? ? ffh 732.42 hz general purpose i/o ports port 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00d0h p0_buf bp07 bp06 bp05 bp04 bp03 bp02 bp01 bp00 00d8h p0 p07 p06 p05 p04 p03 p02 p01 p00 - 0240h p0_cr cp07 cp06 cp05 cp04 cp03 cp02 cp01 cp00 0241h p0_mr - - mp05 mp04 - - mp01 mp00 port 0 is an 8-bit i/o port; each pin can be pr ogrammed as input or output individually. z p0_buf: port 0 output buffer. when p0.n is config ured as an output pin, it outputs the content of p0_buf.n. z p0: values on the pin of port 0 while reading from port 0. z p0_cr: configure p0.0 ~ p0.7 to be input or out put individually. 0: input (default), 1: output z p0_mr: configure the output mode of p0.0 ~ p0 .7 with a 17k ohm pull-high resistor, cmos or nmos open drain ? mp00 (p0_mr.0): p0.0 ~ p0.3 with the pull-high control bit, 0: disable (default), 1:enable ? mp01 (p0_mr.1): p0.0 ~ p0.3 with the cmos or nmos selector, 0: cmos (default), 1: nmos ? mp04 (p0_mr.4): p0.4 ~ p0.7 with the pull-high control bit, 0: disable (default), 1: enable ? mp05 (p0_mr.5): p0.4 ~ p0.7 with the cmos or nmos selector, 0: cmos (default), 1: nmos 3 3 at initial reset, port 0 is all in the input mode. ea ch pin of port 0 can be specified as the input or output mode independently by the p0_cr sfr. when port 0 is used as the output port, cmos or nmos open drain output type can be selected by the p0_mr register. port 0 has 17k ohm internal pull-high resistors that can be enabled/disabled by specif ying the mp00 and mp04 in the p0_mr register respectively. the pull-high resistor is automatically disabled only when the port is configured as cmos output. schmitt trigger circuit is added in the input path of p0.0~p0.3. user should be carefully on setting pin as input with no pull high resistor si nce this setting has potential to cause leakage. when p0.4 and p0.5 are set as input pins, they ar e int0 and int1 interrupt sources. a falling edge at the two pins will set the corresponding bits in the irq_st register to 1, and the external interrupt subroutines will be executed if t he corresponding bits in the ir q_en register are also set. 3 3 port 1
megawin mpc2f35_usb data sheet 13 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00d1h p1_buf bp17 bp16 bp15 bp14 bp13 bp12 bp11 bp10 00d9h p1 p17 p16 p15 p14 p13 p12 p11 p10 - 0244h p1_cr cp17 cp16 cp15 cp14 cp13 cp12 cp11 cp10 0245h p1_mr - - mp15 mp14 - - mp11 mp10 port 1 is an 8-bit i/o port. its structure is the same with port 0 , and refers to port 0 for more information. z p1_buf: port 1 output buffer. when p1.n is confi gured as an output pin, it outputs the content of p1_buf.n. z p1: values on port 1 pins while reading from port 1. z p1_cr: configure p1.0 ~ p1.7 to be input or output individually. 0: input, 1: output z p1_mr: configure the output mode of p1.0 ~ p1 .7 with a 17k ohm pull-high resistor, cmos or nmos open drain 3 3 3 port 2 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00d2h p2_buf bp27 bp26 bp25 bp24 bp23 bp22 bp21 bp20 00dah p2 p27 p26 p25 p24 p23 p22 p21 p20 - 0248h p2_cr cp27 cp26 cp25 cp24 cp23 cp22 cp21 cp20 0249h p2_mr - - mp25 mp24 - - mp21 mp20 port 2 is an 8-bit i/o port, its structure is the same wi th port 0 and refers to port 0 for more information. z p2_buf: port 2 output buffer. when p2.n is confi gured as an output pin, it outputs the content of p2_buf.n. z p2: values on port 2 pins while reading from port 2. z p2_cr: configure p2.0 ~ p2.7 to be input or output individually. 0: input, 1: output z p2_mr: configure the output mode of p2.0 ~ p2 .7 with a 17k ohm pull-high resistor, cmos or nmos open drain port 3 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00d3h p3_buf bp37 bp36 bp35 bp34 bp33 bp32 bp31 bp30 00d9h p3 p37 p36 p35 p34 p33 p32 p31 p30 - 0244h p3_cr cp37 cp36 cp35 cp34 cp33 cp32 cp31 cp30 0245h p3_mr - - mp35 mp34 - - mp31 mp30 port 3 is an 8-bit i/o port, its structure is the same wi th port 0 and refers to port 0 for more information. z p3_buf: port 3 output buffer. when p3.n is confi gured as an output pin, it outputs the content of p3_buf.n. z p3: values on port 3 pins while reading from port 3.
14 mpc2f35_usb data sheet megawin z p3_cr: configure p3.0 ~ p3.7 to be input or output individually. 0: input, 1: output z p3_mr: configure the output mode of p3.0 ~ p3 .7 with a 17k ohm pull-high resistor, cmos or nmos open drain when port 3 is used as the input mode, it provides the pin interrupt function while a falling edge occurs at any pin of the port 3 and will set the p3 bit of the irq_st sfr. the same event can release the stop mode to enable the oscillator, and this interrupt also can release the halt mode if the p3 bit in the rlh_en sfr is set. finally, an interrupt subroutine will be executed if setting the p3 bit in the irq_e sfr. port 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00d1h p4_buf bp47 bp46 bp45 bp44 bp43 bp42 bp41 bp40 ? ? 00dch p4 - - - - - - p41 p40 ? - 0250h p4_cr - - - - - - cp41 cp40 ? ? 0251h p4_mr - - - - - - mp41 mp40 ? ? mpc2f35 only provide two pins (p4.0 and p4.1) on the port 4, and these pins also are i/o pins. the structure is the same with port 0 , and please refers to port 0 for more information. z p4_buf: port 4 output buffer. when p4.n is confi gured as an output pin, it outputs the content of p4_buf.n. z p4: values on port 4 pins while reading from port 4. z p4_cr: configure p4.0 and p4.1 to be input or output individually. 0: input, 1: output z p4_mr: configure the output mode of p4.0 and p4.1 with a 17k ohm pull-high resistor, cmos or nmos open drain 3 i/o pin p0.n data bus buffer output p0_mr.1 p0_cr.x lda p0_buf instruction enable vdd input/output pin --- p0~p4 p0_mr.0 enable lda p0 instruction enable p0_cr.x p0_mr.1 3
megawin mpc2f35_usb data sheet 15 usb interface mpc2f35 provides the interface of ps/2 and usb combinative operation by programming the below registers, the user can be eas ily change the configuration bet ween usb and ps/2 for meeting the environment of the host. usb register access control address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00e0h usb_ctl regc - - - - - uwt urd ? ? 00e1h usb_addr - - ua5 ua4 ua3 ua2 ua1 ua0 ? ? 00e2h usb_di udi7 udi6 udi 5 udi4 udi3 udi2 udi1 udi0 - ? 00e2h usb_do udo7 udo6 udo 5 udo4 udo3 udo2 udo1 udo0 ? - z usb_ctl: usb bus control register, regc: 3.3v regulator control. 0: disable (default), 1: enable urd: usb register read control, writing 1 into this bit to read the usb register addressed by the usb_addr sfr uwt: usb register write control, writing 1 into this bit to write the usb register addressed by the usb_addr sfr z usb_addr: one usb register address to be accessed z usb_di: data to be written into the usb register addressed by the usb_addr sfr z usb_do: data to be read out from the u sb register addressed by the usb_addr sfr mpc2f35 is a low-speed usb 1.1 version compli ant with the usb transceiver and a built-in 3.3v regulator. the 3.3v regulator can be controlled by programming the regc bit in the usb_ctl sfr. there are some usb registers in mpc2f35. the user can access these usb registers through the access the control registers, wh ich is provided by mpc2f35 . the sequence to access usb register should be as the following: a. write sequence: 1. write the address of usb register to be accessed into the usb_addr sfr 2. write 1 into the uwt bit in the usb_ctl sfr 3. write data into the usb_di sfr 4. write 0 into the uwt bit b. read sequence: 1. write the address of usb register to be accessed into the usb_addr sfr 2. write 1 into the urd bit in the usb_ctl sfr 3. read data from the usb_do sfr
16 mpc2f35_usb data sheet megawin 4. write 0 into the urd bit whenever usb engine finished a transaction, it will generate an interrupt to acknowledge mpc2f35. the user can get information about the transacti on through the above sequence. when usb engine received a reset instruction fr om the host, it will reset by itself and generate an interrupt. when usb engine received a wake-up instruction from the host wh ile the device is being in the stop mode, it will generate a signal to enable the oscillator. if the host and the device are both in the stop mode, a falling edge on port 3 can wake-up the device, and then remote wake up the host through usb engine. dpm control address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r w 00e8h dpm_ctl - - - - - - c1 c0 ? ? 00e9h dpmo - - - - - - dpo dmo ? ? 00eah dpmi - - - - - - dpi dmi ? - z c1, c0: usb bus (d+ and d-) mode control selector. 1. 0x: usb bus is at the usb operation (default) 2. 10: usb bus is at the ps/2 interface operation z dpmo: ps/2 data output on usb data bus line (d+/d-), 0: output low, 1: pull-high z dpmi: value on the usb data bus line (read only) while working at the ps/2 operation mpc2f35?s usb bus lines (d+ and d -) have two op erating modes: usb low speed and ps/2 interface mode. user can program the c0 and c1 bit in t he cdpm_ctl sfr to determine the operating mode of usb bus. the dpi and dmi bit in the dpmi sfr will record the content on the d+ and d- pin respectively. the firmware can judge the usb bus line (d+ and d-) connection will be usb or ps/2 protocol by reading the value of the dpi and dmi bit in the dpmi sfr. for ps/2 interface application, the c1 and c0 in the dpm_ctl sfr have to set ?10? first, t hus the usb function will be unavailable. the user programs the value of usb bus (d+/d-) into the dpo and dmo bit in the dpmo sfr when mpc2f35 controls the d+/d- pin for the ps/2 operation. when dp o/dmo is programming as writing 0, it will make the d+/d- pin to output low. on t he other hand, writing 1 will cause these pins to be pulled high. this i/o control operation would be easy to perform the ps/2 interface.
megawin mpc2f35_usb data sheet 17 usb special function registers (sfrs) summary there are 18 special function registers for the oper ation of universal serial bus (usb). the detail definition is described as the following: mnemonic usb device sfrs address description dcon device control register 01h testen ? ? ? ? ? puren conpuen faddr function address register 08h ? a6 a5 a4 a3 a2 a1 a0 fpcon function power control register 12h ? ? frwu ? urst ? frsm fsus mnemonic usb interrupt system sfrs address description fie usb function interrupt enable register 18h ? ? ? frxie3 ftxie2 ftxie1 frxie0 ftxie0 fiflg usb function interrupt flag register 1ah ? ? ? frxd3 ftxd2 ftxd1 frxd0 ftxd0 ien1 usb interrupt e nable register 10h ? ? ? efsr ? ef ? mnemonic usb endpoint sfrs address description epindex endpoint index register 31h ? ? ? ? ? ? epinx1 epinx0 epcon* endpoint control register 21h rxstl txstl ? ? ? rxepen ? txepen rxcnt* receive fifo byte-count register 26h ? ? ? ? rxbc3 rxbc2 rxbc1 rxbc0 rxcon* receive fifo control register 24h rxclr ? ? rxffrc ? ? ? ? rxdat* receive fifo data register 23h rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 rxstat* endpoint receive status register 22h rxseq rxsetup stovw edovw rxsovw ? ? ? txcnt* transmit fifo byte -count register 36h ? ? ? ? txbc3 txbc2 txbc1 txbc0 txcon* transmit fifo control register 34h txclr ? ? ? ? ? ? ? txdat* transmit fifo data register 33h td7 td6 td5 td4 td3 td2 td1 td0 txstat* endpoint transmit status register 32h txseq ? ? ? txsovw ? ? ?
18 mpc2f35_usb data sheet megawin usb sfr description dcon: device control register read/write address: 01h default: 0xxx_xx00 system reset bit number bit mnemonic function 7 testen test mode enable: use for test only. in normal operation, this bit should be cleared to ?0?. 6 - reserved: write zero to this bit. 5 - reserved: write zero to this bit. 4 - reserved: write zero to this bit. 3 - reserved: write zero to this bit. 2 - reserved: write zero to this bit. 1 puren internal pull-up resistor enable: when this bit is set to ?1?, enable internal d- pull-up resistor. after setting this bit, the device will ac t a connection to usb host. 0 conpuen device usp connection pull-up enable: this bit is used by fw to control whether device is connected to upper host/hub via driving bus se0. set ?1? to release bus to expose the d- pull- up resistor. clear ?0? to force bus se0 to inhibit the d- pull-up resistor. default is cleared to ?0? after reset. fw should set ?1? to enable connection to upper host/hub.
megawin mpc2f35_usb data sheet 19 faddr: usb function address register read/write address: 08h default: x000_0000 system reset or usb reset bit number bit mnemonic function 7 - reserved: write zero to this bit. 6:0 a [6:0] function address: this register holds the address for the usb function. during bus enumeration, it is written with a unique value assigned by the host.
20 mpc2f35_usb data sheet megawin fpcon: function power control register read/write address: 12h default: xx0x_xx00 system reset or usb reset bit number bit mnemonic function 7 - reserved: write zero to this bit. 6 - reserved: write zero to this bit. 5 frwu function remote wake-up trigger: this bit is used by the function to initiate a remote wake-up on the usb bus when uc is wake-up by the external trigger. 4 - reserved: write zero to this bit. 3 urst usb reset flag: set by hardware when the function detects the usb bus reset. if this bit is set, and then the chip will generate the interrupt. should be cleared by firmware when serving the usb reset interrupt. 2 - reserved: write zero to this bit. 1 frsm function resume flag: set by hardware when the function detects the resume state on the usb bus. if this bit is set, and then the chip will generate the interrupt. cleared by firmware when servicing the function resume interrupt. 0 fsus function suspend flag: set by hardware when the function detects the suspend state on the usb bus. if this bit is set, and then the chip will generate the interrupt. during the function suspend isr, firmware should clear this bit before enter the suspend mode.
megawin mpc2f35_usb data sheet 21 fie: function interrupt enable register read/write address: 18h default: xxx0_0000 system reset or usb reset bit number bit mnemonic function 7 - reserved: write zero to this bit. 6 - reserved: write zero to this bit. 5 - reserved: write zero to this bit. 4 frxie3 function receive interrupt enable 3: enables the receive done interrupt for function endpoint 3 (frxd3). 3 ftxie2 function transmit interrupt enable 2: enables the transmit done interrupt for function endpoint 2 (ftxd2). 2 ftxie1 function transmit interrupt enable 1: enables the transmit done interrupt for function endpoint 1 (ftxd1). 1 frxie0 function receive interrupt enable 0: enables the receive done interrupt for function endpoint 0 (frxd0). 0 ftxie0 function transmit interrupt enable 0: enables the transmit done interrupt for function endpoint 0 (ftxd0).
22 mpc2f35_usb data sheet megawin fiflg: function interrupt flag register read/write address: 1ah default: xxx0_0000 system reset or usb reset bit number bit mnemonic function 7 - reserved: write zero to this bit. 6 - reserved: write zero to this bit. 5 - reserved: write zero to this bit. 4 frxd3 function receive done flag 3: for endpoint 3, uc can read/write-clear on this bit. this bit is cleared when firmware writes ?1? to it. 3 ftxd2 function transmit done flag 2: for endpoint 2, uc can read/write-clear on this bit. this bit is cleared when firmware writes ?1? to it. 2 ftxd1 function transmit done flag 1: for endpoint 1, uc can read/write-clear on this bit. this bit is cleared when firmware writes ?1? to it. 1 frxd0 function receive done flag 0: for endpoint 0, uc can read/write-clear on this bit. this bit is cleared when firmware writes ?1? to it. 0 ftxd0 function transmit done flag 0: for endpoint 0, uc can read/write-clear on this bit. this bit is cleared when firmware writes ?1? to it.
megawin mpc2f35_usb data sheet 23 ien1: usb interrupt enable register read/write address: 10h default: xxxx_0x0x system reset bit number bit mnemonic function 7 - reserved: write ?one? to this bit. 6 - reserved: write zero to this bit. 5 - reserved: write zero to this bit. 4 - reserved: write zero to this bit. 3 efsr enable function suspend/resume: function suspend/resume/usb reset interrupt enable bit. 2 - reserved: write zero to this bit. 1 ef enable function: transmit/receive done interrupt enable bit for usb function endpoints. 0 - reserved: write zero to this bit.
24 mpc2f35_usb data sheet megawin epindex: endpoint index register read/write address: 31h default: xxxx_xx00 system reset or usb reset bit number bit mnemonic function 7 - reserved: write zero to this bit. 6 - reserved: write zero to this bit. 5 - reserved: write zero to this bit. 4 - reserved: write zero to this bit. 3 - reserved: write zero to this bit. 2 - reserved: write zero to this bit. 1:0 epinx1:0 endpoint index bit 1:0: epindex < [7:0]> = < xxxx xx00> : function endpoint 0 = < xxxx xx01> : function endpoint 1 = < xxxx xx10> : function endpoint 2 = < xxxx xx11> : function endpoint 3
megawin mpc2f35_usb data sheet 25 epcon: endpoint control register (endpoint-indexed) read/write address: 21h default: 00xx_x0x0 system reset or usb reset bit number bit mnemonic function 7 rxstl stall receive endpoint: set this bit to stall the receive endpoint. 6 txstl stall transmit endpoint: set this bit to stall the transmit endpoint. 5 - reserved: write zero to this bit. 4 - reserved: write zero to this bit. 3 - reserved: write ?one? to this bit. 2 rxepen receive endpoint enable: set this bit to enable the receive endpoint. when disabled, the endpoint does not respond to a valid out or setup token. 1 - reserved: write ?one? to this bit. 0 txepen transmit endpoint enable: this bit is used to enable the transmit endpoint. when disabled, the endpoint does not respond to a valid in token.
26 mpc2f35_usb data sheet megawin rxcnt: receive fifo byte-count register (endpoint-indexed) read only address: 26h default: xxxx_0000 sy stem reset or usb reset bit number bit mnemonic function 7 - reserved: write zero to this bit. 6 - reserved: write zero to this bit. 5 - reserved: write zero to this bit. 4 - reserved: write zero to this bit. 3 rxbc3 receive byte count bit 3: store receive byte count. maximum is 8 bytes. 2 rxbc2 receive byte count bit 2: store receive byte count. maximum is 8 bytes. 1 rxbc1 receive byte count bit 1: store receive byte count. maximum is 8 bytes. 0 rxbc0 receive byte count bit 0: store receive byte count. maximum is 8 bytes.
megawin mpc2f35_usb data sheet 27 rxcon: receive fifo control register (endpoint-indexed) read/write address: 24h default: 0xx0_xxxx system reset or usb reset bit number bit mnemonic function 7 rxclr receive fifo clear: set this bit to flush the entire receive fifo. all fifo statuses are reverted to their reset states. hardware clears this bit when the flush operation is completed. 6 - reserved: write zero to this bit. 5 - reserved: write zero to this bit. 4 rxffrc receive fifo read complete: set this bit to release the receive fifo when data set read is complete. hardware clears this bit after the fifo release operation has been finished. 3 - reserved: write zero to this bit. 2 - reserved: write zero to this bit. 1 - reserved: write zero to this bit. 0 - reserved: write zero to this bit.
28 mpc2f35_usb data sheet megawin rxdat: receive fifo data register (endpoint-indexed) read only address: 23h default: xxxx_xxxx system reset or usb reset bit number bit mnemonic function 7:0 rd [7:0] receive fifo data specified by epi ndex is stored and read from this register.
megawin mpc2f35_usb data sheet 29 rxstat: endpoint receive status register (endpoint-indexed) read/write address: 22h default: 0000_0xxx system reset or usb reset bit number bit mnemonic function 7 rxseq receive endpoint sequence bit (read, conditional write): the bit will be toggled on completion of an ack handshake in response to an out token. this bit can be written by firmware if the rxovw bit is set when written along with the new rxseq value. 6 rxsetup received setup transaction: this bit is set by hardware when a valid setup transaction has been received. clear this bit upon detection of a setup transaction or the firmware ready to handle the data/st atus stage of control transfer. 5 stovw start overwrite flag (read-only): set by hardware upon receipt of a setup token for any control endpoint to indicate that the receive fifo is bei ng overwritten with new setup data. this bit is used only for control endpoints. 4 edovw end overwrite flag: this flag is set by hardware during the handshake phase of a setup stage. this bit is cleared by firmware to read fifo data. this bit is only used for control endpoints. 3 rxsovw receive data sequence overwrite bit: write ?1? to this bit to allow the value of the rxseq bit to be overwritten. writing a ?0? to this bit, it has no effect on rxseq. this bit always returns to ?0? when read. 2 - reserved: write zero to this bit. 1 - reserved: write zero to this bit. 0 - reserved: write zero to this bit.
30 mpc2f35_usb data sheet megawin txcnt: transmit fifo byte-count register (endpoint-indexed) write only address: 36h default: xxxx_xxxx system reset or usb reset bit number bit mnemonic function 7 - reserved: write zero to this bit. 6 - reserved: write zero to this bit. 5 - reserved: write zero to this bit. 4 - reserved: write zero to this bit. 3 txbc3 transmit byte count bit 3: store transmit byte count. maximum is 8 bytes. 2 txbc2 transmit byte count bit 2: store transmit byte count. maximum is 8 bytes. 1 txbc1 transmit byte count bit 1: store transmit byte count. maximum is 8 bytes. 0 txbc0 transmit byte count bit 0: store transmit byte count. maximum is 8 bytes.
megawin mpc2f35_usb data sheet 31 txcon: transmit fifo control register (endpoint-indexed) read/write address: 34h default: 0xxx_xxxx system reset or usb reset bit number bit mnemonic function 7 txclr transmit fifo clear: set this bit to flush the entire transmit fifo. all fifo statuses are reverted to their reset states. hardware clears this bit when the flush operation is completed. 6 - reserved: write zero to this bit. 5 - reserved: write zero to this bit. 4 - reserved: write zero to this bit. 3 - reserved: write zero to this bit. 2 - reserved: write zero to this bit. 1 - reserved: write zero to this bit. 0 - reserved: write zero to this bit.
32 mpc2f35_usb data sheet megawin txdat: transmit fifo data register (endpoint-indexed) write only address: 33h default: xxxx_xxxx system reset or usb reset bit number bit mnemonic function 7:0 td [7:0] data to be transmitted in the fifo spec ified by epindex is written to this register.
megawin mpc2f35_usb data sheet 33 txstat: endpoint transmit status register (endpoint-indexed) read/write address: 32h default: 0xxx_0xxx system reset or usb reset bit number bit mnemonic function 7 txseq transmit endpoint sequence bit (read, conditional write): the bit will be transmitted in the next pid and toggled on a valid ack handshake of an in transaction. this bi t can be written by firmware if the txsovw bit is set when written along with the new txseq value. 6 - reserved: write zero to this bit. 5 - reserved: write zero to this bit. 4 - reserved: write zero to this bit. 3 txsovw transmit data sequence overwrite bit: write a "1" to this bit to allow the value of the txseq bit to be overwritten. writing a "0" to this bit has no effect on txseq. this bit always returns to "0" when read. 2 - reserved: write zero to this bit. 1 - reserved: write zero to this bit. 0 - reserved: write zero to this bit.
34 mpc2f35_usb data sheet megawin application circuit 1. normal: vcc vss -rst xtal1 xtal2 d+ d- 6m hz 1 uf p0/p1/p2/ p3/p4 + - 30 pf 30 pf 0.1 uf 0.1 uf 10 uf 15 pf 30 vbus d - d + gnd 30 15 pf vss v3.3 + - note: the capacitor between resb-pi n and ground must be below 0.1uf. 2. usb keyboard: r4 c6 c11 c10 r0 connector 1 2 3 4 c0 c2 vcc r3 c7 y1 6mhz c7 0.1u r5 r1 30 option d2 capslock c14 r2 c5 10u c13 c12 c9 c3 c17 vcc r2 30 c4 c8 1u option r7 c3 30p r1 d3 numlock c5 d1 scrolllock vcc c2 15p c4 30p c1 15p option c6 0.1u u1 MPC2F35E2_40 pin dip 3 2 1 4 14 15 16 17 18 19 20 40 38 37 36 35 34 33 32 31 30 29 28 27 5 6 9 10 11 12 13 26 25 24 23 22 21 7 8 39 d- v3.3 d+ vss p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.1 vcc p0.2/led2 p0.1/led1 p0.0/led0 /rst p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 xtal1 xtal2 p0.6 p0.7 p1.0 p1.1 p1.2 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p0.4/-int0 p0.5/-int1 p0.3/led3 c8 c15 c16 r6 c1
megawin mpc2f35_usb data sheet 35 absolute maximum rating parameter rating unit supply voltage to ground potential -0.5 to +6.0 v maximum current per pin excluding v dd and v ss 25 ma maximum current out of gnd 100 ma maximum current out of vcc 100 ma ambient operating temperature 0 to +70 c storage temperature -40 to +125 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability o f the device. dc characteristics (v dd -v ss = 5.0 v, f osc = 6mhz, ta = 25 c; unless otherwise specified) parameter sym. conditions min. typ. max. unit op. voltage v dd 3.0v v3.3
3.6v 4.35 - 5.5 v op. current i op no load (ext.-v) in normal operation - 12.5 20 ma suspend current i stb internal 7.5k with no load - - 500 a input high voltage v ih - 2 - v dd v input low voltage v il - 0 - 0.8 v port 0, 1, 2, 3 drive current i oh v oh = 4.5v, v dd = 5.0v - 2.5 - ma port 0.4~0.7, 1, 2, 3 sink current i ol1 v ol = 0.4v, v dd = 5.0v - 4.0 - ma port 0.0~0.3 sink current i ol2 v ol = 3.2v, v dd = 5.0v 6 8 - ma internal pull-high resistor r ph v il = 0v - 27k - ac characteristics parameter sym. conditions min. typ. max. unit cpu op. frequency f cpu v dd = 5.0v 0.5 3 - mhz por duration t por f osc = 6 mhz 10 - - ms
36 mpc2f35_usb data sheet megawin package dimensions 40-pin dip 28-ssop
megawin mpc2f35_usb data sheet 37 instruction set summary symbol description acc: accumulator (acc): contents of accumulator acc.n: accumulator bit n x: index register x y: index register y sp: stack pointer register pc: program counter #data: constant parameter c: carry flag z: zero flag i: interrupt disable status b: break status d: decimal mode status v: overflow flag s: sign flag addr 16 : absolute address addr 8 : zero page/relative address addr+(index) : combined address addr 16 : address extend to absolute address (get two addr 8 contents continuously) label: address variable ~: 1?s compliment : and : or : exclusive or : transfer direction, result
38 mpc2f35_usb data sheet megawin instruction set summary (212 instructions) mnemonic operand(s) operation description flag byte cycle adc addr 8 (acc) (acc) + (addr 8 ) + (c) c, z, v,s 2 3 #data (acc) (acc) + #data + (c) c, z, v,s 2 2 (addr 8) (acc) (acc) + [(addr 8) ] + (c) c, z, v,s 2 5 addr 8 , x (acc) (acc) + [addr 8 + (x)] + (c) c, z, v,s 2 4 (addr 8 , x) (acc) (acc) + {[addr 8 + (x) 16 ]} + (c) c, z, v,s 2 6 (addr 8 ), y (acc) (acc) + [(addr 8 16 ) + (y)] + (c) c, z, v,s 2 5 * addr 16 (acc) (acc) + (addr 16 ) + (c) c, z, v,s 3 4 addr 16 , x (acc) (acc) + [addr 16 + (x)] + (c) c, z, v,s 3 4 * addr 16 , y (acc) (acc) + [addr 16 + (y)] + (c) c, z, v,s 3 4 * sbc addr 8 (acc) (acc) ? (addr 8 ) ? (~c) c, z, v,s 2 3 #data (acc) (acc) ? #data ? (~c) c, z, v,s 2 2 (addr 8) (acc) (acc) ? [(addr 8) ] ? (~c) c, z, v,s 2 5 addr 8 , x (acc) (acc) ? [addr 8 + (x)] ? (~c) c, z, v,s 2 4 (addr 8 , x) (acc) (acc) ? {[addr 8 + (x) 16 ]} ? (~c) c, z, v,s 2 6 (addr 8 ), y (acc) (acc) ? [(addr 8 16 ) + (y)] ? (~c) c, z, v,s 2 5 * addr 16 (acc) (acc) ? (addr 16 ) ? (~c) c, z, v,s 3 4 addr 16 , x (acc) (acc) ? [addr 16 + (x)] ? (~c) c, z, v,s 3 4 * addr 16 , y (acc) (acc) ? [addr 16 + (y)] ? (~c) c, z, v,s 3 4 * and addr 8 (acc) (acc) (addr 8 ) z, s 2 3 #data (acc) (acc) #data z, s 2 2 (addr 8) (acc) (acc) [(addr 8) ] z, s 2 5 addr 8 , x (acc) (acc) [addr 8 + (x)] z, s 2 4 (addr 8 , x) (acc) (acc) {[addr 8 + (x) 16 ]} z, s 2 6 (addr 8 ), y (acc) (acc) [(addr 8 16 ) + (y)] z, s 2 5 * addr 16 (acc) (acc) (addr 16 ) z, s 3 4 addr 16 , x (acc) (acc) [addr 16 + (x)] z, s 3 4 * addr 16 , y (acc) (acc) [addr 16 + (y)] z, s 3 4 * note: * add one clock period of page boundary is crossed.
megawin mpc2f35_usb data sheet 39 mnemonic operand(s) operation description flag byte cycle ora addr 8 (acc) (acc) (addr 8 ) z, s 2 3 #data (acc) (acc) #data z, s 2 2 (addr 8) (acc) (acc) [(addr 8) ] z, s 2 5 addr 8 , x (acc) (acc) [addr 8 + (x)] z, s 2 4 (addr 8 , x) (acc) (acc) {[addr 8 + (x) 16 ]} z, s 2 6 (addr 8 ), y (acc) (acc) [(addr 8 16 ) + (y)] z, s 2 5 * addr 16 (acc) (acc) (addr 16 ) z, s 3 4 addr 16 , x (acc) (acc) [addr 16 + (x)] z, s 3 4 * addr 16 , y (acc) (acc) [addr 16 + (y)] z, s 3 4 * eor addr 8 (acc) (acc) (addr 8 ) z, s 2 3 #data (acc) (acc) #data z, s 2 2 (addr 8) (acc) (acc) [(addr 8) ] z, s 2 5 addr 8 , x (acc) (acc) [addr 8 + (x)] z, s 2 4 (addr 8 , x) (acc) (acc) {[addr 8 + (x) 16 ]} z, s 2 6 (addr 8 ), y (acc) (acc) [(addr 8 16 ) + (y)] z, s 2 5 * addr 16 (acc) (acc) (addr 16 ) z, s 3 4 addr 16 , x (acc) (acc) [addr 16 + (x)] z, s 3 4 * addr 16 , y (acc) (acc) [addr 16 + (y)] z, s 3 4 * cmp addr 8 (acc) ? (addr 8 ) ? (~c) c, z, s 2 3 #data (acc) ? #data ? (~c) c, z, s 2 2 (addr 8) (acc) ? [(addr 8) ] ? (~c) c, z, s 2 5 addr 8 , x (acc) ? [addr 8 + (x)] ? (~c) c, z, s 2 3 (addr 8 , x) (acc) ? {[addr 8 + (x) 16 ]} ? (~c) c, z, s 2 6 (addr 8 ), y (acc) ? [(addr 8 16 ) + (y)] ? (~c) c, z, s 2 5 * addr 16 (acc) ? (addr 16 ) ? (~c) c, z, s 3 4 addr 16 , x (acc) ? [addr 16 + (x)] ? (~c) c, z, s 3 4 * addr 16 , y (acc) ? [addr 16 + (y)] ? (~c) c, z, s 3 4 * cpx #data (x) ? #data c, z, s 2 2 addr 8 (x) ? (addr 8 ) c, z, s 2 3 addr 16 (x) ? (addr 16 ) c, z, s 3 4 cpy #data (y) ? #data c, z, s 2 2 addr 8 (y) ? (addr 8 ) c, z, s 2 3 addr 16 (y) ? (addr 16 ) c, z, s 3 4 note: * add one clock period of page boundary is crossed.
40 mpc2f35_usb data sheet megawin mnemonic operand(s) operation description flag byte cycle clc (c) 0 c 1 2 cli (i) 0 i 1 2 cld (d) 0 d 1 2 clv (v) 0 v 1 2 rmb0 addr 8 (addr 8.0 ) 0 z 2 5 ? rmb7 addr 8 (addr 8.7 ) 0 z 2 5 sec (c) 1 c 1 2 sei (i) 1 i 1 2 sed (d) 1 d 1 2 smb0 addr 8 (addr 8.0 ) 1 z 2 5 ? smb7 addr 8 (addr 8.7 ) 1 z 2 5 inc a (acc) (acc) + 1 c, z 1 2 inc addr 8 (addr 8 ) (addr 8 ) + 1 z, s 2 5 addr 8 , x [addr 8 + (x)] [addr 8 + (x)] + 1 z, s 2 6 addr 16 (addr 16 ) (addr 16 ) + 1 z, s 3 6 addr 16 , x [addr 16 + (x)] [addr 16 + (x)] + 1 z, s 3 6 * inx (x) (x) + 1 z, s 1 2 iny (y) (y) + 1 z, s 1 2 dec a (acc) (acc) ? 1 c, z 1 2 dec addr 8 (addr 8 ) (addr 8 ) ? 1 z, s 2 5 addr 8 , x [addr 8 + (x)] [addr 8 + (x)] ? 1 z, s 2 6 addr 16 (addr 16 ) (addr 16 ) ? 1 z, s 3 6 addr 16 , x [addr 16 + (x)] [addr 16 + (x)] ? 1 z, s 3 6 * dex (x) (x) ? 1 z, s 1 2 dey (y) (y) ? 1 z, s 1 2 note: * add one clock period of page boundary is crossed. if the assembler does not support this instruction, please use db to implement it. the op code of rmb0 ~ rmb7 is 07 ~ 77, and the smb0 ~ smb7 is 87 ~ f7.
megawin mpc2f35_usb data sheet 41 mnemonic operand(s) operation description flag byte cycle rol a (c) (acc. 7 ), (acc. (n+1) ) (acc. n ), (acc. 0 ) (c) c, z, s 1 2 rol addr 8 (c) (addr 8 . 7 ), (addr 8 . (n+1) ) (addr 8 . n ), (addr 8 . 0 ) (c) c, z, s 2 5 addr 8 , x (c) [addr 8 + (x) . 7 ], [addr 8 + (x) . (n+1) ] [addr 8 + (x) . n ], [addr 8 + (x) . 0 ] (c) c, z, s 2 6 addr 16 (c) (addr 16 . 7 ), (addr 16 . (n+1) ) (addr 16 . n ), (addr 16 . 0 ) (c) c, z, s 3 6 addr 16 , x (c) [addr 16 + (x) . 7 ], [addr 16 + (x) . (n+1) ] [addr 16 + (x) . n ], [addr 16 + (x) . 0 ] (c) c, z, s 3 6 ror a (acc. 7 ) (c), (acc. n ) (acc. (n+1) ), (c) (acc. 0 ) c, z, s 1 2 ror addr 8 (addr 8 . 7 ) (c), (addr 8 . n ) (addr 8 . (n+1) ), (c) (addr 8 . 0 ) c, z, s 2 5 addr 8 , x [addr 8 + (x) . 7 ] (c), [addr 8 + (x) . n ] [addr 8 + (x) . (n+1) ], (c) [addr 8 + (x) . 0 ] c, z, s 2 6 addr 16 (addr 16 . 7 ) (c), (addr 16 . n ) (addr 16 . (n+1) ), (c) (addr 16 . 0 ) c, z, s 3 6 addr 16 , x [addr 16 + (x) . 7 ] (c), [addr 16 + (x) . n ] [addr 16 + (x) . (n+1) ], (c) [addr 16 + (x) . 0 ] c, z, s 3 6 asl a (c) (acc. 7 ), (acc. (n+1) ) (acc. n ), (acc. 0 ) 0 c, z, s 1 2 asl addr 8 (c) (addr 8 . 7 ), (addr 8 . (n+1) ) (addr 8 . n ), (addr 8 . 0 ) 0 c, z, s 2 5 addr 8 , x (c) [addr 8 + (x) . 7 ], [addr 8 + (x) . (n+1) ] [addr 8 + (x) . n ], [addr 8 + (x) . 0 ] 0 c, z, s 2 6 addr 16 (c) (acc. 7 ), (acc. (n+1) ) (acc. n ), (acc. 0 ) 0 c, z, s 3 6 addr 16 , x (c) [addr 16 + (x) . 7 ], [addr 16 + (x) . (n+1) ] [addr 16 + (x) . n ], [addr 16 + (x) . 0 ] 0 c, z, s 3 6 lsr a (acc. 7 ) 0, (acc. n ) (acc. (n+1) ), (c) (acc. 0 ) c, z, s 1 2 lsr addr 8 (addr 8 . 7 ) 0, (addr 8 . n ) (addr 8 . (n+1) ), (c) (addr 8 . 0 ) c, z, s 2 5 addr 8 , x [addr 8 + (x) . 7 ] 0, [addr 8 + (x) . n ] [addr 8 + (x) . (n+1) ], (c) [addr 8 + (x) . 0 ] c, z, s 2 6 addr 16 (addr 16 . 7 ) 0, (addr 16 . n ) (addr 16 . (n+1) ), (c) (addr 16 . 0 ) c, z, s 3 6 addr 16 , x [addr 16 + (x) . 7 ] 0, [addr 16 + (x) . n ] [addr 16 + (x) . (n+1) ], (c) [addr 16 + (x) . 0 ] c, z, s 3 6
42 mpc2f35_usb data sheet megawin mnemonic operand(s) operation description flag byte cycle lda #data (acc) #data z, s 2 2 lda addr 8 (acc) (addr 8 ) z, s 2 3 (addr 8) (acc) [(addr 8) ] z, s 2 5 addr 8 , x (acc) [addr 8 + (x)] z, s 2 4 (addr 8 , x) (acc) {[addr 8 + (x) 16 ]} z, s 2 6 (addr 8 ), y (acc) [(addr 8 16 ) + (y)] z, s 2 6 * addr 16 (acc) (addr 16 ) z, s 3 4 addr 16 , x (acc) [addr 16 + (x)] z, s 3 4 * addr 16 , y (acc) [addr 16 + (y)] z, s 3 4 * ldx #data (x) #data z, s 2 2 addr 8 (x) (addr 8 ) z, s 2 3 addr 8 , y (x) [addr 8 + (y)] z, s 2 4 addr 16 (x) (addr 16 ) z, s 3 4 addr 16 , y (x) [addr 16 + (y)] z, s 3 4 * ldy #data (y) #data z, s 2 2 addr 8 (y) (addr 8 ) z, s 2 3 addr 8 , x (y) [addr 8 + (x)] z, s 2 4 addr 16 (y) (addr 16 ) z, s 3 4 addr 16 , x (y) [addr 16 + (x)] z, s 3 4 * note: * add one clock period of page boundary is crossed.
megawin mpc2f35_usb data sheet 43 mnemonic operand(s) operation description flag byte cycle sta addr 8 (addr 8 ) (acc) - 2 3 (addr 8) [(addr 8) ] (acc) - 2 5 addr 8 , x [addr 8 + (x)] (acc) - 2 4 (addr 8 , x) {[addr 8 + (x) 16 ]} (acc) - 2 6 (addr 8 ), y [(addr 8 16 ) + (y)] (acc) - 2 6 * addr 16 (addr 16 ) (acc) - 3 4 addr 16 , x [addr 16 + (x)] (acc) - 3 4 * addr 16 , y [addr 16 + (y)] (acc) - 3 4 * stx addr 8 (addr 8 ) (x) - 2 3 addr 8 , y [addr 8 + (y)] (x) - 2 4 addr 16 (addr 16 ) (x) - 3 4 sty addr 8 (addr 8 ) (y) - 2 3 addr 8 , x [addr 8 + (x)] (y) - 2 4 addr 16 (addr 16 ) (y) - 3 4 stz addr 8 (addr 8 ) 00h - 2 3 addr 8 , x [addr 8 + (x)] 00h - 2 4 addr 16 (addr 16 ) 00h - 3 4 addr 16 , x [addr 16 + (x)] 00h - 3 5 tax (x) (acc) z, s 1 2 txa (acc) (x) z, s 1 2 tay (y) (acc) z, s 1 2 tya (acc) (y) z, s 1 2 tsx (x) (sp) z, s 1 2 txs (sp) (x) - 1 2 trb addr 8 (addr 8 ) (~acc) (addr 8 ) - 2 5 addr 16 (addr 16 ) (~acc) (addr 16 ) - 3 6 tsb addr 8 (addr 8 ) (acc) (addr 8 ) - 2 5 addr 16 (addr 16 ) (acc) (addr 16 ) - 3 6 note: * add one clock period of page boundary is crossed.
44 mpc2f35_usb data sheet megawin mnemonic operand(s) operation description flag byte cycle jmp label (pc) label; the label may be address or variable. - 3 3 (label ) (pc) (label) - 3 6 (label, x ) (pc) {[label + (x) 16 ]} - 3 6 bra addr8 (pc) (pc)+addr 8 - 2 3 beq addr 8 (relative) (pc) (pc)+addr 8 if z == 1 (+/- relative) - 2 2 ** bne addr 8 (pc) (pc)+addr 8 if z == 0 (+/- relative) - 2 2 ** bcs addr 8 (pc) (pc)+addr 8 if c == 1 (+/- relative) - 2 2 ** bcc addr 8 (pc) (pc)+addr 8 if c == 0 (+/- relative) - 2 2 ** bmi addr 8 (pc) (pc)+addr 8 if (s == 1) - 2 2 ** bpl addr 8 (pc) (pc)+addr 8 if (s == 0) - 2 2 ** bvs addr 8 (pc) (pc)+addr 8 if (v == 1) - 2 2 ** bvc addr 8 (pc) (pc)+addr 8 if (v == 0) - 2 2 ** bit addr 8 (acc) (addr 8 ) z 2 3 addr 8 , x (acc) [addr 8 + (x)] z 2 4 addr 16 (acc) (addr 16 ) z 3 4 addr 16 , x (acc) [addr 16 + (x)] z 3 4 #data (acc) #data z 2 2 bbr0 addr 8 (pc) (pc)+addr 8 if acc.0 == 0 (+/- relative) - 3 5 ? bbr7 addr 8 (pc) (pc)+addr 8 if acc.7 == 0 (+/- relative) - 3 5 bbs0 addr 8 (pc) (pc)+addr 8 if acc.0 == 1 (+/- relative) - 3 5 ? bbs7 addr 8 (pc) (pc)+addr 8 if acc.7 == 1 (+/- relative) - 3 5 note: ** add one clock period if branch occurs to location in same p age. add two clock periods if branch to another page occurs. if the assembler does not support this instruction, please use db to implement it. the op code of bbr0 ~ bbr7 is 0f ~ 7f, and the bbs0 ~ bbs7 is 8f ~ ff.
megawin mpc2f35_usb data sheet 45 mnemonic operand(s) operation description flag byte cycle jsr label stack (pc), (pc) label - 3 6 rts (pc) pop stack - 1 6 rti (pc) pop stack, restore status register p c, z, i, d, v, s 1 6 pha [(sp)] (acc), (sp) (sp) ? 1 - 1 3 php [(sp)] (p), (sp) (sp) ? 1 - 1 3 phx [(sp)] (x), (sp) (sp) ? 1 - 1 3 phy [(sp)] (y), (sp) (sp) ? 1 - 1 3 pla (acc) [(sp+1)], (sp) (sp) + 1 z, s 1 4 plp (p) [(sp+1)], (sp) (sp) + 1 c, z, i, d, v, s 1 4 plx (x) [(sp+1)], (sp) (sp) + 1 z, s 1 4 ply (y) [(sp+1)], (sp) (sp) + 1 z, s 1 4 nop no operation - 1 2 note: ** add one clock period if branch occurs to location in same p age. add two clock periods if branch to another page occurs.
46 mpc2f35_usb data sheet megawin revision history version date page description a1 2004/04 initial issue a2 2005/01 39 application circuit has been modified. a3 2005/07 17~33 revised usb special function regi sters (sfrs) summary and usb sfr description. a4 2008/12 formatting

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