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cmos 200 mhz quadrature digital upconverter ad9856 rev. c in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . specifications subjec t to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . features universa l low cost modulator solution for communications applications dc to 80 mhz o u tput bandwidth integrated 12 - b it d/a convert e r programmable sample rate in terpolation filter programmable reference clock multipli er internal sin(x)/x compensation filter >52 db sfdr @ 40 mh z a out >48 db sfdr @ 70 mh z a out >80 db narrow-band sfdr @ 70 mhz a out +3 v single-s u pply operation space-saving s u rface-mount packaging bidirectional control bus interface supports burst and continuous tx modes single-tone mode for freque nc y synthes is applications four program m able, pin-sele ctable, modula tor profiles direct interfac e to ad8 320/a d 8321 pg a cable dri v er applic ati o ns hfc data, te lephony, and vi de o modems wireless and sa tellite commun i cations cellu lar base st ations general description the ad9856 in t e g r a t es a hig h sp eed , dir e c t dig i tal syn t h e s i zer (d ds), a hig h p e r f o r ma n c e , hig h s p ee d , 12-b i t digi tal-t o -a nalo g co n v er t e r (d a c ), clo c k m u l t i p li er cir c ui t r y , dig i t a l f i l t ers, an d ot he r d s p f u nc t i ons on a s i ng l e ch ip to f o r m a c o m p l e te q u adra t u r e dig i t a l u p con v er t e r de vic e . th e ad9856 is in t e nde d t o f u n c t i on as a uni v ers a l i/q mo d u l a t o r an d a g i l e u p con v er t e r f o r c o m m u n i c at i o n s ap p l i c at i o n s w h e r e c o s t , s i z e , p o w e r dissi p a t io n, and d y na mic p e r f o r ma n c e a r e cr i t i c a l a t t r ib u t es. the ad9856 is a v a i la b l e in a s p ace-s a vin g s u r f ace-m o un t p a cka g e, and is sp e c if ie d to o p e r a t e o v er t h e ex tende d i n d u st r i a l t e m p era t ur e ra ng e o f ?40c t o +85c. func tio n a l block di agram 00637-c-001 12-bit dac 12 12 12 cosine sine complex data in reference clock in txenable (i / q sync) profile select 1? 2 profile select 3?4 master reset spi interface to ad8320/ad8321 programmable cable driver amplifier dac r set dc-80 mhz output bidirectional spi control interface: 32-bit frequency tuning word frequency update interpolation filter rate reference clock multiplier rate spectral phase inversion enable cable driver amplifier control 12 12 12 12 12 12 d e m u ltiplexer a n d serial-to-parallel conv e r te r 12 12 inv sinc 12 ad9856 4 to 8 2 to 63 2 to 63 4 to 20 prog. 4 to 8 selectable interpolating halfbands selectable interpolating halfbands clock multiplier selectable interpolator selectable interpolator dds and control functions fi g u r e 1 .
ad9856 rev. c | page 2 of 36 table of contents specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 explanation of test levels ........................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 8 typical modulated output spectral plots ................................. 8 typical single-tone output spectral plots ............................... 9 typical narrow-band sfdr spectral plots ............................ 10 typical phase noise spectral plots ........................................... 10 typical plots of output constellations .................................... 11 power consumption .................................................................. 12 serial control bus register ........................................................... 13 register bit definitions .............................................................. 14 theory of operation ...................................................................... 15 modulation mode operation ................................................... 15 input word rate (f w ) vs. refclk relationship .................... 16 i/q data synchronization ......................................................... 16 half-band filters (hbfs) .......................................................... 20 cascaded integrator comb (cic) filter .................................. 21 digital quadrature modulator ................................................. 23 inverse sinc filter (isf) ............................................................. 24 direct digital synthesizer function ........................................ 25 d/a converter ............................................................................ 25 reference clock multiplier ....................................................... 26 throughput and latency ........................................................... 26 control interface ........................................................................ 26 general operation of the serial interface ............................... 26 instruction byte .......................................................................... 27 serial interface port pin descriptions ..................................... 28 msb/lsb transfers .................................................................... 28 notes on serial port operation ................................................ 28 programming/writing the ad8320/ad8321 cable driver amplifier gain control ............................................................. 30 understanding and using pin-selectable modulator profiles ....................................................................................................... 31 power dissipation considerations ........................................... 31 ad9856 evaluation board ........................................................ 32 support ........................................................................................ 32 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 35 revision history 1/05rev. b to rev. c updated format..................................................................universal changes to table 2............................................................................ 5 changes to input word rate (f w ) vs. refclk relationship section.................................................................. 16 changes to cascaded integrator comb (cic) filter section ... 21 updates to direct digital synthesizer function section........... 25 added support section.................................................................. 32 updated outline dimensions ....................................................... 35 changes to ordering guide .......................................................... 35 9/99rev. a to rev. b
ad9856 rev. c | page 3 of 36 specifications v s = +3 v 5%, r set = 3.9 k?, external reference clock frequency = 10 mhz with refclk multiplier enabled at 20. table 1. parameter temp test level min typ max unit ref clock input characteristics frequency range refclk multiplier disabled full vi 5 200 1 mhz refclk multiplier enabled at 4 full vi 5 50 mhz refclk multiplier enabled at 20 full vi 5 10 mhz duty cycle 25c v 50 % input capacitance 25c v 3 pf input impedance 25c v 100 m? dac output characteristics resolution 12 bits full-scale output current 5 10 20 ma gain error 25c i ?10 +10 %fs output offset 25c i 10 a differential nonlinearity 25c v 0.5 lsb integral nonlinearity 25c v 1 lsb output capacitance 25c v 5 pf phase noise @ 1 khz offset, 40 mhz a out refclk multiplier enabled at 20 25c v ?85 dbc/hz refclk multiplier at 4 25c v ?100 dbc/hz refclk multiplier disabled 25c v ?110 dbc/hz voltage compliance range 25c i ?0.5 1.5 v wideband sfdr: 1 mhz analog out 25c iv 70 dbc 20 mhz analog out 25c iv 65 dbc 42 mhz analog out 25c iv 60 dbc 65 mhz analog out 25c iv 55 dbc 80 mhz analog out 25c iv 50 dbc narrow-band sfdr: ( 100 khz window) 70 mhz analog out 25c iv 80 dbc modulator characteristics adjacent channel power (ch power = ?6.98 dbm) 25c iv 50 dbm error vector magnitude 25c iv 1 2 % i/q offset 25c iv 50 55 db inband spurious emissions 25c iv 45 50 dbc pass-band amplitude ripple (dc to 80 mhz) 25c v 0.3 db 1 for 200 mhz operation in modulation mode at 85c operat ing temperature, v s must be 3 v minimum.
ad9856 rev. c | page 4 of 36 parameter temp test level min typ max unit timing characteristics serial control bus maximum frequency full iv 10 mhz minimum clock pulse width high (t pwh ) full iv 30 ns minimum clock pulse width low (t pwl ) full iv 30 ns maximum clock rise/fall time full iv 1 ms minimum data setup time (t ds ) full iv 25 ns minimum data hold time (t dh ) full iv 0 ns maximum data valid time (t dv ) full iv 30 ns wake-up time 2 full iv 1 ms minimum reset pulse width high (t rh ) full iv 5 refclk cycles cmos logic inputs logic 1 voltage 25c i 2.6 v logic 0 voltage 25c i 0.4 v logic 1 current 25c i 12 a logic 0 current 25c i 12 a input capacitance 25c v 3 pf cmos logic outputs (1 ma load) logic 1 voltage 25c i 2.7 ma logic 0 voltage 25c i 0.4 ma power supply +v s current full operating conditions 3 25c i 530 ma burst operation (25%) 25c i 450 ma single-tone mode 25c i 495 ma 160 mhz clock 25c i 445 ma 120 mhz clock 25c i 345 ma power-down mode 25c i 2 ma 2 assuming 1.3 k? and 0.01 f loop filter components. 3 assuming 1.3 kw and 0.01 mf loop filter components.
ad9856 r e v. c | pa ge 5 o f 3 6 absolute maximum ratings a b s o l u te max i m u m r a t i n g s a r e lim i t i ng va l u e s , to b e a p plie d indivi d u a l ly , and b e yo nd w h ich t h e s e r v ic e a b i li ty o f t h e c i r c ui t m a y b e im pa i r e d . f u n c t i o n al o p era b ili t y un d e r a n y o f th ese co ndi t i on s is n o t n e ce ss a r i l y im plie d . e x p o sur e o f a b s o l u t e max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s o f t i me ma y af fe c t d e v i c e rel i a b i l it y . table 2. p a r a m e t e r r a t i n g maximum junction temperature 150c storage temperature ?65c to +150c v s 4 v operating temperature ?40c to +85c digital inputs ?0.7 v to +v s lead temperature (soldering 10 sec) 300c digital output c u rrent 5 ma ja thermal imp e dance 38c/w expl ana t ion of test levels i. 100% p r o d uc t i o n t e st ed . iii. sa m p le t e s t e d o n l y . i v . p a r a me te r i s g u ar an te e d b y d e s i g n an d ch ar a c te r i z a t i on te st i n g . v . p a ra m e t e r is a typ i cal val u e o n ly . vi. de vices a r e 100 % p r o d uc t i o n t e s t ed a t 25c and g u ar an te e d b y d e s i g n a n d ch ar a c te r i z a t i on te st i n g for ind u s t r i al o p er a t in g t e m p era t ur e ra n g e . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad9856 r e v. c | pa ge 6 o f 3 6 pin conf iguration and fu nction descriptions 00637-c-002 36 35 34 33 32 31 30 29 28 27 26 25 13 14 1 5 16 17 1 8 19 20 21 22 2 3 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 43 42 41 40 37 pin 1 identifier top v ie w ( n o t t o s c al e) ad9856 ca data ca enable pll supply pll filter pll gnd agnd i out t x enable d11 d10 dvdd dgnd d9 d8 nc = n o c o nne ct d7 d6 dvdd dgnd i outb agnd avdd dac ref bypass bg ref bypass d5 dac r set nc dvdd dg nd nc d0 d1 d2 d3 d4 nc ag nd sync i/o cs r e fc lk sclk reset ps0 dvdd dg nd ca cl k ps1 sdo sdio f i gure 2. pin config ur ation ta ble 3. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic pin function pin no. mnemonic pin function 1 txenable input pulse that synchronizes the data stream 32 pll gnd pll ground 2 d11 input data (mos t significant bit) 33 pll filter pll loop filter connection 3 d10 input data 34 pll supply pll voltage sup p ly 4, 10, 21, 44 dvdd digital supply voltage 35 ca enable cable driver amp enable 5, 11, 20, 43 dgnd digital ground 36 ca data cable driver am p data 6 to 9 d9 to d6 input data 37 ca clk cable driver am p clock 12 to 16 d5 to d1 input data 38 cs chip select 17 d0 input data (least significan t bit) 39 sdo serial data output 18, 19, 22 nc no internal connecti on 40 sdio serial port i/o 23, 28, 31 agnd analog ground 41 sclk serial port clock 24 bg ref bypass no external connection 1 42 sync i/o performs i/o synchroni z ation 25 dac r set r set resistor connection 45 ps0 profile select 0 26 dac ref bypass no external connection 1 46 ps1 profile select 1 27 avdd analog supply voltage 47 refclk reference clock input 29 i ou t b complem e ntary analog current output of the d a c 48 reset master reset 30 i ou t true analog current output of dac 1 in mos t cas e s , optimal performance is ac hieved with no external conne ction. for extremel y noisy en vironments , bg re f byp a s s ca n be bypassed with up to a 0.1 f ca pa ci t o r t o agn d (pi n 23). d a c r e f b y pa ss ca n be bypa sse d wi t h up t o a 0. 1 f ca pa ci t o r t o a v d d (pi n 27) .
ad9856 rev. c | page 7 of 36 table 4. functional block mode descriptions functional block mode description operating modes 1. comple x quadrature modulator mode. 2. single-tone output mode. input data format programmable: 12-bit, 6-bit, or 3-bit input formats. data input to the ad9856 is 12-bit, twos complement. complex i/q symbol component data is required to be at le ast 2 oversampled, depending upon configuration. input sample rate up to 50 msam ples/sec @ 200 mhz sysclk rate. input reference clock frequency for dc to 80 mhz a out operation (200 mhz sysclk rate) with refc lk multiplier enabled: 10 mhz to50 mhz, programmable via control bus; with re fclk multiplier disabled: 200 mhz. note: for optimum data synchronization, the ad9856 referenc e clock and the input data clock should be derived from the same clock source. internal reference clock multiplier programmable in integer steps over the range of 4 to 20 . can be disabled (effective refclk multiplier = 1) via control bus. output of refclk multiplier = sysclk rate, wh ich is the internal clock rate applied to the dds and dac function. profile select four pin-selectable, preprogrammed formats. available for modulation and single-tone operating modes. interpolating range fixed 4, selectable 2, and selectable 2 to 63 range. half-band filters interpolating filters that provide upsampling and reduce the effects of the cic passband roll-off characteri stics. txenable functionC burst mode when burst mode is enabled via the control bus, the rising edge of the applied txenable pulse should be coincident with, and frame, the in put data packet. this establishes data sampling synchronization. txenable functionC continuous mode when continuous mode is enabled via the control bus, the txenable pin becomes an i/q control line. a logic 1 on txenable indicates i data is being presented to the ad9856. a logic 0 on txenable indicates q data is being presented to the ad9856. each rising edge of txenable resynchronizes the ad9856 input sampling capability. inverse sinc filter precompensates for si n(x)/x roll-off of dac; user bypassable. i/q channel invert [i cos( t) + q sin( t)] or [i cos( t) ? q sin( t)] (default), configurable via control bus, per profile. full sleep mode power dissipation reduced to less than 6 mw when full sleep mode is active; programmable via the control bus.
ad9856 r e v. c | pa ge 8 o f 3 6 typical perf orm ance cha r acte ristics t y p i c a l mo dul a ted o u tput spec tr al pl o t s ?80 ?72 ?64 ?56 ?48 ?40 ?32 ?24 ?16 ?8 0 (dbm) stop 50mhz start 0hz 5mhz/ ref lvl ?25dbm rbw vbw swt 10db dbm rf att unit 10khz 1khz 12.5s 1ap 00637-c-003 f i gure 3. q p sk at 4 2 mh z and 2.5 6 ms /sec; 1 0 .2 4 m h z e x tern al c l o c k w i th r e fclk m u lt ipl i er = 1 2 , cic = 3, hb 3 o n , 2 d a t a ?80 ?72 ?64 ?56 ?48 ?40 ?32 ?24 ?16 ?8 0 (dbm) stop 40mhz start 0hz 4mhz/ ref lvl ? 30dbm rbw vbw swt 10db dbm rf att unit 10khz 1khz 10s 1ap 00637-c-004 0 f i g u re 4. 64- qa m a t 28 m h z and 6 m s /s ec; 3 6 m h z e x te r n al cl ock w i t h r e fclk m u lt ipl i er = 4, cic = 2, h b 3 o f f , 3 d a t a ?80 ?72 ?64 ?56 ?48 ?40 ?32 ?24 ?16 ?8 0 (dbm) stop 80mhz start 0hz 8mhz/ ref lvl ? 25dbm rbw vbw swt 10db dbm rf att unit 10khz 1khz 20s 1ap 00637-c-005 f i g u re 5. 16- qa m a t 65 m h z and 2. 5 6 m s /s ec; 1 0 .2 4 m h z e x tern al c l o c k w i t h r e fclk m u lt ipl i er = 1 8 , cic = 9, hb 3 o f f , 2 d a t a ?80 ?72 ?64 ?56 ?48 ?40 ?32 ?24 ?16 ?8 0 (dbm) stop 50mhz start 0hz 5mhz/ ref lvl ? 30dbm rbw vbw swt 10db dbm rf att unit 10khz 1khz 12.5s 1ap 00637-c-006 f i gure 6. 25 6- qam at 3 8 m h z and 6 m s /sec; 4 8 mh z e x te r n al cl ock w i th r e fclk m u lt ipl i er = 4, cic = 2, h b 3 o f f , 4 d a t a
ad9856 r e v. c | pa ge 9 o f 3 6 ty pic a l single- t one output spec tr al pl o t s ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (dbm) stop 100mhz start 0hz 10mhz/ ref lvl ? 5dbm rbw vbw swt rf att unit 3khz 3khz 28s 20db db 1ap a 00637-c-007 f i g u re 7. 21 m h z c w o u t p ut ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (dbm) stop 100mhz start 0hz 10mhz/ ref lvl ? 5dbm rbw vbw swt rf att unit 3khz 3khz 28s 20db db 1ap a 00637-c-008 f i g u re 8. 65 m h z c w o u t p ut ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (dbm) stop 100mhz start 0hz 10mhz/ ref lvl ? 5dbm rbw vbw swt rf att unit 3khz 3khz 28s 20db db 1ap a 00637-c-009 f i g u re 9. 42 m h z c w o u t p ut ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (dbm) stop 100mhz start 0hz 10mhz/ ref lvl ? 5dbm rbw vbw swt rf att unit 3khz 3khz 28s 20db db 1ap a 00637-c-010 f i gure 10. 7 9 m h z c w o u tput
ad9856 rev. c | page 10 of 36 ty pic a l narro w -band sfdr spe c tr al pl o t s ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 (dbm) span 100khz center 70.1mhz 10khz/ ref lvl ? 5dbm rbw vbw swt 20db db rf att unit 100hz 100hz 50s 1ap a 00637-c-011 f i gure 11. 7 0 .1 mh z na rro w - b a nd sf dr, 1 0 mh z e x te rn al c l ock wit h r e fclk m u lt i p lie r = 2 0 ?120 ?108 ?96 ?84 ?72 ?60 ?48 ?36 ?24 ?12 0 (dbm) span 100khz center 70.1mhz 10khz/ ref lvl ? 5dbm rbw vbw swt 20db rf att unit 100hz 100hz 50s db 1ap a 00637-c-012 f i g u re 12. 7 0 .1 m h z na rro w-b a nd sf dr , 2 00 m h z e x ter n al cl ock wit h r e fclk m u lt i p lie r d i s a b l ed ty pic a l phase noise spec tr al pl o t s ? 120 ? 108 ?96 ?84 ?72 ?60 ?48 ?36 ?24 ?12 0 (dbm) span 5khz center 40.1mhz 500hz/ ref lvl 0dbm rbw vbw swt 30db db rf att unit 30hz 30hz 28s 1ap a fxd ?2.248dbm fxd 00637-c-013 f i gure 13. 4 0 .1 mh z o u tput, 1 0 m h z e x tern al cl ock wit h r e fcl k m u lt i p lie r = 2 0 ? 120 ? 108 ?96 ?84 ?72 ?60 ?48 ?36 ?24 ?12 0 (dbm) span 5khz center 40.1mhz 500hz/ ref lvl 0dbm rbw vbw swt 30db rf att unit 30hz 30hz 28s db 1ap a fxd ?2.248dbm fxd 00637-c-014 f i gur e 1 4 . 40 .1 mh z output, 20 0 mhz ex t e r n a l cl oc k wit h r e fclk m u lt i p lie r d i s a b l ed
ad9856 rev. c | page 11 of 36 ty pic a l p l o t s o f o u tp ut c o n s tella t io n s 00637-c-015 ?1.9607843757 1.96078437567 1.5 trace a: ch 1 qpsk meas time const 300 m /div ?1.5 f i g u re 15. qps k , 6 5 m h z, 2. 56 m s /s e c 00637-c-016 ?1.3071895838 1.30718958378 1 trace a: ch 1 64qam meas time const 200 m /div ?1 f i g u re 16. 6 4 - q a m , 42 m h z, 6 m s /s ec 00637-c-017 ?1.6339869797 1.63398697972 1.25 trace a: ch 1 16qam meas time const 250 m /div ?1.25 f i g u re 17. 1 6 - q a m , 65 m h z, 2.5 6 m s /s ec 00637-c-018 ?1.3071895838 1.30718958378 1 trace a: ch 1 256qam meas time const 200 m /div ?1 f i g u re 18. 2 56- qa m , 4 2 m h z, 6 m s /s e c 00637-c-019 ? 1.9607843757 1.96078437567 1.5 trace a: ch 1 msk1 meas time const 300 m /div ? 1.5 f i g u re 19. gm sk m o dul a t i on, 13 m s /s ec
ad9856 rev. c | page 12 of 36 power c o n s umpti o n p o we r cons ump t ion (mw) 800 1000 1200 1400 1600 clock speed (mhz) 140 120 160 180 200 00637-c-020 hb3 = off hb3 = on +v s = +3v cic = 2 +25c f i gure 20. p o wer consumpt ion vs. clock sp eed ; v s = 3 v , cic = 2, 25c p o we r cons ump t ion (mw) 1200 1300 1400 1500 1600 cic rate 16 03 2 4 8 00637-c-021 hb3 = off hb3 = on +v s = +3v cic = 2 200 mhz +25c 6 4 f i gure 21. p o wer consumpt ion vs . cic r a te; v s = 3 v , 20 0 mhz , 2 c p o we r cons ump t ion (mw) 1050 1150 1250 1350 1450 tx enable duty cycle 25 75 50 100 00637-c-022 +v s = +3v cic = 2 200 mhz +25c f i gure 22. p o wer consumpt ion vs. bur s t d u t y c y cle; v s = 3 v , cic = 2, 20 0 m h z, 2 5 c
ad9856 rev. c | page 13 of 36 serial control bus register table 5. serial control bus register layout register ad9856 register layout address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default (hex) profile 00 sdo active lsb first refclk mult.<4> refclk mult.<3> refclk mult.<2> refclk mult.<1> refclk mult.<0> reserved 15 n/a 01 cic gain continuous mode full sleep mode single-tone mode bypass inverse sinc filter bypass refclk mult. input format select <1> input format select <0> 06 n/a 02 frequency tuning word <7:0> 04 1 03 frequency tuning word <15:8> 00 1 04 frequency tuning word <23:16> 00 1 05 frequency tuning word <31:24> 00 1 06 interpolator rate <5> interpolator rate <4> interpolator rate <3> interpolator rate <2> interpolator rate <1> interpolator rate <0> spectral inversion bypass the third half-band filter fc 1 07 ad8320/ad8321 gain control bits <7:0> 00 1 08 frequency tuning word <7:0> 00 2 09 frequency tuning word <15:8> 00 2 0a frequency tuning word <23:16> 00 2 0b frequency tuning word <31:24> 80 2 0c interpolator rate <5> interpolator rate <4> interpolator rate <3> interpolator rate <2> interpolator rate <1> interpolator rate <0> spectral inversion bypass the third half-band filter 1e 2 0d ad8320/ad8321 gain control bits <7:0> 00 2 0e frequency tuning word <7:0> unset 3 0f frequency tuning word <15:8> unset 3 10 frequency tuning word <23:16> unset 3 11 frequency tuning word <31:24> unset 3 12 interpolator rate <5> interpolator rate <4> interpolator rate <3> interpolator rate <2> interpolator rate <1> interpolator rate <0> spectral inversion bypass the third half-band filter unset 3 13 ad8320/ad8321 gain control bits <7:0> 00 3 14 frequency tuning word <7:0> unset 4 15 frequency tuning word <15:8> unset 4 16 frequency tuning word <23:16> unset 4 17 frequency tuning word <31:24> unset 4 18 interpolator rate <5> interpolator rate <4> interpolator rate <3> interpolator rate <2> interpolator rate <1> interpolator rate <0> spectral inversion bypass the third half-band filter unset 4 19 ad8320/ad8321 gain control bits <7:0> 00 4
ad9856 rev. c | page 14 of 36 register bit definitions control bitsregister address 00h and 01h sdo active register address 00, bit 7. active ig indicates serial port uses dedicated in/out lines. default lo configures serial port as single-line i/o. lsb first register address 00, bit 6. active ig indicates serial port access is lsb-to-msb format. default lo indicates msb-to-lsb format. refclk multiplier register address 00, bits 5, 4, 3, 2, 1 form te reference clock multiplier. alid entries range from 420 (decimal). straigt binary to decimal conversion is implemented. for example, to multiply te reference clock by 19 decimal, program register address 00, bits 51, as 13. default value is 0a (ex). reserved bit register address 00, bit 0. tis bit is reserved. alays set tis bit to logic 1 en riting to tis register. cic gain register address 01, bit 7. te cic gain bit multiplies te cic filter output by 2. see te cascaded integrator comb (cic) filter section for more details. default value is 0 (inactive). continuous mode register address 01, bit 6 is te continuous mode configuration bit. active ig configures te ad9856 to accept continuous-mode timing on te txenable input. a lo configures te device for burst-mode timing. default value is 0 (burst mode). full sleep mode register address 01, bit 5. active ig full sleep mode bit. wen activated, te ad9856 enters a full sutdon mode, consuming less tan 2 ma after completing a sutdon sequence. default value is 0 (aake). single-tone mode register address 01, bit 4. active ig configures te ad9856 for single-tone applications. te ad9856 supplies a single-frequency output as determined by te frequency tuning ord (ftw) selected by te active profile. in tis mode, te 12 input data pins are ignored but sould be tied ig or lo. default value is 0 (inactive). bypass inverse sinc filter register address 01, bit 3. active ig configures te ad9856 to bypass te sin(x)/x compensation filter. default value is 0 (inverse sinc filter enabled). bypass refclk multiplier register address 01, bit 2. active ig configures te ad9856 to bypass te refclk multiplier function. wen active, effectively causes te refclk multiplier factor to be 1. default value is 1 (refclk multiplier bypassed). input format select register address 01, bits 1 and 0, form te input format mode bits. 10b 12-bit mode 01b 6-bit mode 00b 3-bit mode default value is 10b (12-bit mode). profile 1 registersactive when profile inputs are 00b frequency tuning word (ftw) te frequency tuning ord for profile 1 is formed via a concatenation of register addresses 05, 04, 03, and 02. bit 7 of register address 05 is te most significant bit of te profile 1 frequency tuning ord. bit 0 of register address 02 is te least significant bit of te profile 1 frequency tuning ord. te output frequency equation is given as f ot (ftw ssclk)/2 32 . interpolation rate register address 06, bit 7 troug bit 2 form te profile 1 cic filter interpolation rate value. alloed values range from 2 to 63 (decimal). spectral inversion register address 06, bit 1. active ig, profile 1 spectral inversion bit. wen active, inverted modulation is performed i cos(t) sin( t). te default is inactive, logic 0, noninverted modulation i cos(t) sin(t). bypass half-band filter 3 register address 06, bit 0. active ig, causes te ad9856 to bypass te tird alf-band filter stage tat precedes te cic interpolation filter. bypassing te tird alf-band filter negates te 2 upsample inerent it tis filter and reduces te overall interpolation rate of te alf- band filter cain from 8 to 4. default value is 0 (half-band 3 enabled). ad8320/ad8321 gain control register address 07, bit 7 troug bit 0 form te profile 1 ad8320/ad8321 gain bits. te ad9856 dedicates tree output pins, ic directly interface to te ad8320/ad8321 cable driver amp. tis allos direct control of te cable driver via te ad9856. see te error! reference source not found. section for more details. bit 7 is te msb, bit 0 is te lsb. default value is 00. profile 2 registers active when profile inputs are 01b profile 2 register functionality is identical to profile 1, with the eception of the register addresses profile 3 registersactive when profile inputs are 10b profile 3 register functionality is identical to profile 1, with the eception of the register addresses profile 4 registers active when profile inputs are 11b profile 4 register functionality is identical to profile 1, with the eception of the register addresses
ad9856 rev. c | page 15 of 36 theory of operation t o ga in a ge n e r a l underst a ndi ng o f t h e f u n c t i ona l i t y o f t h e ad9856, i t is hel p f u l t o r e f e r t o f i gur e 23, a b l o c k dia g ra m o f t h e de vi ce a r chi t e c t u r e . t h e fol l o w in g is a ge n e r a l des c r i pt io n o f th e d e v i ce fun c t i o n ali t y . l a t e r s e cti o n s d e ta il eac h o f th e d a t a pa th b u il di n g b l oc k s . modul a tion mode oper a t ion the ad9856 ac cep t s 12-b i t da t a -w o r ds, w h ic h a r e s t r o be d in t o t h e d a t a ass e m b ler vi a an in t e r n a l clo c k. t h e i n p u t, txen a b l e , s e r v es as t h e valv e t h a t al lo ws da t a t o b e accepte d o r ig n o r e d b y t h e da t a as s e m b ler . the us er has t h e op t i o n t o fe e d t h e 12- b i t da ta-w o r ds t o t h e ad9856 as sin g le 12-b i t w o rds, d u al 6-b i t w o r d s, o r q u ad 3-b i t w o r d s. thi s p r o v ide s t h e us er w i t h t h e f l e x ib i l it y to u s e fe we r i n te r f a c e pi ns , i f d e s i re d. f u r t he r m ore, th e in co mi n g da ta i s as s u m e d t o be co m p le x in th a t al t e rn a t i n g 1 2 - bit word s are re g a rd e d a s t h e i n p h a s e ( i ) an d qu a d r a tu re ( q ) co m p on e n ts o f a sy m b ol. the ra te a t which t h e 12-b i t w o r d s a r e p r es en t e d t o th e ad9856 is r e f e r r ed t o as th e in p u t s a m p l e ra t e (f in ). n o t e tha t f in is n o t t h e s a m e as t h e b a s e b a n d da t a ra t e p r o v i d e d b y t h e us er . r a t h er , t h e us er s b a s e b a nd da t a is r e q u ir e d to b e u p s a m p le d b y a t le a s t a fac t o r o f tw o ( 2 ) bef o r e bein g a p p l ie d t o t h e ad9856 in o r der to min i mi ze t h e f r e q uen c y - dep e nden t a t te n u a t io n ass o ci a t e d wi t h t h e ci c f i l t er s t a g e (s e e t h e c a s c ade d i n te g r a t o r c o m b (ci c ) f i l t er sec t io n ). the da t a ass e m b ler s p li ts t h e inco min g da ta-wo r d p a irs in t o s e pa r a t e i/ q d a ta s t r e a m s . t h e ra t e a t wh i c h th e i / q d a ta - w o r d p a irs a p p e a r a t t h e o u t p u t o f the da ta as s e m b ler is r e f e r r ed t o as th e i/ q sa m p le ra t e (f iq ). b e ca u s e t w o 12-b i t i n p u t da t a -w o r ds a r e used t o co n s tr uct th e in d i v i d u al i a n d q d a ta pa th s, t h e in p u t s a m p le r a t e is t w ice t h e i / q s a m p le ra te (i.e ., f in = 2 f iq ). o n ce th r o ugh t h e da ta as sem b le r , th e i/ q d a t a s t r e a m s a r e f e d t h r o ug h tw o ha l f -b a nd f i l t ers ( h a l f- b a n d f i l t e r s 1 a n d 2). t h e co m b ina t io n o f t h es e t w o f i l t ers r e s u l t s in a fac t o r o f fo ur (4) i n c r e a s e of t h e s a m p l e r a t e . t h u s , a t t h e output of h a l f - b a n d f i l t er 2, t h e s a m p le ra t e is 4 f iq . i n ad di ti o n t o th e s a m p le ra t e in cr e a s e , t h e hal f-b a nd f i l t ers p r o v i d e t h e lo w-p a s s f i l t er in g char ac te r i st ic ne c e ss ar y to su p p r e s s t h e sp e c t r a l im age s pro d u c e d b y t h e up s a m p l i ng pro c e s s . fu r t he r u p s a m p l i ng i s a v a i la b l e via a n o p ti o n al thi r d half- ba n d f i l t er (h alf-ba n d fi lt e r 3 ) . w h e n s e l e c t e d , t h i s pr ov i d e s a n ov e r a l l up s a m p l i n g fac t o r o f eig h t (8). th us, if h a lf -b and f i l t er 3 is s e lec t e d , t h e s a m p le ra te a t i t s o u t p u t is 8 f iq . a f t e r pa s s i n g thr o ugh t h e h a lf-ba n d f i l t e r s t a g es, th e i/ q d a ta st re ams are fe d to a c a s c a d e d i n te g r a t or c o m b ( c ic ) f i lte r . this f i l t er is conf igur e d as a n i n t e r p ola t in g f i l t er , w h ich a l lo ws f u r t h e r u p sa m p lin g ra t e s o f a n y in teg e r val u e b e tw een 2 an d 63, in cl usi v e . th e c i c f i l t er , li k e t h e ha lf-b an ds, has a b u i l t- in lo w- p a ss cha r ac t e r i st ic. a g a i n, t h is p r o v ide s fo r su p p r essio n o f t h e s p e c t r al i m a g es p r o d uce d b y t h e u p s a m p li n g p r o c es s. the dig i t a l quadra t u r e m o d u la t o r s t a g e f o l l o w in g t h e ci c f i l t e r s i s used t o f r eq ue n c y s h i f t th e ba se ba n d s p ectr um o f th e in co mi n g da ta str e a m u p t o th e d e si r e d ca rri e r f r eq ue n c y (a p r o c es s k n o w n as u p con v ersi o n ). th e ca r r ier f r e q uen c y is c o nt r o l l e d nu m e r i c a l l y by a d i r e c t d i g i t a l s y nt h e s i z e r ( d d s ) . the d d s us es i t s in ter n al r e fer e n c e clo c k (s y s clk) t o g e n e ra te t h e desir e d ca r r ier f r e q uen c y wi t h a h i g h deg r e e o f p r e c isio n. the ca r r i er is a p plie d t o t h e i and q m u l t i p liers in quadra t u r e fashion (90 phas e o f fs et) a nd summe d to y i el d a d a t a st r e am th a t i s t h e m o d u la t e d ca rri e r . n o t e t h a t th e in co m i n g da ta h a s b e e n con v er t e d f r o m a n in pu t s a m p le ra te o f f in to an output s a m p l e r a t e of s y s c l k ( s e e fi g u re 2 3 ) . 00637-c-023 data in t xenable data assembler half-band filter #1 half-band filter #2 i q half-band filter #3 12 12 12 dds inv sinc inv sinc bypass r set a out m = 4...20 refclk n = 2...63 (sysclk) (f4) (f3) (f2) (f1) 3, 6, 12 mu x 12 12 12 cos sin cic filter quadrature modulator mu x 12 dac 12 12 12 12 hbf #3 bypass hbf #3 bypass mu x mux 2 2 mu x hbf #3 bypass n (f5) mu x refclk multiplier (m) 2 f i gur e 2 3 . ad98 56 bl oc k dia g r a m
ad9856 rev. c | page 16 of 36 the s a m p le d car r i er is u l t i ma te ly des t i n e d t o s e r v e as t h e i n p u t d a t a to t h e d i g i t a l - to - a n a l o g c o n v e r te r ( d a c ) i n te g r a t e d on t h e ad9856. the d a c o u t p u t s p e c tr um is dis t o r t e d d u e t o t h e i n t r i n s i c z e ro - o rd e r ho l d e f f e c t a s s o c i ate d w i t h d a c - ge ne r a te d sig n a l s. this dist o r t i o n is det e r m inist i c, h o we ver , a nd fol l o w s t h e fa mi l i a r s i n(x)/x (o r s i n c ) en ve lo p e . b e c a us e t h e s i n c d i s t o r ti o n i s p r e d i c ta b l e , i t i s als o co rr ecta b l e th e r e f o r e , th e p r es en c e o f t h e o p t i o n al i n v e rs e s i n c f i l t er p r e c e d i n g t h e d a c . this is a fir f i l t er , w h ich has a t r a n sfer f u n c t i o n co nfo r min g t o t h e i n v e rs e o f t h e s i n c r e s p on s e . th us, w h en s e le c t e d , i t m o d i f i e s t h e in co m i n g da ta s t r e a m so tha t t h e s i n c d i s t o r ti o n , w h ich w o u l d o t h e r w i s e a p p e a r in t h e d a c o u t p u t sp e c t r um, is vir t ual l y e l imi n a t e d . a s m e n t ion e d e a rlier , t h e o u t p ut d a t a is s a m p le d a t t h e ra t e o f s y scl k . b e c a us e t h e a d 985 6 is desig n e d t o o p era t e a t s y scl k f r eq uen c ies u p t o 200 mh z, ther e is t h e p o t e n t ial d i f f i cul t y o f tr yi n g t o p r o v id e a s t a b le i n p u t c l o c k (refclk ) . al t h o u g h s t a b le, co mmer c ial hig h f r e q uen c y os cil l a t o r s te n d t o be cos t p r ohib i t iv e . t o al le via t e this p r ob lem, th e ad9856 has a b u i l t- in p r og ra mma b l e clo c k m u l t i p lier circ ui t. this al lo ws t h e us er to us e a r e l a ti ve ly lo w f r e q uen c y (th u s, les s exp e n s i v e) os cil l a t o r t o g e n e ra te the refcl k sig n al . the lo w f r eq ue n c y r e fc l k s i gn al ca n th en be m u l t i p l i ed in f r eq ue n c y b y a n in teg e r fac t o r betw een 4 a nd 20, in c l usi v e , t o become t h e sy s c l k s i g n a l . single - t one ou tpu t o p er a t ion the ad9856 can b e co nf igur ed f o r f r eq uen c y s y n t h e sis a p plic a t io n s b y wr i t in g t h e s i n g le-t on e b i t t r ue . i n si n g le- t o n e m o de , t h e ad9 856 dis e n g a g es th e mo d u la t o r a nd p r ecedin g da ta p a th log i c to o u t p u t a s p ec t r al l y p u r e , sin g le-f r e q u en c y sine wa v e . th e ad9 856 p r o v ides f o r a 32-b i t f r eq uen c y t u nin g w o rd , which r e s u l t s in a t u nin g r e s o l u tio n o f 0.046 h z a t a s y sclk ra t e o f 200 mh z. w h en usin g t h e ad9856 as a f r eq uen c y syn t h e sizer , a g e n e ra l r u le is t o limi t t h e f u ndam e n t al o u t p u t f r eq uenc y t o 40% o f s y scl k . this a v o i ds gen e r a t i ng a l ia s e s to o clo s e to t h e des i r e d f u ndam e n t a l o u t p u t f r e q ue n c y , t h us min i m i z i ng t h e co st o f f i l t er in g t h e a l ia s e s. al l a p p l icab le p r og ra mmin g f e a t ur es o f the ad9856 a p p l y w h en co nf igur e d in s i n g le-t one mo de. th e s e fe a t ur es in cl ude: ? f r eq ue n c y h o p p i n g vi a t h e p r o f il e i n p u ts a n d as soci a t ed tu n i ng word, w h i c h a l l o w s f r e q u e nc y sh i f t k e y i ng ( f sk ) mo d u l a t i o n . ? a b il i t y t o b y p a ss th e refclk m u l t i p lier , which r e s u l t s in lo w e r phas e n o is e an d r e d u ce d o u t p ut j i t t e r . ? a b i l i t y t o b y p a ss t h e s i n(x)/x c o m p en s a t i on f i l t er . ? fu l l p o w e r - d o w n m o d e . inpu t word r a te (f w ) v s . r e f c l k re la t i o n sh ip t h e r e i s a fun d a m e n t al r e la ti o n s h i p bet w een t h e i n p u t w o r d ra t e (f w ) a nd t h e f r e q uen c y o f t h e clo c k t h a t s e r v es as t h e t i mi n g s o ur ce f o r th e ad9856 (refcl k). th e f w is de f i n e d as t h e r a te a t w h ic h k-b i t da ta-w o r ds (k = 3, 6, o r 12) a r e p r es en t e d t o t h e ad9856. h o we v e r , th e f o l l o w ing fac t o r s a f f e c t this r e l a tio n s h i p : ? the i n t e r p ol a t i o n ra t e o f t h e c i c f i l t er s t a g e . ? whe t he r or no t h a l f - b a n d fi lte r 3 i s b y p a ss e d . ? the val u e o f t h e refclk m u l t i p lier (if s e le c t e d ). ? inp u t w o r d l e n g t h . this re l a t i onsh ip c a n b e su m m e d as ( ) mi hnf refclk w / 2 = w h er e h, n, i , and m a r e in teg e rs det e r m ined as f o l l o w s: h = 1: half-band filter 3 bypassed 2: half-band filter 3 enabled m = 1: refclk multiplier bypassed 4 m 20: refclk multi p lier e n abled i = 1: full-word input format 2: half-word inp u t format 4: quarte r-wor d input format n = cic interpolatio n rate (2 n 6 3 ) th e s e condi t i ons sho w t h a t ref c lk and f w ha ve a n i n teger ra ti o r e la ti o n s h i p . i t i s v e r y i m p o r t a n t th a t use r s c h oose a v a l u e o f r e fc l k t o en s u r e th a t th i s in t e g e r ra t i o r e la ti o n s h i p i s ma in t a i n e d . i/q d a t a sy nchro n iz a t io n a s m e n t ion e d p r evio us l y , t h e ad9856 accep t s i / q da t a p a irs a nd a tw os co m p lem e n t n u m b e r in g sys t em in t h r e e dif f er en t w o r d len g t h m o des. t h e f u l l -w or d m o de ac cep t s 12-b i t p a r a l l el i a nd q d a t a . t h e h a l f-w o r d mo de acc e p t s d u a l 6-b i t i an d q da t a in pu ts t o fo r m a 12-b i t w o r d . th e qua r t e r - w o r d m o de accep t s m u l t i p le 3-b i t i an d q da ta in p u ts t o f o r m a 12-b i t w o r d . f o r al l w o r d len g th m o des, t h e ad9856 as s e m b les the da t a f o r sig n al p r o c es sing in t o t i m e -alig n e d , p a ral l e l , 12 -b i t i/q p a irs. i n addi tion t o t h e w o r d len g th f l exi b ili t y , t h e ad9856 has tw o i n p u t t i ming m o des, b u rst o r co n t in uo us, t h a t a r e p r og ra mma b l e v i a t h e s e r i al p o r t . f o r b u rst- m o de in p u t t i ming, no ext e r n a l da t a clo c k n e e d s t o b e p r o v ide d , b e ca us e t h e da t a is o v ers a m p le d a t t h e d<11:0 > p i n s usin g t h e s y s t em clo c k (s y s clk). the tx en able p i n is r e q u ir e d t o f r a m e t h e da t a b u rs t, b e ca us e t h e r i sin g e d g e o f txen ab le is us ed t o sy n c hr o n ize t h e ad9856 t o th e in p u t da ta ra t e . th e ad9856 r e g i s t ers th e in p u t da ta a t the a p p r o x - ima t e ce n t er o f t h e da t a val i d t i m e . th us, fo r larg er ci c in t e r p ol a t ion ra t e s, m o r e s y s c lk c y cles a r e a v a i la b l e t o o v ers a m p le t h e in p u t da t a , maximi zing clo c k ji t t e r t o lera n c es.
ad9856 rev. c | page 17 of 36 f o r co n t in uo us-m o d e in p u t timin g , t h e txe n ab le p i n can b e t h o u g h t o f as a d a t a i n p u t clo c k r u nnin g a t h a l f t h e i n p u t sa m p l e ra t e (f w / 2 ) . i n a d d i t i on t o s y nch r on i z a t i o n , f o r c o n t i n - uo us m o de timin g , t h e txen ab le in p u t in dic a t e s w h et h e r a n i o r q in p u t is b e in g p r es e n t e d to t h e d < 11:0> p i n s . i t is in t e nde d t h a t d a t a is p r es e n t e d in a l t e r n a t in g fa shio n such t h a t i da ta is f o l l o w ed b y q da ta . s t a t ed an o t h e r wa y , th e txen ab l e p i n sh o u l d ma in ta in a p p r o x ima t e l y a 50/50 d u ty c y c l e . a s in b u r s t m o d e , t h e ri s i n g ed g e o f txen a b l e s y n c h r o n i z e s th e ad9856 t o t h e in p u t da t a ra t e and t h e da ta is r e g i s t er ed a t t h e a p p r o x ima t e ce n t er o f t h e da t a - v ali d t i m e . th e co n t i n uo us o p era t in g m o de ca n o n l y be us e d in co n j u n c t ion wi t h t h e f u l l - word i n put for m a t . burst mo de in put timing f i g u re 2 4 t h rou g h f i g u re 2 8 s h o w t h e i n put t i m i ng re l a t i on sh ip b e tw e e n tx en able and t h e 1 2 -b i t i n p u t d a t a -w o r d fo r a l l thr e e in p u t f o r m a t m o des w h en t h e ad9856 is co nf igur ed f o r b u rst in pu t t i mi n g . als o sh o w n in t h es e d i a g ram s is t h e t i me- alig n e d , 12 -b i t p a ral l e l i/q da t a as as s e m b led b y t h e ad9856. f i gur e 24 sh o w s th e clas sic b u rst-m o de timing, f o r f u l l -w o r d in p u t m o d e , i n w h ich txe n able f r a m es t h e i n p u t d a t a st r e am. n o t e th a t s e q u e n ti a l i n p u t o f a l t e rn a t i n g i/ q d a t a , s t a r t i n g w i th i da t a , is r e q u ir e d . the i n p u t s a m p le r a te fo r f u l l -w o r d m o de, w h e n t h e t h ir d ha lf - b a nd f i l t er is enga ge d , is g i ve n b y n sysclk f in 4 / = w h er e n is t h e ci c in t e r p ola t io n ra t e . the i n p u t s a m p le r a te fo r f u l l -w o r d m o de, w h e n t h e t h ir d ha lf - b a nd f i l t er is n o t en ga ge d is g i ven b y : n sysclk f in 2 / = w h er e n is t h e ci c in t e r p ola t io n ra t e fi g u r e 2 5 s h ow s a n a l t e r n at e t i m i n g m e t h o d f o r t x e n a b l e w h en t h e ad98 56 is co nf igur e d in f u l l -w o r d , b u rst- m o d e o p era t ion. th e ben e f i t o f this t i min g is tha t t h e ad9856 r e syn c hr o n i z es t h e in p u t s a m p l i n g log i c w h e n t h e r i sin g e d g e of txen ab le is det e c t e d . the lo w tim e on txe n able is limi ted to o n e i n p u t s a m p le p e r i o d and m u st b e l o w d u r i n g t h e q da t a p e r i o d . th e maxim u m hig h tim e on txe n able is unlimi t e d . th us, unl i mi t e d hig h t i m e on txen ab le r e s u l t s in the timin g dia g ram o f f i gu r e 24. s e e f i gure 28 f o r th e ra mif i ca tion s o f v i o l a t in g t h e t x en a b l e lo w tim e co n s tra i n t w h en o p e r a t i n g in b u rst m o de . f i gur e 26 sh o w s t h e in p u t t i mi ng fo r ha lf-w o r d m o de, b u rst in p u t t i min g op era t io n. i n ha lf -w o r d mo de , d a t a is in pu t o n t h e d<11: 6> in p u ts. t h e d<5:0> in pu ts ar e un us e d in t h i s m o de and sh ou ld b e t i e d to d g nd o r d v dd . th e ad9856 exp e c t s t h e da t a t o b e in p u t in t h e f o l l o w in g ma nner : i<11:6 > , i<5:0>, q < 11 :6>, q<5:0>. d a ta i s t w o s c o m p l e m e n t ; th e s i gn b i t i s d < 1 1 > i n th e n o ta t i o n i<11:0>, q<11: 0>. the i n p u t s a m p le ra t e fo r half- w o r d m o de , w h en t h e t h ir d half- b a nd f i l t er is enga ge d , is g i ve n b y n sysclk f in 4 / = w h er e n is t h e ci c in t e r p ola t io n ra t e . the i n p u t s a m p le ra t e fo r half- w o r d m o de , w h en t h e t h ir d half- b a nd f i l t er is n o t en ga ge d is g i ven b y : n sysclk f in 2 / = w h er e n is t h e ci c in t e r p ola t io n ra t e . f i gur e 27 sh o w s th e i n p u t tim i n g f o r q u a r t e r - w o r d , b u r s t i n p u t ti m i n g o p e r a t i o n . i n q u a r t e r - w o r d m o de , da ta is in p u t on t h e d<11:9> in p u ts. th e d<8:0> in pu ts ar e un us e d in t h i s m o de and sh ou ld b e t i e d to d g nd o r d v dd . th e ad9856 exp e c t s t h e da t a t o b e in p u t in th e f o l l o w in g ma nn er : i<11:9 > , i<8:6>, i<5:3 > , i<2:0>, q<11:9>, q<8:6 > , q<5:3>, q < 2 : 0>. da ta is tw o s co m p lem e n t ; th e s i g n b i t is d<11> in t h e n o t a tio n i < 11:0>, q<11:0>. the i n p u t s a m p le ra t e fo r q u a r t e r - w o r d m o de , w h en t h e t h ird ha lf-b and f i l t er is en ga ge d , is g i ven b y : n sysclk f in / = w h er e n is t h e ci c in t e r p ola t io n ra t e . n o te t h a t h a lf- b an d f i l t er 3 m u st b e e n ga ge d w h en op er a t i n g in qua r t e r - w o r d m o de . f i gur e 28 des c r i b e s t h e e nd o f b u rst t i m i n g and in ter n a l da t a a s sem b l y . n o t e th a t in b u r s t-m o d e o p e r a t i o n , if th e t x en a b le in p u t is lo w f o r m o r e than on e in p u t s a m p le p e r i o d , n u m e r i c a l z e ro s are i n te r n a l ly ge ne r a te d a nd p a ss e d to t h e d a t a p a t h l o g i c fo r sig n al p r o c e s sin g . this is n o t valid fo r co n t in uo us-m o d e o p er a t ion, as is dis c uss e d l a ter . t o en s u r e p r o p e r o p era t io n, t h e minim u m t i me b e tw e e n fal l i n g an d r i s i ng e d ge s of t x e n a b l e i s one i n put s a m p l e p e r i o d .
ad9856 rev. c | page 18 of 36 00637-c-024 txenable d(11:0) internal i internal q i0 q0 i1 q1 i2 q2 i3 q3 i4 q4 i0 i1 i2 i3 q0 q2 q3 q1 f i gure 24. 12-bit i n put mode , classic b u rst t i ming 00637-c-025 txenable d(11:0) internal i internal q i0 q0 i1 q1 i2 q2 i3 q3 i4 q4 i0 i1 i2 i3 q0 q1 q2 q3 f i gure 25. 12-bit i n put mode , altern ate t x enable t i ming 00637-c-026 txenable d(11:6) internal i internal q i0 i1 q0 q1 i0(11:6) i0(5:0) q0(5:0) i1(11:6) i1(5:0) q1(11:6) q1(5:0) i2(11:6) q0(11:6) i2(5:0) f i gure 2 6 . 6 - bi t inp u t mo d e , burst mode ti mi ng 00637-c-027 i0(11:9) i0(8:6) i0(5:3) i0(2:0) q0(11:9) q0(8:6) q0(5:3) q0(2:0) i1(11:9) i1(8:6) txenable d(11:9) internal i internal q i0 q0 f i gure 2 7 . 3 - bi t inp u t mo d e , burst mode ti mi ng 00637-c-028 txenable d(11:0) internal i internal q in qn i0 q0 i1 q1 in in?2 in?1 qn?2 qn? 1 qn logic 0 logic 0 i0 q0 f i gure 28. end of b u rst mode input timing
ad9856 rev. c | page 19 of 36 c o ntinuous m o de inp u t ti m i ng the ad9856 is co nf igur ed f o r co n t in uo us m o de in p u t timing b y wr i t ing t h e c o n t in uo us m o de b i t tr ue (l og ic 1). th e co n t i n uo us m o de b i t is i n r e g i st er addr es s 01 h, bi t 6. th e ad9856 m u st b e co nf igur ed f o r f u l l -w o r d in p u t f o r m a t wh en o p e r a t in g in co n t in uo us m o d e i n p u t tim i n g . th e i n p u t d a ta ra t e e q ua t i o n s de s c r i b e d p r e v i o u sly fo r f u l l -w o r d mo de a p ply fo r co n t in uo us m o de . f i gur e 25, w h ic h is t h e al t e r n a t e b u rs t m o de ti m i n g dia g ra m , i s also th e co n t in uo us m o d e in p u t ti mi n g . f i gur e 29 an d f i gur e 30 sh o w w h a t t h e in t e r n al da ta as s e m b l e r p r es en ts t o t h e sig n al p r o c es si n g log i c w h e n t h e txen a b le in p u t is h e l d st a t ic fo r g r e a t e r t h a n o n e i n p u t s a m p le p e r i o d . ple a s e n o te t h a t t h e t i m i n g di a g r a m sh o w n i n f i gur e 29 a nd f i g u r e 3 0 d e ta i l i n c o r r e c t ti m i n g r e la t i o n s h i p s be t w e e n tx en a b le and da t a . t h e y a r e o n ly p r es en te d to indi ca te t h a t th e ad9856 r e s y n c hr o n izes p r op erl y a f t e r det e c t in g a r i sin g e d g e o f txen a b le. als o n o te t h a t t h e s i g n if ic a n t dif f er en ce b e tw e e n b u rst and co n t in uo us m o de o p er a t io n is t h a t i n a d di ti o n t o sy n c h r o n i z in g t h e da ta , t x en ab le i s used t o indi ca t e w h et h e r a n i o r q in p u t is b e in g s a m p l e d . do n o t en ga g e c o n t in uo us m o de sim u l t an eo u s l y wi t h t h e refclk m u l t i p lier f u n c t i on. this co r r u p ts t h e ci c i n t e r - p o la t i n g f i l t er , fo r c in g unr e co v e ra b l e ma t h e m a t ical o v er f l o w t h a t c a n on ly b e re s o lve d b y iss u ing a r e s e t c o mmand. t h e p r ob lem is d u e to t h e pll fa i l ing t o b e lo ck e d to t h e r e fer e n c e clo c k w h i l e n o n z er o d a t a is b e i n g clo c k e d in t o t h e in t e r p ola t io n st a g es f r o m t h e d a t a in pu ts. t h e r e co mm e nde d s e q u e n ce is to f i rs t en ga g e t h e refclk m u l t i p lier f u n c t i on (al l o w in g a t le as t 1 m s f o r loo p s t a b iliz a t i o n ) a n d th en e n ga g e co n t in uo us m o d e vi a so f t w a r e . 00637-c-029 qn in+1 qn+1 in+2 qn+2 in+3 qn+3 in+4 qn+4 in+5 in+1 in in?1 in+2 in+3 txenable d(11:0) internal i internal q qn?1 qn qn+ 3 qn+ 4 in+ 4 f i g u re 29. cont inu o us m o d e input ti ming t x e na ble st at ic hig h ( f or i llus t r a t i ve purpos es o n l y ) 00637-c-030 qn in+1 qn+1 in+2 qn+2 in+3 qn+3 in+4 qn+4 in qn+2 qn+1 in in? 1 in+3 txenable d(11:0) internal i internal q qn?1 qn qn + 3 f i g u re 30. cont inu o us m o d e input ti ming t x e na ble st at ic l o w ( f or i llus t r a t i ve pu rpos es on ly )
ad9856 rev. c | page 20 of 36 half-band fil t ers (hb f s) b e f o r e p r e s e n tin g a de ta ile d d e scri p t i o n o f th e h b fs, r e call tha t th e i n p u t da ta s t r e a m i s r e p r e s en ta t i v e o f co m p le x d a ta ; i . e . , t w o in p u t s a m p les ar e r e q u ir e d t o pr o d uce on e i/q da t a p a ir . th e i/q s a m p le ra t e is o n e-half t h e in p u t da t a ra t e . the i/q s a m p le r a te ( t he r a te a t w h i c h i or q s a m p l e s are pre s e n te d to t h e i n put o f t h e fi r s t h a l f - b a n d fi l t e r ) i s r e f e r r e d t o a s f iq . b e ca us e t h e ad9856 is a q u adra t u r e m o d u l a t o r , f iq r e p r es en ts t h e b a s e b a nd o f th e in t e rn al i/ q sa m p l e pa i r s. i t s h o u ld be em p h a s iz ed h e r e th a t f iq is n o t t h e s a me as t h e b a s e b a nd o f t h e us er s sym b ol ra t e da t a , w h ich m u s t b e u p s a m p le d b e fo r e p r es en t a t i o n t o t h e ad9856 (as is exp l a i n e d la t e r). the i/q s a m p le ra t e (f iq ) p u ts a li mi t o n t h e mi n i m u m ba n d w i d t h n e ces s a r y t o tra n sm i t t h e f iq sp e c t r um. t h is is t h e fa mi l i a r n y q u ist li mi t a nd is e q u a l t o one h a l f f iq , whic h is r e f e r r ed t o as f ny q . hb f 1 is a 47-t a p f i l t er tha t p r o v ides a fac t o r -o f - tw o in cr eas e in th e s a m p l i n g ra te . hb f 2 is a 15 -ta p f i l t er o f f e r i n g a n addi tio n a l fac t o r -o f-tw o incr ease in t h e s a m p lin g r a t e . t o g e t h er , h b f 1 a nd hb f 2 p r o v ide a fac t o r -o f-fo ur in cr eas e in th e s a m p lin g ra t e (4 f iq or 8 f ny q ). th e i r c o m b i n e d ins e r t io n loss is a m e re 0.01 db , s o vir t ual l y n o los s o f sig n al le ve l o c c u rs thr o ug h t h e f i rs t tw o h b fs. hb f 3 is a n 11-t a p f i l t er an d , if s e le c t e d , i n c r e a s e s t h e s a m p l i ng r a te b y a n a d d i t i on a l f a c t or of t w o . t h u s , th e ou t p u t s a m p le ra t e o f hb f 3 is 8 f iq o r 16 f ny q . hb f 3 exhi b i ts 0.03 db o f sig n al-leve l l o s s . a s s u ch, t h e los s in sig n al l e vel t h rou g h a l l t h re e h b f s i s o n ly 0 . 0 4 d b a n d m a y b e i g nore d f o r al l p r ac tical p u r p os es. i n r e la t i o n t o phas e r e s p o n s e , a l l t h r e e hbfs a r e li n e a r phas e f i l t ers. a s s u ch, vir t ual l y n o phas e dist o r t i o n is i n t r o d uce d wi t h i n t h e p a ss b a nd o f t h e f i l t e r s. this is a n im p o r t a n t fe a t ur e as phas e dist o r t i o n is gen e ra l l y i n t o lera b l e i n a d a t a tra n smis sio n sy s t em. i n a d d i t i on to k n o w le dge o f t h e in s e r t io n lo ss and phas e re sp ons e of t h e h b f s , s o me k n o w l e d g e of t h e f r e q u e nc y r e s p o n s e o f t h e hb fs is us ef u l as w e l l . the com b in e d f r eq uen c y r e s p o n s e o f h b f 1 a n d 2 is sh o w n in f i gur e 31 a nd f i gur e 32. the us a b le b a nd w i d t h o f t h e f i l t er cha i n p u ts a limi t o n t h e m a xi m u m da ta ra t e tha t ca n be p r o p a g a t ed th r o ugh t h e d e v i ce . a lo ok a t t h e p a ss-b and de t a i l of t h e h b f 1 an d hf b 2 r e sp o n s e indica t e s tha t t o ma in t a in a n am p l i t ude er r o r o f n o m o r e than 1 db , us ers a r e res t r i c t e d t o sig n als ha v i n g a band wid t h o f n o m o r e t h an ab o u t 90% o f f ny q . t o k e ep t h e b a n d wi d t h o f t h e da t a in t h e f l a t p o r t i o n o f t h e f i l t er p a s s b a n d , us ers m u s t o v ers a m p le t h e b a s e b a nd da t a b y a t le ast a f a c t o r o f tw o p r io r t o p r es en t i n g i t t o t h e ad985 6. w i th ou t o v er -s a m p l in g, t h e n y q u is t band- wi d t h o f t h e b a s e b a nd da t a co r r esp o nds to t h e f ny q . a s s u c h , th e u p pe r en d o f th e da ta ba n d w i d t h s u f f e r s 6 d b o r m o r e o f a tte n u a t i o n d u e to t h e f r e q u e nc y re sp ons e of h b f 1 and h b f 2 . f u r t h e r m o r e , if th e bas e band da ta a p p l ied t o the ad9856 has been p u l s e s h a p ed , t h e r e i s a n ad di ti o n al co n c ern . t y p i call y , p u ls e sha p in g is a p plie d t o t h e b a s e b a nd d a t a v i a a f i l t er h a v i n g a r a is e d c o s i ne re sp ons e . i n su c h c a s e s , an v a lu e is u s e d to m o dif y t h e b a nd w i d t h o f t h e da t a w h er e t h e v a l u e o f is s u ch tha t 0 1. a val u e o f 0 c a us es t h e da ta band wid t h t o co r r es p o n d t o t h e n y q u is t b a nd w i d t h. a val u e o f 1 ca us es t h e d a t a b a n d wi d t h to b e ex te nde d to t w ice t h e n y q u ist b a ndwi d t h . th us, wi t h 2 o v ers a m p ling o f t h e b a s e b a n d d a t a a nd = 1, t h e n y q u ist b a nd w i d t h o f t h e da t a co r r es p o n d s wi t h t h e i/q n y q u ist b a ndwi d t h . a s st a t e d e a rlier , t h is r e su l t s in p r ob lems n e a r t h e u p pe r ed g e o f t h e d a ta ba n d w id th d u e t o th e f r eq uen c y re sp ons e of h b f 1 and 2 . ?100 ?90 ?70 ?30 ?10 10 ?50 ?80 ?40 ?20 0 ?60 magnitude (db) 2. 0 1. 5 0. 5 1 . 0 0 2 . 5 3. 0 3 . 5 4. 0 displayed frequency is relative to i/q nyq. bw 00637-c-031 f i g u re 31. h a lf -b an d 1 and 2 f r equ e nc y r e s p ons e ?6 ?5 ?4 ?3 ?2 ?1 0 1 magnitude (db) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 displayed frequency is relative to i/q nyq. bw 00637-c-032 f i gur e 3 2 . p a ss -band d e ta il : com b i n ed f r eq uenc y response o f h b f 1 a n d 2 t o r e i t era t e , t h e us er m u s t ov e r s a m p l e t h e b a s e b a nd da t a b y a t le ast a f a c t or of t w o (2). i n addi tio n , t h er e is a f u r t h e r r e s t r i c t io n o n p u ls e s h a p i n gt h e maxi m u m val u e o f t h a t ca n b e im pl e- m e n t e d is 0.8. this is be ca us e the da t a ban d wid t h be co m e s 1/2(1 + ) f ny q = 0.9 f ny q , w h i c h p u t s th e d a ta b a n d w i d t h a t th e ext r em e e d g e o f t h e f l a t p o r t io n o f t h e f i l t er r e sp o n s e . i f a p a r t ic u l a r a p pli c a t ion r e q u ir es a n va l u e b e twe e n 0.8 an d 1, t h e n t h e us er m u s t ov e r s a m p l e t h e base ba n d da t a b y a t lea s t a fa c t or of f o ur (4) .
ad9856 rev. c | page 21 of 36 i n a p plic a t io n s r e q u ir in g b o t h a lo w d a t a ra t e and a h i g h o u t p ut s a m p le ra te , a t h ir d h b f is a v aila b l e (h b f 3). s e le c t in g h b f 3 o f f e r s a n u p sa m p lin g ra tio o f eigh t (8) ins t ead o f f o ur (4 ). t h e co m b in e d f r eq uen c y r e s p o n s e of hb f 1, 2, a nd 3 is s h o w n in f i gur e 33 an d f i gur e 34. c o m p a r in g t h e p a ss- b a nd de t a i l o f hbf 1 a nd 2 wi t h t h e p a ss -b and det a i l o f hbf 1, 2, a nd 3, h b f 3 h a s vi r t uall y n o i m pa c t o n f r eq ue n c y r e s p o n se f r o m 0 t o 1 (wh e r e 1 co r r es p o n d s t o f ny q ). ?100 ?90 ?70 ?30 ?10 10 ?50 ?80 ?40 ?20 0 ?60 magnitude (db) 4 3 12 05 displayed frequency is relative to i/q nyq. bw 6 7 8 00637-c-033 f i g u re 33. h a lf -b an d 1, 2, and 3 f r equ e nc y r e s p ons e ?6 ?5 ?4 ?3 ?2 ?1 0 1 magnitude (db) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 displayed frequency is relative to i/q nyq. bw 00637-c-034 f i g u re 34. p a s s -ba n d d e t a i l : co mbin e d f r eq uenc y r e s p o n s e of hbf 1 t o 3 c a sc aded integr a t or c o mb ( c ic ) fil t er a ci c f i l t er is u n lik e a typ i cal f i r f i l t er in tha t i t o f f e rs th e f l e x ib i l it y to h a nd l e d i f f e r i n g i n put a n d out p ut s a m p l e r a te s (o nl y in in t e g e r ra tios, h o w e v e r) . i n t h e p u r e s t s e n s e , a ci c f i l t er ca n p r o v ide ei t h er an i n cr e a s e o r a de cr e a s e in t h e s a m p le r a t e a t th e o u t p u t r e la t i v e t o th e i n p u t , d e pe n d i n g o n th e a r c h i - t e c t ur e . i f t h e i n t e g r a t ion s t a g e p r e c e d es t h e com b s t a g e , t h e ci c f i l t er p r o v ides s a m p le ra t e r e d u c t io n (de c ima t io n). w h e n t h e co m b s t a g e p r e c e d es t h e i n teg r a t o r s t a g e t h e ci c f i l t er p r o v ides a n in creas e in s a m p le ra t e (in t er p o l a tion). i n t h e ad9856, t h e ci c f i l t er is co nf igur ed as a n in ter p ola t o r a pro g r a m m a bl e i n te r p o l a t or a n d prov i d e s a s a m p l e r a t e in cr eas e , r , s u ch tha t 2 r 6 3 . i n a d d i t i on t o t h e ab i l i t y t o p r o v id e a chan ge i n s a m p le ra te b e tw e e n i n p u t and o u t p u t , a cic f i l t er a l s o has a n i n t r in sic lo w - p a ss f r e q u e nc y re sp ons e char ac te r i st ic . t h e f r e q u e nc y re sp ons e o f a ci c f i l t er dep e n d s o n : ? t h e ra te c h a n g e ra tio , r. ? the o r der o f t h e f i l t er , n. ? the n u m b er o f uni t dela ys p e r st a g e , m. the sys t e m f u nc t i o n , h(z), o f a ci c f i l t er is g i ven b y : n rm n rm z z z z h ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? = ? = ? ? ? the fo r m o n t h e fa r r i g h t has t h e ad van t a g e o f p r o v i d in g a re su lt f o r z = 1 ( c or re sp ond i ng t o z e ro f r e q u e nc y or d c ) . t h e al t e rn a t e f o rm yi e l d s a n in d e t e r m i n a t e f o rm ( 0 /0 ) f o r z = 1 , b u t is o t h e r w is e iden t i ca l. t h e on ly va r i a b l e p a ra m e t e r fo r th e ad9856 ci c f i l t er is r . m a nd n a r e f i xed a t 1 an d 4, r e s p ec ti ve l y . th us, th e ci c sys t em f u n c tio n f o r th e ad9856 sim p lif i es t o : 4 1 0 4 1 1 1 ) ( ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? = ? = ? ? ? r r z z z z h the t r a n sfer f u n c t i on is g i v e n b y : 4 1 0 ) 2 ( 4 ) 2 ( ) 2 ( 1 1 ) ( ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? = ? = ? ? ? r f j f j fr j e e e f h the f r e q uen c y r e sp o n s e in t h is fo r m is such t h a t f is s c a l e d to t h e output s a m p l e r a te of t h e c i c f i lte r . th a t i s , f = 1 co r r es p o n d s t o t h e f r e q ue n c y o f t h e o u t p ut s a m p le ra t e o f t h e ci c f i l t er . h(f/r) yie l ds t h e f r e q uen c y r e s p o n s e w i t h r e sp e c t to t h e in p u t s a m p l e o f t h e ci c f i l t er . f i gur e 35 t o f i gur e 44 sh o w t h e ci c f r e q ue n c y r e sp o n s e and p a ss-b and d e t a i l fo r r = 2 a n d r = 63, wi th hbf 3 b y p a s s ed . f i gur e 45 t o f i gur e 50 a r e simil a r , b u t h b f 3 is s e l e c t e d . n o te t h e f l a t ter p a ss-b and r e sp o n s e w h e n hb f 3 is em plo y e d . a s wi t h h b fs, c o n s idera t ion m u st b e g i ven t o t h e f r e q ue n c y - dep e nden t a t t e n u a t ion t h a t t h e ci c f i l t er in t r o d uces o v er t h e f r eq ue n c y ra n g e o f th e da ta t o b e tra n sm i t t e d . n o t e th a t t h e ci c f r e q uen c y r e s p o n s e f i gur e s ha v e f ny q a s t h e i r re f e re nc e f r eq ue n c y ; i . e . , un i t y (1) o n th e f r eq ue n c y scal e co rr e s po n d s to f ny q . i f t h e inco min g da ta tha t is a p p l ie d t o t h e ad9856 is o v e r s a m p l e d b y a f a c t or of 2 ( a s re qu i r e d ) , t h e n t h e n y qu i s t b a ndwi d t h o f t h e a p plie d da t a is o n e-h a l f f ny q o n t h e ci c f r eq uen c y r e s p o n s e f i gur e s. a lo ok a t t h e 0.5 p o in t o n t h e p a s s - b a nd d e t a i l f i gu r e s r e ve a l s a w o rst-ca s e a t te n u a t io n o f a b ou t 0.25 db (hb f 3 b y p a s s e d , r = 6 3 ). this, o f co urs e , as s u m e s p u lse-s h a p e d da ta wi t h = 0 (mini m u m b a n d wi d t h s c ena r io). w h en a va l u e of = 1 is us e d , t h e b a ndwi d t h o f t h e da t a co r r es p o n d s t o f ny q (t h e p o in t1. 0 o n t h e ci c f r e q uen c y s c ale). th us, t h e w o rst-cas e a t t e n u a t ion f o r = 1 is a b o u t 0.9 db .
ad9856 rev. c | page 22 of 36 ?150 ?120 ?90 ?60 ?30 0 m a gnitude (db) 16 12 48 02 0 2 4 2 displayed frequency is relative to i/q nyq. bw 00637-c - 035 8 3 2 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 m a gnitude (db) ?1.0 ?0.5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 displayed frequency is relative to i/q nyq. bw 00637-c - 037 f i g u re 35. cic f ilt er f r eq uenc y r e s p on s e (r = 2, hfb 3 b y p a s s e d) f i g u re 36. p a s s -ba n d d e t a i l (r = 2 , hf b 3 b y p a s s e d) ?150 ?120 ?90 ?60 ?30 0 m a gnitude (db) 0 7 2 144 216 258 360 432 504 displayed frequency is relative to i/q nyq. bw 00637-c - 036 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 m a gni t ude (db) ?1.0 ?0.5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 displayed frequency is relative to i/q nyq. bw 00637-c - 038 f i g u re 37. cic f ilt er f r eq uenc y r e s p on s e (r = 63, hfb 3 b y pas s e d) f i g u re 38. p a s s -ba n d d e t a i l (r = 6 3 , h f b 3 b y p a s s e d) the deg r e e o f t h e im p a c t o f t h e a t t e n u a t io n in t r o d uce d b y t h e ci c f i l t er o v er t h e n y q u is t b a nd w i d t h o f t h e da t a is a p pli c a t ion sp e c if ic. the us er m u st de ci de h o w m u ch a t t e n u a t ion is accep t ab le. i f le ss a t t e n u a t io n is desir e d , t h e n a d d i t i o n a l o v e r sa m p lin g o f th e ba se ba n d da ta m u s t be em p l o y ed . al ter n a t i v e l y , t h e us er ca n p r e c om p e n s a t e t h e b a s e b a nd da t a bef o r e p r es en tin g i t t o t h e ad9 856. tha t is, if t h e da ta is p r eco m pe n s a t e d th r o ug h a f i l t er th a t h a s a f r eq ue n c y r e s p o n se cha r ac t e r i s t ic, w h ich is t h e i n vers e o f t h e ci c f i l t er r e s p o n s e , t h e n t h e o v e r a l l s y ste m re sp ons e c a n b e ne arly p e r f e c t l y f l a t te n e d o v er t h e b a ndwi d t h o f t h e da t a . an o t h e r is s u e to co n s ider w i t h t h e ci c f i l t ers i s in s e r t io n los s . u n fo r t una t e l y , ci c ins e r t io n l o ss is n o t f i xe d , b u t is a f u n c t i on o f r , m, a nd n. b e ca us e m, an d n a r e f i xed f o r th e ad9856, t h e ci c ins e r t io n l o ss is a f u n c t i o n o f r o n ly . i n ter p ola t ion ra t e s tha t a r e an in t e g e r p o w e r - o f -2 r e s u l t in n o in s e r t io n loss. h o w e v e r , a l l n o nin t eger p o w e r - o f -2 in t e r p ol a t i o n ra t e s r e su l t i n a sp e c if ic am o u n t o f in s e r t io n loss. t o h e l p o v er com e t h e ins e r t io n los s p r ob lem, th e ad9856 p r o v i d es t h e user a m e a n s t o bo os t th e ga i n th r o ugh t h e ci c s t a g e b y a f a c t o r o f 2 (via t h e cic ga i n b i ts e e t h e s e r i al c o n t r o l bus re g i s t er s e c t ion). the r e as o n fo r t h is fe a t ur e is t o al lo w t h e us er to t a k e adva n t a g e o f t h e f u l l d y na mic ra n g e o f t h e d a c, t h us max i miz i n g t h e sig n a l -to - n o is e ra t i o (s nr) a t t h e o u t p ut o f t h e d a c s t a g e . i t is b e s t t o o p era t e t h e d a c o v er i t s f u ll-scale ra n g e in o r d e r t o min i mize t h e in h e r e n t q u a n t i za tio n ef fe c t s ass o ci a t e d w i t h a d a c. an y sig n if ic a n t loss t h r o ug h t h e ci c s t a g e is r e f l e c t e d a t t h e d a c o u t p u t as a r e d u c t io n in s n r . the d e g r ad a t ion i n s n r can b e o v er co m e b y b o o s t i n g t h e ci c o u t p u t le ve l . t a b l e 6 tab u la t e s in s e r t io n los s as a f u n c t i o n o f r . the val u es a r e pr o v ide d i n li ne ar a n d de c i b e l fo r m , b o t h wi t h a n d w i th o u t th e f a ct o r - o f - 2 g a i n e m p l o y e d . a wo r d o f ca u t i o n: w h e n th e c i c g a i n b i t i s a c ti v e , e n s u r e t h a t th e da t a s u p p l i e d t o t h e ad985 6 is s c ale d do wn t o yie l d an o v eral l ga in o f u n i t y (1) t h r o ug h t h e ci c f i l t er s t a g e . g a in s in exces s o f uni t y a r e li k e l y t o c a us e o v er f l o w er r o rs in t h e da t a pa th , co m p r o m i si n g t h e vali di t y o f th e a n alog o u t p u t si gn al .
ad9856 rev. c | page 23 of 36 ?150 ?120 ?90 ?60 ?30 0 m a gnitude (db) 16 12 48 02 0 2 4 2 displayed frequency is relative to i/q nyq. bw 00637-c -039 8 3 2 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 m a gnitude (db) ?1.0 ?0.5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 displayed frequency is relative to i/q nyq. bw 00637-c -041 f i g u re 39. cic f ilt er f r eq uenc y r e s p on s e (r = 2, hbf 3 s e l e c t ed) f i g u re 40. p a s s -ba n d d e t a i l (r = 2 , h b f 3 s e lec t ed) ?150 ?120 ?90 ?60 ?30 0 m a gnitude (db) 0 144 288 432 576 720 864 1008 displayed frequency is relative to i/q nyq. bw 00637-c - 040 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 m a gni t ude (db) ?1.0 ?0.5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 displayed frequency is relative to i/q nyq. bw 00637-c - 042 f i g u re 41. cic f ilt er f r eq uenc y r e s p on s e (r = 63, hbf 3 ac t i ve) f i g u re 42. p a s s -ba n d d e t a i l (r = 6 3 , h b f 3 ac t i ve) digit a l qu adr a ture modul a t o r f o l l o w in g t h e c i c f i l t er s t a g e t h e i a nd q da t a ( w hich ha ve b e e n p r o c ess e d inde p e n d e n t l y u p to t h is p o i n t ) a r e mixe d i n t h e mo d u l a tor st age to pro d u c e a di g i t a l mo d u l a te d c a r r i e r . th e c a r r i e r f r e q u e nc y i s s e l e c t e d b y pro g r a m m i ng t h e d i re c t d i g i t a l syn t h e sizer (s e e th e dir e c t d i g i tal s y n t h e sizer f u n c tion s e c t ion) wi th t h e a p p r o p r i a t e 32-b i t t u nin g w o r d via t h e ad9856 co n t r o l r e g i s t ers. th e dds sim u l t an e o us l y g e n e ra t e s a dig i tal (s am p l e d ) s i ne a n d c o s i ne w a ve a t t h e pro g r a m m e d c a r r i e r f r e q u e nc y . t h e dig i t a l si n e and co sin e d a t a is m u l t i p lie d b y t h e q a nd i d a t a , r e s p ecti v e l y , t o cr ea t e t h e q u ad ra t u r e co m p o n en t s o f t h e o r ig inal da t a u p co n v er t e d t o t h e ca r r i er f r e q uen c y . th e q u a d r a t u r e co m p o n e n ts a r e dig i t a l l y sum m e d and p a ss e d o n to t h e sub s e q u e n t st age s . the k e y p o in t is t h a t t h e mo d u l a t i o n is do ne d i g i t a l l y , w h ich elim in a t es t h e phas e an d gain i m b a lan c e an d c r osst a l k issues t y p i call y a s soci a t ed w i th a n al og m o d u la t o r s . n o t e th a t th e m o d u l a t e d sig n a l is ac t u a l ly a n u m b er st r e am s a m p le d a t t h e ra t e o f s y s c lk , w h ich is t h e s a m e ra t e a t w h ich t h e d a c is c l o c k e d (s ee f i g u r e 23). n o te t h a t t h e arch ite c tu re of t h e qu a d r a tu re m o d u l a tor re su lt s in a 3 db l o ss of s i g n a l l e v e l. t o v i s u a l i z e t h is , as su me t h a t b o t h th e i da t a a n d q da ta a r e f i x e d a t th e m a xim u m pos s i b le d i g i tal val u e , x . then t h e o u t p ut o f t h e m o d u l a t o r , y , is : y = x cos() + x sin() = x [cos() + sin()] f r om t h i s e q u a t i on , y a ssu me s a m a x i m u m v a lu e of x 2 (a ga in o f 3 db). h o w e v e r , if t h e s a m e n u m b er of b i ts wer e used t o r e p r e s en t t h e y val u es, as is us e d t o r e pr es en t t h e x val u es, a n o v er f l o w w o u l d o c c u r . t o p r e v en t t h is , a n ef fe c t i v e d i v i de -b y-t w o is i m p l em en t e d o n t h e y val u es , w h ich r e d u ces t h e max i m u m v a l u e o f y b y a f a c t or of t w o . b e c a u s e d i v i s i o n b y tw o r e s u l t s in a 6 db los s , t h e mo d u l a t o r yie l ds a n o v eral l los s of 3 db (3 db ? 6 db = ?3 db , o r 3 db o f lo ss).
ad9856 rev. c | page 24 of 36 table 6. cic interpolation filter insertion loss table default gain 2 gain interpolation rate (linear) (db) (linear) (db) 2 1.0000 0.000 2.0000 6.021 3 0.8438 ?1.476 1.6875 4.545 4 1.0000 0.000 2.0000 6.021 5 0.9766 ?0.206 1.9531 5.815 6 0.8438 ?1.476 1.6875 4.545 7 0.6699 ?3.480 1.3398 2.541 8 1.0000 0.000 2.0000 6.021 9 0.7119 ?2.951 1.4238 3.069 10 0.9766 ?0.206 1.9531 5.815 11 0.6499 ?3.743 1.2998 2.278 12 0.8438 ?1.476 1.6875 4.545 13 0.5364 ?5.411 1.0728 0.610 14 0.6699 ?3.480 1.3398 2.541 15 0.8240 ?1.682 1.6479 4.339 16 1.0000 0.000 2.0000 6.021 17 0.5997 ?4.441 1.1995 1.580 18 0.7119 ?2.951 1.4238 3.069 19 0.8373 ?1.543 1.6746 4.478 20 0.9766 ?0.206 1.9531 5.815 21 0.5652 ?4.955 1.1305 1.065 22 0.6499 ?3.743 1.2998 2.278 23 0.7426 ?2.585 1.4852 3.436 24 0.8438 ?1.476 1.6875 4.545 25 0.9537 ?0.412 1.9073 5.609 26 0.5364 ?5.411 1.0728 0.610 27 0.6007 ?4.427 1.2014 1.593 28 0.6699 ?3.480 1.3398 2.541 29 0.7443 ?2.565 1.4886 3.455 30 0.8240 ?1.682 1.6479 4.339 31 0.9091 ?0.827 1.8183 5.193 32 1.0000 0.000 2.0000 6.021 33 0.5484 ?5.219 1.0967 0.802 34 0.5997 ?4.441 1.1995 1.580 35 0.6542 ?3.686 1.3084 2.335 36 0.7119 ?2.951 1.4238 3.069 37 0.7729 ?2.237 1.5458 3.783 38 0.8373 ?1.543 1.6746 4.478 39 0.9051 ?0.866 1.8103 5.155 40 0.9766 ?0.206 1.9531 5.815 41 0.5258 ?5.583 1.0517 0.437 42 0.5652 ?4.955 1.1305 1.065 43 0.6066 ?4.342 1.2132 1.679 44 0.6499 ?3.743 1.2998 2.278 45 0.6952 ?3.157 1.3905 2.863 46 0.7426 ?2.585 1.4852 3.436 47 0.7921 ?2.024 1.5842 3.996 48 0.8438 ?1.476 1.6875 4.545 49 0.8976 ?0.938 1.7952 5.082 default gain 2 gain interpolation rate (linear) (db) (linear) (db) 50 0.9537 ?0.412 1.9073 5.609 51 0.5060 ?5.917 1.0120 0.104 52 0.5364 ?5.411 1.0728 0.610 53 0.5679 ?4.914 1.1358 1.106 54 0.6007 ?4.427 1.2014 1.593 55 0.6347 ?3.949 1.2693 2.072 56 0.6699 ?3.480 1.3398 2.541 57 0.7065 ?3.018 1.4129 3.002 58 0.7443 ?2.565 1.4886 3.455 59 0.7835 ?2.120 1.5669 3.901 60 0.8240 ?1.682 1.6479 4.339 61 0.8659 ?1.251 1.7317 4.770 62 0.9091 ?0.827 1.8183 5.193 63 0.9539 ?0.410 1.9077 5.610 inverse sinc filter (isf) the ad9856 is almost entirely a digital device. the input signal is made up of a time series of digital data-words. these data- words propagate through the device as numbers. ultimately, this number stream must be converted to an analog signal. to this end, the ad9856 incorporates an integrated dac. the output waveform of the dac is the familiar staircase pattern typical of a signal that is sampled and quantized. the staircase pattern is a result of the finite time that the dac holds a quantized level until the next sampling instant. this is known as a zero-order hold function. the spectrum of the zero-order hold function is the sin(x)/x, or sinc, envelope. the series of digital data-words presented at the input of the dac represent an impulse stream. it is the spectrum of this impulse stream, which is the desired output signal. due to the zero-order hold effect of the dac, however, the output spectrum is the product of the zero-order hold spectrum (the sinc envelope) and the fourier transform of the impulse stream. thus, there is an intrinsic distortion in the output spectrum, which follows the sinc response. the sinc response is deterministic and totally predictable. thus, it is possible to predistort the input data stream in a manner that compensates for the sinc envelope distortion. this can be accomplished by means of an isf. the isf incorporated on the ad9856 is a 17-tap, linear phase fir filter. its frequency response characteristic is the inverse of the sinc envelope. data sent through the isf is altered to correct for the sinc envelope distortion. note, however, that the isf is sampled at the same rate as the dac. thus, the effective range of the sinc envelope compensation only extends to the nyquist frequency (1/2 of the dac sample rate).
ad9856 rev. c | page 25 of 36 f i gur e 43 sh o w s t h e ef fe c t i v e n ess o f t h e is f i n c o r r e c t i n g fo r t h e si nc d i stor t i on . t h e pl ot i n clu d e s a g r a p h of t h e si nc en ve lo p e , t h e isf r e s p o n s e an d t h e s y stem r e s p o n s e (w hich is th e p r o d uc t o f t h e s i n c and is f r e s p o n s e s). n o t e tha t t h e is f exhi b i ts an in s e r t io n los s o f 3.1 db . th us, sig n al lev e l s a t t h e o u t p u t o f the ad9856 wi t h t h e is f b y p a s s e d a r e 3.1 db hig h er th a n w i th t h e is f e n ga g e d . f o r m o d u la t e d o u t p u t si gn als, h o we ver , w h ich ha ve a rel a t i vely wi de b a nd w i d t h, t h e b e n e f i ts o f t h e s i n c com p e n s a t i on us u a l l y o u tw ei g h t h e 3 db los s i n o u t p u t leve l . the decisio n o f w h ether t o us e t h e is f is a n a p plic a t ion sp e c if ic sy st em des i g n issue . ?4 ?3 ?2 ?1 0 1 (db) 2 3 4 0 0.1 0.2 0.3 0.4 0.5 frequency normalized to sample rate isf sinc system 00637-c-043 f i gure 43. in vers e s i nc f i lte r r e s p ons e direc t dig i t a l sy nt he sizer func tio n the dir e c t dig i t a l syn t h e sizer ( d ds) b l o c k g e nera t e s t h e sine/ cosin e ca r r i er r e fer e n c e sig n als t h a t a r e dig i t a l l y m o d u l a t e d b y t h e i / q d a t a p a t h s . t h e dd s f u nc t i o n i s f r e q u e nc y tu ne d v i a t h e s e r i a l co n t rol p o r t wi t h a 3 2 -b i t t u ning w o r d . this a l lo ws t h e ad9856 s o u t p u t ca r r i er f r eq uen c y t o be v e r y p r ecis e l y t u n e d wh ile still p r o v id i n g o u t p u t f r eq ue n c y a g ili t y . the eq ua tion r e la t i n g o u t p u t f r e q uen c y o f the ad9856 dig i tal mo d u l a tor to t h e f r e q u e nc y t u n i ng word ( f t w or d ) and t h e sy st em clo c k (s y s cl k) is g i ve n as: () 32 2 / sysclk ftword a out = w h er e a ou t and sy s c l k f r e q ue n c ies a r e in h z a nd ft w o rd is a decimal n u m b er f r o m 0 t o 4,2 94,967,296 (2 31 ). f o r exa m ple , f i nd t h e f t w o r d fo r a out = 41 mh z and s y scl k = 122. 88 mh z. if a ou t = 41 mh z and s y scl k = 122.88 mh z, t h en: hex aaaab ftword 556 = l o adin g 556 aa aab h in t o co n t r o l b u s r e g i s t ers 02hC05h (f o r p r o f ile 1) p r og ra m s th e ad9856 f o r a out = 41 mh z, g i v e n a s y s c lk f r eq uen c y o f 12 2.88 mh z. a t e c h n i ca l t u to r i a l o n d i g i ta l s i g n a l s y n t hes i s is a v a i la b l e o n t h e analog d e v i ces w e bsi t e a t : h t t p ://w w w .a nal o g.co m/u p lo adedf i les/t u t o r i al s/450968421d d s_t u t o r i a l _r e v 1 2 -2-99.p d f the t u t o r i a l p r o v ide s b a sic a p pl ica t io n s i n fo r m a t io n fo r a va r i ety o f dig i t a l syn t h e sis im p l em e n t a tio n s, as w e l l as a deta ile d expla n a t ion o f a l ias e s . d/a c o n v e r ter a 12-b i t dig i tal-t o -a nalog co n v er t e r (d a c ) is us ed t o con v er t t h e dig i t a l l y p r o c es s e d wa v e fo r m i n t o a n a n alog sig n al . th e w o rs t-cas e s p ur io us sig n als d u e t o t h e d a c a r e t h e ha r m o n ics o f th e f u ndam e n t al sig n al an d t h eir al ias e s (s ee th e ad9851 c o m p let e - dds da ta sh ee t f o r a d e ta ils a b o u t alia sed im a g e s ). the wideband 1 2 -b i t d a c in t h e ad9856 main ta in s sp ur io us- f r e e dy n a m i c r a nge ( s f d r ) p e r f or m a nc e of ? 6 0 d b c up to a ou t = 42 mh z a nd ?55 db c u p t o a ou t = 65 mh z. the con v ersio n p r o c es s p r o d uc es alias e d com p o n e n ts o f t h e fun d a m e n t al si g n al a t n sy s c l k f carrier ( n = 1, 2, 3). th es e a r e typ i cal l y f i l t er e d w i t h a n exter n al rl c f i l t er a t t h e d a c o u t p u t . i t is im p o r t a n t f o r this a n alog f i l t er t o ha v e a s u f f i cien tly f l a t ga i n an d l i ne a r phas e r e sp on s e acr o ss t h e b a nd w i d t h o f i n te re s t to a v oi d mo d u l a t i on i m p a i r me n t s . a n i n e x p e ns ive s e v e n t h-o r der el li p t ic al lo w - p a ss f i l t er is s u f f i cien t t o s u p p r es s t h e a l ias e d co m p o n e n ts fo r hfc n e tw o r k a p pli c a t io ns. the ad9856 p r o v ides tr ue a nd co m p lem e n t c u r r en t o u t p u t s on p i n s 30 an d 29, r e s p ec ti ve l y . the f u l l -s cale ou t p u t c u r r en t is s e t by t h e r set r e sis t o r a t p i n 25. th e v a l u e o f r set fo r a p a r t ic u l ar i ou t is det e r m i n e d b y out set i r 39.936/ = f o r exa m p l e , if a f u l l -s cal e o u t p u t c u r r en t o f 20 ma is des i r e d , th en r set = (39. 936/0.02), o r a p p r o x ima t e l y 2 k?. e v er y do ub l i n g o f t h e r set val u e hal v e s t h e ou t p u t c u r r en t. m a xim u m o u t p ut c u r r en t i s sp e c if ie d as 20 ma. the f u l l -s c a le ou t p u t c u r r en t ran g e o f th e ad9 856 is 5 ma t o 20 ma. f u l l -s ca le o u t p ut c u r r en ts o u tside o f t h is ra n g e deg r ade s f d r p e r f o r ma n c e. s f d r is als o s l ig h t l y a f f e c t ed b y o u t p u t ma t c hing, t h a t is, t h e tw o o u t p u t s sh o u ld be ter m ina t e d e q u a l l y fo r b e st s f dr p e r f o r manc e. the o u t p u t lo ad sh o u l d b e lo c a te d as clos e as p o ssi b le t o t h e ad9856 p a c k a g e t o minimize s t ra y ca p a ci tan c e a nd ind u c t an ce. the lo ad m a y b e a si m p le r e sisto r t o g r o u n d , an o p a m p c u r r en t-t o -v ol t a g e co n v er t e r , o r a t r a n sfo r m e r - c o u p le d cir c ui t. i t i s b e st not to a tte m p t to d i re c t ly dr ive h i g h ly re a c t i ve l o a d s (s uc h as a n l c f i l t er). dr i v in g an l c f i l t er wi t h o u t a t r a n sfo r m e r r e q u ir es t h a t t h e f i l t er b e do ub l y t e r m ina t e d fo r b e st p e r f o r ma nce, t h a t is, t h e f i l t er in p u t and ou t p ut sh o u ld b o t h b e r e sis t i v e l y t e r m ina t e d wi t h t h e a p p r o p r i a t e val u es. the p a ra l l e l co m b in a t io n o f t h e tw o t e r m ina t io n s d e t e r m i n es t h e
ad9856 rev. c | page 26 of 36 load that the ad9856 sees for signals within the filter pass band. for example, a 50 ? terminated input/output low-pass filter looks like a 25 ? load to the ad9856. the output compliance voltage of the ad9856 is ?0.5 v to +1.5 v. any signal developed at the dac output should not exceed +1.5 v, otherwise, signal distortion results. furthermore, the signal may extend below ground as much as 0.5 v without damage or signal distortion. the use of a transformer with a grounded center tap for common-mode rejection results in signals at the ad9856 dac output pins that are symmetrical about ground. as previously mentioned, by differentially combining the two signals the user can provide some degree of common-mode signal rejection. a differential combiner might consist of a transformer or an op amp. the object is to combine or amplify only the difference between two signals and to reject any common, usually undesirable, characteristic, such as 60 hz hum or clock feedthrough that is equally present on both input signals. the ad9856 true and complement outputs can be differentially combined using a broadband 1:1 transformer with a grounded, center-tapped primary to perform differential combining of the two dac outputs. reference clock multiplier because the ad9856 is a dds-based modulator, a relatively high frequency system clock is required. for dds applications, the carrier is typically limited to about 40% of sysclk. for a 65 mhz carrier, the system clock required is above 160 mhz. to avoid the cost associated with these high frequency references and the noise coupling issues associated with operating a high frequency clock on a pc board, the ad9856 provides an on- chip programmable clock multiplier (refclk multiplier). the available clock multiplier range is from 4 to 20, in integer steps. with the refclk multiplier enabled, the input reference clock required for the ad9856 can be kept in the 10 mhz to 50 mhz range for 200 mhz system operation, which results in cost and system implementation savings. the refclk mult- iplier function maintains clock integrity as evidenced by the ad9856s system phase noise characteristics of ?105 dbc/hz (a out = 40 mhz, refclk multiplier = 6, offset = 1 khz) and virtually no clock related spurii in the output spectrum. external loop filter components consisting of a series resistor (1.3 k?) and capacitor (0.01 f) provide the compensation zero for the refclk multiplier pll loop. the overall loop perform- ance has been optimized for these component values. throughput and latency data latency through the ad9856 is easiest to describe in terms of sysclk clock cycles. latency is a function of the ad9856 configuration primarily affected by the cic interpolation rate and whether the third half-band filter is engaged. when the third half-band filter is engaged, the ad9856 latency is given by 126 n + 37 sysclk clock cycles, where n is the cic interpolation rate. if the ad9856 is configured to bypass the third half-band filter, the latency is given by 63 n + 37 sysclk clock cycles. these equations should be considered estimates, as observed latency may be data dependent. the latency was calculated using the linear delay model for the fir filters. in single-tone mode, frequency hopping is accomplished via changing the profile input pins. the time required to switch from one frequency to another is < 50 sysclk cycles with the inverse sinc filter engaged. with the inverse sinc filter bypassed, the latency drops to < 35 sysclk cycles. control interface the flexible ad9856 synchronous serial communications port allows easy interface to many industry standard micro- controllers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including the motorola 6905/11 spi? and intel? 8051 ssr protocols. the interface allows read/write access to all registers that configure the ad9856. single or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. the ad9856s serial interface port can be configured as a single-pin i/o (sdio) or two unidirectional pins for input/output (sdio/sdo). general operation of the serial interface there are two phases to a communication cycle with the ad9856. phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad9856, coincident with the first eight sclk rising edges. the instruction byte provides the ad9856 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer (1 to 4), and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9856. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the ad9856 and the system controller. phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. normally, using one communication cycle in a multibyte transfer is the preferred method. however, single-byte communication cycles are useful to reduce cpu overhead when register access requires one byte only. examples of this may be to write the ad9856 sleep bit, or an ad8320/ad8321 gain control byte.
ad9856 rev. c | page 27 of 36 a t the co m p let i o n o f a n y co mm unica t io n c y c l e , t h e ad9856 s e r i al p o r t co n t r o l l er exp e c t s t h e n e xt e i g h t r i si n g sclk e d g e s t o b e t h e inst r u c t io n b y t e o f t h e n e xt comm u n ica t io n c y cle . al l da ta in p u t to th e ad9856 is r e g i s t er ed o n t h e r i sin g e d g e o f sclk. al l da ta is dr i v en o u t o f th e ad9856 o n t h e fal l i n g e d ge of s c l k . fi g u re 4 4 t h rou g h f i g u re 4 7 s h ow t h e ge ne r a l o p era t ion o f the ad9856 s e r i al p o r t . instruc t i o n b y te the inst r u c t io n b y t e con t a i n s t h e fol l o w in g i n fo r m a t io n as shown i n t a bl e 7 . table 7. i n struction byte in fo rmation msb d6 d5 d4 d3 d2 d1 lsb r/w n1 n0 a4 a3 a2 a1 a0 r/ w bi t 7 de t e r m i n es w h et h e r a r e ad o r wr i t e da t a t r a n sfer oc cu r s a f t e r th e i n s t r u cti o n b y t e w r i t e . logi c hi g h in di ca t e s a r e ad o p er a t io n. l o g i c zer o i ndic a tes a wr i t e o p e r a t io n. n1, n0 bi ts 6 a nd 5 o f t h e inst r u c t io n b y te deter m i n e t h e n u m b er o f b y t e s t o b e t r a n sfer r e d d u r i n g t h e da t a t r a n sfer c y cl e o f t h e co mm uni c a t io ns c y cle . t a b l e 8 sh o w s t h e de co de b i ts. table 8. n1 , n 0 deco de bits n1 n0 desc rip t io n 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes a4, a3, a2, a1, a0 b i ts 4, 3, 2, 1, 0 o f th e in str u c t io n b y t e det e r m i n e w h ich r e g i s t er is acc e s s e d d u r i ng t h e da t a t r a n sfer p o r t io n o f t h e c o mm uni c a t io n s c y cle . f o r m u l t ib y t e t r a n sfers, t h is addr es s is t h e st a r t i n g b y t e addr es s. th e r e ma ini n g r e g i s t e r addr ess e s a r e g e n e ra t e d b y t h e ad9856. i 7 sdio instruction cycle data transfer cycle sclk cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00637-c-044 f i g u re 44. s e ri al p o r t writ ing tim i ng c lock st al l l o w d o7 instruction cycle data transfer cycle don't care i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 sdio s clk cs sdo d o6 d o5 d o4 d o3 d o2 d o1 d o0 00637-c-045 f i g u re 45. th r e e - wi r e s e ri al p o r t r e ad ti ming c lo ck st a ll l o w i 7 sdio instruction cycle data transfer cycle sclk cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00637-c-046 f i g u re 46. s e ri al p o r t writ e ti ming c lo ck st a ll hig h i 7 sdio instruction cycle data transfer cycle scl k cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d o7 d o6 d o5 d o4 d o3 d o2 d o1 d o0 00637-c-047 f i gure 47. t w o - w i re s e ri a l p o r t r e ad tim i ng c l o ck st al l high
ad9856 rev. c | page 28 of 36 serial interface port pin descriptions sclkserial clock the serial clock pin is used to synchronize data to and from the ad9856 and to run the internal state machines. sclk maximum frequency is 10 mhz. cs chip select active low input that allows more than one device on the same serial communications lines. the sdo and sdio pins go to a high impedance state when this input is high. if driven high during any communications cycle, that cycle is suspended until cs is reactivated low. chip select can be tied low in systems that maintain control of sclk. sdioserial data i/o data is always written into the ad9856 on this pin. however, this pin can be used as a bidirectional data line. the config- uration of this pin is controlled by bit 7 of register address 0h. the default is logic 0, which configures the sdio pin as bidirectional. sdoserial data out data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad9856 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. sync i/o synchronizes the i/o port state machines without affecting the addressable registers contents. an active high input on the sync i/o pin causes the current communication cycle to abort. after sync i/o returns low (logic 0), another communication cycle may begin, starting with the instruction byte write. ca clk output clock pin to the ad8320/ad8321. if using the ad9856 to control the ad8320/ad8321 programmable cable driver amplifier, connect this pin to the clk input of the ad8320/ ad8321. ca data output data pin to the ad8320/ad8321. if using the ad9856 to control the ad8320/ad8321 programmable cable driver amplifier, connect this pin to the sdata input of the ad8320/ ad8321. ca enable output enable pin to the ad8320/ad8321. if using the ad9856 to control the ad8320/ad8321 programmable cable driver amplifier, connect this pin to the daten input of the ad8320/ad8321. msb/lsb transfers the ad9856 serial port can support both msb-first or lsb-first data formats. this functionality is controlled by the reg0<6> bit. the default value of reg0<6> is low (msb first). when reg0<6> is set active high, the ad9856 serial port is in lsb first format. the instruction byte must be written in the format indicated by reg0<6>. that is, if the ad9856 is in lsb-first mode, the instruction byte must be written from least significant bit to most significant bit. multibyte data transfers in msb format can be completed by writing an instruction byte that includes the register address of the most significant byte. in msb-first mode, the serial port internal byte address generator decrements for each byte required of the multibyte commun- ication cycle. multibyte data transfers in lsb-first format can be completed by writing an instruction byte that includes the register address of the least significant byte. in lsb-first mode, the serial port internal byte address generator increments for each byte required of the multibyte communication cycle. notes on serial port operation the ad9856 serial port configuration bits reside in bit 6 and bit 7 of register address 0h. it is important to note that the configuration changes immediately upon writing to this register. for multibyte transfers, writing to this register may occur during the middle of a communication cycle. care must be taken to compensate for this new configuration for the remainder of the current communication cycle. the ad9856 serial port controller address can roll from 19h to 0h for multibyte i/o operations if the msb-first mode is active. the serial port controller address can roll from 0h to 19h for multibyte i/o operations if the lsb-first mode is active. the system must maintain synchronization with the ad9856 or the internal control logic is not able to recognize further instructions. for example, if the system sends an instruction byte for a 2-byte write, then pulses the sclk pin for a 3-byte write (24 additional sclk rising edges), communication synchronization is lost. in this case, the first 16 sclk rising edges after the instruction cycle properly write the first two data bytes into the ad9856, but the next eight rising sclk edges are interpreted as the next instruction byte, not the final byte of the previous communication cycle. in the case where synchronization is lost between the system and the ad9856, the sync i/o pin provides a means to reestablish synchronization without reinitializing the entire chip. the sync i/o pin enables the user to reset the ad9856 state machine to accept the next eight sclk rising edges to be coincident with the instruction phase of a new communication cycle. by applying and removing a high signal to the sync i/o pin, the ad9856 is set to once again begin performing the communication cycle in synchronization with the system. any information that had been written to the ad9856 registers during a valid communication cycle prior to loss of synchronization remains intact.
ad9856 rev. c | page 29 of 36 symbol definition min t pre setup time 30ns t sclk period of serial data clock 100ns t dsu serial data setup time 30ns t sclkpwh serial data clock pulsewidth high 40ns t sclkpwl serial data clock pulsewidth low 40ns t dhld serial data hold time 0ns cs sclk sdio 1st bit 2nd bit t dsu t dhld t sclkpwh t sclkpwl t sclk t pre cs 00637-c-048 f i g u re 48. ti m i ng d i ag r a m f o r d a t a writ e t o a d 9 8 56 symbol definition max t dv data valid time 30ns cs sclk sdio 1st bit 2nd bit t dv sdo 00637-c-049 f i g u re 49. ti m i ng d i ag r a m f o r r e ad f r om a d 9 8 5 6
ad9856 rev. c | page 30 of 36 pr ogr a mming/writing the ad83 20/ad8321 c a ble driver amplifie r gain c o ntrol p r og ra mmin g th e ga in con t r o l r e g i s t er o f the ad8320/ad8321 p r og ra mma b l e ca b l e dr i v er a m plif ier ca n b e ac co m p lish e d v i a th e ad9856 s e r i al p o r t . f o ur 8-b i t r e g i s t ers (o ne p e r p r o f ile) wi thin t h e ad9 856 s t o r e the gain val u e t o be wr i t t e n t o t h e ad8320/ad83 21. the ad832 0/ad8321 is wr i t t e n via thr e e dedica t e d ad9 856 o u t p u t p i n s tha t a r e dir e c t l y co nn ec t e d t o th e ad8320 /ad8321 s e r i al in p u t p o r t . th e t r a n sf er o f da ta f r o m t h e ad9856 t o the ad8320/ad8321 r e q u ir es 136 s y scl k c l o c k c y c l es a n d o c c u rs u p o n detec t io n o f thr e e co ndi t i on s. e a ch co nd i t io n is d e s c r i b e d n e x t . power-up r e set u p o n ini t ial p o w e r u p , t h e ad9856 c l ea rs (l og ic 0) th e con t en ts o f co n t r o l r e g i s t ers 07h, 0dh, 1 3 h, an d 19 h, w h ic h def i n e s t h e lo w e s t ga in s e t t in g o f th e ad83 20/ad8321. th us, th e ad9856 wr i t es al l 0s o u t o f th e ad8320/ad8321 s e r i al in t e r f ac e . change in pro f ile sel e ction bits (ps1, ps0) the ad9856 s a m p les t h e ps1, ps0 in p u t p i n s and wr i t es t o t h e ad8320/ ad83 21 ga in co n t r o l r e g i s t er w h en a c h a n g e in p r o f ile is det e r m in ed . the da t a wr i t t e n t o t h e ad832 0/ad8321 comes f r o m th e ad98 56 ga in co n t r o l r e g i s t er as s o c i a t ed wi t h t h e cu rr e n t p r o f il e . serial port write of a d 9856 registers containing ad8320/ad8321 data the ad9856 wr i t es t o t h e ad8 320/ad8321 wi th da ta f r o m t h e ga in co n t r o l r e g i s t er as s o c i a t e d wi t h t h e c u r r en t p r o f i l e when ev er an y ad9856 ga in con t r o l r e g i s t er is u p da t e d . the us er do es n o t ha v e t o wr i t e t h e ad9856 in an y p a r t ic u l a r o r der o r t o be con c er n e d wi t h time b e tw een wr i t es. i f th e ad9856 is c u r r en tl y wr i t ing t o th e ad832 0/ad8321 whil e o n e o f t h e f o u r ad9856 ga in co n t r o l r e g i s t ers is bein g addr es s e d , t h e ad9856 imm e dia t e l y t e r m ina t es t h e ad8320/ad8321 wr i t e s e q u ence (wi t h o u t u p da tin g t h e ad8320/ad8321) an d b e g i n s a n e w ad8320/ad83 21 wr i t e s e q u ence . gain transfer g2 gain transfer g1 ca enable ca clk t ds ca data valid data word g1 msb...lsb valid data word g2 t wh t ck t es t eh 8 clock cycles symbol definition min t ds ca data setup time 6.5ns t dh ca data hold time 2ns t wh ca clock pulse high 9ns t ck ca clock period 25ns t es ca enable setup time 17ns t eh ca enable hold time 2.0ns 00637-c-050 f i g u re 50. p r og r a m m ab le cab l e d r ive r a m pl if ie r o u t p ut cont rol inte r f ace ti ming
ad9856 rev. c | page 31 of 36 understanding and using pin-selectable modulator profiles the ad9856 quadrature digital upconverter is capable of storing four preconfigured modulation modes called profiles that define the following: ? output frequency32 bits ? interpolation rate6 bits ? spectral inversion status1 bit ? bypass third half-band filter1 bit ? gain control of ad8320/ad83218 bits output frequency this attribute consists of four 8-bit words loaded into four register addresses to form a 32-bit frequency tuning word (ftw) for each profile. the lowest register address corresponds to the least significant 8-bit word. ascending addresses correspond to increasingly significant 8-bit words. the output frequency equation is given as: f out = ( ftw sysclk )/2 32 . interpolation rate consists of a 6-bit word representing the allowed interpolation values from 2 to 63. interpolation is the mechanism used to up sample or multiply the input data rate such that it exactly matches that of the dds sample rate (sysclk). this implies that the system clock must be an exact multiple of the symbol rate. this 6-bit word represents the 6 msbs of the eight bits allocated for that address. the remaining two bits contain the spectral inversion status bit and half-band bypass bit. spectral inversion single bit that when at logic 0 the default or noninverted output from the adder is sent to the following stages. a logic 1 causes the inverted output to be sent to the following stages. the noninverted output is described as i cos(t) ? q sin(t). the inverted output is described as i cos(t) + q sin(t). this bit is located adjacent to the lsb at the same address as the interpolation rate previously described. bypass third half-band filter a single bit located in the lsb position of the same address as the interpolation rate. when this bit is logic 0, the third half- band filter is engaged and its inherent 2 interpolation rate is applied. when this bit is logic 1, the third half-band filter is bypassed and the 2 interpolation rate is negated. this allows users to input higher data ratesrates that may be too high for the minimum interpolation rate if all three half-band filters with their inherent 2 interpolation rate are engaged. the effect is to reduce the minimum interpolation rate from 8 to 4. ad8320/ad8321 gain control an 8-bit word that controls the gain of an ad8320/ad8321 programmable gain amplifier connected to the ad9856 with the 3-bit spi interface bus. gain range is from ?10 db (00 hex) to +26 db (ffhex). the gain is linear in v/v/lsb and follows the equation a v = 0.316 + 0.077 code, where code is the decimal equivalent of the 8-bit gain word. profile selection after profiles have been loaded into the appropriate registers, the user may select which profile to use with two input pins: ps0 and ps1, pins 45 and 46. table 9 shows how profiles are selected. table 9. profile select matrix ps1 ps0 profile 0 0 1 0 1 2 1 0 3 1 1 4 except while in single-tone mode, it is recommended that users suspend the txenable function by bringing the pin to logic 0 prior to changing from one profile to another and then re- asserting txenable. this assures that any discontinuities resulting from register data transfer are not transmitted up or downstream. furthermore, changing interpolation rates during a burst may create an unrecoverable digital overflow condition that interrupts transmission of the current burst until a reset and reloading procedure is completed. power dissipation considerations the majority of the ad9856 power dissipation comes from digital switching currents. as such, power dissipation is highly dependent upon chip configuration. the major contributor to switching current is the maximum clock rate at which the device is operated, but other factors can play a significant role. factors such as the cic interpolation rate, and whether the third half-band filter and inverse sinc filters are active, can affect the power dissipation of the device. it is important for the user to consider all of these factors when optimizing performance for power dissipation. for example, there are two ways to achieve a 6 ms/s transmission rate with the ad9856. the first method uses an f max of 192 mhz; the other method uses an f max of 144 mhz, which reduces power dissipation by nearly 25%. for the first method, the input data must be externally 4 upsampled. the ad9856 must be configured for a cic interpolation rate of three while bypassing the 3rd half-band filter. this results in an i/q input sample rate of 24 mhz which is further upsampled by a factor of 8 mhz to 192 mhz.
ad9856 rev. c | page 32 of 36 the second method requires an f max of 144 mhz with externally 2 upsampled input data. the ad9856 is configured for a cic interpolation rate of 3 while bypassing the 3rd half- band filter. the input i/q sample rate is 12 mhz, which is further upsampled by a factor of 12 mhz to 144 mhz. for burst applications with relatively long nonbursting periods, the sleep bit is useful for saving power. when in sleep mode, power is reduced to below 6 mw. consideration must be given to wake-up time, which generally is in the 400 s to 750 s range. for applications that cannot use the sleep bit due to this wake-up time, there is an alternate method of reducing power dissipation when not transmitting. by writing the bypass refclk multiplier bit active, the power is reduced by nearly the refclk multiplier factor. for example, if the external reference clock is 16 mhz and refclk multiplier is set to 10, all clocks divide down by a factor of 10 when the refclk multiplier is bypassed. this effectively scales down the power dissipation by nearly a factor of 10. in this case, both the refclk multiplier function and the dac, which use relatively little power, remain fully powered. the refclk multiplier circuit is locked to the 16 mhz external reference clock, but its output is driving a very small loadthus, there is little power dissipation. when the refclk multiplier is reactivated, the acquisition time is small. in this power reduction technique, the larger the refclk multiplier factor, the larger the power savings. the ad9856 is specified for operation at +3.0 v 5%. the thermal impedance of the device in the 48-lqfp plastic package is 38c/w. at 200 mhz operation, power dissipation is 1.5 w. this permits operation over the industrial temperature range without exceeding the maximum junction temperature of 150c. to realize this quoted thermal impedance, all power and ground pins must be soldered down to a multilayer pcb with power and ground copper planes directly available at the package pins. under worst-case conditions, that is, with power supplies at 2.85 v and ambient temperatures of 85c, device operation at 200 mhz is guaranteed for single-tone mode only. for modulation mode at 200 mhz, 85c operation, the minimum power supply voltage is 3.0 v. ad9856 evaluation board an evaluation board is available to facilitate bench and system analysis of ad9856 quadrature digital upconverter. the ad9856 printed circuit board (pcb) contains the ad9856 device and windows? software that the device to be controlled via the printer port of a pc. the dac output is provided on a jack for spectral analysis. th e ad9856/pcb provides a single- ended 65 mhz, 5 ?, elliptical low-pass filter on the output of the dac. the user can also implement the ad8320/ad8321 program- mable cable driver amplifier on the ad9856/pcb evaluation board. the ad8320/ad8321 gain is programmed through the ad9856 via the menu driven control software. support applications assistance is available for the ad9856 and the ad9856/pcb evaluation board. please call 1-800-analogd or visit www.analog.com.
ad9856 rev. c | page 33 of 36 dvdd +12v +3.3v gnd c3 10 f c29 0.1 f c24 0.1 f c30 0.1 f c31 0.1 f c4 10 f c27 0.1 f c22 0.1 f c25 0.1 f c14 0.1 f c8 0.1 f c5 0.1 f c20 0.1 f c1 10 f c2 10 f avdd gnd w2 v cc 2y4 2y3 2y2 2y1 1y4 1y3 1y2 1y1 2a4 2a3 2a2 2a1 1a4 1a3 1a2 1a1 gnd u6 74hc244a 1g 2g 17 15 13 11 8 6 4 2 10 20 3 5 7 9 12 14 16 18 +3.3v +3.3v gnd w3 +3.3v 74hc132 1a 1b 1y 2a 2b 2y dgnd dvdd 4b 4a 4y 3b 3a 3y u8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 cs rbe +3.3v rbe sdio +3.3v sdo gnd p2 7 4 hc 125a 1g 1a 1y 2g 2a 2y gnd v cc 4g 4a 4y 3g 3a 3y u3 14 13 12 11 10 9 8 1 2 3 4 5 6 7 rbe v cc q0 q1 q2 q3 q4 q5 q6 q7 clock oe d0 d1 d2 d3 d4 d5 d6 d7 gnd u7 74hc574 +3.3v r8 10k ? +3.3v r11 10k ? r10 10k ? sclk cs sync i/o rst ps0 ps1 gnd rbe +3.3v rbe latch sclk sdio rst sync i/o e23 e24 e16 19 1 e17 e18 e19 +3.3v cadata 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 vcc1 vin vref vcc gnd 1 gnd 2 byp gnd 3 gnd 4 gnd 5 sdata clk daten gnd vocm pd +12v +12v +12v vout u4 ad8320/21 c28 0.1 f +12v caclk caen r9 62 ? j13 +12v j12 c23 0.1 f 75 ? output j11 gnd w11 podn r6 1.3k ? c26 0.1 f c21 0.1 f e20 e21 e22 rbe sdo 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 power down control 50 ? input 0.1 f 14 13 12 11 10 9 8 1 2 3 4 5 6 7 00637-c-051 48 47 45 42 40 38 j3 rst sync i/o j8 sclk j4 sdo j14 caclk j6 j7 j5 r7 50 ? ps0 ps1 caenb r1 3.92 ? gnd dvdd c17 7pf c18 33pf c19 22pf l1 120nh l2 100nh l3 100nh c10 68pf c11 100pf c12 82pf c13 56pf j9 c16 0.01 f r5 1.3k ? c15 0.1 f 13 thru 20 are nc 21 thru 40 are gnd j2 txenable d11 d10 dvdd dgnd d9 d8 d7 d6 dvdd dgnd d5 ca data ca enable pll supply pll filter pll gnd agnd i out i outb agnd avdd dac ref bypass dac r set 36 35 34 33 32 31 30 29 28 27 26 25 j10 r eset refclk ps1 ps0 dv dd dgnd syn c i /o sc lk sd io sd o cs ca clk d4 d3 d2 d1 d0 nc nc dgnd dv dd nc agnd bg re f b ypa ss 13 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 20 gnd dvdd p1 gnd dv dd dut ad9856 sdio j15 gnd w6 w5 w4 cadat avdd c9 0.1 f w7 avdd r3 25 ? r4 50 ? dv dd c7 0.1 f avdd j1 w8 cs gnd w1 e14 e15 e12 e13 w9 e10 e11 e7 e9 e6 e4 e5 e8 e2 e3 e1 p3 gnd +3.3v +12v 1 2 3 4 5 avdd dvdd w10 e25 e26 refclkin txenable 65mhz low pass filter reset nc = no connect 46 44 43 41 39 37 14 19 20 21 22 23 24 f i g u re 51. a d 9 8 5 6 / p cb ev al uat i on bo ar d e l ec t r ic al s c he mat i c
ad9856 rev. c | page 34 of 36 00637-c -052 f i g u re 52. pcb lay out p a t t ern f o r f o u r -layer a d 9 8 5 6 pc b ev aluat i o n b o a r d layer 1 ( t op)sig n al r o ut ing and ground plan e 00637-c - 053 f i g u re 53. pcb lay out p a t t ern f o r f o u r -layer a d 9 8 5 6 pc b ev aluat i o n b o a r d layer 2 ground plan e 00637-c - 054 f i g u re 54. pcb lay out p a t t ern f o r f o u r -layer a d 9 8 5 6 pc b ev aluat i o n b o a r d layer 3du t +v , +5 v and 1 2 v p o wer plan e bo t t o m s i d e m a de i n u . s . a . a d 9 8 56 r e v . c 00637-c - 055 f i g u re 55. pcb lay out p a t t ern f o r f o u r -layer a d 9 8 5 6 pc b ev aluat i o n b o a r d layer 4 ( b ot to m) s ig na l r o ut ing ad8320/21 programmable cable driver amplifier enable and gain control bus 75 ? lp filter ad9856 quadrature digital upconverter ciu control processor direct control lines control bus 75 ? diplexer to 75 ? cable plant upstream to downstream demodulator 75 ? data in 8-20mhz ref clock in 00637- c - 056 f i gure 5 6 . ba s i c impl em ent a ti on o f a d 9 856 di g i tal m o d u l a to r a n d ad832 0/ ad83 21 p r o g r a mm a b l e c a bl e d r i v er a m pli f i e r in 5 m h z t o 65 m h z hfc r e t u rn- p at h a p pli c at ion v dd digital out i out i out b v dd v dd digital in 00637-c-057 f i gure 57. equiv a le nt i/o c i rcuits
ad9856 rev. c | page 35 of 36 outline dimensions top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc sq seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 compliant to jedec standards ms-026bbc f i g u re 58. 4 8 -l ead l o w p r of i l e q u ad f l at p a ckag e [l qf p ] (st - 48) d i m e ns i o ns s h o w n in inc h es mi ll i m et e r s ordering guide model temperature r a nge package descri ption package option ad9856ast ?40 c to +85 c 48-lead low profile quad flat package [lqfp] st-48 ad9856/pcb evaluation boar d
ad9856 rev. c | page 36 of 36 notes ? 2005 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c00637C0 C 1/05(c)

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