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document id# 081247 date: sep 20, 2007 rev: b version: 2 distribution: public document tm le87213a worldwide xdsl dual channel line driver bd870 series applications ? asymmetrical digital subscr iber loop (adsl, adsl+, adsl2, adsl2+) line drivers ? g.lite line drivers ? hdsl, hdsl2, hdsl4, shdsl line drivers ? dslam, co, dlc, blc, mdu/mtu line drivers features ? two-channel differential line drivers ? low power ? 720 mw per channel, typical (adsl+ mode) (showtime, >5 kft 26 awg cable, not including load) ? 670 mw per channel, typical (adsl mode) (showtime, >5 kft 26 awg cable, not including load) ? operates directly from a typical telecom power supply without a dc-to-dc converter and a 3.3 v supply ? integrated lightning and surge protection ? 50 v p differential signal at the driver outputs ? i out max 95 ma into 100- ? load ? mtpr of 70 db, typical ? minimum external component count ~ 10 discretes per channel ? can output 20.8 dbm power into 100- ? load with step down transformer ? thermal shutdown ? small footprint ? 32-pin (8 x 8 mm) qfn related literature ? 080791 quad flat no-lead (qfn) package application note ordering information 1. the green package meets rohs directive 2002/95/ec of the european council to minimize the environmental impact of electrical equipment. 2. for delivery using a tape and reel packing system, add a "t" suffix to the opn (ordering part number) when placing an order. device package packing 2 le87213aqc 32-pin qfn, 8 x 8 mm tray LE87213AFQC 32-pin qfn, 8 x 8 mm (green package) 1 description the le87213a device, from the zarlink battery dire ct? family bd870 series devices, int egrates two fully differential line drivers, optimized feed ba ck components, on-chip surge protection diodes and bias control stages into a small 8 x 8 mm 2 qfn package. it contains all the active components needed to implement adsl2+ downstream transmitters for two lines. the le87213a d evice is built on zarlink?s hig h-voltage process that allows for dire ct operation from a standard telecom, negative battery supply (and a 3.3-v supply). in contrast, typical line cards toda y supply the power to the line drivers locally, via dc-to-dc converter modules. the elimination of these additional modules translates into cost and power savings at the system level. operation from a centralized source of power makes the le87213a device a unique, less costly, more efficient solution for xdsl line driver applications. the le87213a device is one of the most cost- effective and easy-to-use parts for today?s xdsl applications. block diagram ddwnn1 ddwnp1 vcc agnd vbat bgnd ay1 by1 + + ? ? v bias + ? ddwnn2 ddwnp2 ay2 by2 + + ? ? v bias + ? discon1 control logic1 pdown1 discon2 control logic2 pdown2
le87213a data sheet 2 zarlink semiconductor inc. table of contents applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 lightning and power surges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 downstream path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 device operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 pdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 disconnect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 operating mode control decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 package assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 supply currents and power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 device specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 application circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 physical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 32-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 device operational notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 line transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 transformer turns ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 downstream filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 receiver and hybrid circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 revision a1 to b1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 revision b1 to b2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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le87213a data sheet 3 zarlink semiconductor inc. product description the le87213a device is a low-power , dual xdsl dif ferential l ine driver. it is p art of zarlink?s family of integrate d line drivers capable of operating from a standard negative battery supp ly. its integration of feedback components and on-chip surge protection diodes makes it one of the most in tegrated line drivers on the market today. the le87213a device was designed on a high voltage, high bandwidth bipolar process in which fast slew rate and low distortion amplifiers were implemented. it requires one line transformer per line for isolation and for compliance with iec60950-1, 2001 a nd ul60950 standards. the line driver amplifiers in the le8721 3a device were designed with an optimized bandwidth for xdsl applications as well as for fa st slew rates of 300 v/s. lightning and power surges the le87213a device has built-in lightning and power surge protection. when used with the components listed in the pcb layout , on page 8 , it needs no other external protector to me et the requirements for adsl line cards. block description refer to the datapath provider for the application circuit. downstream path the downstream signal is applied at the ddwnp/ddwnn pins, and is amplified by a fixed voltage gain (k dwn ) before being applied to the ay and by pins. the amplifiers driving the ay and by pins are dc biased to approximately on e-half of the vbat pin voltage. the typical differential output vo ltage swing between ay and by pins is |vba t| - 4 v. this allows the use of a ste p- down transformer for the line interface. control logic this block controls the bias currents of the input stage and the bias current of the output amplifiers as described in the device operating modes section below. device operating modes the two lines of the le87213a are completely independent and can be programmed to be in different operating modes. the logic signal level of pins discon1 an pdown1 cont rols the operating mode of line 1, the logic signal level of pins discon2 and pdown2 controls the operating mode of line 2. active mode in this mode, all stages are biased and operational. pdown mode in this mode, the line driver amplifier?s power consumption is reduced. the bias curre nt in the output stage drops to almost ha lf full power stage. the part is adsl compliant in this stage. disconnect mode in this mode, the bias is turned off to all stag es to save power. the device is not operational. operating mode control decoding discon 1 pdown 1 line 1 operating mode 00 active 01 pdown 1x disabled discon 2 pdown 2 line 2 operating mode 00 active 01 pdown 1x disabled
le87213a data sheet 4 zarlink semiconductor inc. connection diagram notes: 1. pin 1 is marked for orientation. 2. the le87213a device incorporates an exposed die pad on the underside of its package. the pad acts as a heat sink and must be connected to a copper plane through thermal vias, for proper heat dissipation ( see pcb layout , on page 8. ). pin descriptions pin pin name type description pdown 1 , pdown 2 control bits input active/pdown mode control bit. ddwnp 1 , ddwnn 1 , ddwnp 2 , ddwnn 2 differential downstream input the differential downstream si gnal from the data afe is ac coupled to these pins. discon 1 , discon 2 disconnect input disables the line co mpletely by pulling it to vcc. ay 1 , by 1 ay 2 , by 2 a/b line driver output differential downstream line driver outputs. vbat negative battery power negative power supply. vcc power supply power +3.3 v analog power supply. agnd analog ground ground low voltage ground return. bgnd battery ground ground battery ground return. n/c no connect not connected. exposed pad isolated exposed pad on underside of device must be connected to a heat spreading area. the agnd plane is recommended. exposed pad le87220qc 32-pin qfn 1 21 20 19 18 17 22 23 24 2 3 4 5 6 7 8 10 912 11 14 13 16 15 32 31 30 29 28 27 26 25 top view ddwnp 2 ddwnn 2 n/c n/c n/c n/c n/c ay 2 ddwnn 1 ddwnp 1 n/c n/c n/c n/c n/c n/c n/c by 2 n/c n/c bgnd ay 1 vbat by 1 n/c pdown 1 discon 1 discon 2 vcc pdown 2 n/c agnd le87213a
le87213a data sheet 5 zarlink semiconductor inc. absolute maximum ratings stresses above the values listed under absolute maximum ratings can cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ra tings for extended periods can affect device reliability. note: 1. thermal limiting circuitry on chip will s hut down the circuit at a junction temperat ure of about 165c. continuous operation above 145c junction temperature may degrade device reliability. 2. the thermal performance of a thermally enhanced package is assu red through optimized printed circuit board layout. specified performance requires that the exposed thermal pad be soldered to an equally sized exposed copper surface, whic h, in turn, conducts heat thr ough multiple vias to a large internal copper plane ( see pcb layout , on page 8. ). thermal resistance the junction to air thermal resistance of the le87213a device in a 32-pin qfn package is 30c/w (measured with infinite externa l heat sinking). please refer to zarlink?s qfn package application note, available from http://www.zarlink.com , for layout and heat sinking guidelines. package assembly the standard (non-green) package devices are assembled with i ndustry-standard mold compounds, and the leads possess a tin/ lead (sn/pb) plating. these packages are compatible with conv entional snpb eutectic solder board assembly processes. the peak soldering temperature should not exceed 225c during printed circuit board assembly. the green package devices are assembled with enhanced, environmen tal compatible lead-free, halogen-free, and antimony-free materials. the leads possess a matte-tin plating which is compat ible with conventional board assembly processes or newer lead- free board assembly processes. the peak soldering temperature should not exceed 245c during printed circuit board assembly. refer to ipc/jedec j-std-020b table 5-2 for the recommended solder reflow temperature profile. operating ranges zarlink guarantees the performance of this device over commercial (0c to 7 0c) and industrial ( 40c to 85c) temperature ranges by conducting electrical characterization over each range and by conduc ting a production test with single insertion coup led with periodic sampling. these characterization and test procedur es comply with section 4.6.2 of bellcore gr-357-core component reliability assurance requirement s for telecommunications equipment. the le87213a is designed to operate with a standard telecom battery . the normal operating voltage of such batteries is -52 v, and the le87213a is designed to give optimal performance in te rms of power dissipation if used with the provided applications circuit. however, because the le87213a is d esigned on zarlink?s pro prietary high voltage, h igh bandwidth process, the p art will continue to remain in operation without an y degradation in data performance should the battery drop to as low as -42 v, or charg e to as high as -72 v. should there be a need to operate the part continuously at such voltages, a different applications circuit should be considered to achieve best power performance. lower volt age operation can be achieved by adding a buck-boost regulator. the le87213a is designed to operate with the t1.315 specified telecom battery, without any need for changes in the reference design. storage temperature 55 d t a d +150c ambient temperature, under bias 40 d t a d +85c v cc with respect to agnd 0.4 v to +6 v v bat with respect to bgnd +0.4 v to -75 v bgnd with respect to agnd (1 ms) 5.5 v to +0.2 v maximum current into ay, by continuous 200 ma 100 s (f = 0.1 hz) 1 a 1 s (f = 0.1 hz) 2.5 a 250 ns (f = 0.1 hz) 5.5 a peak current output, ay or by pins 200 ma pdown, discon pins with respect to agnd ?0.4 v to (v cc + 0.4 v) maximum power dissipation, t a = 85c (see notes 1 and 2) 2 w esd immunity (human body model) jesd22 class 1c compliant esd immunity (charge device model) class c6 1500 - 2000 v ambient temperature -40c to +85c v cc +3.3 v 5% v bat -42 v to -72 v bgnd with respect to agnd -2 to +0.1vdc
le87213a data sheet 6 zarlink semiconductor inc. electrical characteristics v bat = -52 v, v cc = +3.3 v, t a = 25c unless otherwise specified. supply currents and power consumption values listed in the table below are per line, and include the load power. note: 1. in the active state, 96.6 mw is dissipated in the loop and 7.5 mw is dissipated in the transform er plus the series drive resi stors. for device power dissipation, su btract these values from the numbers listed in the table above. test circuit only one of two channels is shown. note: 1. component values are the same as those listed in the pcb layout , on page 8 unless otherwise noted. operational state condition t a v bat (ma) v cc (ma) device power (mw) note min typ max min typ max min typ max active training at 5 kft 26 awg cable 25c 16 5.3 850 1. showtime at 5 kft 26 awg cable, 19.85 dbm 25c 15.5 5.3 824 19.85 dbm signal into 100 : load with 2.45:1 transformer 25c 15.5 5.3 824 full range 15.5 5.6 826 pdown 25c 14.5 5.3 772 full range 14.5 5.3 772 disconnect full range 15.365 + 3.3 v + ? 52 v control logic circuit + ? r 1 c 2 c 1 c 8 c 9 v tx v dwn v ay,by ddwnn1 ddwnp1 vcc agnd vbat bgnd ay1 by1 + discon1 + ? ? v bias + ? control logic1 u1 le87220 pdown1 t 1 tip(a)1 ring(b)1 r sec1 r pri1 r pri2 r sec2 c 5 c 6 z loop v loop r 2 r 3 r 11 r 10 le87213a
le87213a data sheet 7 zarlink semiconductor inc. specifications device specifications typical conditions: v bat = 52 v, v cc = 3.3 v, transformer turns ratio = 2.45:1 min/max parameters: t = 40 to +85c; typ, t a = 25c, pdown=0 (full power) note: parameters in the following "device specifications" tables are guaranteed by characterization. refer to test circuit , on page 6 . table 1. pdown = 0 (full power) specification condition min typ max unit note ac characteristics vn dwn output differential noise voltage, at (ay, by) v tx =0 v, 25 khz to 2208 khz 0.6 1.0 r ddwn differential input impedance ddwnp to ddwnn 28k 40k 52k k : v aydc , v bydc ay, by dc bias voltage v psrr vcc vcc to ay, by 20 khz 400 khz all operating modes 800 khz 2 mhz ?38 db ?26 -24 ?20 psrr vbat vbat to ay, by 20 khz 400 khz all operating modes 800 khz 2 mhz ?50 ?44 -37 ?32 psrr bdnd bgnd to ay, by 20 khz 400 khz all operating modes 800 khz 2 mhz ?50 ?50 -50 ?50 crosstalk between lines xtalk fc=100 khz, vout=2vpp 70 80 db 1. , 2. fc=2208 khz, vout=2vpp 50 60 v in, dwn input amplitude, ac coupled 1.0 v iout, max iout max into 100 ohm load 95 ma logic inputs (pdown1, pdown2, discon1 and discon2) v ih logic 1, high level input voltage 2 vcc v v il logic 0, low level input voltage agnd 0.8 i ih pdown = vcc 100 a i il pdown = agnd -100 i ih discon = vcc 100 i il discon = agnd -100 device performance: s r slew rate at v ay?by 250 300 v/s hd2 f c=1mhz, rl=100ohms, vout=2vp-p -70 dbc 3. hd3 f c=1mhz, rl=100ohms, vout=2vp-p -70 dbc mtpr downstream multitone power ratio itu, g.992.1 mtpr test peak to rms ratio = 5.8 70 db k dwn k dwn = v ay,by /v dwn 25 khz to 2208 khz 46 48 50 v/v k dwn vs. frequency -3 db 5 mhz p v hz ----------- v bat 2 ---------------- 0.25 ? v bat 2 ---------------- 0.75 + v bat 2 ---------------- 1.75 +
le87213a data sheet 8 zarlink semiconductor inc. notes: 1. crosstalk is measured with one line transmi tting signal, the other line is enabled but v tx is set to 0 v. 2. crosstalk: 3. measured with a 2.45:1 transformer and a 100- : load. application circuit refer to the datapath reference design. pcb layout the le87213a device contains high gain and high bandwidth amplifiers . the amplifier inputs of each line are connected to the ddwnp/ddwnn pins, the output are connected to the ay and by pi ns. to prevent coupling of the high level output signals into the low level ddwnp/ddwnn pins, pcb tracks and components connected to ay, by, and going to t he tip (a) and ring (b) terminals must be well separated from tracks connected to ddwnp/ddwnn pins. t he components c1, c2, r1, r10, and r11 (and the corresponding components of line 2) should be as close as practical to ddwnp/ddwnn pins. the le87213a device provides an analog ground pin (agnd) as a return for low level currents and a battery ground pin (bgnd) as a return for high level currents. the differential drivers of the le87213a devi ce do not produce any load current into the agnd leads, but the amplifier currents are still circulating in the vbat and bgnd pins. a bypass capacitor between vbat and bgnd is required to be close to the device. agnd and bgnd tracks sh ould only be tied together at a single point, clos e to the power connector of the card. the le87213a device uses a thermally enhanced package equipped with an exposed pad on the bottom side. the printed circuit board surface must have a copper pad covering the full surface of the thermal pad. the copper pad must be fitted with a minimum of 16 thermal transfer vias on a 1 mm pitch with a via diameter of 0.3 to 0.33 mm, and be connected to a large internal copper plane for proper heat dissipation. the agnd plane is recommended. the thermal transfer vias should be connected to the thermal pad and to the agnd plane without thermal relieve tracks. the agnd plane should be the second layer from the top of the pcb for the best power dissipation. in multi-line applications, the le87213a devices must be positioned in the layout to ensure a minimum distance of 1 inch (cente r to center) between devices. passive non-heat producing components can be placed be tween the le87213a devices. table 2. pdown = 1 (power down) specification condition min typ max unit note ac characteristics vn dwn output differential noise voltage, at (ay, by) v tx =0 v, 25 khz to 1104 khz 0.6 1.0 r ddwn differential input impedance ddwnp to ddwnn 28k 40k 52k k : v aydc , v bydc ay, by dc bias voltage v crosstalk between lines xtalk fc=100 khz, vout=2vpp 70 80 db 1. , 2. fc=1104 khz, vout=2vpp 50 60 v in, dwn input amplitude, ac coupled 1.0 v iout, max iout max into 100 ohm load 80 ma device performance: s r slew rate at v ay?by 200 250 v/s hd2 f c=1mhz, rl=100ohms, vout=2vp-p -67.5 dbc 3. hd3 f c=1mhz, rl=100ohms, vout=2vp-p -67.5 dbc mtpr downstream multitone power ratio itu, g.992.1 mtpr test peak to rms ratio = 5.8 67.5 db k dwn k dwn = v ay,by /v dwn 25 khz to 1104 khz 46 48 50 v/v k dwn vs. frequency -3 db 4 mhz p v hz ----------- v bat 2 ---------------- 0.25 ? v bat 2 ---------------- 0.75 + v bat 2 ---------------- 1.75 + xtalk db 20 v ay by , 1 v ay by , 2 -------------------------------- - ?1 ? log =
le87213a data sheet 9 zarlink semiconductor inc. physical dimensions 32-pin qfn note: packages may have mold tooling markings on the surface. these ma rkings have no impact on the form, fit or function of the de- vice. markings will vary with the mold tool used in manufacturing. notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. is in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jep 95-1 and ssp-012. details of the t erminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. coplanarity applies to the exposed pad as well as the terminals. 6. reference document: jedec mo-220. 7. lead width deviates from the jedec mo-220 standard. 32-pin qfn min nom max a 0.80 0.90 1.00 a2 b 0.18 0.23 0.28 d d2 5.70 5.80 5.90 e e2 5.70 5.80 5.90 e l 0.43 0.53 0.63 n a1 0.00 0.02 0.05 a3 aaa bbb ccc 0.57 ref 32 lead qfn symbol 0.10 0.10 0.20 0.20 ref 32 0.80 bsc 8.00 bsc 8.00 bsc
le87213a data sheet 10 zarlink semiconductor inc. device operational notes power supplies the le87213a device is implemented in a high-v oltage process that allows direct powering from the ?42 v to ?72 v battery supply without the need for dc to dc converters. this saves significant power that would otherwise be wa sted in the dc to dc converter . the noise on (referenced to agnd) the battery supply (vbat pin) a nd on the +3.3 v supply (vcc pin) should be below the limits as shown in figure 1 , in order not to affect the data performance. figure 1. allowed noise on power supply pins (referenced to agnd) line transformer a step-down transformer is used to interf ace the le87213a device with the tip (a) an d ring (b) line terminals. the transformer injects the data signal onto the loop and provides dielectric isolation and impedance matching bet ween the loop and the line dr iver. the turn ratio of the transformer can be optimized to matc h the loop signal level to the driver output swing (see transformer turns ratio , on page 11 ). transformer specifics figure 2 represents a simplified transformer model in which the boxed block is an ideal transformer with an infinite bandwidth. figure 2. le87213a transformer 0 20 40 60 80 100 120 140 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 frequency khz noise uv/rthz vbat vcc ` primary secondary r pri l pri l leak r sec c pri z intr n : 1 z sec tip(a) ring(b)
le87213a data sheet 11 zarlink semiconductor inc. transformer turns ratio the transformer turns ratio n is restricted by the maximum peak di fferential signal at ay/by pins, which must stay within the le87213a device's dynamic range. the output voltage range is typically equal to |v batmin | ? 4 v. the maximum peak voltage (across 100 : at tip (a) and ring (b) leads of a fdm ad sl signal using 224 downstream carriers for a combined rms power of 19.85 dbm and a peak-to-rms ratio of 5.8) is 36.05 v pp differential. to account for the voltage drop across z sec , this voltage must be scaled up by a factor of 1.086. t he required peak differential signal at the ay/by pins would be 39.15 v pp or 19.6 v pp per driver if the transformer had a 1:1 turn ratio. using this information the transformer turns ratio can be calculated as . the transformer turns ratio for a nominal battery voltage of ?52 v is then n=2.45:1 . the le87213a device is designed to operate with battery voltage in the range of ?42 v to ?72 v. the data transformer turns rati o can be optimized for the specific battery voltage range, but the turns ratio must be limited to less than 2.7:1 secondary to pr imary (where the primary side is connected to tip (a) and ring (b)) if 19.85 dbm needs to be produced at the output. this limitation is imposed by the le87213a device internal bias levels. downstream filtering the input differential impedance (r ddwn ) of the ddwnp/ddwnn pins can vary by as much as 30%, and consequently a lower value external resistor r 1 is used to set the differential input impedance (refer to the data path reference design). a high-pass filter with a ?3 db corner frequency of is formed by c 1 and c 2 in conjunction with r in to attenuate the low frequency noise of the downstream signal where r in = r 10 + r 11 + (r 1 || r ddwn ) . in addition to rejecting the low frequency signals from the data afe, the input capacitors also block dc currents from flowing between ddwnp/ddwnn and the data af e outputs. with the recommended r 1 value of 5.49 k : , r 10 = r 11 = 2.67 k : and c 1 = c 2 = 1.5 nf provides a corner frequen cy of around 25 khz. resistors r 10, r 11 and r 1 can be used to adjust the downstream signal level. figure 3. downstream gain of the application circuit , on page 8 receiver and hybrid circuit the receive and hybrid circuit architecture depends greatly on the data afe being used in the design. some data afes have built-in input differential amplifiers for the receive circuits. these amplifiers should be used to implement the receive and h ybrid n v bat 4v ? 19.6v ------------------------------ = f dwnhpf 1 2 s r in c in -------------------------- = c in c 1 c 2 ? c 1 c 2 + -------------------- = 0 5 10 15 20 25 10k 100k 1000k 10000k frequency hz downstream gain db db(v loop /vtx) z loop =100 ohms
le87213a data sheet 12 zarlink semiconductor inc. functions. if the afe does not have such amplifiers, then external low noise amplifiers are requi red to implement these functio ns. figure 4 shows a typical implementation of the receive and hybrid functions. figure 4. receive and hybrid circuit components selection the dc blocking capacitor c 6 is required on the primary or line side of the tr ansformer in order to avoid applying a dc short across tip (a) and ring (b) terminals. the value of the line side capacitor depends on transformer primary inductance chosen to give desired ?3 db high pass point. according to t1.413, the im pedance measured across tip (a) and ring (b) at 4 khz must be greater than 1100 : , which requires a capacitance of less than 35 nf for the series combination of c 6 and any external dc blocking capacitor. the minimum transformer primary inductance required is dictated by the low end of the upstream frequency band, which is typically around 25-30 khz. since the transformer primary inductan ce shunts the line, it should be relatively high to avoid sig nal attenuation and maintain an acceptable match across the desir ed bandwidth. a high impedance can be obtained by using a transformer with a high primary side inductance while maintain ing relatively low dc resistance for minimum insertion loss. besides using it for its isolation and high common-mode rejection it is also used as part of the high-pass splitter function. if the -3 db point is chosen to be around 20 khz, the minimum primary (line side) inductance required would be . for the le87213a device, a tran sformer primary side inductance of >800 h is recommended data afe agnd upp upn r 5 c 11 r 4 c 10 r 6 r 7 r 8 r 9 c 12 c 13 + - + - receiver and hybrid circuit hyb- rec+ rec- hyb+ l pri z loop 2 s 20 khz ------------------------------ 100 2 s 20 khz ------------------------------ 796 p h | ==
le87213a data sheet 13 zarlink semiconductor inc. revision history revision a1 to b1 ? added opn for green package in ordering information , on page 1 ? added column and note to ordering information , on page 1 to indicate packing system ? revised 32-lead qfn drawing in physical dimensions , on page 9 to show chamfer revision b1 to b2 ? enhanced format of package drawing in physical dimensions , on page 9 ? added new headers/footers due to zarlink purchase of legerity on august 3, 2007
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