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100 mhz to 2400 mhz i/q modulator with integrated fractional - n pll and vc o data sheet adrf6755 rev. b document feedback information furnished by analog devices is believed t o be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329 .4700 ? 2012 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features i / q modulator with integrated f ractional - n pll and vco gain control s pan: 4 7 db in 1 db steps output frequency range: 1 0 0 mhz to 2400 mhz output 1 db c ompression: 8 dbm at lo = 1800 mhz output ip3 : 20.5 dbm at lo = 1800 mhz noise floor: ? 161 dbm /hz at lo = 1800 mhz baseband m odulation bandwidth: 600 mhz ( 3 db) output frequency resolution: 1 hz spi and i 2 c - compatible serial i nterface s power supply: 5 v/ 380 ma general d escription the adrf6755 is a highly integrated quadrature modulator, frequency synthesizer, and programmable attenuator. the device covers an opera ting frequency range from 1 0 0 mhz to 240 0 mhz for use in satellite, cellular , and broadband communications. the adrf6755 modulator includes a high modulus , fractional - n frequency synthesizer with integrated vco , providing less than 1 hz frequency resolution, and a 47 db digitally controlled output attenuator with 1 db steps. control of all the on - c hip registers is through a user - selected spi interface or i 2 c interface. the device operates from a single power supply ranging from 4.75 v to 5.25 v. figure 1. rset cs txdis dgnd agnd 2 doubler 5-bit divider reference current setting refin refin 2 phase frequency detector + ? rfdivider vco core 0/90 regout v c c 1 v c c 2 v c c 3 v c c 4 adrf6755 lomon lomon rfout 47db gaincontrol range n-counter cr9[7:4] cp nc ibb ibb vtune 3 . 3 v r e g u l a t o r qbb qbb vreg1 vreg2 vreg3 vreg4 vreg5 vreg6 spi/i 2 c interface sdi/sda clk/scl sdo ccomp1 ccomp2 ccomp3 nc ldet charge pump third-order fractional interpolator fractional register modulus 2 25 integer register 10465-001
adrf6755 data sheet rev. b | page 2 of 48 table of contents features .............................................................................................. 1 general description ......................................................................... 1 revision h istory ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 8 absolute maximum ratings .......................................................... 10 esd caution ................................................................................ 10 pin configuration and function des criptions ........................... 11 typical performance characteristics ........................................... 13 theory of operation ...................................................................... 21 overview ...................................................................................... 21 pll synthesizer and vco ......................................................... 21 quadrature modulator .............................................................. 24 attenuator .................................................................................... 25 voltage regulator ....................................................................... 25 i 2 c interface ................................................................................ 25 spi interface ................................................................................ 27 program mo des .......................................................................... 29 register map ................................................................................... 31 register map summary ............................................................. 31 register bit descriptions ........................................................... 3 2 suggested power - up sequence ..................................................... 35 initial register write sequence ................................................ 35 evaluation board ............................................................................ 37 general description ................................................................... 37 hardware description ............................................................... 37 pcb artwork ............................................................................... 41 bill of materials ........................................................................... 44 outline dimensions ....................................................................... 45 ordering guide .......................................................................... 45 revision history 4 /1 3 rev. a to rev. b changes to ordering guide .......................................................... 45 1 1 /12 rev. 0 to rev. a changes to figure 1 .......................................................................... 1 changes to input frequency parameter, table 1 .......................... 6 changes to bit 7 description , table 27 and bit 6 description, table 27 ............................................................................................ 34 change d 0 x00 to 0x60 in step 13 ................................................. 35 updated outline dimensions ....................................................... 45 changes to ordering guide .......................................................... 45 7 /12 revision 0: initial version
data sheet adrf6755 rev. b | page 3 of 48 specifications v cc = 5 v 5% , o perating temperature range = ? 40c to +85c , i/q inputs = 0.9 v p - p differential sine waves in quadrature on a 500 mv dc bias, refin = 80 mhz, pfd = 40 mhz, b aseband frequency = 1 mhz, lomon off , l oop bandwidth ( lbw ) = 100 khz, i cp = 5 ma, unless otherwise noted. table 1 . parameter test conditions /comments min typ max unit operating frequency range 1 00 2 40 0 mhz rf output = 100 mhz rfout pin nominal output power v iq = 0.9 v p - p differential ? 0. 2 dbm gain flatness any 40 mhz 2.0 db output p1db 9. 0 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = ?6 dbm per tone 2 1 .0 dbm output return loss attenuator setting = 0 db ? 12 db lo carrier feedthrough 1 attenuator setting = 0 db to 47 db ? 5 5 dbc 2 lo carrier feedthrough attenuator setting = 0 db to 47 db ? 80 dbm sideband suppression ? 7 0 dbc noise floor i/q inputs = 0 v p - p differential, attenuator setting = 0 db ? 153 dbm/hz baseband harmonics ? 60 dbc synthesizer spurs integer boundary < loop bandwidth ? 85 dbc >10 mhz offset from carrier ? 90 dbc phase noise 100 hz offset ? 106 dbc/hz 1 khz offset ? 116 dbc/hz 10 khz offset ? 127 dbc/hz 100 khz offset ? 131 dbc/hz 1 mhz offset ? 146 dbc/hz 10 mhz offset ? 152 dbc/hz integrated phase noise 1 khz to 8 mhz integration bandwidth 0.0 2 rms rf output = 300 mhz rfout pin nominal output power v iq = 0.9 v p - p differential 0. 2 dbm gain flatness any 40 mhz 0.5 db output p1db 9.3 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = ?6 dbm per tone 23.0 dbm output return loss attenuator setting = 0 db ? 20 db lo carrier feedthrough 1 attenuator setting = 0 db to 47 db ? 50 dbc 2 lo carrier feedthrough attenuator setting = 0 db to 47 db ? 75 dbm sideband suppression ? 7 0 dbc noise floor i/q inputs = 0 v p - p differential, attenuator setting = 0 db ? 158 dbm/hz baseband harmonics ? 60 dbc synthesizer spurs integer boundary < loop bandwidth ? 85 dbc >10 mhz offset from carrier ? 85 dbc phase noise 100 hz offset ? 105 dbc/hz 1 khz offset ? 113 dbc/hz 10 khz offset ? 117 dbc/hz 100 khz offset ? 122 dbc/hz 1 mhz offset ? 145 dbc/hz 10 mhz offset ? 150 dbc/hz integrated phase noise 1 khz to 8 mhz integration bandwidth 0.04 rms
adrf6755 data sheet rev. b | page 4 of 48 parameter test conditions /comments min typ max unit rf output = 700 mhz rfout pin nominal output power v iq = 0.9 v p - p differential 0. 2 dbm gain flatness any 40 mhz 0.5 db output p1db 9.4 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = ?6 dbm per tone 23.0 dbm output return loss attenuator setting = 0 db ? 16 db lo carrier feedthrough 1 attenuator setting = 0 db to 47 db ? 48 dbc 2 lo carrier feedthrough attenuator setting = 0 db to 47 db ? 70 dbm sideband suppression ? 70 dbc noise floor i/q inputs = 0 v p - p differential, attenuator setting = 0 db ? 158 dbm/hz baseband harmonics ? 60 dbc synthesizer spurs integer boundary < loop bandwidth ? 6 0 dbc >10 mhz offset from carrier ? 85 dbc phase noise 100 hz offset ? 97 dbc/hz 1 khz offset ? 106 dbc/hz 10 khz offset ? 112 dbc/hz 100 khz offset ? 115 dbc/hz 1 mhz offset ? 139 dbc/hz 10 mhz offset ? 154 dbc/hz integrated phase noise 1 khz to 8 mhz integration bandwidth 0.07 rms rf output = 900 mhz rfout pin nominal output power v iq = 0.9 v p - p differential 0.0 dbm gain flatness any 40 mhz 0.5 db output p1db 9.2 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = ?6 dbm per tone 22.8 dbm output return loss attenuator setting = 0 db ? 15 db lo carrier feedthrough 1 attenuator setting = 0 db to 47 db ? 48 dbc 2 lo carrier feedthrough attenuator setting = 0 db to 47 db ? 68 dbm sideband suppression ? 60 dbc noise floor i/q inputs = 0 v p - p differential, attenuator setting = 0 db ? 158.5 dbm/hz attenuator setting = 0 db to 21 db, carrier offset = 10 mhz ? 152 dbc/hz attenuator setting = 21 db to 47 db, carrier offset = 10 mhz ? 171 dbm/hz baseband harmonics ? 60 dbc synthesizer spurs integer boundary < loop bandwidth ? 6 0 dbc >10 mhz offset from carrier ? 80 dbc phase noise 100 hz offset ? 94 dbc/hz 1 khz offset ? 104 dbc/hz 10 khz offset ? 109 dbc/hz 100 khz offset ? 114 dbc/hz 1 mhz offset ? 139 dbc/hz 10 mhz offset ? 154 dbc/hz integrated phase noise 1 khz to 8 mhz integration bandwidth 0.11 rms rf output = 1800 mhz rfout pin nominal output power v iq = 0.9 v p - p differential ? 0. 4 dbm gain flatness any 40 mhz 0.5 db output p1db 8.0 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = ?6 dbm per tone 20.5 dbm output return loss attenuator setting = 0 db ? 13 db lo carrier feedthrough 1 attenuator setting = 0 db to 47 db ? 45 dbc 2 lo carrier feedthrough attenuator setting = 0 db to 47 db ? 53 dbm sideband suppression ? 4 5 dbc
data sheet adrf6755 rev. b | page 5 of 48 parameter test conditions /comments min typ max unit noise floor i/q inputs = 0 v p - p differential, attenuator setting = 0 db ? 161 dbm/hz attenuator setting = 0 db to 21 db, carrier offset = 10 mhz ? 150 dbc/hz attenuator setting = 21 db to 47 db, carrier offset = 10 mhz ? 170 dbm/hz baseband harmonics ? 58 dbc synthesizer spurs integer boundary < loop bandwidth ? 60 dbc >10 mhz offset from carrier ? 75 dbc phase noise 100 hz offset ? 89 dbc/hz 1 khz offset ? 99 dbc/hz 10 khz offset ? 103 dbc/hz 100 khz offset ? 108 dbc/hz 1 mhz offset ? 133 dbc/hz 10 mhz offset ? 152 dbc/hz integrated phase noise 1 khz to 8 mhz integration bandwidth 0.17 rms rf output = 1875 mhz rfout pin nominal output power v iq = 0.9 v p - p differential ? 0. 6 dbm gain flatness any 40 mhz 0.5 db output p1db 7.8 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = ?6 dbm per tone 20.2 dbm output return loss attenuator setting = 0 db ? 13 db lo carrier feedthrough 1 attenuator setting = 0 db to 47 db ? 45 dbc 2 lo carrier feedthrough attenuator setting = 0 db to 47 db ? 52 dbm sideband suppression ? 50 dbc noise floor i/q inputs = 0 v p - p differential, attenuator setting = 0 db ? 160 dbm/hz attenuator setting = 0 db to 21 db, carrier offset = 10 mhz ? 150 dbc/hz attenuator setting = 21 db to 47 db, carrier offset = 10 mhz ? 170 dbm/hz baseband harmonics ? 60 dbc synthesizer spurs integer boundary < loop bandwidth ? 60 dbc >10 mhz offset from carrier ? 73 dbc phase noise 100 hz offset ? 89 dbc/hz 1 khz offset ? 97 dbc/hz 10 khz offset ? 103 dbc/hz 100 khz offset ? 108 dbc/hz 1 mhz offset ? 133 dbc/hz 10 mhz offset ? 152 dbc/hz integrated phase noise 1 khz to 8 mhz integration bandwidth 0.18 rms rf output = 2100 mhz rfout pin nominal output power v iq = 0.9 v p - p differential ? 1.0 dbm gain flatness any 40 mhz 0.5 db output p1db 7.4 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = ?6 dbm per tone 19.5 dbm output return loss attenuator setting = 0 db ? 12 db lo carrier feedthrough 1 attenuator setting = 0 db to 47 db ? 44 dbc 2 lo carrier feedthrough attenuator setting = 0 db to 47 db ? 51 dbm sideband suppression ? 45 dbc noise floor i/q inputs = 0 v p - p differential, attenuator setting = 0 db ? 161 dbm/hz attenuator setting = 0 db to 21 db, carrier offset = 10 mhz ? 149 dbc/hz attenuator setting = 21 db to 47 db, carrier offset = 10 mhz ? 170 dbm/hz baseband harmonics ? 60 dbc synthesizer spurs integer boundary < loop bandwidth ? 60 dbc >10 mhz offset from carrier ? 67 dbc
adrf6755 data sheet rev. b | page 6 of 48 parameter test conditions /comments min typ max unit phase noise 100 hz offset ? 88 dbc/hz 1 khz offset ? 98 dbc/hz 10 khz offset ? 101 dbc/hz 100 khz offset ? 108 dbc/hz 1 mhz offset ? 134 dbc/hz 10 mhz offset ? 152 dbc/hz integrated phase noise 1 khz to 8 mhz integration bandwidth 0.25 rms rf output = 2400 mhz rfout pin nominal output power v iq = 0.9 v p - p differential ? 1. 7 dbm gain flatness any 40 mhz 0.5 db output p1db 6.5 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = ?6 dbm per tone 18.5 dbm output return loss attenuator setting = 0 db ? 11 db lo carrier feedthrough 1 attenuator setting = 0 db to 47 db ? 43 dbc 2 lo carrier feedthrough attenuator setting = 0 db to 47 db ? 60 dbm sideband suppression ? 40 dbc noise floor i/q inputs = 0 v p - p differential, attenuator setting = 0 db ? 160.5 dbm/hz attenuator setting = 0 db to 21 db, carrier offset = 10 mhz ? 148 dbc/hz attenuator setting = 21 db to 47 db, carrier offset = 10 mhz ? 170 dbm/hz baseband harmonics ? 55 dbc synthesizer spurs integer boundary < loop bandwidth ? 55 dbc >10 mhz offset from carrier ? 64 dbc phase noise 100 hz offset ? 85 dbc/hz 1 khz offset ? 96 dbc/hz 10 khz offset ? 100 dbc/hz 100 khz offset ? 107 dbc/hz 1 mhz offset ? 132 dbc/hz 10 mhz offset ? 152 dbc/hz integrated phase noise 1 khz to 8 mhz integration bandwidth 0.25 rms reference characteristics refin pin input frequency with reference divide -by - 2 enabled 10 300 mhz with reference divide -by - 2 disabled 10 165 mhz with reference doubler enabled 10 80 mhz input sensitivity ac - coupled 0.4 vreg v p -p input capacitance 10 pf input current 100 a charge pump i cp sink/source programmable, rset = 4.7 k high value 5 ma low value 312.5 a absolute accuracy 4.0 % vco gain k vco 25 mhz/v synthesizer lo = 100 mhz to 2400 mhz frequency resolution 1 hz frequency settling any step size, maximum frequency error = 100 hz 0.17 ms maximum frequency step for no autocalibration frequency step with no autocalibration routine; register cr24, bit 0 = 1 100/2 rfdiv khz phase detector frequency 10 40 mhz
data sheet adrf6755 rev. b | page 7 of 48 parameter test conditions /comments min typ max unit gain control gain range 47 db step size 1 db relative step accuracy fixed frequency, adjacent steps, a ll attenuation steps , lo > 300 mhz 2 0.3 db over full frequency range , adjacent steps , all attenuation steps, lo > 300 mhz 3 1.5 db absolute step accuracy 4 47 db attenuation step , lo > 300 mhz 5 ? 2.0 db output settling time any step; output power settled to 0.2 db 15 s output disable txdis pin off isolation rfout, attenuator setting = 0 db to 47 db, txdis high ? 100 dbm lo, attenuator setting = 0 db to 47 db, txdis high ? 75 dbm 2 lo, attenuator setting = 0 db to 47 db, txdis high ? 50 dbm turn - on settling time txdis high to low: output power to 90% of envelope 180 ns frequency settling to 100 hz 20 s turn - off settling time txdis low to high (to ?55 dbm) 350 ns monitor output lomon, lomon pins nominal output power ? 24 dbm baseband inputs ibb, ibb , qbb, qbb pins i and q input bias level 500 mv 3 db bandwidth 600 mhz logic inputs input high voltage, v inh cs, txdis pins 1.4 v input low voltage, v inl cs, txdis pins 0.6 v input high voltage, v inh sdi/sda, clk/scl pins 2.1 v input low voltage, v inl sdi/sda, clk/scl pins 1.1 v input current, i inh /i inl cs, txdis, sdi/sda, clk/scl pins 1 a input capacitance, c in cs, txdis, sdi/sda, clk/scl pins 10 pf logic outputs output high voltage, v oh sdo, ldet pins; i oh = 500 a 2.8 v output low voltage, v ol sdo, ldet pins; i ol = 500 a 0.4 v sda (sdi/sda); i ol = 3 ma 0.4 v power supplies vcc1, vcc2, vcc3, vcc4, vreg1, vreg2, vreg3, vreg4, vreg5, vreg6, and regout pins ; regout normally connected to vreg1, vreg2, vreg3, vreg4, vreg5, and vreg6 voltage range vcc1, vcc2, vcc3, and vcc4 4.75 5 5.25 v regout, vreg1, vreg2, vreg3, vreg4, vreg5, and vreg6 3.3 v supply current vcc 1 , vcc 2 , vcc 3 , and vcc 4 combined; regout con - nected to vreg1, vreg2, vreg3, vreg4, vreg5, and vreg6 380 420 ma power - down current cr29[0] = 0, power down modulator , cr12[2] = 1, power down pll , cr28[4] = 1, power down rfdivider , cr27[2] = 0, power down lomon 7 ma operating temperature ? 40 +85 c 1 lo carrier feedthrough is expressed in dbc relative to the rf output power changing as the attenuator is stepped. lo carrier feedthrough is constant as the rf output is altered due to a change in the i/q input amplitude. 2 for relative step accuracy at lo < 300 mhz, refer to figure 37. 3 for relative step accuracy over frequency range at lo < 300 mhz, refer to figure 39. 4 all other attenuation steps have an absolute error of <2.0 db. 5 for absolute step accuracy at lo < 300 mhz, refer to figure 40.
adrf6755 data sheet rev. b | page 8 of 48 timing characteristics i 2 c interface timing table 2. parameter 1 symbol limit unit scl clock frequency f scl 400 khz max scl pulse width high t high 600 ns min scl pulse width low t low 1300 ns min start condition hold time t hd;sta 600 ns min start condition setup time t su;sta 600 ns min data setup time t su;dat 100 ns min data hold time t hd;dat 300 ns min stop condition setup time t su;sto 600 ns min data valid time t vd;dat 900 ns max data valid acknowledge time t vd;ack 900 ns max bus free time t buf 1300 ns min 1 see figure 2. figure 2. i 2 c port timing diagram sda t hd;sta t su;dat start condition stop condition s ss p scl 1/ f scl t high t low t hd;dat t vd;dat and t vd;ack (ack signal only) t buf t su;sto t su;sta 10465-002
data sheet adrf6755 rev. b | page 9 of 48 spi interface timing table 3. parameter 1 symbol limit unit clk frequency f clk 20 mhz max clk pulse width high t 1 15 ns min clk pulse width low t 2 15 ns min start condition hold time t 3 5 ns min data setup time t 4 10 ns min data hold time t 5 5 ns min stop condition setup time t 6 5 ns min sdo access time t 7 15 ns min cs to sdo high impedance t 8 25 ns max 1 see figure 3. figure 3. spi port timing diagram t 1 t 3 cs clk sdi sdo t 6 t 8 t 7 t 2 t 5 t 4 10465-003
adrf6755 data sheet rev. b | page 10 of 48 absolute maximum ratings table 4. parameter rating vcc1, vcc2, vcc3, and vcc4 supply voltage ?0.3 v to +6 v vreg1, vreg2, vreg3, vreg4, vreg5, and vreg6 supply voltage ?0.3 v to +4 v ibb, ibb , qbb, and qbb 0 v to 2.5 v digital i/o ?0.3 v to +4 v analog i/o (other than ibb, ibb , qbb, and qbb ) ?0.3 v to +4 v maximum junction temperature 125c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet adrf6755 rev. b | page 11 of 48 pin con figuration and funct ion descriptions figure 4 . pin configuration table 5 . pin function descriptions pin no . mnemonic description 11 , 55, 56, 41, 42, 1 vcc1 to vcc4 positive power supplies for i/q modulator. a pply a 5 v power supply to vcc1 , which should be dec oupled with power supply decoupli ng capacitors. connect vcc2, vcc3 , and vcc4 to the same 5 v power supply. 12 regout 3.3 v output s upply . d rives vreg1, vreg2, vreg3, vreg4, vreg5 , and vreg6. 13 , 14, 15, 16, 31, 36 vreg1 to vreg6 positive power supplies for pll synthesizer, vco , and serial port. connect t hese pins to regout (3.3 v) and decouple them separately. 6, 19, 20, 21, 22, 23, 24, 37, 39, 40, 46, 47, 49, 50, 51, 52, 53, 54 agnd analog ground. connect to a low impedance ground plane . 32 dgnd digital ground. connect to the same low impedance ground plane as the agnd pins . 2 , 3 ibb , ibb differential in - phase baseband inputs. these high impedance inputs must be dc bi ased to approx - imately 500 mv dc and should be driven from a low impedance source. nominal characterized ac signal swing is 450 mv p - p on each pin. these inputs are not self - biased and must be externally biased. 4 , 5 qbb , q bb differential quadrature baseband inputs. these high impedance inputs must be dc - biased to approximately 500 mv dc and should be driven from a low impedance source. nominal charac - terized ac signal swing is 450 mv p - p on each pin. these inputs are not self - biased and must be externally biased. 33 , 34, 35 ccomp1 to ccomp3 internal compensation node s. the s e pin s must be decoupled to ground with a 100 nf capacitor. 38 vtune control input to the vco. this voltage determines the output frequency and is derived from filtering the cp output voltage. 7 rset charge pump current set. connecting a resistor between this pin and ground sets the maximum charge pump output current. the relationship between i cp and r set is as follows: set cpmax r i 5 . 23 = where r set = 4.7 k and i cp max = 5 ma. 9 cp charge pump output. when enabled, this output provides i cp to the external loop filter, which , in turn, drives the internal vco. 27 cs chip select, cmos input. when cs is high, the data stored in the shift registers is loaded into one of 31 latches. in i 2 c mode , when cs is high, the slave address of the device is 0x60 , and , when cs is low, the slave address is 0x40 . pin 1 indic a t or 1 vcc4 2 ibb 3 ibb 4 qbb 5 qbb 6 agnd 7 rset 8 nc 9 cp 10 nc 1 1 vcc1 12 regout 13 vreg1 14 vreg2 35 ccomp3 36 vreg6 37 agnd 38 vtune 39 agnd 40 agnd 41 vcc3 42 vcc3 34 ccomp2 33 ccomp1 32 dgnd 31 vreg5 30 clk/sc l 29 sdi/sd a 15 vreg3 16 vreg4 17 refin 19 agnd 21 agnd 20 agnd 22 agnd 23 agnd 24 agnd 25 lomon 26 lomon 27 cs 28 sdo 18 refin 45 txdis 46 agnd 47 agnd 48 rfout 49 agnd 50 agnd 51 agnd 52 agnd 53 agnd 54 agnd 44 ldet 43 muxout top view (not to scale) adrf6755 55 vcc2 56 vcc2 notes 1. nc = no connect. do not connect to this pin. 2. connect exposed pad to ground plane via a low impedance path. 10465-004
adrf6755 data sheet rev. b | page 12 of 48 pin no . mnemonic description 29 sdi/sda serial data input for spi port / ser ial data input/output for i 2 c port. in spi mode, this pin is a high impedance cmos data input , and data is loaded in an 8 - bit word. in i 2 c mode, this pin is a bidirec - tional port. 30 clk/scl serial clock input for spi/i 2 c port. this serial clock is used to clock in the serial data to the registers. this input is a high impedance cmos input. 28 sdo serial data output for spi port. register states can be read back on the sdo data output line. 17 refin reference input. this high impedance cmos input should be ac - coupled. 18 refin reference input bar . this pin should be either grounded or ac - coupled to ground. 48 rfout rf output. single - ended, 50 , internally biased rf output . this p in must be ac - c oupled to the load. 45 txdis output disable. this pin can be used to disable the rf output. connect to a high logic level to disable the output. connect to a low logic level for normal operation. 25 , 26 lomon , lomon differential monitor outputs. these pins provide a replica of the internal local oscillator frequency (1 lo) at four different power levels: ? 6 dbm, ? 12 dbm, ? 18 dbm, and ?24 dbm , approximately . these open - collector outputs must be terminated with external resistors to regout . these outputs can be disabl ed through serial port programming and should be tied to regout if not used. 8, 10 nc no connect. do not connect to these pins. 44 ldet lock detect. this output pin indicates the state of the pll: a high lev el indicates a locked condition, whereas a low level indicates a loss of lock condition. 43 muxout mux output. this pin is a test output for diagnostic use only. do not connect to this pin . exposed paddle ep exposed paddle. connect to ground plane via a low impedance path .
data sheet adrf6755 rev. b | page 13 of 48 typical performance characteristics v cc = 5 v 5%, o perating temperature range = ? 40c to +85c , i/q inputs = 0.9 v p - p differential sine waves in quadrature on a 500 mv dc bias, refin = 8 0 mhz, pfd = 4 0 mhz, b aseband frequency = 1 mhz, lomon is off, loop bandwidth (lbw) = 100 khz, i cp = 5 ma, unless otherwise noted. a nominal condition is defined as 25 c, 5.00 v, a n d an lo frequency of 1800 mhz . a worst - case condition is defined as having the worst - case temperature, su pply voltage , and lo frequency. figure 5 . output power vs. lo frequency, supply , and temperature figure 6 . output power distribution at nominal and worst - case conditions figure 7 . sideband suppression vs. lo frequency, supply, and temperature figure 8 . sideband suppression distribution at nominal and worst - case conditions figure 9. lo carrier feedthrough vs. lo frequency, attenuation, supply, and temperature figure 10 . lo carrier feedthrough distribution at nominal and worst - case conditions and attenuation setting ?5 ?4 ?3 ?2 ?1 0 1 2 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 output power (dbm) lo frequenc y (mhz) 25 c; 5v 85 c; 4.75v 85 c; 5.25v ?40 c; 4.75v ?40 c; 5.25v 10465-005 0 5 10 15 20 25 ?4.2 ?3.8 ?3.4 ?3.0 ?2.6 ?2.2 ?1.8 ?1.4 ?1.0 ?0.6 ?0.2 0.2 0.6 1.0 occurrence (%) output power (dbm) nominal worst case 10465-006 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 sideband suppression (dbc) lo frequenc y (mhz) +2 5 c, 5.00v +8 5 c, 4.75v +8 5 c, 5.25v ?4 0 c, 4.75v ?4 0 c, 5.25v 10465-108 0 10 20 30 40 50 60 ?60 ?55 ?50 ?45 ?40 ?35 ?30 occurrence (%) sideband suppression (dbc) nominal worst case 10465-009 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 carrier feedthrough (dbc) lo frequenc y (mhz) 10465- 1 10 0 10 20 30 40 50 60 70 80 ?60 ?58 ?56 ?54 ?52 ?50 ?48 ?46 ?44 ?42 ?40 ?38 ?36 ?34 ?32 ?30 occurrence (%) lo carrier feedthrough (dbc) nominal worst case 10465-0 1 1
adrf6755 data sheet rev. b | page 14 of 48 figure 11 . 2 lo carrier feedthrough vs. lo frequency, attenuation, supply, and temperature figure 12 . output p1db compression point at worst - case lo frequency vs. supply and temperature figure 13 . output p1db compression point vs. lo frequency at nominal conditions figure 14 . output p1db compression point distribution at nominal and worst - case conditions figure 15 . output ip3 vs. lo frequency at nominal conditions figure 16 . output ip3 distribution at nominal and worst - case conditions ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 lo frequenc y (mhz) attenuation = 0db attenuation = 12db attenuation = 21db attenuation = 33db attenuation = 47db 2 lo carrier feedthrough (dbm) 10465- 1 12 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 ?25 ?20 ?15 ?10 ?5 0 5 10 0.1 1 10 ideal output power ? output power (dbm) output power (dbm) differentia l input vo lt age (v p-p) 1db compression point 10465-013 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 output p1db (dbm) lo frequenc y (mhz) 10465- 1 15 0 5 10 15 20 25 30 35 40 45 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 occurrence (%) output p1db (dbm) nominal worst case 10465-014 10 12 14 16 18 20 22 24 26 28 30 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 output ip3 intercept point (dbm) lo frequenc y (mhz) 10465- 1 17 0 5 10 15 20 25 30 35 40 45 50 15 16 17 18 19 20 21 22 occurrence (%) output ip3 (dbm) nominal worst case 10465-016
data sheet adrf6755 rev. b | page 15 of 48 figure 17 . lo off isolation vs. lo frequency, attenuation, supply, and temperature figure 18 . 2 lo off isolation vs. lo frequency, attenuation, supply, and temperature figure 19 . second - order and third - order harmonic distortion vs. lo frequency, supply, and temperature figure 20 . noise floor at 0 db attenuation vs. output power at nominal conditions figure 21 . noise floor at 1 0 mhz offset frequency distribution at worst - case conditions and different attenuation settings figure 22 . normalized i and q input bandwidth ?13 0 ?12 0 ?1 1 0 ?10 0 ?9 0 ?8 0 ?7 0 ?6 0 10 0 30 0 50 0 70 0 90 0 1 10 0 130 0 150 0 170 0 190 0 210 0 230 0 250 0 l o o ff i so l a t io n (d b m ) l o f r eq u en c y (mh z) a ttenua t io n = 0 d b a ttenua t io n = 21 d b a ttenua t io n = 47 d b 10465 - 1 1 8 ?130 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 2 x lo off isol a tion (dbm) lo frequenc y (mhz) attenuation = 0db attenuation = 47db attenuation = 21db 10465- 1 19 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 output power (dbc) lo frequenc y (mhz) upper third harmonic ( f lo + 3 f bb ) upper second harmonic ( f lo + 2 f bb ) lower second harmonic ( f lo ? 2 f bb ) lower third harmonic ( f lo ? 3 f bb ) 10465-120 ?165 ?163 ?161 ?159 ?157 ?155 ?153 ?151 ?149 ?147 ?145 ?25 ?20 ?15 ?10 ?5 0 5 10 noise floor (dbm/hz) output power (dbm) 10465-022 0 10 20 30 40 50 60 70 80 90 100 ?180 ?176 ?172 ?168 ?164 ?160 ?156 ?152 ?148 ?144 ?140 occurrence (%) noise floor a t 10mhz offset frequenc y (dbm/hz) and (dbc/hz) attenuation = 21db (dbc/hz) attenuation = 47db (dbm/hz) attenuation = 21db (dbm/hz) attenuation = 0db (dbc/hz) 10465-167 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1 10 100 1000 normalized output power (db) i and q baseband input frequenc y (mhz) 10465-023
adrf6755 data sheet rev. b | page 16 of 48 figure 23 . output return loss at different attenuation settings vs. output frequency, supply , and temperature figure 24 . rf output spectral plot over a 10 mhz span figure 25 . rf output spectral plot over a 100 mhz span figure 26 . rf output spectral plot over a wide span figure 27 . phase noise performance vs. lo frequency, nominal conditions figure 28 . phase noise performance vs. lo frequency, supply, and temperature ?28 ?26 ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 s22 (db) output frequenc y (mhz) attenuation = 0db attenuation = 21db and 47db 10465-123 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 rf output (dbm) frequency (mhz) lower sideband carrier feedthrough suppressed sideband second harmonic third harmonic 10465-025 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1825 1835 1845 1855 1865 1875 1885 1895 1905 1915 1925 rf output (dbm) frequenc y (mhz) lower sideband carrier feedthrough suppressed sideband third harmonic 10465-026 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 1 2 3 4 5 6 7 8 9 10 r f output (dbm) frequenc y (mhz) 3 lo harmonic lower sideband 2 lo harmonic 4 lo harmonic 5 lo harmonic 10465-027 ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 100 1k 10k 100k 1m 10m phase noise (dbc/hz) offset frequenc y (hz) lo frequency = 2400mhz lo frequency = 1200mhz lo frequency = 580mhz lo frequency = 290mhz lo frequency = 100mhz 10465-160 ?160 ?150 ?140 ?130 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 100 1k 10k 100k 1m 10m phase noise (dbc/hz) offset frequenc y (hz) lo frequency = 2500mhz lo frequency = 100mhz 10465-128
data sheet adrf6755 rev. b | page 17 of 48 figure 29 . phase noise performance distribution at worst - case conditions figure 30 . integrated phase noise over an integration bandwidth of 1 khz to 8 mhz vs. lo frequency at nominal conditions figure 31 . integrated phase noise distribution over an integration bandwidth of 1 khz to 8 mhz at 1875 mhz and 2310 mhz figure 32 . phase noise performance vs. lo frequency, nominal conditions with narrow loop bandwidth figure 33 . integer boundary spur performance vs. lo frequency, supply, and temperature figure 34 . spurs > 10 mhz from carrier vs. lo frequency, supply, and temperature ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 100 1k 10k 100k 1m 10m phase noise (dbc/hz) offset frequenc y (hz) 10465-129 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 rms jitter (degrees) lo frequenc y (mhz) 10465-133 0 10 20 30 40 50 60 70 80 90 0.10 0.15 0.20 0.25 0.30 0.35 0.40 occurrence (%) rms jitter (degrees) 1875mhz 2310mhz 10465-034 10465-168 ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 100 1k 10k 100k 1m 10m phase noise (dbc/hz) offset frequency (hz) 900mhz phase noise (dbc/hz) 1800mhz phase noise (dbc/hz) 2100mhz phase noise (dbc/hz) ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 integer bounda r y spurs (dbc) lo frequenc y (mhz) +25c 5v max spur +85c 4.75v max spur +85c 5.25v max spur ?40c 4.75v max spur ?40c 5.25v max spur 10465-166 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 spurs > 10mhz offset frequenc y (dbc) lo frequenc y (mhz) reference spurs at 80mhz offset pfd spurs at 40mhz offset 10465-132
adrf6755 data sheet rev. b | page 18 of 48 figure 35 . pll frequency settling time at worst - case lo frequency with lock detect shown figure 36 . attenuator gain vs. lo frequency by gain code, all attenuator code steps figure 37 . attenuator relative step accuracy over all attenuation steps vs. lo frequency, nominal conditions figure 38 . attenuator relative step accuracy distribution at nominal and worst - case conditions, lo > 300 mhz, all attenuation steps figure 39 . attenuator relative step accuracy across full output frequency range distribution at nominal and worst - case conditions, lo > 300 mhz, all attenuation steps figure 40 . attenuator absolute step accuracy over all attenuation steps vs. lo frequency, nominal conditions 0.1 1 10 100 1k 10k 100k 1m 10m 100m 1g ?50 ?30 ?10 10 30 50 70 90 1 10 130 150 170 190 210 230 250 frequenc y error (hz) time ( s) start of acquisition acquisition to 100hz number of pfd cycles to declare ldet = 4096 ldet 10465-134 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 output power (dbm) lo frequenc y (mhz) 10465-131 10465-138 ?1.5 ?1.0 ?0.5 0 0.5 1.0 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 a ttenu a t or rel a tive ste p accurac y (db) lo frequenc y (mhz) 0 10 20 30 40 50 60 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 occurrence (%) a ttenu a t or rel a tive ste p accurac y (db) nominal worst case 10465-136 0 2 4 6 8 10 12 14 ?3.25 ?2.75 ?2.25 ?1.75 ?1.25 ?0.75 ?0.25 0.25 0.75 1.25 1.75 2.25 2.75 3.25 occurrence (%) a ttenu a t or rel a tive ste p accurac y across ful l output frequenc y range (db) nominal worst case 10465-137 ?10 ?8 ?6 ?4 ?2 0 2 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 a ttenu a t or absolute ste p accurac y (db) lo frequenc y (mhz) 10465-141
data sheet adrf6755 rev. b | page 19 of 48 figure 41 . attenuator absolute step accuracy distribution at nominal and worst - case conditions, lo > 300 mhz, all attenuation steps figure 42 . gain flatness in any 40 mhz for all attenuation steps vs. lo frequency at nominal conditions figure 43 . attenuator setting time to 0.2 db for small steps (1 db to 6 db) at nominal conditions figure 44 . attenuator settling time to 0.5 db for small steps (1 db to 6 db) at nominal conditions figure 45 . attenuator settling time to 0.2 db for large steps (7 db to 47 db) at nominal conditions figure 46 . attenuator settling time to 0.5 db for large steps (7 db to 47 db) at nominal conditions 0 5 10 15 20 25 30 ?5.0 ?4.6 ?4.2 ?3.8 ?3.4 ?3.0 ?2.6 ?2.2 ?1.8 ?1.4 ?1.0 ?0.6 ?0.2 0.2 occurrence (%) a ttenu a t or absolute ste p accurac y (db) nominal worst case 10465-139 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 gain fl a tnees in an y 40mhz (db) lo frequenc y (mhz) 10465-145 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 40 45 50 settling time ( s) st arting a ttenu a t or step 10465-163 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 40 45 50 settling time ( s) st arting a ttenu a t or step 10465-162 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 35 40 45 50 settling time ( s) st arting a ttenu a t or step 10465-161 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 35 40 45 50 settling time ( s) s t arting a ttenu a t or step 10465-164
adrf6755 data sheet rev. b | page 20 of 48 figure 47 . attenuator settling time to 0.2 db and 0.5 db distribution at nominal and worst - case conditions for typical small step figure 48 . attenuator settling time to 0.2 db and 0.5 db distribution at nominal and worst - case conditions for worst - case small step (36 db to 42 db) figure 49 . attenuator settling time to 0.2 db and 0.5 db distribution at nominal and worst - case conditions for typical large step figure 50 . attenuator settling time to 0.2 db and 0.5 db distribution at nominal and worst - case conditions for worst - case large step (47 db to 0 db) figure 51 . txdis settling time at worst - case supply and temperature 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 occurrence (%) a ttenu a t or settling time ( s) nominal settling time to 0.2db worst case settling time to 0.2db nominal settling time to 0.5db worst case settling time to 0.5db 10465-146 0 10 20 30 40 50 60 70 80 90 100 0 3 6 9 12 15 18 21 24 occurrence (%) a ttenu a t or settling time ( s) nominal settling time to 0.2db worst case settling time to 0.2db nominal settling time to 0.5db worst case settling time to 0.5db 10465-147 0 10 20 30 40 50 60 70 80 90 100 0 3 6 9 12 15 18 21 occurrence (%) a ttenu a t or settling time ( s) nominal settling time to 0.2db worst case settling time to 0.2db nominal settling time to 0.5db worst case settling time to 0.5db 10465-148 0 5 10 15 20 25 30 35 40 45 50 0 3 6 9 12 15 18 21 24 27 30 33 occurrence (%) a ttenu a t or settling time (s) 10465-149 nominal settling time to 0.2db worst case settling time to 0.2db nominal settling time to 0.5db worst case settling time to 0.5db ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 1 2 3 4 5 6 7 8 output power (dbm) txdis settling time (s) txdis turn-on = 180ns turn-off= 350ns 10465-144
data sheet adrf6755 rev. b | page 21 of 48 theory of operation o verview the adrf6755 device can be divided into the following basic building blocks: ? pll s ynthesizer and vco ? quadratur e m odulator ? attenuator ? voltage r egulator ? i 2 c /spi i nterface each of these building blocks is described in detail in the section s that follow . pll s ynthesizer and vco overview the phase - locked loop ( pll ) consists of a fractional - n frequency synthesizer with a 25- bit fixed modulus, allowing a frequency resolution of less than 1 hz over the entire frequency range. it also has an inte grated voltage - controlled oscillator (vco) with a fundamental output freque ncy ranging from 2310 mhz to 4800 mhz. an rf divider, controlled by register cr28, bits[2:0], extends the lower limit of the local oscillator (lo) frequency range to 100 mhz. see table 6 for more detail s on register cr28. reference input section the reference input stage is shown figure 52 . sw1 and sw2 are normally closed switches. sw3 is normally open. when power - down is initiated, sw3 is closed , and sw1 and sw2 are open. this ensures that there is no loading of the refin pin at power - down. figure 52 . reference input stage reference input path the on - chip reference frequency doubler allows the input reference signal to be doubled. this is useful for increasing the pfd comparison frequency. making the pfd frequency higher improves the noise performance of the system. doubling the pfd frequency usually improves the in - band phase noise performance by up to 3 dbc/hz. the 5 - bit r - divider allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 32 are allowed. an additional divide - by - 2 (2) function in the reference input path allows for a greater division range. figure 53 . referenc e input path the pfd frequency equation is f pfd = f refin [(1 + d )/( r (1 + t ))] (1 ) where: f refin is the reference input frequency. d is the doubler bit. r is the programmed divide ratio of the binary 5 - bit programmable reference divider ( 1 to 32). t is the r / 2 divider setting bit ( cr10[6] = 0 or 1). if no division is required, it is recommended that the 5 - bit r - divider and the divide - by - 2 be disabled by setting cr5[4] = 0 . if an even numbered division is required, enable the divide - by - 2 by setting cr5[4] = 1 and cr10[6] = 1 and implement the remainder of the division in the 5 - bit r - divider. if an odd number div ision is required , set cr5[4 ] = 1 and implement all of the division in the 5 - bit r - divider. rf fractional - n divider the rf fractional - n divid er allows a division ratio in the pll feedback path that can range from 23 to 4095 . the relationship between the fractional - n divider and the lo frequency is described in the int and frac relationship section . int and frac relationship the integer ( int ) and fractional ( frac ) values make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (pfd) frequency . see the example changing the lo frequency section for more info rmation. the lo frequency equation is lo = f pfd ( int + ( frac /2 25 ))/2 rfdiv (2 ) where: lo is the local oscillator frequency . f pfd is the pfd frequency. int is the integer component of the required division factor and is controlled by the cr6 and cr7 registers . frac is the f r actional component of the required division factor and is controlled by the cr0 to cr3 registers . rfdiv is set in register cr28, bits[2:0 ] , and controls the setting of the divider at the output of the pll. figure 54 . rf fractional - n divider buffer to r-divider refin 100 n? nc sw2 sw3 nc nc sw1 power-down control 10465-052 2 doubler 5-bit r-divider from refin pin to pfd 2 10465-053 n-counter int reg to pfd rf n-divider n = int + frac/2 25 from vco output dividers frac value third-order fractional interpolator 10465-054
adrf6755 data sheet rev. b | page 22 of 48 phase frequency detector (pfd) and charge pump the pfd takes inputs from the r - divider and the n - counter and produces an output prop ortional to the phase and frequency differ - ence between them (see figure 55 for a simplified schematic) . the pfd includes a fixed delay element that sets the width of t he antibacklash pulse , ensuring that there is no dead zone in the pfd transfer fun ction . figure 55 . pfd simplified schematic lock detect (ld et ) ld et (p in 44) signal s when the pll has achieved lock to an error frequency of less than 1 00 hz. on a write to register cr0 , a new pll acquisition cycle starts , and the ld et signal goes low. when lock has been achi e ved, this signal returns high. voltage - controlled oscillator ( vco ) the vco core in the adrf6755 consists of three separate vcos , each with 16 overlapping bands. this configuration of 48 bands allows the vco frequency rang e to extend from 2310 mhz to 480 0 mhz. the thre e vcos are divided by a program mable divider, rf div , control led by register cr28, bits[2:0] . this divider p rov ides divisions of 1, 2, 4 , 8, and 16 to ensure that the frequency range is extended from 144.375 mhz (2310 mhz/ 16) to 4800 mhz (480 0 mhz/1). a divide - by - 2 quadrature circuit in the path to the modulator then provides th e full lo frequency range from 100 mhz to 2400 mhz. figure 56 shows a sweep of v tune vs. lo frequency demonstrating the three vcos overlapping and the multiple overlapping bands within each vc o at the lo frequency range of 100 mhz to 2400 mhz. no te that figure 56 include s the rfdiv being incorporated to provide further divisions of the fundamental vco frequency; thus, each vco is used on multiple different occasions throughout the full lo frequency range. the choice of three 16 - band vcos and an rfdiv allows the wide frequency range to be covered without large vco sensitivity (k vco ) or resultant poor phase noise and spurious performance. figure 56 . v tune vs. lo frequency the vco displays a variation of k vco as v tune varies within the band and from band to band. figure 57 shows how k vco varies across the full frequency range. figure 57 is useful when calculating the loop filter bandwidth and individual loop filter components using adisimpll?. adisimpll is an analog devices, inc., simulator that aids in pll design, particula rly with respect to the loop filter. it reports parameters such as phase noise, integrated phase noise, and acquisition time for a particular set of input conditions. adisimpll can be downloaded from www.anal og.com/adisimpll . figure 57 . k vco vs. lo frequency autocalibration the correct vco and band are chosen automatically by the vco and band select circuitry when register cr0 is updated. this is referred to as autocalibration. the autocalibration time is set by register cr25. autocalibration time = ( bscdiv 28)/ pfd (3) where: bscdiv = register cr25, bits[7:0]. pfd = pfd frequency. for a pfd frequency of 40 mhz, set bscdiv = 100 to set an autocalibration time of 70 s. u3 clr2 q2 d2 u2 down up hi hi cp ?in +in charge pump del a y clr1 q1 d1 u1 10465-055 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 v tune (v) lo frequenc y (mhz) 10465-157 0 10 20 30 40 100 300 500 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 k vco (mhz/v) lo frequenc y (mhz) 10465-158
data sheet adrf6755 rev. b | page 23 of 48 note that bs cdiv must be recalculated if the pfd frequency is changed. the recommended autocalibration setting is 70 s. during this time, the vco v tune is disconnected from the output of the loop filter and is connected to an internal reference voltage. a typical fre quency acquisition is shown in figure 58. figure 58 . pll acquisition after autocalibration, normal pll action resumes, and the correct frequency is acquired to within a frequency error of 1 00 hz in 170 s typically. for a maximum cumulative step of 100 khz/2 rfdiv , autocalibration can be turned off by setting register cr24, bit 0 = 1 . this enables cumulative pll acquisi - tions of 100 khz ( for rfdiv = 1, 50 k hz for rfdiv = 2 , and so on) to occur without the autocalibration procedure, which improves acquisition times significantly (see figure 59). f igure 59 . pll acquisition without autocalibration for a 100 khz step programming the correct lo frequency there are two steps to programming the correct lo frequency. the user must calculate the rfdiv value based on the required lo frequency and pfd frequency, and the n - divider ratio that is required in the pll. 1. calculate the value of rfdiv, which is used to program register cr28, bits[2:0] and cr27, bit 4 from the following lookup table , table 6 . table 6 . rfdiv lookup table lo frequency (mhz) rfdivider cr28[2:0] = rfdiv cr27[4] 1155 < lo < 240 0 divide -by -1 000 1 577.5 < lo 1155 divide -by -2 001 0 288.75 < lo 577.5 divide -by -4 010 0 144.375 < lo 288.75 divide - by - 8 011 0 100 < lo 144.375 divide -by -16 100 0 2. using the following equation, calculate the value of the n - divider: n = (2 rfdiv lo )/ f pfd (4) where: n is the n - divider value. rfdiv is the setting in register cr28, bits[2:0]. lo is the local oscillator frequency. f pfd is the pfd frequency. this equation is a different representation of equation 2. example to program the correct lo frequency assume that the pfd frequency is 40 mhz and that the required lo frequency is 1875 mhz. from table 6 , 2 rfdiv = 1 (rfdiv = 0) n = (1 1875 10 6 ) / ( 40 10 6 ) = 46.875 the n - divider value is composed of integ er (int) and fractional (frac) components according to the following equation: n = int + frac /2 25 (5) int = 46 and frac = 29,360,128 the appro priate registers must then be programmed according to the register map . the order in which the register s are programmed is important. writing to cr0 initiates a pll acquisition cycle. if the programmed lo frequency requires a change in the value of cr27[4] ( see table 6 ), cr2 7 should be the last registe r programmed, preceded by cr0. if the programmed lo frequency does not require a change in the value of cr27[4] , it is optional to omit the write to cr27 and , in that case , cr0 should be the last register programmed. 0.1 1 10 100 1k 10k 100k 1m 10m 100m 1g 0 25 50 75 100 125 150 175 200 225 250 frequenc y error (hz) time (s) 10465-156 autocal time (s) acquisition to 100hz 1 10 100 1k 10k 100k 1m 0 50 100 150 200 frequenc y error (hz) time (s) acquisition to 100hz 10465-159
adrf6755 data sheet rev. b | page 24 of 48 q uadratur e modulator overview a basic block diagram of the adrf6755 quadrature modulator circuit is shown in figure 60 . the vco /rf divider generates a signal at the 2 lo frequency , which is then divided down to give a signal at the lo frequency. this signal is then split into in - phase and quadrature component s to provide the lo signals that drive the mixers. figure 60 . block diagram of the quadrature modulator the i and q baseband input signals are converted to currents by the v - to - i stages, which then drive the two mixers. the outpu ts of these mixers combine to feed the single - ended output. this single - ended output is then fed to the attenuator and , finally , to the external rfout signal pin. baseband inputs the baseband inputs , qbb , qbb , ibb, and ibb , must be driven from a differential sour ce. the nominal drive level of 0.9 v p - p differential (450 mv p - p on each pin) should be biased to a common - mode level of 500 mv dc. t o set the dc bias level at the baseband inputs, refer to figure 61. the average output current on each of the ad9779 outputs is 10 ma. a current of 10 ma flowing through each of the 50 ? resistors to ground produce s the desired dc bias of 500 mv at each of the baseband inputs. figure 61 . establishing dc bias level on baseband inputs the di fferential baseband inputs (qbb , qbb , ibb , and ibb) consist of the bases of pnp transistors, which present a high impedance of about 30 k? in parallel with approximately 2 pf of capacitance. the impedance is approximately 30 k? below 1 mhz and start s to roll off at higher freque ncy . a 100 ? differential termination is recommended at the baseband inputs , and this dominate s the input impedance as seen by the input baseband signal. this ensures that the input impedance , as seen by the input circuit , remains flat across the baseband bandwidth . see figure 62 for a typical configuration . figure 62 . typical baseband input configuration the swing of the ad 9779 output currents ranges from 0 ma to 20 ma. the ac voltage swing is 1 v p - p single - ended or 2 v p - p differential with the 50 ? resistors in place. the 100 ? differen - tial termination resistors at the baseband inputs have the effect of limiting this swing without changing the dc bias condition of 500 mv. the low - pass filter is used to filter the dac outputs and remove images when driving a modulator. another consideration is that the baseband inputs actually source a c urrent of 240 a ou t of each of the four inputs. this current must be taken into account when setting up the dc bias of 500 m v. i n the initial example based on figure 61 , an error of 12 mv occur s due to the 240 a current flowing through the 50 ? resistor. analog devices recommend s that the accuracy of the dc bias should be 500 mv 25 m v. it is also important that this 240 a current ha ve a dc path to ground. optimization the carrier f eedthrough and the sideband suppression performance of the adrf6755 can be improved over the specifications in table 1 by using the following optimization techniques. carrier feedthrough nulling carrier feedthrough results from dc offsets that occur between the p and n inputs of each of the differential baseb and inputs. normally these inputs are set to a dc bias of approximately 500 m v. however , if a dc offset is introduced between the p and n inputs of either or both i and q inputs, the carrier feedthrough is affected in either a positive or a negative fashi on. note that the dc bias level remains at 500 mv (average p and n level). the i channel offset is often held constant while the q channel offset is varied until a minimum carrier feedthrough level is obtained. then , while retaining the new q channel offse t, the i c hannel offset is adjusted until a new minimum is reached. this is usually per - formed at a single frequency and , thus , is not optimized over the complete frequency range. multiple optimizations at different vco rf divider v-to-i v-to-i ibb ibb qbb qbb rfout to attenuator quad phase splitter 2 10465-060 50? 50? 50? 50? out1_p out1_n out2_n out2_p adrf6755 current output dac (example: ad9779) ibb ibb qbb qbb 10465-061 50? 50? 50? 50? out1_p out1_n out2_n out2_p adrf6755 current output dac (example: ad9779) ibb ibb qbb qbb 100? low- pass filter 100? low- pass filter 10465-062
data sheet adrf6755 rev. b | page 25 of 48 frequencies must be performed to ensure optimum carrier feed - through across the full frequency range. sideband suppression nulling sideband suppression results from relative gain and relat ive phase offsets between the i channel and q channel and can be optimized through adjustments to those two parameters. adjusting only one parameter improves the sideband suppression only to a point. for optimum sideband suppression, an iterative adjustment between phase and amplitude is required. a ttenuator the dig ital attenuator consists of six attenuation blo ck s: 1 db , 2 db, 4 db, 8 db, and two 16 db blocks ; each is separately controlled. each attenuation block consists of field effect transistor (fet) switches and resistors that form either a pi - shaped or a t - shaped attenuator. by controlling the states of t he fet switches through the control lines, each attenuation block can be set to the pass state (0 db) or the attenuation state ( 1 db to 47 db ). the various combinations of the six blocks provide the attenuation states from 0 db to 47 db in 1 db increments. voltage r egulator the voltage regulator is powered from a 5 v supply that is provid ed by vcc1 (p in 11) and pro duc es a 3.3 v nominal regulated output voltage, r egout, on p in 12. this pin must be connected (external to the ic) to the vreg1 through vreg6 pa ckage pins. decouple t he regulator output (r egout ) with a parallel combination of 10 pf and 220 f capacitors . the 220 f capacitor , which is recommended for best performance, decouples broadband noise , leading to better phase noise. each v reg x pin sh ould have the following decoupling capacitors: 100 nf multilayer ceramic with an additional 10 pf in parallel, both placed as close as possible to the device under test ( dut ) power supply pins. x7r or x5r capacitors are recom mended. see t he evaluation board section f or more information . i 2 c interface the adrf6755 supports a 2 - wire, i 2 c - compatible serial bus that drives multiple peripherals. the serial data (sda) and serial clock (sc l ) inputs carry information between any devices that are con nected to the bus. each slave device is recognized by a unique address. the adrf6755 has two possible 7 - bit slave addresses for both read and write operations. the msb of the 7 - bit slave address is set to 1. bit a 5 of the slave address is set by the cs pin (pin 27) . bits[4:0] of the sl ave address are set to all 0s. the slave address consists of the seven msbs of an 8 - bit word. the lsb of the word sets either a read or a write operation (see figure 63 ). logic 1 corresponds to a read operation, wh ereas logic 0 corresponds to a write operation. to control the device on the bus, the following protocol must be followed. the master initiates a data transfer by establishing a start condition, defined by a high - to - low transition on sda while sc l remains high. this indicates that an address/data stream follows. all peripherals respond to the start condition and shift the next eight bits (the 7 - bit address and the r/w bit). the bits are transferred from msb to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices then with draw from the bus a nd maintain an idle condition. during t he idle condition , the device monitors the sda and scl lines waiting for the start condition and the correct transmitted address. the r/w bit determines the direction of t he data. logic 0 on the lsb of the first byte indicate s that the master writes information to the peripheral. logic 1 on the lsb of the first byte indicate s that the master reads information from the peripheral. the adrf6755 acts as a standard slave device on the b us. the data on the sda pin (pin 29) is eight bits long , supporting the 7 - bit addresses plus the r/w bit. the adrf6755 has 34 subad dresses to enable the user - accessible internal registers. therefore, it interprets the first byte as the device address and the second byte as the starting subaddress. auto - increment mode is supported, which allows d ata to be read from or written to the starting sub - address and each sub s equent address without manually addressing the subsequent subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one - by - one basis without updating all regi sters. stop and start conditions can be detected at any stage of the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the id le condition. if an invalid subaddress is issu ed by the user, the adrf6755 does not issue an acknowledge and returns to the idle condition. in a no acknowledge condition, the sda line is not pulled low on the ninth pulse. see figure 64 and figure 65 for sample write and read data transfers , figure 66 for the timing protocol , and figure 2 for a more detailed timing diagram. figure 63 . slave address configuration 1 a5 0 0 0 0 0 x msb = 1 set b y pin 27 (cs) 0 = wr 1 = rd sla ve address[6:0] r/w ctr l 10465-063
adrf6755 data sheet rev. b | page 26 of 48 figure 64. i 2 c write data transfer figure 65. i 2 c read data transfer figure 66. i 2 c data transfer timing s slave addr, lsb = 0 (wr) a(s) a(s) a(s) data subaddr a(s) p data s = start bit p = stop bit a(s) = acknowledge by slave 10465-064 s s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a(m) = no acknowledge by master s slave addr, lsb = 0 (wr) slave addr, lsb = 1 (rd) a(s) a(s) subaddr a(s) data a(m) data p a(m) 10465-065 start bit s stop bi t p ack ack wr ack d0 d7 a0 a7 a5 a6 slave addr[4:0] slave address subaddress data subaddr[6:1] data[6:1] scl sda 10465-066
data sheet adrf6755 rev. b | page 27 of 48 spi interface the adrf6755 also supports the spi protocol. the part powers up in i 2 c mode but is not locked in this mode. to stay in i 2 c mode, it is recommended that the user tie the cs line to either 3.3 v or gnd, thus disabling spi mode. it is not possible to lock the i 2 c mode, but it is possible to select and lock the spi mode. to select and lock the spi mode, three pulses must be sent to the cs pin, as shown in figure 67. when the spi protocol is locked in, it cannot be unlocked while the device is still powered up. to reset the serial interface, the part must be powered down and powered up again. serial interface selection the cs pin controls selection of the i 2 c or spi interface. figure 67 shows the selection process that is required to lock the spi mode. to communicate with the part using the spi protocol, three pulses must be sent to the cs pin. on the third rising edge, the part selects and locks the spi protocol. consistent with most spi standards, the cs pin must be held low during all spi communication to the part and held high at all other times. spi serial interface functionality the spi serial interface of the adrf6755 consists of the cs, sdi (sdi/sda), clk (clk/scl), and sdo pins. cs is used to select the device when more than one device is connected to the serial clock and data lines. clk is used to clock data in and out of the part. the sdi pin is used to write to the registers. the sdo pin is a dedicated output for the read mode. the part operates in slave mode and requires an externally applied serial clock to the clk pin. the serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. figure 68 shows an example of a write operation to the adrf6755 . data is clocked into the registers on the rising edge of clk using a 24-bit write command. the first eight bits represent the write command, 0xd4; the next eight bits are the register address; and the final eight bits are the data to be written to the specific register. figure 69 shows an example of a read operation. in this example, a shortened 16-bit write command is first used to select the appropriate register for a read operation, the first eight bits representing the write command, 0xd4, and the final eight bits representing the specific register. then the cs line is pulsed low for a second time to retrieve data from the selected register using a 16-bit read command, the first eight bits representing the read command, 0xd5, and the final eight bits representing the contents of the register being read. figure 3 shows the timing for both spi read and spi write operations. figure 67. selecting the spi protocol spi locked on third rising edge spi framing edge c b a spi locked on third rising edge spi framing edge c b a cs (starting high) cs (starting low) 10465-067
adrf6755 data sheet rev. b | page 28 of 48 figure 68. spi byte write example figure 69. spi byte read example register address write command [0xd4] start cs clk sdi d7 d6 d5 d4 d3 d2 d1 d0 d0 d7 d6 d5 d4 d3 d2 d1 ? ? ? ? ? ? ? ? ? data byte stop cs (continued) clk (continued) sdi (continued) d7 d6 d5 d4 d3 d2 d1 d0 10465-068 register address write command [0xd4] start data byte read command [0xd5] start stop cs clk sdi cs clk sdi sdo d7 d6 d5 d4 d3 d2 d1 d0 d0 d7 d6 d5 d4 d3 d2 d1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 x xxxxxxx x xxxxxxx ? ? ? ? ? ? ? ? ? 10465-069
data sheet adrf6755 rev. b | page 29 of 48 program modes the adrf6755 has 34 8-bit registers to allow program control of a number of functions. either an spi or an i 2 c interface can be used to program the register set. for details about the interfaces and timing, see figure 63 to figure 69. the registers are documented in table 8 to table 28. several settings in the adrf6755 are double-buffered. these settings include the frac value, the int value, the 5-bit r-divider value, the reference frequency doubler, the r/2 divider, the rfdiv value, and the charge pump current setting. this means that two events must occur before the part uses a new value for any of the double-buffered settings. first, the new value is latched into the device by writing to the appropriate register. next, a new write must be performed on register cr0. when register cr0 is written, a new pll acquisition takes place. for example, updating the fractional value involves a write to register cr3, register cr2, register cr1, and register cr0. register cr3 should be written to first, followed by register cr2 and register cr1, and, finally, register cr0. the new acquisition begins after the write to register cr0. double buffering ensures that the bits written to do not take effect until after the write to register cr0. 12-bit integer value register cr7 and register cr6 program the integer value (int) of the feedback division factor (n); see equation 5 for details. the int value is a 12-bit number whose msbs are programmed through register cr7, bits[3:0]. the lsbs are programmed through register cr6, bits[7:0]. the lo frequency setting is described by equation 2. an alternative to this equation is provided by equation 4, which details how to set the n-divider value. note that these registers are double buffered. 25-bit fractional value register cr3 to register cr0 program the fractional value (frac) of the feedback division factor (n); see equation 5 for details. the frac value is a 25-bit number whose msb is programmed through register cr3, bit 0. the lsb is programmed through register cr0, bit 0. the lo frequency setting is described by equation 2. an alternative to this equation is described by equation 4, which details how to set the n-divider value. note that these registers are double buffered. rfdiv value the rfdiv value is dependent on the value of the lo frequency. the rfdiv value can be selected from the list in table 6. apply the selected rfdiv value to equation 4, together with the lo frequency and pfd frequency values, to calculate the correct n-divider value. reference input path the reference input path consists of a reference frequency doubler, a 5-bit reference divider, and a divide-by-2 function (see figure 53). the doubler is programmed through register cr10, bit 5. the 5-bit divider and divide-by-2 are enabled by programming register cr5, bit 4, and the division ratio is programmed through register cr10, bits[4:0]. the r/2 divider is programmed through register cr10, bit 6. note that these registers are double-buffered. charge pump current register cr9, bits[7:4], specify the charge pump current setting. with an r set value of 4.7 k, the maximum charge pump current is 5 ma. the following equation applies: i cpmax = 23.5/ r set the charge pump current has 16 settings from 312.5 a to 5 ma. for the loop filter that is specified in the application solution, a charge pump current of 5 ma (register cr9[7:4] = 0xf) gives a loop bandwidth of 100 khz, which is the recommended loop bandwidth setting. transmit disable control (txdis) the transmit disable control (txdis) is used to disable the rf out- put. txdis is normally held low. when asserted (brought high), it disables the rf output. register cr14 is used to control which circuit blocks are powered down when txdis is asserted. to meet both the off isolation power specifications and the turn-on/ turn-off settling time specifications, a value of 0x80 should be loaded into register cr14. this effectively ensures that the attenuator is always enabled when txdis is asserted, even if other circuitry is disabled. power-down/power-up control bits the four programmable power-up and power-down control bits are as follows: ? register cr12, bit 2. master power control bit for the pll, including the vco. this bit is normally set to a default value of 0 to power up the pll. ? register cr28, bit 4. controls the rfdivider. this bit is normally set to a default value of 0 to power up the rfdivider. ? register cr27, bit 2. controls the lo monitor outputs, lomon and lomon . the default is 0 when the monitor outputs are powered down. setting this bit to 1 powers up the monitor outputs to one of four options, ?6 dbm, ?12 dbm, ?18 dbm, or ?24 dbm, as controlled by register cr27, bits[1:0]. ? register cr29, bit 0. controls the quadrature modulator power. the default is 0, which powers down the modulator. write a 1 to this bit to power up the modulator.
adrf6755 data sheet rev. b | page 30 of 48 lock detect (ld et ) lock detect is enabled by setting register cr23, bit 4, to 1. the l ock d etect circuit is based on monitoring the up / down pulses from the pfd. as acquisition proceeds, the width of these pulses r educes until they are less than a target width (set by cr23[2]) . at this point , a count of the number of successive pfd cycles is initiated , where the width of the up / down pulses remai ns less that the target width. when this count reaches a target count (s et by cr13[6] and cr23[3]), ldet is set. the truth table for declaring ldet is given in table 7 . table 7 . declaring ldet ldcount1 cr13[6] ldcount0 cr23[3] number of pfd cycles to declare ldet 0 0 2048 0 1 3072 1 0 4096 1 1 16, 384 the appropriate setting to use depends on the pfd frequency as well as the desired accuracy when ldet is declared. the ldet setting does not affect th e acquisition time of the pll. it only affects the time at which ldet goes high . vco autocalibration the vco uses an autocalibration technique to select the correct vc o and band , as explained in the autocalibration section. register cr24 , bit 0 , controls whether the auto c alibration is enabled. for normal operation, autocalibration must be enabled. however, if using cumulative frequency steps of 100 k hz /2 rfdiv or less, autocalibration can be disabled by setting t his bit to 1 and then a new acquisition is initiated by writing to register cr0. attenuator the attenuator can be programmed from 0 db to 47 db in steps of 1 db. control is through r egister cr30 , bits [ 5 :0]. revision readback the revision of the silicon die can be read back via register cr33.
data sheet adrf6755 rev. b | page 31 of 48 r egister m ap register map summary table 8 . register map summary register address (hex) register name type descrip tion 0x00 cr0 read/write fractional word 4 0x01 cr1 read/write fractional word 3 0x02 cr2 read/write fractional word 2 0x03 cr3 read/write fractional word 1 0x04 cr4 read/write reserved 0x05 cr5 read/write 5 - bit r eference divider s enable 0x06 cr6 read/write integer word 2 0x07 cr7 read/write integer word 1 and muxout control 0x08 cr8 read/write reserved 0x09 cr9 read/write charge pump current setting 0x0a cr10 read/write reference frequency control 0x0b cr11 read/write reserved 0x0c cr12 read/write pll power - up 0x0d cr13 read/write lock detector control 2 0x0e cr14 read/write t xdis control 0x0f cr15 read/write reserved 0x10 cr16 read/write reserved 0x11 cr17 read/write reserved 0x12 cr18 read/write reserved 0x13 cr19 read/write reserved 0x14 cr20 read/write reserved 0x15 cr21 read/write reserved 0x16 cr22 read/write reserved 0x17 cr23 read/write lock d etector c ontrol 1 0x18 cr24 read/write autocalibration 0x19 cr25 read/write autocalibration timer 0x1a cr26 read/write reserved 0x1b cr27 read/write lo monitor output and lo selection 0x1c cr28 read/write lo selection 0x1d cr29 read/write modulator 0x1e cr30 read/write attenuator 0x1f cr31 read only reserved 0x20 cr32 read only reserved 0x21 cr33 read only re vision code
adrf6755 data sheet rev. b | page 32 of 48 register bit descrip tions table 9 . register cr0 (address 0x00), fractional word 4 bit description 1 7 fraction al word f7 6 fractional word f6 5 fractional word f5 4 fractional word f4 3 fractional word f3 2 fractional word f2 1 fractional word f1 0 fractional word f0 (lsb) 1 double - buffered. loaded on a write to register cr0. table 10 . register cr1 (address 0x01), fractional word 3 bit description 1 7 fractional word f15 6 fractional word f14 5 fractional word f13 4 fractional word f12 3 fractional word f11 2 fractional word f10 1 fractional word f9 0 fractional word f8 1 double - buffered. loaded on a write to register cr0. table 11 . register cr2 (address 0x02), fractional word 2 bit description 1 7 fractional word f23 6 fractional word f22 5 fractional word f21 4 fractional word f20 3 fractional word f19 2 fractional word f18 1 fractional word f17 0 fractional word f16 1 double - buffered. loaded on a write to register cr0. table 12. register cr3 (address 0x03), fractional word 1 bit description 7 set to 0 6 set to 0 5 set to 0 4 set to 0 3 set to 0 2 set to 1 1 set to 0 0 fractional word f24 (msb) 1 1 double - buffered. loaded on a write to register cr0. table 13 . register cr5 (address 0x05), 5 - bit reference divider enable bit description 7 set to 0 6 set to 0 5 set to 0 4 5 - bit r - divider and divide -by -2 enable 1 0 = disable 5 -b it r - divider and divide -by -2 (default) 1 = enable 5 -b it r - divider and divide -by -2 3 set to 0 2 set to 0 1 set to 0 0 set to 0 1 double - buffered. loaded on a write to register cr0. table 14 . register cr6 (address 0x06), integer word 2 bit description 1 7 integer word n7 6 integer word n6 5 integer word n5 4 integer word n4 3 integer word n3 2 integer word n2 1 integer word n1 0 integer word n0 1 double - buffered. loaded on a write to register cr0. table 15 . register cr7 (address 0x07), integer word 1 and muxout control bit description [7:4] muxout control 0000 = tristate 0001 = logic high 0010 = logic low 1101 = r eference clock /2 1110 = rf fractional -n divider clock /2 3 integer word n11 1 2 integer word n10 1 1 integer word n9 1 0 integer word n8 1 1 double - buffered. loaded on a write to register cr0.
data sheet adrf6755 rev. b | page 33 of 48 table 16 . register cr9 (address 0x09), charge pump current setting bit description [7:4] charge pump current 1 0000 = 0.31 25 ma (default) 0001 = 0.63 ma 0010 = 0.94 ma 0011 = 1.25 ma 0100 = 1.57 ma 0101 = 1.88 ma 0110 = 2.19 ma 0111 = 2.50 ma 1000 = 2.81 ma 1001 = 3.13 ma 1010 = 3.44 ma 1011 = 3.75 ma 1100 = 4.06 ma 1101 = 4.38 ma 1110 = 4.69 ma 1111 = 5.00 ma 3 set to 0 2 set to 0 1 set to 0 0 set to 0 1 double - buffered. loaded on a write to register cr0. table 17 . register cr10 (address 0x0a), reference frequency control bit description 7 set to 0 1 6 r/2 divider setting 1 0 = bypass r/2 divider (default) 1 = select r/2 divider 5 reference frequency doubler ( r - doubler ) enable 1 0 = disable doubler (default) 1 = enable doubler [4:0] 5 - bit r - divider setting 1 00000 = divide by 32 (default) 00001 = divide by 1 00010 = divide by 2 11110 = d ivide by 30 11111 = divide by 31 1 double - buffered. loaded on a write to register cr0. table 18 . register cr12 (address 0x0c), pll power -up bit description 7 set to 0 6 set to 0 5 set to 0 4 set to 1 3 set to 1 2 power down pll 0 = power up pll (default) 1 = power down pll 1 set to 0 0 set to 0 table 19 . register cr13 (address 0x0d) , lock detector control 2 bit description 7 set to 1 6 ldcount1 (s ee table 7 ) 5 set to 1 4 set to 0 3 set to 1 2 set to 0 1 set to 0 0 set to 0 table 20 . register cr1 4 (address 0x0e), t x d is control bit description 7 txdis _ lo clk 0 = lo clock always running 1 = s top lo clock when txdis = 1 6 set to 0 5 set to 0 4 set to 0 3 set to 0 2 set to 0 1 set to 0 0 set to 0 table 21 . register cr23 (address 0x17), lock detector control 1 bit description 7 set to 0 6 set to 1 5 set to 1 4 lock detector enable 0 = lock detector disabled (default) 1 = lock detector enabled 3 lock detector up/down count , ldcount0 (see table 7 ) 2 lock detector precision 0 = l ow, coarse (10 ns) 1 = h igh, fine (6 ns) 1 set to 0 0 set to 0
adrf6755 data sheet rev. b | page 34 of 48 table 22 . register cr24 (address 0x18), autocalibration bit description 7 set to 0 6 set to 0 5 set to 0 4 set to 1 3 set to 1 2 set to 0 1 set to 0 0 disable autocalibration 0 = enable autocalibration (default) 1 = disable autocalibration table 23 . register cr25 (address 0x19), autocalibration timer bit description [7:0] autocalibration timer t able 24 . register cr27 (a ddress 0x1b), lo monitor output and lo selection bit description 7 set to 0 6 set to 0 5 set to 0 4 frequency r ange ; s et according to table 6 3 set to 0 2 power up lo monitor output 0 = power down (default) 1 = power up [1:0] monitor output power into 50 00 = ?24 dbm (default) 01 = ?18 dbm 10 = ?12 dbm 11 = ?6 dbm table 25 . register cr28 (address 0x1c), lo selection bit description 7 set to 0 6 set to 0 5 set to 0 4 power d own rfdivider 0 = power up (default) 1 = power down 3 set to 1 [2: 0 ] rfdiv 1 , s et according to table 6 1 double - buffered. loaded on a write to register cr0. table 26 . register cr29 (address 0x1d), modulator bit description 7 set to 1 6 set to 0 5 set to 0 4 set to 0 3 set to 0 2 set to 0 1 set to 0 0 power up modulator 0 = power down (default) 1 = power up table 27 . register cr30 (address 0x1e), attenuator bit description 7 set to 0 6 set to 0 [5 :0] attenuator a5 to attenuator a0 00000 0 = 0 db 0000 0 1 = 1 db 000 0 10 = 2 db 011111 = 31 db 110000 = 32 db 110001 = 33 db 111101 = 45 db 111110 = 46 db 1 11111 = 47 db table 28 . register cr33 (address 0x21), revision code 1 bit description [ 7 :0] revision code 1 read - only register.
data sheet adrf6755 rev. b | page 35 of 48 s uggested power - up sequence i nitial register writ e s equence after applying power to the part, perform the initial register write sequence that follows . n ote that register cr33, register cr 32, and register cr 31 are read - only reg isters. also , note that all writ able register s should be written to on power - up. refer to the register map section for more details on all registers. 1. w rite 0x00 to register cr30. set the attenuator to 0 db gain. 2. w rite 0x80 to register cr29 . the m odulator is powered do wn. the modulator is powered down by default to ensure that no spurious signals can occur on the rf output when the pll is car rying out it s first acquisition. the modulator should be powered up only when the pll is locked. 3. write 0x0x to register cr28 . rfdiv depends on the value of the lo frequency to be used and is set according to table 6 . note that register cr28, bit 3, is set to 1. 4. w rite 0xx0 to register cr27 . bit 4 depends on the lo frequency to be used and is set ac cording to table 6 . 5. write 0x00 to register cr26. reserved register. 6. w rite 0x64 to register cr25 , the a utocalibration t imer . this setting applies for pfd = 40 mhz. for other pfds, refer to equation 3 in the vco autocalibration section. 7. w rite 0x18 to register cr24 . enable autocal ibration . 8. w rite 0x70 to register cr23 . enable the lock detector and choose the recommended lock detect timing . this setting applies to pfd = 40 mhz. for other pfds, refer to the lock detect (ldet) section in the program modes section . 9. w rite 0x80 to register cr22 . reserved register. 10. w rite 0x00 to re gister cr21 . reserved register. 11. write 0x00 to register cr20 . reserved register. 12. write 0x80 to register cr19 . reserved register. 13. write 0x 6 0 to register cr18 . reserved register. 14. write 0x00 to register cr17 . reserved register. 15. write 0x00 to register cr16 . reserved register. 16. write 0x00 to register cr15 . reserved register. 17. write 0x80 to register cr14 . stop lo when txdis = 1 . 18. write 0xe8 to register cr13 . this setting applies to pfd = 40 mhz. for other pfds, refer to the lock detect (ldet ) section in the program modes section . 19. write 0x18 to register cr12 . power up the pll. 20. write 0x00 to register cr11 . reserved register. 21. write to register cr10 . r efer to the reference input path section , in particular equation 1 . 22. write 0xf0 to register cr9 . with the recommended loop filter component values and r set = 4. 7 k? , as shown in figure 70 , the charge pump current is set to 5 ma for a loop bandwidth of 10 0 khz. 23. write 0x00 to register cr8. reserved r egister. 24. write 0x0x to register cr7 . set according to equation 2 in the theory of operation section. also, set the muxout pin to tristate. 25. write 0xxx to register cr6 . set according to e quation 2 in the theory of operation section. 26. write to register cr5 . refer to the reference input path section , in particular equation 1 . 27. write 0x01 to register cr4 . reserved register. 28. write 0000010x b inary to register cr3 . set according to equation 2 in the theory of operation section. 29. write 0xxx to register cr2 . set according to equation 2 in the theory of operation section. 30. write 0xxx to register cr1 . set according to equation 2 in the theory of operation section. 31. write 0xxx to register cr0 . set according to equation 2 in the theory of operation section. register cr0 must be the l ast register written for all the double - buffered bit writes to take effect. 32. write to register cr27 , setting bit 4 according to table 6 . 33. monitor the ldet output or wait 170 s to ensure that the pll is locked. 34. write 0x81 to register cr29 . power up the modulator. the write to register cr29 do es not need to be followed by a write to register cr0 because this register is not double - buffered . e xample changing the lo frequency following is an example of how to change the lo frequency after the initialization sequence. using an example in which the pll is locked to 2000 m hz, the following conditions apply: ? f pfd = 4 0 mhz (assumed) ? divide ratio n = 5 0 ; therefore, int = 5 0 decimal and frac = 0 ? rf di vider = divide - by - 1. see table 6 . register cr28[2:0] = 000 register cr27[4] = 1 the int registers contain the following values: register cr 7 = 0x00 and register cr6 = 0x 32 the frac registers contain the following values: register cr3 = 0x0 4 , register cr 2 = 0 x 00, register cr1 = 0x00, and register cr0 = 0x00
adrf6755 data sheet rev. b | page 36 of 48 to ch ange the lo frequency to 9 25 m hz , ? f pfd = 4 0 mhz (assumed) ? divide ratio n = 46.25 ; therefore , int = 46 decima l and frac = 8,388,608 ? rfdi vider = divide - by - 2. see table 6 . register cr28[2:0] = 001 register cr27[ 4 ] = 0 t he int registers contain the following values : register cr 7 = 0x00 and register cr6 = 0x 2e t he frac registers contain the following value s: register cr3 = 0x04, register cr2 = 0x8 0 , register cr1 = 0x00, and register cr0 = 0x00 note that register cr 27 should be the last write in this sequence , preceded by cr0 . writing to register cr0 causes all double - buffered registers to be updated, including the int , frac , and rfdiv registers, and starts a new pll acquisition.
data sheet adrf6755 rev. b | page 37 of 48 evaluation board g eneral descript ion the e va l - adrf6755sd z evaluation board is designed to allow the user to evaluate the performance of the adrf6755 . it contains the following: ? i / q modulator with integrated f ractional - n pll and vco ? connector to interface to a standard usb interface board (spd - s) that must be ordered with the e va l - adrf6755sd z board. ? dc biasing and filter circuitry for the baseband inpu ts ? low - pass loop filter circuitry ? an 8 0 mhz reference clock ? circuitry to monitor the lomon outputs ? sma connectors for power supplies and the rf output the evaluation board is supplied with the associated driver software to allow easy programming of the adrf6755 . h ardware description for more information, refer to the circuit diagram in figure 70. power supplies an external 5 v supply, d ut +5 v (j14) , drives both an on - chip 3.3 v regulator and the quadrature modulator. the regulator feeds the vreg 1 through vreg6 pins on the chip with 3.3 v. these pins power the pll circuitry. the external reference cloc k generator should be driven by a 3 .3 v supply. this supply should be connected via an sma connector , osc +v (j15) . recommended decoupling for supplies the externa l dut + 5 v supply is decoupled initially by a 10 f capacitor and then further by a parallel combination of 100 nf and 10 pf capacitors that are placed as close to the dut as possible for good local decoupling. the regulator output should be decoupled by a parallel combination of 10 pf and 220 f capacitors . the 220 f capacitor decouples broadband noise , which leads to better phase noise and is recommended for best performance. case s ize c 220 f capacitors ar e used to minimize area. place a parallel combination of 100 nf and 10 pf capacitors on each vreg x pin , as close to the pins as possible. the impedance of these capacitors should be low and constant across a broad frequ ency range. surface - mount multilayered ceramic chip (mlcc) c lass ii capacitors provide very low esl and esr , which assist in decoupling supply noise effectively. they also provide good temperature stability a nd good ag ing characteristics. capacitance also changes v s. applied bias voltage. larger case sizes have less capacitance change vs. applied bias voltage and have lower esr but higher esl. the 0603 size capacitors provide a good compromise. x5r and x7r capacitors are examples of these types of capacitors and are recommended for decoupling. spi interface the spi interface is provided by an additional spd - s board. this m ust be ordered with the adrf6755 evaluation board. the s ystem d emonstration p latform (sdp) is a hardware and software platform that provides a means to communicate from the pc to analog devices products and systems that require digital control and/or readback (see figure 71) . the sdp - s controller board connect s to the pc via usb 2.0 and to the adrf6755 evaluation b oard via a sm all footprint , 120 - pin connector . th e sdp - s ( s erial only interface ) is a low cost, small form factor, sdp controller board. baseband inputs the pair of i and q baseband inputs are served by sma inputs (j2 to j5) so that they can be driven directly from an external generator or a dac board , both of which can also provide t he dc bias required. the re is also an option to filter the baseband inputs , although filtering may not be required , depending on the quality of the baseband source. loop filter a fourth - order loop filter is provided at the output of the charge pump and is required to adequately filter noise from the - modulator used in the n - divider. with the c harge pump current set to a v alue of 5 ma and using the on - chip vco, the loop bandwidth is approximately 10 0 khz , and the phase margin is 55 . c 0 g capacitors are re commend ed for use in the loop filter because they have low dielectric absorption , which is required for fast and accurat e settling time. the use of non - c0g capacitors may result in a long tail being introduced into the settling time transient. reference input the reference input can be supplied by a n 80 mhz jauch clock generator or by an external clock through the use of connector refin ( j7 ) . the frequency range of the pfd input is from 10 mhz to 4 0 mhz ; if the 80 mhz clock generator is used, the on - chip 5 - bit reference frequency divider or the divide - by - 2 divider s hould be used to set the pfd frequen cy to 4 0 mhz to optimiz e phase noise performance. lomon outputs these pins are differential lo monitor outputs that provide a replica of the internal lo frequency at 1 lo. the single - ended power in a 50 ? load can be programmed to ? 24 dbm, ? 18 dbm, ? 12 dbm , or ? 6 dbm. these open - collector outputs must be terminated to 3.3 v. b e c a u s e both outputs must be terminated to 50 ? , options a re provided to terminate to 3.3 v using on - board 50 ? resistors or by series inductors (or a ferrite bead) , in which case the 50 ? termination is provided by the measuring instrument. if not used, these outputs should be tied to regout .
adrf6755 data sheet rev. b | page 38 of 48 ccomp x pins the ccomp x pins are internal compensation nodes that must be decoupled to ground with a 100 nf capacitor. muxout muxout is a test output that all ows different internal nodes to be monitored. it is a cmos output stage that requires no terminati on . lock detect ( ldet ) lock detect is a cmos output that indicates the state of the pll. a high level indicates a locked condition , and a low level indicates a loss of lock condition. txdis this input disables the rf output. it can be driven from an external stimulus or simply connected high or low by j umper j18. rf output (rfout) rfout (j12) is the rf output of the adrf6755 .
data sheet adrf6755 rev. b | page 39 of 48 figure 70 . applications circuit schematic 10465-071
adrf6755 data sheet rev. b | page 40 of 48 figure 71 . applications circuit schematic sdp - s 10465-078
data sheet adrf6755 rev. b | page 41 of 48 pcb a rtwork component placement figure 72 . evaluation board, top side component placement figure 73 . evaluation board, bottom side component placement 10465-072 10465-073
adrf6755 data sheet rev. b | page 42 of 48 pcb layer information figure 74. evaluation bo ard, top sidelayer 1 figure 75. evaluation board, bottom sidelayer 4 10465-074 10465-075
data sheet adrf6755 rev. b | page 43 of 48 figure 76. evaluation board, groundlayer 2 figure 77. evaluation board powerlayer 3 10465-076 10465-077
adrf6755 data sheet rev. b | page 44 of 48 bill of materials table 29 . bill o f materials qty reference designator description manufacturer part number 1 dut adrf6755 , 56 - lead 8 mm 8 mm lfcsp analog devices adrf 6755 acpz 1 y2 crystal oscillator, 80 mhz jauch o 80.0 - jo75-b - 3.3-2 -t1 1 conn 1 connector, fx8 -120s - sv(21) hirose fec 1324660 2 c1, c21 capacitor, 10 f, 25 v, tantalum, taj - c avx fec 197518 1 2 c4, c6, c8, c1 0, c12, c14, c16, c18, c19, c48, c53, c55 capacitor, 10 pf, 50 v, ceramic, c0g, 0402 murata fec 8819564 1 4 c5, c7, c9, c11, c13, c15, c17, c22 , c47, c49 to c52, c54 capacitor, 100 nf, 25 v, x7r, ceramic, 0603 avx fec 317287 1 c20 capacitor, 220 f, 6.3 v, tantalum, case size c avx fec 197087 4 c30 to c33 capacitor spacing , 0402 (do not install) 1 c26 capacitor, 1 .2 n f, 50 v, c 0 g , ceramic, 0603 kemet fec 1813421 1 c24 capacitor, 47 nf, 50 v, c 0 g , ceramic, 1206 murata fec 8820201 2 c 23, c25 capacitor, 560 pf, 50 v, np 0 , ceramic, 0603 murata fec 1828912 2 c38, c39 capacitor, 1 nf, 50 v, c0g, ceramic, 0402 murata fec 8819556 3 c44 , c46, c57 capacitor, 100 pf, 50 v, c0g, ceramic, 0402 murata fec 8819572 1 1 j2 to j 5 , j7, j10 to j12 , j14, j15, txdis sma end launch connector johnson/emerson 142 - 0701 - 851 2 j18, j21 jumper, 3 - pin + shunt harwin fec 148533 and fec 150411 2 l1, l2 i nductor, 20 nh, 0402, 5% te connectivity fec 1265424 2 l3, l4 inductor, 10 h, 0805, lqm series vishay fec 1653752 5 r6 to r9, r36 resistor, 0 , 1/16 w, 1%, 0402 multicomp fec 1357983 2 r10, r11 resistor, 0402, spacing (do not install) 1 r13 resistor, 4.7 k , 1/10 w, 1%, 0603 bourns fec 2008358 2 r12, r1 6 resistor, 160 , 1/16 w, 1%, 0603 multicomp fec 9330 658 1 r15 resistor, 15 0 , 1/16 w, 1%, 0603 multicomp fec 933 0593 2 r62 resistor, 0603, spacing (do not install) 3 r35, r44, r45 resistor, 51 , 1/16 w, 5%, 0402 bourns fec 2008358 4 r48 to r51 resistor, 330 , 1/10 w, 5%, 0805 vishay fec 1739223 3 r59 to r6 1 resistor, 100 , 1/10 w, 5%, 0805 vishay fec 1652907 2 r63, r64 resistor, 100 k, 1/16 w, 1%, 0603 multicomp fec 9330402 1 d1 led , r ed , 0805, 1.8 v , l ow c urrent rohm fec 1685056 1 u1 ic 24lc32a - i/ms eeprom msop-8 microchip fec 133 - 4660
data sheet adrf6755 rev. b | page 45 of 48 outline dimensions figure 78. 56-lead lead frame chip scale package [lfcsp_vq] 8 mm 8 mm body, very thin quad (cp-56-4) dimensions shown in millimeters ordering guide model 1, 2 temperature range package description package option ADRF6755ACPZ ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq], tray cp-56-4 ADRF6755ACPZ-r7 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq], 7" tape and reel cp-56-4 eval-adrf6755sdz evaluation board eval-sdp-cs1z sdp-s controller board; interface to eval-adrf6755sdz (also required) eval-sdp-cb1z sdp-b controller board; interf ace to eval-adrf6755sdz (alternative solution) 1 z = rohs compliant part. 2 choose either eval-sdp-cs1z or eval-sdp-cb1z as eval-adrf6755sdz interface solution. compliant to jedec standards mo-220-vlld-2 top view side view 1 56 14 15 43 42 28 29 0.50 0.40 0.30 0.30 0.23 0.18 0.20 ref 12 max 1.00 0.85 0.80 6.50 ref seating plane 0.60 max 0.60 max coplanarity 0.08 0.05 max 0.02 nom 0.20 min for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. pin 1 indicator 8.10 8.00 sq 7.90 7.85 7.75 sq 7.65 0.50 bsc bottom view exposed pad p i n 1 i n d i c a t o r 06-11-2012-a 0.80 max 0.65 typ 6.65 6.50 sq 6.35
adrf6755 data sheet rev. b | page 46 of 48 notes
data sheet adrf6755 rev. b | page 47 of 48 notes
adrf6755 data sheet rev. b | page 48 of 48 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2012C2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10465-0-4/13(b)

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