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march 1998 1/80 this is preliminary information ona new product in development orundergoing evaluation. details are subject to change without notice. r rev. 1.1 st72272 8-bit mcus with 8 to 16k rom/otp/eprom, 384 to 512 bytes ram, adc, dac (pwm), timer and i 2 c product preview n user program memory rom/otp/eprom: 8 to 16k bytes n data ram: 384 to 512 bytes (256 bytes stack) n master reset and power-on reset n run, wait, slow, halt and ram retention modes n 18 i/o lines: 1 programmable interrupt input 5 high sink outputs 4 analog alternate inputs 8 alternate functions emi filtering n programmable watchdog (wdg) n 16-bit timer with 2 input capture and 2 output compare functions (with 1 output pin) n 8-bit analog to digital converter with 4 channels n four 10-bit digital to analog converter channels with pwm output n fast i 2 c multi master interface n 63 basic instructions and 17 main address modes n 8x8 unsigned multiply instruction n true bit manipulation n versatile development tools (dos and windows) including assembler, linker, c-compiler, archiver, source level debugger, and hardware emulator device summary features st72272k2 st72272k4 program memory - bytes 8k 16k ram (stack) - bytes 384 (256) 512 (256) 10-bit d/a converter 4 channels a/d converter 4 channels 16-bit timer 1 i 2 c bus 1 multimaster i/os 24 operating supply 4.0 to 5.5 v cpu frequency 8 mhz max (24 mhz quartz) temperature range 0 cto+70 c package so34 - sdip32 pso34 psdip32 csdip32 1
2/80 table of contents 80 st72272 . ...........................................1 1 general description . . ....................................................4 1.1 introduction . . . . . . . ..................................................4 1.2 pin description . . . . . . . ................................................5 1.3 memorymap ..........................................................7 2 central processing unit . . . ..............................................10 2.1 introduction . . . . . . . .................................................10 2.2 mainfeatures .......................................................10 2.3 cpu registers .......................................................10 3 clocks, reset, interrupts & power saving modes . . . . . . . .................13 3.1 clocksystem........................................................13 3.1.1 general description . . . ..............................................13 3.1.2 external clock . . ...................................................13 3.2 reset ................................................................14 3.2.1 introduction .......................................................14 3.2.2 external reset . . . . . . . ..............................................14 3.2.3 reset operation . . . . . . . . . . . . . . . .....................................14 3.2.4 power-on reset . . . . . . . . . . . . . . . .....................................14 3.3 interrupts . .........................................................16 3.4 power saving modes . . . ..............................................19 3.4.1 introduction .......................................................19 3.4.2 slowmode ........................................................19 3.4.3 waitmode ........................................................19 3.4.4 haltmode.........................................................20 3.5 register description . . . . . . . .........................................21 4 on-chip peripherals ......................................................22 4.1 i/oports.............................................................22 4.1.1 introduction .......................................................22 4.1.2 functional description ...............................................22 4.1.3 register description . . . ..............................................26 4.2 watchdog timer (wdg) . . . . . . . . . . . . . ..................................28 4.2.1 introduction .......................................................28 4.2.2 main features . . ...................................................28 4.2.3 functional description ...............................................29 4.2.4 register description . . . ..............................................29 4.3 16-bit timer . .........................................................30 4.3.1 introduction .......................................................30 4.3.2 main features . . ...................................................30 4.3.3 functional description ...............................................30 4.3.4 register description . . . ..............................................40 4.4 i2c bus interface (i2c) . . . . . . . .........................................45 4.4.1 introduction .......................................................45 4.4.2 main features . . ...................................................45 4.4.3 general description . . . ..............................................45 4.4.4 functional description ...............................................47 2
3/80 table of contents 4.4.5 register description . . . ..............................................50 4.5 pwm/brm generator (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................55 4.5.1 introduction .......................................................55 4.5.2 main features . . ...................................................55 4.5.3 functional description ...............................................55 4.5.4 register description . . . ..............................................59 4.6 8-bit a/d converter (adc) . . . ..........................................61 4.6.1 introduction .......................................................61 4.6.2 main features . . ...................................................61 4.6.3 functional description ...............................................62 4.6.4 register description . . . ..............................................63 5 instruction set . .........................................................64 5.1 st7 addressing modes . . . . . . . . . . . . . ..................................64 5.1.1 inherent . .........................................................65 5.1.2 immediate . . . . . . . .................................................65 5.1.3 direct ............................................................65 5.1.4 indexed (no offset, short, long) . . .....................................65 5.1.5 indirect (short, long) . . . . . . . .........................................65 5.1.6 indirect indexed (short, long) . . . . . . . . . . . ..............................66 5.1.7 relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . .....................66 5.2 instruction groups .................................................67 6 electrical characteristics . . . . ..........................................70 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . .........................70 6.2 recommended operating conditions. . . . .............................71 6.3 dc electrical characteristics . . ....................................72 6.4 a/d converter characteristics ......................................72 6.5 pwm (dac) characteristics . . . . . . . . . . . . . . . . . . .........................73 6.6 i2c characteristics . . . . . . . . ..........................................73 7 general information . . . . . . . ..............................................75 7.1 eprom erasure . . . . . . . ...............................................75 7.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................76 7.3 ordering information . . . . . . . . . . . . . ..................................78 7.3.1 transfer of customer code . . . . . . . . . . . . . . . . . . .........................78 3
4/80 st72272 1 general description 1.1 introduction the st72272 series is a hcmos microcontroller unit (mcu) from the st7 family with a dedicated d/a converter peripherals offering 4 pwm outputs. it is based around an industry standard 8-bit core and offers an enhanced instruction set. the processor runs with an external clock up to 24 mhz with a 5.5v supply. due to the fully static design of this device, operation down to dc is possible. under software control the st72272 can be placed in wait, slow or halt mode thus reducing power consumption. the enhanced instruction set and addressing modes afford real programming potential. in addition to standard 8-bit data management the st7 features true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes on the whole memory. the device includes an on-chip oscillator, cpu, 8 to 16 kbytes rom/otp/eprom, 384 to 512 bytes ram, 18 i/o lines, a timer with 2 input captures and 2 output compares, a 4-channel a/d converter, an i 2 c multi master, a watchdog reset and a 4-channel 10-bit d/a converter with pwm output. figure 1. st72272 block diagram address and data bus v ss oscin oscout reset adc port c i 2 c port d timer dac (pwm) internal clock v dd program (384 to 512 bytes) ram port b port a pa4-pa7 pb0-pb2 pc0 pc2-pc6 pd0-pd2 pd6 power supply 8-bit core alu control da1-da4 watchdog osc mode selection :3 (8k to 16k bytes) icap2 icap1 memory pb7 (4 bits) (4 bits) (6 bits) (4 bits) 4
5/80 st72272 1.2 pin description figure 2. 34-pin so package pinout figure 3. 32-pin sdip package pinout note : several pins of the i/o ports assume software programmable alternate functions as shown in the pin description. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 18 19 20 da1 da2 da3 da4 nu ain3/pb7 ain2/pb2 nu v ss v dd 28 27 26 25 24 23 22 21 nc ain1/pb1 ain0/pb0 icap1 (1) v pp on eprom/otp only 15 16 17 29 30 31 32 33 34 pd6 pd2 pd1 test/v pp (1) reset pa4 pa5 pa6 pc6 pc5/sdai pc4/scli pc3 pc2 pa7 oscin oscout nc pc0/ocmp icap2 pd0 (ei0) da1 da2 da3 da4 nu nu v ss v dd 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ain3/pb7 ain2/pb2 ain1/pb1 ain0/pb0 icap1 pd6 pd2 pd1 test/v pp (1) reset pa4 pa5 pa6 pc6 pc5/sdai pc4/scli pc3 pc2 pa7 oscin oscout pc0/ocmp icap2 pd0 (1) v pp on eprom/otp only (ei0) 5
6/80 st72272 pin description (cont'd) table 1. 34-pin so and 32-pin sdip package pin description note: s= supply pin n so34 pin n sdip32 pin name type description remarks 1 1 da1 o 10-bit d/a (pwm output) for analog controls, after external filtering 2 2 da2 o 10-bit d/a (pwm output) 3 3 da3 o 10-bit d/a (pwm output) 4 4 da4 o 10-bit d/a (pwm output) 5 5 nu non user pin. must be left unconnected 6 6 nu non user pin. must be left unconnected 77v ss s ground 88v dd s main power supply 9 nc not connected 10 9 pb7/ain3 i/o port b7 or adc analog input 3 11 10 pb2/ain2 i/o port b6 or adc analog input 2 12 11 pb1/ain1 i/o port b5 or adc analog input 1 13 12 pb0/ain0 i/o port b4 or adc analog input 0 14 13 icap1 timer input capture 1 not for general purpose i/o 15 14 pd6 i/o port d6 16 15 pd2 i/o port d2 17 16 pd1 i/o port d1 18 17 pd0 i/o port d0 external interrupt: ei0 19 18 icap2 timer input capture 2 with 256 prescaler not for general purpose i/o 20 19 pc0/ocmp i/o port c0 or timer output compare 21 20 pc2 i/o port c2 22 21 pc3 i/o port c3 23 22 pc4/scli i/o port c4 or i 2 c serial clock 24 23 pc5/sdai i/o port c5 or i 2 c serial data 25 24 pc6 i/o port c6 high current 26 nc not connected 27 25 oscout o input/output oscillator pin. these pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator. 28 26 oscin i 29 27 pa7 i/o port a7 high current 30 28 pa6 i/o port a6 high current 31 29 pa5 i/o port a5 high current 32 30 pa4 i/o port a4 high current 33 31 reset i/o bidirectional. active low. top priority non maskable interrupt. it can be used to reset exter- nal peripherals. 34 32 v pp /test s test mode pin. in eprom devices acts as programming voltage input v pp . this pin should be tied low in user mode 6
7/80 st72272 1.3 memory map figure 4. program memory map table 2. interrupt vector map vector address description remarks ffe0-ffe1h ffe2-ffe3h ffe4-ffe5h ffe6-ffe7h ffe8-ffe9h ffea-ffebh ffec-ffedh ffee-ffef h fff0-fff1h fff2-fff3h fff4-fff5h fff6-fff7h fff8-fff9h fffa-fffbh fffc-fffdh fffe-ffffh reserved reserved i 2 c interrupt vector timer overflow interrupt vector timer output compare interrupt vector timer input capture interrupt vector reserved reserved ei0 interrupt vector reserved reserved reserved reserved reserved trap interrupt vector reset vector internal interrupts a a a external interrupt software interrupt cpu interrupt 0000h 512 bytes ram interrupt & reset vectors hw registers 0080h 007fh reserved (see table 3) c000h ffe0h ffffh (see table 2) 16k bytes bfffh rom/ot p/eprom short addressing ram (zero page) 16-bit addressing ram 0080h 027fh 00ffh 0100h 01ffh 0200h short addressing ram (zero page) 0080h 00ffh 01ffh 384 bytes ram 027fh 0280h 01ffh ffdfh 8k bytes e000h rom 256 bytes stack / 16-bit addressing ram 256 bytes stack / 16-bit addressing ram 7
8/80 st72272 memory map (cont'd) table 3. hardware register memory map address block register label register name reset status remarks 0000h 0001h port a padr paddr port a data register port a data direction register 00h 00h r/w r/w 0002h 0003h port c pcdr pcddr port c data register port c data direction register 00h 00h r/w r/w 0004h 0005h port d pddr pdddr port d data register port d data direction register 00h 00h r/w r/w 0006h 0007h 0008h port b pbdr pbddr pbicfgr port b data register port b data direction register port b input pull-up configuration register 00h 00h 00h r/w r/w r/w 0009h miscr miscellaneous register 00h r/w 000ah 000bh adc adcdr adccsr adc data register adc control status register 00h 00h read only r/w 000ch wdg wdgcr watchdog control register 7fh r/w 000dh 000fh reserved area (3 bytes) 00010h itr itrfre interrupt register 00h r/w 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh tim timcr2 timcr1 timsr timic1hr timic1lr timoc1hr timoc1lr timchr timclr timachr timaclr timic2hr timic2lr timoc2hr timoc2lr timer control register 2 timer control register 1 timer status register timer input capture 1 high register timer input capture 1 low register timer output compare 1 high register timer output compare 1 low register timer counter high register timer counter low register timer alternate counter high register timer alternate counter low register timer input capture 2 high register timer input capture 2 low register timer output compare 2 high register timer output compare 2 low register 00h 00h 00h xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0020h 0023h reserved area (4 bytes) 0024h 0025h 0026h 0027h 0028h 0029h pwm1 brm21 pwm2 pwm3 brm43 pwm4 10 bit pwm / brm register 80h 00h 80h 80h 00h 80h r/w r/w r/w r/w r/w r/w 002ah to 0042h reserved area (25 bytes) 0043h tim icap pin configuration warning : write 0ch in this register to use the icap1 and icap2 functions. 08h r/w 8
9/80 st72272 0044h 0058h reserved area (21 bytes) 0059h 005ah 005bh 005ch 005dh 005eh 005fh i 2 c i2cdr i2coar i2cccr i2csr2 i2csr1 i2ccr i 2 c data register reserved i 2 c (7 bits) slave address register i 2 c clock control register i 2 c status register 2 i 2 c status register 1 i 2 c control register 00h 00h 00h 00h 00h 00h r/w r/w r/w read only read only r/w 0060h to 007fh reserved area (32 bytes) address block register label register name reset status remarks
10/80 st72272 2 central processing unit 2.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 main features n enable executing 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes (with indirect addressing mode) n two 8-bit index registers n 16-bit stack pointer n 8 mhz cpu internal frequency n low power modes n maskable hardware interrupts n non-maskable software interrupt 2.3 cpu registers the 6 cpu registers shown in figure 5 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 5. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 87 0 reset value = stack higher address reset value = 10 11x101 reset value = xxh reset value = xxh reset value = xxh x = undefined value
11/80 st72272 central processing unit (cont'd) condition code register (cc) read/write reset value: 111x1010 the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask . this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptable because the i bit is set by hardware when you en- ter it and reset by the iret instruction at the end of the interrupt routine. if the i bit is cleared by soft- ware in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the abit test and brancho, shift and rotate instructions. 70 111hi nzc
12/80 st72272 central processing unit (cont'd) stack pointer (sp) read/write reset value: 01 ffh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (seefigure 6). since the stack is 256 bytes deep, the most signif- icant byte is forced by hardware. following an mcu reset, or after a reset stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer can be directly accessed by a ld instruction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 6. when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 6. stack manipulation example 15 8 00000001 70 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h
13/80 st72272 3 clocks, reset, interrupts & power saving modes 3.1 clock system 3.1.1 general description the mcu accepts either a crystal or ceramic res- onator, or an external clock signal to drive the in- ternal oscillator. the internal clock (f cpu )isde- rived from the external oscillator frequency (f osc ) . the external oscillator clock is first divided by 3, and an additional division factor of 2 can be ap- plied if slow mode is selected by resetting the sms bit in the miscellaneous register. this reduc- es the frequency of the f cpu ; the clock signal is also routed to the on-chip peripherals. the cpu clock signal consists of a square wave with a duty cycle of 50%. the internal oscillator is designed to operate with an at-cut parallel resonant quartz crystal resona- tor in the frequency range specified for f osc . the circuit shown in figure 7 is recommended when using a crystal, and table 4 lists the recommend- ed capacitance and feedback resistance values. the crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. use of an external cmos oscillator is recom- mended when crystals outside the specified fre- quency ranges are to be used. table 4 . recommended crysta l values legend: c l1 ,c l2 = maximum total capacitance on pins oscin and oscout (the value includes the ex- ternal capacitance tied to the pin plus the parasitic capacitance of the board and of the device). r smax = maximum series parasitic resistance of the quartz allowed. note: the tables relate to the quartz crystal only (not ceramic resonator). 3.1.2 external clock an external clock may be applied to the oscin in- put with the oscout pin not connected. the t ox- ov specifications does not apply when using an external clock input. the equivalent specification of the external clock source should be used in- stead of t oxov (see electrical characteristics). figure 7. crystal/ceramic resonator figure 8. clock prescaler block diagram 24 mhz unit r smax 70 25 20 ohms c l1 22 47 56 pf c l2 22 47 56 pf oscin oscout c oscin c oscout r p oscin oscout c oscin c oscout r p %3 %2 cpuclk to cpu and peripherals
14/80 st72272 3.2 reset 3.2.1 introduction there are three sources of reset: reset pin (external source) power-on reset (internal source) watchdog (internal source) the reset service routine vector is located at ad- dress fffeh-ffffh. 3.2.2 external reset the reset pin is both an input and an open-drain output with integrated pull-up resistor. when one of the internal reset sources is active, the reset pin is driven low to reset the whole application. 3.2.3 reset operation the duration of the reset condition, which is also reflected on the output pin, is fixed at 4096 internal cpu clock cycles. a reset signal originating from an external source must have a duration of at least 1.5 internal cpu clock cycles in order to be recog- nised. at the end of the power-on reset cycle, the mcu may be held in the reset condition by an ex- ternal reset signal. the reset pin may thus be used to ensure v dd has risen to a point where the mcu can operate correctly before the user pro- gram is run. following a power-on reset event, or after exiting halt mode, a 4096 cpu clock cycle delay period is initiated in order to allow the oscil- lator to stabilise and to ensure that recovery has taken place from the reset state. during the reset cycle, the device reset pin acts as an output that is pulsed low. in its high state, an internal pull-up resistor of about 300k w is con- nected to the reset pin. this resistor can be pulled low by external circuitry to reset the device. 3.2.4 power-on reset this circuit detects the ramping up of v dd , and generates a pulse that is used to reset the applica- tion (at approximately v dd = 2v). power-on reset is designed exclusively to cope with power-up conditions, and should not be used in order to attempt to detect a drop in the power supply voltage. caution : to re-initialize the power-on reset, the power supply must fall below approximately 0.8v (vtn), prior to rising above 2v. if this condition is not respected, on subsequent power-up the reset pulse may not be generated. an external reset pulse may be required to correctly reactivate the circuit. figure 9. reset block diagram internal reset watchdog reset oscillator signal counter reset 300k to st7 reset v dd
15/80 st72272 reset (cont'd) table 5. list of sections affected by reset, wait and halt (refer to 3.6 for wait and halt modes) figure 10. reset timing diagram note: refer to electrical characteristics for values of t ddr and t oxov section reset wait halt cpu clock running at 4 mhz x timer prescaler reset to zero x timer counter set to fffch x all timer enable bits set to 0 (disabled) x data direction registers set to 0 (as inputs) x set stack pointer to 01ffh x force internal address bus to restart vector fffeh, ffffh x set interrupt mask bit (i-bit, cc) to 1 (interrupt disable) x set interrupt mask bit (i-bit, cc) to 0 (interrupt enable) x x reset halt latch x reset wait latch x disable oscillator (for 4096 cycles) x x set timer clock to 0 x x watchdog counter reset x watchdog register reset x port data registers reset x other on-chip peripherals: registers reset x v dd oscin f cpu ffff fffe pc reset watchdog reset t ddr t oxov 4096 cpu clock cycles delay
16/80 st72272 3.3 interrupts the st7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in table 6 and a non-maskable software in- terrupt (trap). the interrupt processing flowchart is shown in figure 11. the maskable interrupts must be enabled clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsec- tion). when an interrupt has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. the i bit of the cc register is set to prevent addi- tional interrupts. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to table 6 for vector addresses). the interrupt service routine should finish with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared and the main program will resume. priority management by default, a servicing interrupt can not be inter- rupted because the i bit is set by hardware enter- ing in interrupt routine. in the case several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (seetable 6). non maskable software interrupts this interrupt is entered when the trap instruc- tion is executed regardless of the state of the i bit. it will be serviced according to the flowchart on figure 11. interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specific men- tioned interrupts allow the processor to leave the halt low power mode (refer to the aexit from halta column in table 6). external interrupts external interrupt vectors can be loaded in the pc register if the corresponding external interrupt oc- curred and if the i bit is cleared. these interrupts allow the processor to leave the halt low power mode. the external interrupt polarity can be selected through the miscellaneous register or interrupt register (if available) (see section 3.5). an external interrupt triggered on edge will be latched and the interrupt request automatically cleared on entering the interrupt service routine. more than one input pin can be connected to the same interrupt request (depending on the device). in this case, all inputs configured as interrupt are logically ored. warning: the type of polarity defined in the mis- cellaneous or interrupt register (if available) ap- plies to the ei source. in case of an ored source, a low level on an i/o pin configured as input with interrupt, masks the interrupt request even in case of rising-edge polarity. peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: the i bit of the cc register is cleared. the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: writing a0o to the corresponding bit in the status register or an access to the status register while the flag is set followed by a read or write of an associated register. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed.
17/80 st72272 interrupts (cont'd) figure 11. interrupt processing flowchart from reset execute instruction stack pc, x, a, cc set i bit load pc from interrupt vector restore pc, x, a, cc from stack interrupt n y i bit set n y iret fetch next instruction y n this clears i bit by default vr01172d
18/80 st72272 interrupts (cont'd) table 6. interrupt mapping * many flags can cause an interrupt: see peripheral interrupt status register description. source block description register label flag exit from halt vector address priority order reset reset n/a n/a yes fffeh-ffff h trap software interrupt n/a n/a no fffch-fffdh not used fff2h-fffbh ei0 ext. interrupt pd0, falling edge itrfre ei0f yes fff0h-fff1h not used ffech-ffefh timer input capture 1 timsr icf1 no ffeah-ffebh input capture 2 icf2 output compare 1 ocf1 ffe8h-ffe9h output compare 2 ocf2 timer overflow tof ffe6h-ffe7h i2c i2c interface interrupt i2csr1 i2csr2 * ffe4h-ffe5h not used ffe0h-ffe3h highest priority priority lowest
19/80 st72272 3.4 power saving modes 3.4.1 introduction there are three power saving modes. slow mode is selected by setting the relevant bits in the mis- cellaneous register. wait and halt modes may be entered using the wfi and halt instructions. 3.4.2 slow mode in slow mode, the oscillator frequency can be di- vided by a value defined in the miscellaneous register. the cpu and peripherals are clocked at this lower frequency. slow mode is used to reduce power consumption, and enables the user to adapt clock frequency to available supply voltage. note: on reset, slow mode is selected by default (f osc /6). 3.4.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. all peripher- als remain active. during wait mode, the i bit (cc register) is cleared, so as to enable all interrupts. all other registers and memory remain unchanged. the mcu will remain in wait mode until an inter- rupt or reset occurs, whereupon the program counter branches to the starting address of the in- terrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 12 below. figure 12. wait flow chart wfi instruction reset interrupt y n n y cpu clock oscillator periph. clock i-bit on on cleared off cpu clock oscillator periph. clock i-bit on on set on fetch reset vector or service interrupt 4096 cpu clock cycles delay if reset note: before servicing an interrupt, the cc register is pushed on the stack. the i-bit is set during the inter- rupt routine and cleared when the cc register is popped.
20/80 st72272 power saving modes (cont'd) 3.4.4 halt mode the halt mode is the mcu lowest power con- sumption mode. the halt mode is entered by exe- cuting the halt instruction. the internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. the halt mode cannot be used when the watchdog is enabled, if the halt instruction is executed while the watchdog system is enabled, a watchdog reset is generated thus resetting the en- tire mcu. when entering halt mode, the i bit in the cc reg- ister is cleared so as to enable external interrupts. if an interrupt occurs, the cpu becomes active. the mcu can exit the halt mode upon reception of an interrupt or a reset. refer to the interrupt map- ping table. the oscillator is then turned on and a stabilization time is provided before releasing cpu operation. the stabilization time is 4096 cpu clock cycles. after the start up delay, the cpu continues oper- ation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. figure 13. halt flow chart n n external interrupt* reset halt instruction 4096 cpu clock fetch reset vector or service interrupt cycles delay cpu clock oscillator periph. clock i-bit on on set on cpu clock oscillator periph. clock i-bit off off cleared off y y wdg enabled? n y reset watchdog * or some specific interrupts note: before servicing an interrupt, the cc register is pushed on the stack. the i-bit is set during the inter- rupt routine and cleared when the cc register is popped.
21/80 st72272 3.5 register description miscellaneous register (miscr) read/write reset value: 0000 0000 (00h) bit 7:6 = reserved bit 5 = sms slow mode select. this bit is set and cleared by software. it is used to select the slow or fast mode cpu frequency. 0: f cpu = oscillator frequency / 6 (slow mode) 1: f cpu = oscillator frequency / 3 (normal mode) bit 4:1 = reserved bit 0 = poc0 pwm/brm output configuration bit . this bits is set and cleared by software. they se- lect the pwm/brm output configuration for pins da1-da4. 0: push-pull 1: open drain interrupt register (itrfre) read/write reset value: 0000 0000 (00h) bit 7 = ei0f falling edge detector flag. this bit is set by hardware when a falling edge oc- curs on the pin assigned to ei0. it is cleared by software. when this bit is set, an interrupt is gener- ated if the corresponding ite bit =1 and the i bit in the cc register = 0. 0: no falling edge detected 1: falling edge detected bit 6:4 = reserved bit 3:0 = ei0ite interrupt enable bit . this bit is set and cleared by software. 0: interrupt disabled 1: interrupt enabled 70 - - sms - - - - poc0 70 ei0f - - - ei0ite - - -
22/80 st72272 4 on-chip peripherals 4.1 i/o ports 4.1.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: analog signal input (adc) alternate signal input/output for the on-chip pe- ripherals. external interrupt generation an i/o port is composed of up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital out- put. 4.1.2 functional description each port is associated to 2 main registers: data register (dr) data direction register (ddr) and some of them to an optional register: option register (or) each i/o pin may be programmed using the corre- sponding register bits in ddr and or registers: bit x corresponding to pin x of the port. the same cor- respondence is used for the dr register. the following description takes into account the or register, however some specific ports do not provide this register. the generic i/o block dia- gram is shown on figure 14. 4.1.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. notes : 1. all the inputs are triggered by a cmos schmitt trigger. 2. when switching from input mode to output mode, the dr register should be written first to output the correct value as soon as the port is con- figured as an output. 4.1.2.2 external interrupt generation an i/o can be used to generate an external inter- rupt request to the cpu. external interrupts are enabled and their polarity selected using the or, misc and itrfre registers (where available). each external interrupt vector is linked to a dedi- cated group of i/o port pins (see interrupts sec- tion). if more than one input pin is selected simul- taneously as interrupt source, this is logically ored. for this reason if one of the interrupt pins is tied low, it masks the other ones. 4.1.2.3 output mode the pin is configured in output mode by setting the corresponding ddr register bit. in this mode, writing a0o or a1o to the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. note : in this mode, the interrupt function is disa- bled. 4.1.2.4 digital alternate function when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin has to be configured in input mode. in this case, the pin's state is also digitally readable by addressing the dr register. note: when the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (ddr = 0). warning : the alternate function must not be acti- vated as long as the pin is configured as input with interrupt, in order to avoid generating spurious in- terrupts.
23/80 st72272 i/o ports (cont'd) 4.1.2.5 analog alternate function when the pin is used as an adc input the i/o must be configured as input, floating. the analog multi- plexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maximum ratings.
24/80 st72272 i/o ports (cont'd) figure 14 . i/o block diagram table 7. port mode configuration legend : 0 - present, not activated 1 - present and activated notes : no or register on some ports (see register map). adc switch on ports with analog alternate functions. dr ddr latch latch data bus dr sel ddr sel v dd pad analog switch analog enable (adc) m u x alternate alternate alternate enable common analog rail alternate m u x alternate input pull-up (s ee t able below ) output p-buffer (s ee t able b elow ) n-buffer 1 0 1 0 or latch or sel pull-up condition enable enable gnd (s ee t able below ) (s ee n ote below ) cmos schmitt trigger or external interrupt request configu ration mode pull-up p-buffer floating 0 0 pull-up 1 0 push-pull 0 1 true open drain not present not present open drain (logic level) not present 0
25/80 st72272 i/o ports (cont'd) 4.1.2.6 device specific configurations table 8. st72272k port configuration *reset state. note: the da1-da4 output pins are configurable as push pull or open drain using the poc0 bit in the mis- cellaneous register. port pin name input (ddr=0) output (ddr=1) or=0* or=1 or=0 or=1 port a pa4:7 floating true open drain, high sink capability port b pb0:2, pb7 pull-up floating (for analog conversion only) push-pull port c pc0 pull-up push-pull pc2:pc5 floating open drain pc6 pull-up push-pull port d pd1:pd2, pd6 pull-up push-pull
26/80 st72272 i/o ports (cont'd) 4.1.3 register description data registers (dr) read/write reset value: 0000 0000 (00h) bit 7:0 = d7-d0 data register 8 bits. the behaviour of the dr register depends on the selected input/output configuration. writing the dr register is always taken in account even if the pin is configured as an input. reading the dr register returns either the dr register latch content (pin configured as output) or the digital value applied to the i/o pin (pin configured as input). data direction registers (ddr) read/write reset value: 0000 0000 (00h) (input mode) bit 7:0 = dd7-dd0 data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bit is set and cleared by software. 0: input mode 1: output mode option register (or) read/write reset value: 0000 0000 (00h) bit 7 = ad7 digital/analog input configuration . 0: the pull-up is connected and pin configured as digital input (reset condition) 1: the pull-up is disconnected and the pin is con- figured as analog input. bit 6:3 = reserved bit 2:0 = ad[2:0] digital/analog input configura- tion bits . 0: the pull-up is connected and pin configured as digital input (reset condition) 1: the pull-up is disconnected and the pin is con- figured as analog input. 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 70 ad7 - - - - ad2 ad1 ad0
27/80 st72272 i/o ports (cont'd) table 9. i/o port register map and reset values address (hex.) register label 76543210 0000h padr reset value d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 0001h paddr reset value dd7 0 dd6 0 dd5 0 dd4 0 dd3 0 dd2 0 dd1 0 dd0 0 0002h pcdr reset value d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 0003h pcddr reset value dd7 0 dd6 0 dd5 0 dd4 0 dd3 0 dd2 0 dd1 0 dd0 0 0004h pddr reset value d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 0005h pdddr reset value dd7 0 dd6 0 dd5 0 dd4 0 dd3 0 dd2 0 dd1 0 dd0 0 0006h pbdr reset value d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 0007h pbddr reset value dd7 0 dd6 0 dd5 0 dd4 0 dd3 0 dd2 0 dd1 0 dd0 0 0008h pbor reset value ad7 0 - 0 - 0 - 0 - 0 ad2 0 ad1 0 ad0 0
28/80 st72272 4.2 watchdog timer (wdg) 4.2.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counter's contents before the t6 bit be- comes cleared. 4.2.2 main features n programmable timer (64 increments of 49,152 cpu cycles) n programmable reset n reset (if watchdog activated) after a halt instruction or when the t6 bit reaches zero figure 15. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) 49152 t1 t2 t3 t4 t5
29/80 st72272 watchdog timer (cont'd) 4.2.3 functional description the counter value stored in the cr register (bits t6:t0), is decremented every 49,152 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t6:t0) rolls over from 40h to 3fh (t6 become cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. the value to stored in the cr register must be between ffh and c0h (see table 10): the wdga bit is set (watchdog enabled) the t6 bit is set to prevent generating an imme- diate reset the t5:t0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. table 10. watchdog timing (f cpu = 8 mhz) notes: following a reset, the watchdog is disa- bled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. 4.2.4 register description control register (cr) read/ write reset value: 0111 1111 (7fh) bit 7= wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled bit 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 become cleared) if wdga=1. table 11. wdg register map cr register initial value wdg timeout period (ms) max ffh 393.216 min c0h 6.144 70 wdga t6 t5 t4 t3 t2 t1 t0 address (hex.) register name 765 4 3210 0c reset value cr wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1
30/80 st72272 4.3 16-bit timer 4.3.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals ( input capture ) or generation of up to two out- put waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the cpu clock prescaler. 4.3.2 main features n programmable prescaler: f cpu divided by 2, 4 or 8. n overflow status flag and maskable interrupt n external clock input (must be at least 4 times slower than the cpuclock speed) with the choice of active edge n output compare functions with 2 dedicated 16-bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt n input capture functions with 2 dedicated 16-bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt n pulse width modulation mode (pwm) n one pulse mode n 5 alternate functions on i/o ports* the block diagram is shown infigure 16. *note: some external pins are not available on all devices. refer to the device pin out description. when reading an input signal which is not availa- ble on an external pin, the value will always be `1'. 4.3.3 functional description 4.3.3.1 counter the principal block of the programmable timer is a 16-bit free running increasing counter and its as- sociated 16-bit registers: counter registers counter high register (chr) is the most sig- nificant byte (msb). counter low register (clr) is the least sig- nificant byte (lsb). alternate counter registers alternate counter high register (achr) is the most significant byte (msb). alternate counter low register (aclr) is the least significant byte (lsb). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (overflow flag), (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. the timer clock depends on the clock control bits of the cr2 register, as illustrated intable 12. the value in the counter register repeats every 131.072, 262.144 or 524.288 internal processor clock cycles depending on the cc1 and cc0 bits.
31/80 st72272 16-bit timer (cont'd) figure 16. timer block diagram mcu-peripheral interface counter alternate register output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 0 0 0 ocf2 ocf1tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 cr1 cr2 sr 6 16 888 8 88 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc1 cc0 16 bit free running counter
32/80 st72272 16-bit timer (cont'd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the msb first, then the lsb value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the msb several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the lsb of the count value at the time of the read. an overflow occurs when the counter rolls over from ffffh to 0000h then: the tof bit of the sr register is set. a timer interrupt is generated if: toie bit of the cr1 register is set and i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. notes: the tof bit is not cleared by accesses to aclr register. this feature allows simultaneous use of the overflow function and reads of the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 4.3.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in cr2 register. the status of the exedg bit determines the type of level transition on the external clock pin ext- clk that will trigger the free running counter. the counter is synchronised with the falling edge of the internal cpu clock. at least four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock frequen- cy must be less than a quarter of the cpu clock frequency. lsb is buffered read msb at t0 read lsb returns the buffered lsb value at t0 at t0 + d t other instructions beginning of the sequence sequence completed
33/80 st72272 16-bit timer (cont'd) figure 17. counter timing diagram, internal clock divided by 2 figure 18. counter timing diagram, internal clock divided by 4 figure 19. counter timing diagram, internal clock divided by 8 cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register overflow flag tof fffc fffd 0000 0001 cpu clock internal reset timer clock counter register overflow flag tof cpu clock internal reset timer clock counter register overflow flag tof fffc fffd 0000
34/80 st72272 16-bit timer (cont'd) 4.3.3.3 input capture in this section, the index, i , may be 1 or 2. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition detected by the icap i pin (see figure 5). ic i rregister is a read-only register. the active transition is software programmable through the iedg i bit of the control register (cr i ). timing resolution is one count of the free running counter: ( f cpu /(cc1.cc0) ). procedure to use the input capture function select the follow- ing in the cr2 register: select the timer clock (cc1-cc0) (see table 12). select the edge of the active transition on the icap2 pin with the iedg2 bit. and select the following in the cr1 register: set the icie bit to generate an interrupt after an input capture. select the edge of the active transition on the icap1 pin with the iedg1 bit. when an input capture occurs: icf i bit is set. theic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 21). a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. note: after reading the ic i hr register, transfer of input capture data is inhibited until the ic i lr regis- ter is also read. the ic i r register always contains the free running counter value which corresponds to the most re- cent input capture. during halt mode, if at least one valid input cap- ture edge occurs on the icap i pin, the input cap- ture detection circuitry is armed. this does not set any timer flags, and does not awake-upo the mcu. if the mcu is awoken by an interrupt, the input capture flag will become active, and data corre- sponding to the first valid edge during halt mode will be present. ms byte ls byte icir ic i hr ic i lr
35/80 st72272 16-bit timer (cont'd) figure 20. input capture block diagram figure 21. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r ic2r edge detect circuit1 ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge.
36/80 st72272 16-bit timer (cont'd) 4.3.3.4 output compare in this section, the index, i , may be 1 or 2. this function can be used to control an output waveform or indicating when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: assigns pins with a programmable value if the ocie bit is set sets a flag in the status register generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the free run- ning counter each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/(cc1.cc0) ). procedure to use the output compare function, select the fol- lowing in the cr2 register: set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i function. select the timer clock (cc1-cc0) (see table 12). and select the following in the cr1 register: select the olvl i bit to applied to the ocmp i pins after the match occurs. set the ocie bit to generate an interrupt if it is needed. when match is found: ocf i bit is set. the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset and stays low until valid compares change it to a high level). a timer interrupt is generated if the ocie bit is set in the cr2 register and the i bit is cleared in the cc register (cc). clearing the output compare interrupt request is done by: 3. reading the sr register while the ocf i bit is set. 4. an access (read or write) to the oc i lr register. note: after a processor write cycle to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. if the oc i e bit is not set, the ocmp i pin is a gen- eral i/o port and the olvl i bit will not appear when match is found but an interrupt could be gen- erated if the ocie bit is set. the value in the 16-bit oc i r register and the olv i bit should be changed after each successful com- parison in order to control an output waveform or establish a new elapsed timeout. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = desired output compare period (in seconds) f cpu = internal clock frequency t presc = timer clock prescaler (cc1-cc0 bits, see table 12) the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: write to the oc i hr register (further compares are inhibited). read the sr register (first step of the clearance of the ocf i bit, which may be already set). write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr d oc i r= d t * f cpu t presc
37/80 st72272 16-bit timer (cont'd) figure 22. output compare block diagram figure 23. output compare timing diagram, internal clock divided by 2 output compare 16-bit circuit oc1r 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r internal cpu clock timer clock counter output compare register compare register latch ocfi and ocmpi pin (olvli=1) cpu writes ffff ffff fffd fffd fffe ffff 0000 fffc
38/80 st72272 16-bit timer (cont'd) 4.3.3.5 forced compare mode in this section i may represent 1 or 2. the following bits of the cr1 register are used: when the folv i bit is set, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is not set, and thus no interrupt re- quest is generated. 4.3.3.6 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in section 4.3.3.7). 2. select the following in the the cr1 register: using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. select the edge of the active transition on the icap1 pin with the iedg1 bit . 3. select the following in the cr2 register: set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. set the opm bit. select the timer clock cc1-cc0 (see table 12). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and olvl2 bit is loaded on the ocmp1 pin. when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 24). note: the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. the icf1 bit is set when an active edge occurs and can generate an interrupt if the icie bit is set. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. figure 24. one pulse mode timing folv2 folv1 olvl2 olvl1 event occurs counter is initialized to fffch ocmp1 = olvl2 counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle counter .... fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1
39/80 st72272 16-bit timer (cont'd) 4.3.3.7 pulse width modulation mode pulse width modulation mode enables the gener- ation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. the pulse width modulation mode uses the com- plete output compare 1 function plus the oc2r register. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal. 2. load the oc1r register with the value corre- sponding to the length of the pulse if (olvl1=0 and olvl2=1). 3. select the following in the cr1 register: using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc1r register. using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. set the pwm bit. select the timer clock (cc1-cc0) (seetable 12). if olvl1=1 and olvl2=0 the length of the pulse is the difference between the oc2r and oc1r registers. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = desired output compare period (seconds) f cpu = internal clock frequency (see miscella- neous register) t presc = timer clock prescaler (cc1-cc0 bits , see table 12) the output compare 2 event causes the counter to be initialized to fffch (see figure 25). note: after a write instruction to the oc i hr regis- ter, the output compare function is inhibited until the oc i lr register is also written. the icf1 bit is set by hardware when the counter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. therefore the input capture 1 function is inhibited but the input capture 2 is available. the ocf1 and ocf2 bits cannot be set by hard- ware in pwm mode therefore the output compare interrupt is inhibited. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. figure 25. pulse width modulation mode timing oc i r value = t * f cpu t presc -5 counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set counter 34e2 fffc fffd fffe 2ed0 2ed1 2ed2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1
40/80 st72272 16-bit timer (cont'd) 4.3.4 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1
41/80 st72272 16-bit timer (cont'd) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 enable. 0: output compare 1 function is enabled, but the ocmp1 pin is a general i/o. 1: output compare 1 function is enabled, the ocmp1 pin is dedicated to the output compare 1 capability of the timer. bit 6 = oc2e output compare 2 enable. 0: output compare 2 function is enabled, but the ocmp2 pin is a general i/o. 1: output compare 2 function is enabled, the ocmp2 pin is dedicated to the output compare 2 capability of the timer. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bit 3, 2 = cc1-cc0 clock control. the value of the timer clock depends on these bits: table 12. clock control bits bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin extclk will trigger the free running counter. 0: a falling edge triggers the free running counter. 1: a rising edge triggers the free running counter. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu /4 0 0 f cpu /2 0 1 f cpu /8 1 0 external clock (where available) 11
42/80 st72272 16-bit timer (cont'd) status register (sr) read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) regis- ter. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) reg- ister. bit 5 = tof timer overflow. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr reg- ister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred.to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) reg- ister. bit 2-0 = reserved, forced by hardware to 0. input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 icf1 ocf1 tof icf2 ocf2 0 0 0 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb
43/80 st72272 16-bit timer (cont'd) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb
44/80 st72272 table 13. 16-bit timer register map warning: write 0ch in the config register to use the icap1 and icap2 pins (set bits 3 and 2). address (hex.) register name 76543210 11 cr2 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg 12 cr1 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 13 sr icf1 ocf1 tof icf2 ocf2 0 0 0 14 ic1hr msb lsb 15 ic1lr msb lsb 16 oc1hr msb lsb 17 oc1lr msb lsb 18 chr msb lsb 19 clr msb lsb 1a achr msb lsb 1b aclr msb lsb 1c ic2hr msb lsb 1d ic2lr msb lsb 1e oc2hr msb lsb 1f oc2lr msb lsb 43 config reset value - 0 - 0 - 0 - 0 - 1 icap 0 - 0 - 0
45/80 st72272 4.4 i 2 c bus interface (i2c) 4.4.1 introduction the i 2 c bus interface serves as an interface be- tween the microcontroller and the serial i 2 c bus. it provides both multimaster and slave functions, and controls all i 2 c bus-specific sequencing, pro- tocol, arbitration and timing. it supports fast i 2 c mode (400khz). 4.4.2 main features parallel bus /i 2 c protocol converter multi-master capability interrupt generation standard i 2 c mode/fast i 2 c mode 7-bit addressing n i 2 c slave mode start bit detection flag detection of misplaced start or stop condition transfer problem detection address matched detection default address detection end of byte transmission flag transmitter/receiver flag stop bit detection n i 2 c master mode i 2 c bus busy flag arbitration lost flag end of byte transmission flag transmitter/receiver flag clock generation 4.4.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i 2 c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i 2 c bus and a fast i 2 c bus. this selection is made by soft- ware. mode selection the interface can operate in the four following mo- des: slave transmitter/receiver master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from slave to master after it generates a start condition and from master to slave in case of arbitration loss or a stop generation, this allows multi-master capabi- lity. communication flow in master mode, it initiates a data transfer and ge- nerates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode, the interface is capable of recogni- sing its own address (7-bit), and the general call address. the general call address detection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte following the start condi- tion is the address byte; it is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer tofig- ure 26. figure 26. i 2 c bus protocol scl sda 12 8 9 msb ack stop start condition condition vr02119b
46/80 st72272 i 2 c bus interface (cont'd) acknowledge may be enabled and disabled by software. the i 2 c interface address and/or general call ad- dress can be selected by software. the speed of the i 2 c interface may be selected between standard (0-100khz) and fast i 2 c (100- 400khz). sda/scl line control transmitter mode: the interface holds the clock line low before transmission to wait for the micro- controller to write the byte in the data register. receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. the scl frequency (f scl ) is controlled by a pro- grammable clock divider which depends on the i 2 c bus mode. when the i 2 c cell is enabled, the sda and scl ports must be configured as floating open-drain output or floating input. in this case, the value of the external pull-up resistance used depends on the application. when the i 2 c cell is disabled, the sda and scl ports revert to being standard i/o port pins. figure 27. i 2 c interface block diagram data register (dr) data shift register comparator own address register (oar) clock control registe r (ccr) status register 1 (sr1) control registe r (cr) sdai scli control logic status register 2 (sr2) inter rupt clock control data control scl sda
47/80 st72272 i 2 c bus interface (cont'd) 4.4.4 functional description refer to the cr, sr1 and sr2 registers insection 4.4.5. for the bit definitions. by default the i 2 c interface operates in slave mode (m/sl bit is cleared) except when it initiates a transmit or receive sequence. 4.4.4.1 slave mode as soon as a start condition is detected, the address is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). address not matched : the interface ignores it and waits for another start condition. address matched : the interface generates in se- quence: acknowledge pulse if the ack bit is set. evf and adsl bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 reg- ister, holding the scl line low (see figure 28 transfer sequencing ev1). next, read the dr register to determine from the least significant bit if the slave must enter receiver or transmitter mode. slave receiver following the address reception and after sr1 re- gister has been read, the slave receives bytes from the sda line into thedr register via the inter- nal shift register. after each byte the interface ge- nerates in sequence: acknowledge pulse if the ack bit is set evf and btf bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 re- gister followed by a read of the dr register, hol- ding the scl line low (see figure 28 transfer se- quencing ev2). slave transmitter following the address reception and after sr1 register has been read,the slave sends bytes from the dr register to the sda line via the internal shift register. the slave waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 28 transfer sequencing ev3). when the acknowledge pulse is received: the evf and btf bits are set by hardware with an interrupt if the ite bit is set. closing slave communication after the last data byte is transferred a stop con- dition is generated by the master. the interface detects this condition and sets: evf and stopf bits with an interrupt if the ite bit is set. then the interface waits for a read of the sr2 re- gister (see figure 28 transfer sequencing ev4). error cases berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and the berr bits are set with an interrupt if the ite bit is set. if it is a stop then the interface discards the data, released the lines and waits for another start condition. if it is a start then the interface discards the data and waits for the next slave address on the bus. af : detection of a non-acknowledge bit. in this case, the evf and af bits are set with an inter- rupt if the ite bit is set. note : in both cases, scl line is not held low; however, sda line can remain low due to possible ?0? bits transmitted last. it is then necessary to re- lease both lines by software. how to release the sda / scl lines set and subsequently clear the stop bit while btf is set. the sda/scl lines are released after the transfer of the current byte.
48/80 st72272 i 2 c bus interface (cont'd) 4.4.4.2 master mode to switch from default slave mode to master mode a start condition generation is needed. start condition and transmit slave address setting the start bit while the busy bit is clea- red causes the interface to switch to master mode (m/sl bit set) and generates a start condition. once the start condition is sent: the evf and sb bits are set by hardware with an interrupt if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the dr register with the slave address byte, holding the scl line low (see figure 28 transfer sequencing ev5). then the slave address byte is sent to the sda line via the internal shift register. after completion of this transfer (and acknowledge from the slave if the ack bit is set): the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the cr register (for exam- ple set pe bit), holding the scl line low (see fi- gure 28 transfer sequencing ev6). next the master must enter receiver or transmit- ter mode. master receiver following the address transmission and after sr1 and cr registers have been accessed, themaster receives bytes from the sda line into thedr regis- ter via the internal shift register. after each byte the interface generates in sequence: acknowledge pulse if if the ack bit is set evf and btf bits are set by hardware with an in- terrupt if the ite bit is set. then the interface waits for a read of the sr1 re- gister followed by a read of the dr register, hol- ding the scl line low (see figure 28 transfer se- quencing ev7). to close the communication: before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit clea- red). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte. master transmitter following the address transmission and after sr1 register has been read, the master sends bytes from the dr register to the sda line via the inter- nal shift register. the master waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 28 transfer sequencing ev8). when the acknowledge bit is received, the interface sets: evf and btf bits with an interrupt if the ite bit is set. to close the communication: after writing the last byte to the dr register, set the stop bit to gene- rate the stop condition. the interface goes auto- matically back to slave mode (m/sl bit cleared). error cases berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set by hardware with an interrupt if ite is set. af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. arlo: detection of an arbitration lost condition. in this case the arlo bit is set by hardware (with an interrupt if the ite bit is set and the interface goes automatically back to slave mode (the m/sl bit is cleared). note : in all these cases, the scl line is not held low; however, the sda line can remain low due to possible ?0? bits transmitted last. it is then neces- sary to release both lines by software.
49/80 st72272 i 2 c bus interface (cont'd) figure 28. transfer sequencing legend: s=start, p=stop, a=acknowledge, na=non-acknowledge evx=event (with interrupt if ite=1) ev1: evf=1, adsl=1, cleared by reading sr1 register. ev2: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register. ev3: evf=1, btf=1, cleared by reading sr1 register followed by writing dr register. ev3-1: evf=1, af=1, cleared by reading sr1 register. ev4: evf=1, stopf=1, cleared by reading sr2 register. ev5: evf=1, sb=1, cleared by reading sr1 register followed by writing dr register. ev6: evf=1, cleared by reading sr1 register followed by writing cr register (for example pe=1). ev7: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register. ev8: evf=1, btf=1, cleared by reading sr1 register followed by writing dr register. figure 29. event flags and interrupt generation slave receiver: slave transmitter: master receiver: master transmitter: s address a data1 a data2 a ..... datan a p ev1 ev2 ev2 ev2 ev4 s address a data1 a data2 a .... . datan na p ev1 ev3 ev3 ev3 ev3-1 ev4 s address a data1 a data2 a .... . datan na p ev5 ev6 ev7 ev7 ev7 s address a data1 a data2 a ..... datan a p ev5 ev6 ev8 ev8 ev8 ev8 btf adsl sb af stopf arlo berr evf interrupt ite * * evf can also be set by ev6 or an error from the sr2 register.
50/80 st72272 i 2 c bus interface (cont'd) 4.4.5 register description i 2 c control register (cr) read / write reset value: 0000 0000 (00h) bit 7:6 = reserved. forced to 0 by hardware. bit 5 = pe peripheral enable. this bit is set and cleared by software. 0: peripheral disabled 1: master/slave capability notes: when pe=0, all the bits of the cr register and the sr register except the stop bit are reset. all outputs are released while pe=0 when pe=1, the corresponding i/o pins are se- lected by hardware as alternate functions. to enable thei 2 c interface, write the cr register twice with pe=1 as the first write only activates the interface (only pe is set). bit 4 = engc enable general call. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). the 00h general call address is ac- knowledged (01h ignored). 0: general call disabled 1: general call enabled bit 3 = start generation of a start condition . this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0) or when the start condition is sent (with interrupt generation if ite=1). in master mode: 0: no start generation 1: repeated start generation in slave mode: 0: no start generation 1: start generation when the bus is free bit 2 = ack acknowledge enable. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received bit 1 = stop generation of a stop condition . this bit is set and cleared by software. it is also cleared by hardware in master mode. note: this bit is not cleared when the interface is disabled (pe=0). in master mode: 0: no stop generation 1: stop generation after the current byte transfer or after the current start condition is sent. the stop bit is cleared by hardware when the stop condition is sent. in slave mode: 0: no stop generation 1: release the scl and sda lines after the cur- rent byte transfer (btf=1). in this mode the stop bit has to be cleared by software. bit 0 = ite interrupt enable. this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe=0). 0: interrupts disabled 1: interrupts enabled refer to figure 29 for the relationship between the events and the interrupt. scl is held low when the sb, btf or adsl flags or an ev6 event (see figure 28) is detected. 70 0 0 pe engc start ack stop ite
51/80 st72272 i 2 c interface (cont'd) i 2 c status register 1 (sr1) read only reset value: 0000 0000 (00h) bit 7 = evf event flag. this bit is set by hardware as soon as an event oc- curs. it is cleared by software reading sr2 register in case of error event or as described infigure 28. it is also cleared by hardware when the interface is disabled (pe=0). 0: no event 1: one of the following events has occurred: btf=1 (byte received or transmitted) adsl=1 (address matched in slave mode while ack=1) sb=1 (start condition generated in master mode) af=1 (no acknowledge received after byte transmission if ack=1) stopf=1 (stop condition detected in slave mode) arlo=1 (arbitration lost in master mode) berr=1 (bus error, misplaced start or stop condition detected) address byte successfully transmitted in mas- ter mode. bit 6 = reserved. forced to 0 by hardware. bit 5 = tra transmitter/receiver. when btf is set, tra=1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after de- tection of stop condition (stopf=1), loss of bus arbitration (arlo=1) or when the interface is disa- bled (pe=0). 0: data byte received (if btf=1) 1: data byte transmitted bit 4 = busy bus busy . this bit is set by hardware on detection of a start condition and cleared by hardware on detection of a stop condition. it indicates a communication in progress on the bus. this information is still updat- ed when the interface is disabled (pe=0). 0: no communication on the bus 1: communication ongoing on the bus bit 3 = btf byte transfer finished. this bit is set by hardware as soon as a byte is cor- rectly received or transmitted with interrupt gener- ation if ite=1. it is cleared by software reading sr1 register followed by a read or write of dr reg- ister. it is also cleared by hardware when the inter- face is disabled (pe=0). following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is sent, this bit is set only after the ev6 event (see figure 28). btf is cleared by reading sr1 register followed by writ- ing the next byte in dr register. following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading sr1 register followed by reading the byte from dr register. the scl line is held low while btf=1. 0: byte transfer not done 1: byte transfer succeeded bit 2 = adsl address matched (slave mode). this bit is set by hardware as soon as the received slave address matched with the oar register con- tent or a general call is recognized. an interrupt is generated if ite=1. it is cleared by software read- ing sr1 register or by hardware when the inter- face is disabled (pe=0). the scl line is held low while adsl=1. 0: address mismatched or not received 1: received address matched bit 1 = m/sl master/slave. this bit is set by hardware as soon as the interface is in master mode (writing start=1). it is cleared by hardware after detecting a stop condition on the bus or a loss of arbitration (arlo=1). it is also cleared when the interface is disabled (pe=0). 0: slave mode 1: master mode bit 0 = sb start bit (master mode). this bit is set by hardware as soon as the start condition is generated (following a write start=1). an interrupt is generated if ite=1. it is cleared by software reading sr1 register followed by writing the address byte in dr register.it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no start condition 1: start condition generated 70 evf 0 tra busy btf adsl m/sl sb
52/80 st72272 i 2 c interface (cont'd) i 2 c status register 2 (sr2) read only reset value: 0000 0000 (00h) bit 7:5 = reserved. forced to 0 by hardware. bit 4 = af acknowledge failure . this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while af=1. 0: no acknowledge failure 1: acknowledge failure bit 3 = stopf stop detection (slave mode). this bit is set by hardware when a stop condition is detected on the bus after an acknowledge (if ack=1). an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while stopf=1. 0: no stop condition detected 1: stop condition detected bit 2 = arlo arbitration lost . this bit is set by hardware when the interface los- es the arbitration of the bus to another master. an interrupt is generated if ite=1. it is cleared by soft- ware reading sr2 register or by hardware when the interface is disabled (pe=0). after an arlo event the interface switches back automatically to slave mode (m/sl=0). the scl line is not held low while arlo=1. 0: no arbitration lost detected 1: arbitration lost detected bit 1 = berr bus error. this bit is set by hardware when the interface de- tects a misplaced start or stop condition. an inter- rupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the in- terface is disabled (pe=0). the scl line is not held low while berr=1. 0: no misplaced start or stop condition 1: misplaced start or stop condition bit 0 = gcal general call (slave mode). this bit is set by hardware when a general call ad- dress is detected on the bus while engc=1. it is cleared by hardware detecting a stop condition (stopf=1) or when the interface is disabled (pe=0). 0: no general call address detected on bus 1: general call address detected on bus 70 0 0 0 af stopf arlo berr gcal
53/80 st72272 i 2 c interface (cont'd) i 2 c clock control register (ccr) read / write reset value: 0000 0000 (00h) bit 7 = fm/sm fast/standard i 2 c mode. this bit is set and cleared by software. it is not cleared when the interface is disabled (pe=0). 0: standard i 2 c mode 1: fast i 2 c mode bit 6:0 = cc6-cc0 7-bit clock divider. these bits select the speed of the bus (f scl )de- pending on the i 2 c mode. they are not cleared when the interface is disabled (pe=0). standard mode (fm/sm=0): f scl <= 100khz f scl =f cpu /(2x([cc6..cc0]+2)) fast mode (fm/sm=1): f scl > 100khz f scl =f cpu /(3x([cc6..cc0]+2)) note: the programmed f scl assumes no load on scl and sda lines. i 2 c data register ( dr) read / write reset value: 0000 0000 (00h) bit 7:0 = d7-d0 8-bit data register. these bits contains the byte to be received or transmitted on the bus. transmitter mode: byte transmission start auto- matically when the software writes in the dr reg- ister. receiver mode: the first data byte is received au- tomatically in the dr register using the least sig- nificant bit of the address. then, the next data bytes are received one by one after reading the dr register. i 2 c own address register (oar) read / write reset value: 0000 0000 (00h) bit 7:1 = add7-add1 interface address . these bits define the i 2 c bus address of the inter- face. they are not cleared when the interface is disabled (pe=0). bit 0 = add0 address direction bit. this bit is don't care, the interface acknowledges either 0 or 1. it is not cleared when the interface is disabled (pe=0). note: address 01h is always ignored. 70 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0 70 d7 d6 d5 d4 d3 d2 d1 d0 70 add7 add6 add5 add4 add3 add2 add1 add0
54/80 st72272 i2c interface (cont'd) table 14. i 2 c register map address (hex.) register name 765 4 3210 5f cr pe engc start ack stop ite 5e sr1 evf tra busy btf adsl m/sl sb 5d sr2 af stopf arlo berr gcal 5c ccr fm/sm cc6 .. cc0 5b oar add7 .. add0 59 dr dr7 .. dr0
55/80 st72272 4.5 pwm/brm generator (dac) 4.5.1 introduction this pwm/brm peripheral includes a 6-bit pulse width modulator (pwm) and a 4-bit binary rate multiplier (brm) generator. it allows the digital to analog conversion (dac) when used with external filtering. 4.5.2 main features n fixed frequency: f cpu /64 n resolution: t cpu n steps of v dd /2 10 (5mv if v dd =5v) n 4 channels (pwm0-pwm3) 4.5.3 functional description the 10 bits of the 10-bit pwm/brm are distributed as 6 pwm bits and 4 brm bits. the generator con- sists of a 10-bit counter (common for all channels), a comparator and the pwm/brm generation logic. pwm generation the counter increments continuously, clocked at internal cpu clock. whenever the 6 least signifi- cant bits of the counter (defined as the pwm coun- ter) overflow, the output level for all active chan- nels is set. the state of the pwm counter is continuously compared to the pwm binary weight for each channel, as defined in the relevant pwm register, and when a match occurs the output level for that channel is reset. this pulse width modulated signal must be fil- tered, using an external rc network placed as close as possible to the associated pin. this pro- vides an analog voltage proportional to the aver- age charge passed to the external capacitor. thus for a higher mark/space ratio (high time much greater than low time) the average output voltage is higher. the external components of the rc net- work should be selected for the filtering level re- quired for control of the system variable. each output may individually have its polarity in- verted by software, and can also be used as a log- ical output. figure 30. pwm generation counter 63 compare value overflow overflow overflow 000 t pwm output t t cpu x64
56/80 st72272 pwm/brm generator (cont'd) pwm/brm outputs the pwm/brm outputs are assigned to dedicated pins. in these pins, the pwm/brm outputs are connect- ed to a serial resistor which must be taken into ac- count to calculate the rc filter (seefigure 31). in any case, the rc filter time must be higher than t cpu x64. figure 31. typical pwm output filter table 15. 6-bit pwm ripple after filtering with rc filter (r=1k w ), f cpu =8mhz v dd =5v pwm duty cycle 50% r=r int +r ext (rext is optional). note : after a reset these pins are tied low by de- fault and are not in a high impedance state. figure 32. pwm simplified voltage output after filtering 1k (max) c ext output voltage stage r int output r ext cext ( m f) v ripple (mv) 0.128 78 1.28 7.8 12.8 0.78 v dd 0v 0v dd v v ripple (mv) v outavg ochargeo odischargeo ochargeo odischargeo 0v v v 0v outavg v (mv) ripple v ochargeo odischargeo ochargeo odischargeo pwmout dd dd pwmout output voltage output voltage
57/80 st72272 pwm/brm generator (cont'd) brm generation the brm bits allow the addition of a pulse to wid- en a standard pwm pulse for specific pwm cy- cles. this has the effect of afine-tuningo the pwm duty cycle (without modifying the base duty cycle), thus, with the external filtering, providing additional fine voltage steps. the incremental pulses (with duration of t cpu )are added to the beginning of the original pwm pulse. the pwm intervals which are added to are speci- fied in the 4-bit brm register and are encoded as shown in the following table. the brm values shown may be combined together to provide a summation of the incremental pulse intervals specified. the pulse increment corresponds to the pwm res- olution. for example,if data 18h is written to the pwm register data 06h (00000110b) is written to the brm reg- ister with a 8mhz internal clock (125ns resolution) then 3.0 m s-long pulse will be output at 8 m s inter- vals, except for cycles numbered 2,4,6,10,12,14, where the pulse is broadened to 3.125 m s. note. if 00h is written to both pwm and brm reg- isters, the generator output will remain at a0o. con- versely, if both registers hold data 3fh and 0fh, respectively, the output will remain at a1o for all in- tervals 1 to 15, but it will return to zero at interval 0 for an amount of time corresponding to the pwm resolution (t cpu ). an output can be set to a continuous a1o level by clearing the pwm and brm values and setting pol = a1o (inverted polarity) in the pwm register. this allows a pwm/brm channel to be used as an additional i/o pin if the dac function is not re- quired. table 16. bit brm added pulse intervals (interval #0 not selected). figure 33. brm pulse addition (pwm > 0) brm 4 - bit data incremental pulse intervals 0000 none 0001 i = 8 0010 i = 4,12 0100 i = 2,6,10,14 1000 i = 1,3,5,7,9,11,13,15 t cpu x64 t cpu x64 t cpu x64 t cpu x64 increment m=1 m=0 m=2 t cpu x64 m=15
58/80 st72272 pwm/brm generator (cont'd) figure 34. simplified filtered voltage output schematic with brm added figure 35. graphical representation of 4-bit brm added pulse positions vdd pwmout 0v vdd output voltage 0v brm = 1 brm = 0 t cpu brm extended pulse == = 0100 bit2=1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pwm pulse number (0-15) brm value 0001 bit0=1 0001 bit0=1 0100 bit2=1 examples 0110 1111
59/80 st72272 pwm/brm generator (cont'd) figure 36. precision for pwm/brm tuning for vouteff (after filtering) 4.5.4 register description on a channel basis, the 10 bits are separated into two data registers: 4.5.4.1 pulse binary weight register channel 0 pulse binary weight register (pwm0) channel 1 pulse binary weight register (pwm1) channel 2 pulse binary weight register (pwm2) channel 3 pulse binary weight register (pwm3) read / write reset value 1000 0000 (80h) bit 7 = reserved (forced by hardware to a1o) bit 6 = pol polarity bit for channel i. 0: the channel i outputs is a a1o level during the bi- nary pulse and a a0o level after. 1: the channel i outputs is a a0o level during the bi- nary pulse and a a1o level after. bit 5:0 = p[5:0] pwm pulse binary weight for channel i. this register contains the binary value of the pulse. 4.5.4.2 brm registers channels 1+0 brm register (brm10) channels 3+2 brm register (brm32) read / write reset value: 0000 0000 (00h) this register defining the intervals where an incre- mental pulse is added to the beginning of the orig- inal pwm pulse. two brm channel values share the same register. bit 7:4 = b[7:4] brm bits (channel i+1). bit 3:0 = b[3:0] brm bits (channel i) note: from the programmer's point of view, the pwm and brm registers can be regarded as be- ing combined to give one data value. for example : effective (with external rc filtering) dac value 70 1 pol p5 p4 p3 p2 p1 p0 70 b7 b6 b5 b4 b3 b2 b1 b0 1polpppppp+bbbb 1polppppppbbbb
60/80 st72272 table 17. pwm (dac) register map address (hex.) register name 765 4 3210 24 pwm1 pol p5 ..p0 25 brm21 brm channel 2 brm channel 1 26 pwm2 pol p5 ..p0 27 pwm3 pol p5 ..p0 28 brm43 brm channel 4 brm channel 3 29 pwm4 pol p5 ..p0
61/80 st72272 4.6 8-bit a/d converter (adc) 4.6.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 8 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 8 different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control/status register. 4.6.2 main features n 8-bit conversion n up to 8 channels with multiplexed input n linear successive approximation n data register (dr) which contains the results n conversion complete status flag n on/off bit (to reduce consumption) the block diagram is shown infigure 37. figure 37. adc block diagram sample analog mux ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 0 coco ch0 ch1 ch2 - - adon (control status register) csr ad7 ad0 ad1 ad2 ad3 ad6 ad5 (data register) dr & hold f cpu analog to digital converter ad4
62/80 st72272 8-bit a/d converter (adc) (cont'd) 4.6.3 functional description the high level reference voltage v dda must be connected externally to the v dd pin. the low level reference voltage v ssa must be connected exter- nally to the v ss pin. in some devices (refer to de- vice pin out description) high and low level refer- ence voltages are internally connected to the v dd and v ss pins. conversion accuracy may therefore be degraded by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. characteristics the conversion is monotonic meaning the result never decreases if the analog input does not and never increases if the analog input does not. if input voltage is greater than or equal to v dd (voltage reference high) then results = ffh (full scale) without overflow indication. if input voltage v ss (voltage reference low) then the results = 00h. the conversion time is 64 cpu clock cycles in- cluding a sampling time of 31.5 cpu clock cycles. the a/d converter is linear and the digital result of the conversion is given by the formula: where reference voltage is v dd -v ss . the accuracy of the conversion is described in the electrical characteristics section. procedure refer to the csr and sr registers section 4.6.4 for the bit definitions. the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the csr register: select the ch2 to ch0 bits to assign the ana- log channel to convert. refer totable 18. set the adon bit. then the a/d converter is enabled after a stabilization time (typically 30 m s). it then performs a continuous conversion of the selected channel. when a conversion is complete the coco bit is set by hardware. no interrupt is generated. the result is in the dr register. a write to the csr register aborts the current con- version, resets the coco bit and starts a new conversion. notes: the a/d converter may be disabled by re- setting the adon bit. this feature allows reduced power consumption when no conversion is need- ed. the a/d converter is not affected by wait mode. when the mcu enters halt mode with the a/d converter enabled, the converter is disabled until the halt mode is exited and the start-up delay has elapsed. a stabilisation time is also required before accurate conversions can be performed. digital result = 255 * input voltage reference voltage
63/80 st72272 8-bit a/d converter (adc) (cont'd) 4.6.4 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7 = coco conversion complete. this bit is set by hardware. it is cleared by soft- ware reading the result in the dr register or writing to the csr register. 0: conversion is not complete. 1: conversion can be read from the dr register. bit 6 = reserved. must always be cleared. bit 5 = adon a/d converter on. this bit is set and cleared by software. 0: a/d converter is switched off. 1: a/d converter is switched on. note: a typically 30 m s delay time is necessary for the adc to stabilize when the adon bit is set. bit 4 = reserved. forced by hardware to 0. bit 3 = reserved. must always be cleared. bits 2-0: ch2-ch0 channel selection. these bits are set and cleared by software. they select the analog input to convert. table 18. channel selection (*the number of pins varies according to the de- vice. refer to the device pinout). data register (dr) read only reset value: 0000 0000 (00h) bit 7:0 = ad7-ad0 analog converted value. this register contains the converted analog value in the range 00h to ffh. reading this register reset the coco flag. table 19. adc register map 70 coco - adon 0 - ch2 ch1 ch0 pin* ch2 ch1 ch0 ain0 0 0 0 ain1 0 0 1 ain2 0 1 0 ain3 0 1 1 ain4 1 0 0 ain5 1 0 1 ain6 1 1 0 ain7 1 1 1 70 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 address (hex.) register name 765 4 3210 0b csr coco - adon 0 - ch2 ch1 ch0 0a dr ad7 .. ad0
64/80 st72272 5 instruction set 5.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 20. st7 addressing mode overview addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3
65/80 st72272 st7 addressing modes (cont'd) 5.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 5.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the the operand value. . 5.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 5.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 5.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
66/80 st72272 st7 addressing modes (cont'd) 5.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 21. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 5.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/indir ect instructions function jrxx conditional jump callr call relative
67/80 st72272 5.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent probate pockets are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret code condition flag modification sim rim scf rcf
68/80 st72272 instruction groups (cont'd) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned >
69/80 st72272 instruction groups (cont'd) jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m hinzc pop cc cc m push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z
70/80 st72272 6 electrical characteristics 6.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. for proper operation it is recommended that v i and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (v dd or v ss ). power considerations .the average chip-junc- tion temperature, t j , in celsius can be obtained from: t j = ta + pd x rthja where: t a = ambient temperature. rthja = package thermal resistance (junction-to ambient). p d =p int +p port p int =i dd xv dd (chip internal power). p port = port power dissipation (determined by the user). note: stresses above those listed as aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. symbol parameter value unit v dd supply voltage -0.3 to 6.0 v v dda analog reference voltage -0.3 to 6.0 v v i input voltage v ss - 0.3 to v dd + 0.3 v v o output voltage v ss - 0.3 to v dd + 0.3 v iv dd total current into v dd (source) tbd ma iv ss total current out of v ss (sink) tbd ma t j junction temperature 150 c t stg storage temperature -60 to 150 c
71/80 st72272 6.2 recommended operating conditions figure 38. maximum operating frequency (fmax) versus supply voltage (v dd ) note: the shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions. symbol parameter test condition s value unit min. typ. max. t a operating temperature 1 suffix version 0 70 c v dd operating supply voltage f cpu = 8 mhz f cpu = 4 mhz 4.5 4.0 5.5 5.5 v f osc oscillator frequency v dd = 4.0v v dd = 4.5v 0 0 12 24 mhz 2.5 3 3.5 4 4.5 5 5.5 6 supply volt age (v dd ) maximum 24 12 functi onality is not guaranteed in this area frequency (mhz)
72/80 st72272 6.3 dc electrical characteristics (t a = 0 to +70 c unless otherwise specified) notes: 1. hysteresis voltage between switching levels 2. cpu running with memory access. 3. all peripherals in stand-by 6.4 a/d converter characteristics (t a = 0 to +70 c unless otherwise specified) note : noise at av dd ,av ss <10mv symbol parameter test conditions value unit min. typ. max. v il input low level voltage all input pins v dd x 0.3 v v ih input high level voltage all input pins v dd x 0.7 v v hys hysteresis voltage 1) all input pins v dd = 5v tbd v v ol low level output voltage all output pins v dd = 5.0v; i ol = +10 m a v dd = 5.0v; i ol = + 1.6ma 0.1 0.4 v low level output voltage high sink i/o pins v dd = 5.0v; i ol = +10 m a v dd = 5.0v; i ol = +1.6ma v dd = 5.0v; i ol = +10ma 0.1 0.4 1.5 v oh high level output voltage all output pins v dd = 5.0v; i ol =-10 m a v dd = 5.0v; i ol = 1.6ma 4.9 4 v i il i ih input leakage current all input pins but reset v in =v ss (no pull-up configured) v in =v dd 0.1 10 m a input leakage current reset pin v in =v ss v in =v dd -50 10 i dd supply current in run mode 2) v dd = 5.0v f osc = 12 mhz, f cpu =4mhz f osc = 24 mhz, f cpu =8mhz tbd 14 tbd 18 ma supply current in slow mode 3) v dd = 5.0v f osc = 12 mhz, f cpu =2mhz f osc = 24 mhz, f cpu =4mhz tbd ma supply current in wait mode 3) v dd = 5.0v f osc = 12 mhz, f cpu =4mhz f osc = 24 mhz, f cpu =8mhz tbd 12 tbd 18 ma supply current in halt mode i load =0ma v dd = 5.0v 250 500 m a symbol parameter test condit ions value unit min. typ. max. res resolution 8 bit dle ile differential linearity error integral linearity error f osc = 24 mhz 0.3 0.5 1 lsb t c conversion time f cpu = 8 mhz 8 m s
73/80 st72272 6.5 pwm (dac) characteristics 6.6 i2c characteristics pwm/brm electrical and timings symbol parameter conditions min typ max unit f repetition rate t cpu = 125ns 125 khz res resolution t cpu = 125ns 125 ns s output step v dd = 5v, 10 bits 5 mv v dd = 5v, 12 bits 1.25 mv r s serial resistor - 700 1000 ohms i2c electrical specifications parameter symbol unit standard mode i2c fast mode i2c min max min max hysteresis of schmitt trigger inputs fixed input levels v dd -related input levels v hys v n/a n/a n/a n/a 0.2 0.05 v dd pulse width of spikes which must be sup- pressed by the input filter t sp ns n/a n/a 0 ns 50 ns output fall time from vih min to vil max with a bus capacitance from 10 pf to 400 pf with up to 3 ma sink current at vol1 with up to 6 ma sink current at vol2 t of ns n/a 250 n/a 20+0.1cb 20+0.1cb 250 250 input current each i/o pin with an input voltage between 0.4v and 0.9 v dd max i m a - 10 10 -10 10 capacitance for each i/o pin c pf 10 10 n/a = not applicable cb = capacitance of one bus in pf i2c bus timings parameter standard i2c fast i2c symbol unit min max min max bus free time between a stop and start con- dition 4.7 1.3 t buf ms hold time start condition. after this period, the first clock pulse is generated 4.0 0.6 t hd:sta m s low period of the scl clock 4.7 1.3 t low m s high period of the scl clock 4.0 0.6 t high m s set-up time for a repeated start condition 4.7 0.6 t su:sta m s data hold time 0 1) 0 1) 0.9 2) t hd:dat ns data set-up time 250 100 t su:dat ns rise time of both sda and scl signals 1000 20+0.1cb 300 tr ns fall time of both sda and scl signals 300 20+0.1cb 300 tf ns
74/80 st72272 notes: 1. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl. 2. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. set-up time for stop condition 4.0 0.6 t su:sto ns capacitive load for each bus line 400 400 cb pf i2c bus timings parameter standard i2c fast i2c symbol unit min max min max
75/80 st72272 7 general information 7.1 eprom erasure eprom version devices are erased by exposure to high intensity uv light admitted through the transparent window. this exposure discharges the floating gate to its initial state through induced photo current. it is recommended that the eprom devices be kept out of direct sunlight, since the uv content of sunlight can be sufficient to cause functional fail- ure. extended exposure to room level fluorescent lighting may also cause erasure. an opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting con- ditions. covering the window also reduces i dd in power-saving modes due to photo-diode leakage currents. an ultraviolet source of wave length 2537 ? yield- ing a total integrated dosage of 15 watt-sec/cm 2 is required to erase the device. it will be erased in 15 to 20 minutes if such a uv lamp with a 12mw/cm 2 power rating is placed 1 inch from the device win- dow without any interposed filters.
76/80 st72272 7.2 package mechanical data figure 39. 34-pin plastic small outline package figure 40. 32-pin shrink plastic dual in line package dim. mm inches min typ max min typ max a 2.46 2.64 0.097 0.104 a1 0.13 0.29 0.005 0.0115 b 0.36 0.48 0.014 0.019 c 0.23 0.32 0.0091 0.0125 d 17.73 18.06 0.698 0.711 e 7.42 7.59 0.292 0.299 e 1.02 0.040 h 10.16 10.41 0.400 0.410 h 0.64 0.74 0.025 0.029 k 0 8 l 0.61 1.02 0.024 0.040 number of pins n34 so34s dim. mm inches min typ max min typ max a 3.56 3.76 5.08 0.140 0.148 0.200 a1 0.51 0.020 a2 3.05 3.56 4.57 0.120 0.140 0.180 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.76 1.02 1.40 0.030 0.040 0.055 c 0.20 0.25 0.36 0.008 0.010 0.014 d 27.43 27.94 28.45 1.080 1.100 1.120 e 9.91 10.41 11.05 0.390 0.410 0.435 e1 7.62 8.89 9.40 0.300 0.350 0.370 e 1.78 0.070 ea 10.16 0.400 eb 12.70 0.500 l 2.54 3.05 3.81 0.100 0.120 0.150 number of pins n32 1 n b d vr01725j n/2 b1 e a l see lead detail e 1 e 3 a 2 a 1 e c e b e a
77/80 st72272 figure 41. 32-pin shrink ceramic dual in-line package dim. mm inches min typ max min typ max a 3.63 0.143 a1 0.38 0.015 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.64 0.89 1.14 0.025 0.035 0.045 c 0.20 0.25 0.36 0.008 0.010 0.014 d 29.41 29.97 30.53 1.158 1.180 1.202 d1 26.67 1.050 e 10.16 0.400 e1 9.45 9.91 10.36 0.372 0.390 0.408 e 1.78 0.070 g 9.40 0.370 g1 14.73 0.580 g2 1.12 0.044 l 3.30 0.130 7.37 0.290 number of pins n32 cdip32sw
78/80 st72272 7.3 ordering information each device is available for production in user pro- grammable version (otp) as well as in factory coded version (rom). otp devices are shipped to customer with a default blank content ffh, while rom factory coded parts contain the code sent by customer. there is one common eprom version for debugging and prototyping which features the maximum memory size and peripherals of the sub- family. care must be taken to only use resources available on the target device. contact sales office for further ordering informa- tion and availablity. 7.3.1 transfer of customer code customer code is made up of the rom contents and the list of the selected options (if any). the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file gener- ated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to sgs-thomson using the correctly completed option list appended. the sgs-thomson sales organization will be pleased to provide detailed information on con- tractual points. figure 42. rom factory coded device types figure 43. otp user programmable device types note: the ST72E272K4D0 (32-pin ceramic sdip) is used as the eprom version for the above devices. the eprom devices are tested for operation at 25 c only. device package temp. range xxx / code name (defined by sgs-thomson) 1= standard 0 to +70 c b= plastic dip m= plastic soic st72272k2 st72372k4 device package temp. range special feature (defined by sgs-thomson) 1= industrial -40 to +85 c b= plastic dip m= plastic soic st72t272k2 st72t272k4 xxx
79/80 st72272 st72272 microcontroller option list customer ............................. address ............................. ............................. contact ............................. phone no ............................. reference ............................. sgs-thomson microelectronics references device: [ ] st72272 package: [ ] dual in line plastic [ ] small outline plastic: [ ] standard (stick) [ ] tape & reel temperature range: [ ] 0 cto+70 c special marking: [ ] no [ ] yes o_ _ _________o authorized characters are letters, digits, '.', '-', '/' and spaces only. maximum character count: sdip32: 10 so34: 16 comments : supply operating range in the application: oscillator frequency in the application: notes ............................. signature ............................. date .............................
80/80 st72272 notes information furnished is believed to be accurate andreliable. however, sgs-tho mson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomso n microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-tho mson microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of sgs-thomson microelectronics. ? 1998 sgs-tho mson microelectronics - all rights reserved. purchase of i 2 c components by sgs-thomson microelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a.

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