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ultrafast 3.3 v single-supply comparators preliminary technical data adcmp572/adcmp573 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features 3.3 v/5.2 v single-supply operation 150 ps propagation delay 15 ps overdrive and slew rate dispersion 8 ghz equivalent input bandwidth 100 ps minimum pulse width 35 ps typical output rise/fall 5 ps deterministic jitter (dj) 1 ps random jitter (rj) on-chip terminations at both input pins robust inputs with no output phase reversal resistor programmable hysteresis differential latch control power supply rejection > 70 db applications automatic test equipment (ate) high speed instrumentation pulse spectroscopy medical imaging and diagnostics high speed line receivers threshold detection peak and zero-crossing detectors high speed trigger circuitry clock and data signal restoration functional block diagram v p noninverting input v tp termination v tn termination v n inverting input le input rh input q output q output le input 04409-0-025 adcmp572 adcmp573 cml/ rspecl v cco v cci figure 1. general description the adcmp572/adcmp573 are ultrafast comparators fabricated on analog devices, inc.s proprietary xfcb3 silicon germanium (sige) bipolar process. the adcmp572 features cml output drivers, and the adcmp573 features reduced swing pecl (rspecl) output drivers. both devices offer 150 ps propagation delay and 100 ps minimum pulse width for 10 gbps operation with 5 ps deterministic jitter (dj) and 1 ps rms random jitter (rj). overdrive and slew rate dispersion is typically less than 15 ps. a flexible power supply scheme allows either device to operate with a single +3.3 v positive supply and a ?0.2 v to +1.2 v input signal range, or with split input/output supplies to support a wider ?0.2 v to +3.2 v input signal range and an independent range of output levels. 50 ? on-chip termination resistors are provided at both inputs with the optional capability to leave open (on an individual pin basis) for applications requiring high impedance inputs. the cml output stage is designed to directly drive 400 mv into 50 ? transmission lines terminated to between 3.3 v to 5.2 v. the rspecl output stage is designed to drive 400 mv into 50 ? terminated to v cco ? 2 v and is compatible with several commonly used pecl logic families. the comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. high speed latch and programmable hysteresis features are also provided. the adcmp572/adcmp573 are available in a 16-lead lfcsp package.
adcmp572/adcmp573 preliminary technical data rev. pra | page 2 of 16 table of contents electrical characteristics ................................................................. 3 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 esd protection circuit ................................................................ 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 7 application in formation.................................................................. 9 power/ground layout and bypassing ....................................... 9 cml/rspecl output stage ....................................................... 9 using/disabling the latch feature..............................................9 optimizing high speed performance ..................................... 10 comparator propagation delay dispersion .......................... 10 comparator hysteresis .............................................................. 11 minimum input slew rate requirement ................................ 11 typical application circuits.......................................................... 12 timing information ....................................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14
preliminary technical data adcmp572/adcmp573 rev. pra | page 3 of 16 electrical characteristics v cci = v cco = 3.3 v, t a = 25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit dc input characteristics 1 input offset voltage v os ?5.0 2.0 +5.0 mv input voltage range v p , v n v cci = 3.3 v, v cco = 3.3 v ?0.2 +1.2 v v cci = 5.2 v, v cco = 3.3 v ?0.2 +3.2 v offset voltage tempco ? v os /dt 10.0 v/c input bias current i p , i n open termination ?50.0 ?25.0 0.0 a input bias current tempco 50.0 na/c input offset current ?5.0 2.0 +5.0 a input capacitance c p , c n tbd pf input resistance, differential mode open termination 50 k? input resistance, common mode open termination 500 k? max safe input differential v cci v active gain a v 54 db v cci = 3.3 v, v cco = 3.3 v, v cm = 0.0 v to 1.0 v 50 db common-mode rejection cmr v cci = 5.2 v, v cco = 3.3 v, v cm = 0.0 v to 3.0 v 40 db hysteresis rh = 1 mv latch enable characteristics adcmp572 latch enable input high v ih v il +0.2 v cco v cco +0.2 v latch enable input low v il 2.8 v ih ?0.4 v ih ?0.2 v latch setup time t s v od = 100 mv 0 ps latch hold time t h v od = 100 mv 10 ps adcmp573 latch enable input high v ih v il +0.2 v cco ?0.8 v cco ?0.6 v latch enable input low v il 1.8 v ih ?0.4 v ih ?0.2 v latch setup time t s v od = 100 mv 0 ps latch hold time t h v od = 100 mv 10 ps latch enable input impedance 47.5 50.0 52.5 ? latch to output delay t ploh, t plol v od = 100 mv 150 ps latch minimum pulse width t pl v od = 100 mv 100 ps dc output characteristics adcmp572 (cml) output impedance z out 47.5 50.0 52.5 ? output voltage high v oh 50 ? terminate to v cco v cco ?0.10 v cco ?0.05 v cco v output voltage low v ol 50 ? terminate to v cco v oh ?0.45 v oh ?0.40 v oh ?0.35 v output voltage differential 50 ? terminate to v cco 350 400 450 mv temperature coefficient, v oh ? v oh /dt 50 ? terminate to v cco tbd mv/c temperature coefficient, v ol ? v ol /dt 50 ? terminate to v cco tbd mv/c adcmp573 (rspecl) output voltage high v oh 50 ? terminate to v cco ?2.0 v cco ?0.90 v cco ?0.80 v cco ?0.70 v output voltage low v ol 50 ? terminate to v cco ?2.0 v oh ?0.45 v oh ?0.40 v oh ?0.35 v output voltage differential 50 ? terminate to v cco ?2.0 350 400 450 mv 1 under no circumstances should the input voltages exceed the supply voltages by more than 0.5 v.
adcmp572/adcmp573 preliminary technical data rev. pra | page 4 of 16 parameter symbol conditions min typ max unit ac performance propagation delay t pd v cci = 3.3 v, v od = 200 mv 150 170 ps v cci = 3.3 v, v od = 20 mv 165 ps v cci = 5.2 v, v od = 200 mv 145 ps propagation delay tempco ? t pd /dt 0.5 ps/c prop delay skewrising transition to falling transition v od = 200 mv, 1 v/ns 10 ps v cci = 3.3 v, 1 v/ns input 5 propagation delay vs. duty cycle v cci = 5.2 v, 1 v/ns input 10 ps pulse width dispersion ? t pd / ? pw 100 ps to 10 ns 5 10 ps 50 mv to 1.0 v 10 overdrive dispersion ? t pd / ? v od 5 mv to 1.0 v 15 ps ps slew rate dispersion 1 v/ ns to 10 v/ns, 50% 15 ps propagation delay vs. common-mode voltage ? t pd / ? v cm 5 ps/v equivalent input bandwidth bw eq 0.0 v to 400 mv input t r = t f = 35 ps, 20/80 6.0 8.0 ghz toggle rate 10.0 12.5 gbps deterministic jitter dj v od = 200 mv, 5 v/ns, prbs 32 ?1 nrz, 10 gbps 5 ps rms random jitter rj v od = 200 mv, 5 v/ns, 5 ghz, 50% duty cycle 1 ps minimum pulse width pw min ? t pd / ? pw < 5 ps 100 ps rise time t r 20/80 35 ps fall time t f 20/80 35 ps power supply input supply voltage range v cci 3.1 5.4 v output supply voltage range v cco 3.1 5.4 v positive supply differential v cci ?v cco ?0.2 +2.3 v adcmp572 (cml) v cci = 3.3 v, v cco = 3.3 v, terminate 50 ? to v cco 44 52 positive supply current i vcci + i vcco v cci = 5.2 v, v cco = 5.2 v, terminate 50 ? to v cco 44 52 ma v cci = 3.3 v, v cco = 3.3 v, terminate 50 ? to v cco 145 160 power dissipation p d v cci = 5.2 v, v cco = 5.2 v, terminate 50 ? to v cco 240 265 mw adcmp573 (rspecl) v cci = 3.3 v, v cco = 3.3 v, 50 ? to v cco ? 2 v 66 74 positive supply current i vcci + i vcco v cci = 5.2 v, v cco = 5.2 v, 50 ? to v cco ? 2v 68 76 ma v cci = 3.3 v, v cco = 3.3 v, 50 ? to v cco ? 2v 145 160 power dissipation p d v cci = 5.2 v, v cco = 5.2 v, 50 ? to v cco ? 2v 175 195 mw power supply rejectionv cci psr vcci v cci =3.3 v 5%, v cco = 3.3 v 74 db
preliminary technical data adcmp572/adcmp573 rev. pra | page 5 of 16 absolute maximum ratings table 2. parameter rating supply voltages input supply voltage (v cci to gnd) ?0.5 v to +6.0 v output supply voltage (v cco to gnd) ?0.5 v to +6.0 v positive supply differential (v cci ? v cco ) ?0.5 v to +3.5 v input voltages input voltage ?0.5 v to v cci + 0.5 v differential input voltage ( v cci + 0.5 v) input voltage, latch enable ?0.5 v to v cco + 0.5 v hysteresis control pin applied voltage (rh to gnd) ?0.5 v to +1.5 v maximum input/output current 1 ma output current adcmp572 (cml) 100 ma adcmp573 (rspecl) ?35 ma temperature operating temperature, ambient 0c to 85c operating temperature, junction 150c storage temperature range ?65c to +150c lead temperature (10 sec) 300c thermal considerations the adcmp572/adcmp573 lfcsp 16-lead package has a ja (junction to ambient thermal resistance) of 70c/w in still air. stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. esd protection circuit all input and output pins contain analog devices proprietary esd protection diodes. v cc gnd input 04409-0-012 figure 2. equivalent esd protection circuit
adcmp572/adcmp573 preliminary technical data rev. pra | page 6 of 16 pin configuration and fu nction descriptions 04409-0-026 5 v cci 6 le 7 le 8 v cco /v tt adcmp572 adcmp573 top view (not to scale) 1 v tp pin1 2 v p 3 v n 4 v tn 16 v cci 15 gnd 14 rh 13 gnd v ccq 12 q 11 q 10 v cco 9 figure 3. adcmp572/adcmp573 pin configuration table 3. pin function descriptions pin no. mnemonic description 1 v tp termination resistor return pin for v p input. 2 v p noninverting analog input. 3 v n inverting analog input. 4 v tn termination resistor return pin for v n input. 5, 16 v cci positive supply voltage for input stage. 6 le latch enable input pin, inverting side. in compare mode (le = low), the output tracks changes at the input of the comparator. in latch mode (le = high), the output reflects the input st ate just prior to the comparators being placed in latch mode. le must be driven in compliment with le. 7 le latch enable input pin, noninverting side. in compare mode (le = high), the output tracks changes at the input of the comparator. in latch mode (le = low), the outp ut reflects the input state just prior to the comparators being placed in latch mode. le must be driven in compliment with le . 8 v cco /v tt termination return pin for the le/le input pins. for the adcmp572 (cml output stage), this pin should be connected to the positive v cco supply. for the adcmp573 (rspecl output stage), th is pin should be connected to the v cco C 2 v termination potential. 13, 15 gnd ground. 9, 12 v cco positive supply voltage for the cml/rspecl output stage. 10 q inverting output. q is at logic low if the analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n , provided the comparator is in compare mode. see the le/le description (pins 6 and 7) for more information. 11 q noninverting output. q is at logic high if th e analog voltage at the noninverting input v p is greater than the analog voltage at the inverting input, v n , provided the comparator is in compare mode. see the le/le description (pins 6 and 7) for more information. 14 rh hysteresis control pin. leave this pin disconnect ed for zero hysteresis. connect to gnd with a suitably sized resistor to add the desired amount of hysteresis. refer to figure 9 for proper sizing of rh hysteresis control resistor. heatsink n/c the metallic back surface of the package is not electric ally connected to any part of the circuit, and it can be left floating for best elec trical isolation between the packag e handle and the substrate of the die. but it can also be soldered to the applic ation board if improved th ermal and/or mechanical stability is desired.
preliminary technical data adcmp572/adcmp573 rev. pra | page 7 of 16 typical performance characteristics v cci = v cco = 3.3 v, t a = 25c, unless otherwise noted. figure 4. propagation delay vs. input overdrive figure 5. propagation delay vs. input slew rate figure 6. propagation delay vs. input common mode figure 7. propagation delay vs. temperature figure 8. rise/fall time vs. temperature figure 9. hysteresis vs. rh control resistor
adcmp572/adcmp573 preliminary technical data rev. pra | page 8 of 16 figure 10. input bias current vs. input differential figure 11. input bias current vs. input common mode figure 12. input bias current vs. temperature figure 13. input offset voltage vs. temperature figure 14. output levels vs. temperature
preliminary technical data adcmp572/adcmp573 rev. pra | page 9 of 16 application information power/ground layout and bypassing the adcmp572/adcmp573 comparators are very high speed sige devices. consequently, it is essential to use proper high speed design techniques to achieve the specified performance. of critical importance is the use of low impedance supply planes, particularly the output supply plane (v cco ) and the ground plane (gnd). individual supply planes are recom- mended as part of a multilayer board. providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. it is also important to adequately bypass the input and output supplies. a 1 f electrolytic bypass capacitor should be placed within several inches of each power supply pin to ground. in addition, multiple high quality 0.1 f bypass capacitors should be placed as close as possible to each of the v cci and v cco supply pins and should be connected to the gnd plane with redundant vias. high frequency bypass capacitors should be carefully selected for minimum inductance and esr. parasitic layout inductance should also be strictly avoided to maximize the effectiveness of the bypass at high frequencies. if the input and output supplies are connected separately such that v cci v cco , then care should be taken to bypass each of these supplies separately to the gnd plane. a bypass capacitor should not be connected between them. it is recommended that the gnd plane separate the v cci and v cco planes when the circuit board layout is designed to minimize coupling between the two supplies and to take advantage of the additional bypass capacitance from each respective supply to the ground plane. this enhances the performance when split input/output supplies are used. if the input and output supplies are connected together for single-supply operation such that v cci = v cco , then coupling between the two supplies is unavoidable; however, every effort should be made to keep the supply plane adjacent to the gnd plane to maximize th e additional bypass capacitance this arrangement provides. cml/rspecl output stage specified propagation delay dispersion performance can be achieved only by using proper transmission line terminations. the outputs of the adcmp572 are designed to directly drive 400 mv into 50 ? cable or microstrip and/or stripline transmis- sion lines properly terminated to the v cco supply plane. the cml output stage is shown in the simplified schematic diagram in figure 15. the outputs are each back-terminated with 50 ? for best transmission line matching. the rspecl outputs of the adcmp573 are illustrated in figure 16and should be terminated to v cco ? 2 v. as an alternative, thevenin equivalent termina- tion networks may also be used in either case if the direct termination voltage is not readily available. if high speed output signals must be routed more than a centimeter, microstrip or stripline techniques are essential to ensure proper transition times and to prevent output ringing and pulse-width dependant propagation delay dispersion. for the most timing critical applications where transmission line reflections pose the greatest risk to performance, the adcmp572 provides the best match to 50 ? output transmission paths. q 16ma 50 ? q 04409-0-037 v cco gnd figure 15. simplified schematic diagram of the adcmp572 cml output stage 4ma 100 ? 04409-0-038 v cco gnd q q figure 16. simplified schematic diagram of the adcmp573 rspecl output stage using/disabling the latch feature the latch inputs (le/ le ) are active low for latch mode, and are internally terminated with 50 ? resistors to pin 8. this corresponds to the v cco supply for the adcmp572 and the v tt pin for the adcmp573. all v cco pins should be connected to the supply plane for maximum performance, and the v tt pin should be connected externally to v cco C 2 v, preferably to its own low inductance plane. when using the adcmp572, the latch function can be disabled by connecting the le pin to gnd with an external pull-down resistor and leaving the le pin unconnected. to prevent excessive power dissipation, the resistor should be 750 ? when v cco = 3.3 v, and 1.2 k? when
adcmp572/adcmp573 preliminary technical data rev. pra | page 10 of 16 v cco = 5.2 v. when using the adcmp573 comparator, the latch can be disabled by connecting the le pin to v cco with an external 500 ? resistor, and leaving the le pin disconnected. in this case, the resistor value does not depend on the chosen v cco supply voltage, assuming the v tt pin is properly connected to v cco C 2 v. optimizing high speed performance as with any high speed comparator, proper design and layout techniques are essential to obtaining the specified performance. stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and can often cause oscillation. discontinuities along input and output transmission lines can also severely limit the specified pulse-width dispersion performance. for applications working in a 50 ? environment, input and output matching has a significant impact on data dependant (or deterministic) jitter (dj) and pulse-width dispersion perform- ance. the adcmp572/adcmp573 comparators provide internal 50 ? termination resistors for both v p and v n inputs, and the adcmp572 provides 50 ? back terminated outputs. the return side for each input termination is pinned out separately with the v tp and v tn pins, respectively. if a 50 ? termination is desired at one or both of the v p /v n inputs, then the v tp and v tn pins can be connected (or disconnected) to (from) the desired termination potential as required. the termination potential should be carefully bypassed using high quality bypass capacitors as discussed above to prevent undesired aberrations on the input signal due to parasitic inductance in the circuit board layout. if a 50 ? input termination is not desired, either one or both of the v tp /v tn termination pins can be left disconnected. in this case, the pins should be left floating with no external pull-downs or bypassing capacitors. it should be understood that when leaving an input termination disconnected, the internal resistor acts as a small stub on the input transmission path and can cause problems for very high speed inputs. reflections should then be expected from the comparator inputs because they no longer provide a matched impedance to the input path leading to the device. it then becomes important to back-match the drive source impedance to the input transmission path to minimize multiple reflections. for applications in which the comparator is very close to the driving signal source, the source impedance should be mini- mized. high source impedance in combination with parasitic input capacitance of the comparator could cause an undesirable degradation in bandwidth at the input, thus degrading the overall response. although the adcmp572/ adcmp573 comparators have been designed to minimize input capacitance, some parasitic capacitance is inevitable. it is therefore recommended that the drive source impedance be no more than 50 ? for best high speed performance. comparator propagation delay dispersion the adcmp572/adcmp573 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mv to 500 mv. propagation delay dispersion is a variation in propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold). propagation delay dispersion is a specification that becomes important in high speed time critical applications such as data communication, automatic test and measurement, instrumenta- tion, and event-driven applications such as pulse spectroscopy, nuclear instrumentation, and medical imaging. dispersion is defined as the variation in propagation delay as the input over- drive conditions are changed (figure 17 and figure 18). for the adcmp572/adcmp573, dispersion is typically <15 ps because the overdrive is varied from 5 mv to 500 mv, and the input slew rate is varied from 1 v/ns to 10 v/ns. this specification applies for both positive and negative signals since the adcmp572/ adcmp573 has substantially equal delays for either positive- going or negative-going inputs. q/q output input voltage 500mv overdrive 20mv overdrive dispersion v n v os 04409-0-027 figure 17. propagation delayoverdrive dispersion q/q output input voltage 10v/ns 1v/ns dispersion v n v os 04409-0-028 figure 18. propagation delayslew rate dispersion
preliminary technical data adcmp572/adcmp573 rev. pra | page 11 of 16 comparator hysteresis the addition of hysteresis to a comparator is often desirable in a noisy environment or when the differential input amplitudes are relatively small or slow moving. the transfer function for a comparator with hysteresis is shown in figure 19. if the input voltage approaches the threshold (0.0 v in this example) from the negative direction, the comparator switches from a low to a high when the input crosses +v h /2. the new switching threshold becomes ?v h /2. the comparator remains in the high state until the threshold ?v h /2 is crossed from the positive direction. in this manner, noise centered on 0.0 v input does not cause the comparator to switch states unless it exceeds the region bounded by v h /2. output input 0 v ol v oh +v h 2 ?v h 2 04409-0-005 figure 19. comparator hysteresis transfer function the customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. a limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. the external feedback network can also introduce significant parasitics that reduce high speed performance, and can even induce oscillation in some cases. an alternative method for applying hysteresis is to introduce a small static differential voltage between the le and le inputs. hysteresis generated in this manner is independent of output swing and is symmetric around the switching threshold. a limitation of this approach is that the amount of hysteresis rapidly becomes a strong function of the le/ le input differential, and can be become difficult to predict and control accurately. the typical variation of hysteresis with le/ le differential input voltage is shown in figure 20. figure 20. comparator hysteresis vs. latch enable differential input the adcmp572/adcmp573 comparators offer another programmable hysteresis feature that can significantly improve the accuracy and stability of the desired hysteresis. by connecting an external pull-down resistor from the rh pin to gnd, a variable amount of hysteresis can be applied. leaving the rh pin disconnected disables the feature, and hysteresis is then less than 1 mv as specified. the maximum hysteresis that can be applied using this method is approximately 25 mv. figure 21 illustrates the amount of hysteresis applied as a function of external resistor va lue. the advantages of applying hysteresis in this manner are im proved accuracy, stability, and reduced component count. an ex ternal bypass capacitor is not recommended on the rh pin because it would likely degrade the jitter performance of the device. figure 21. hysteresis vs. rh control resistor minimum input slew rate requirement as with all high speed comparators, a minimum slew rate requirement must be met to ensure that the device does not oscillate as the input signal crosses the threshold. this oscillation is due in part to the high input bandwidth of the comparator and the feedback parasitics inherent in the package. analog devices recommends a minimum slew rate of 50 v/s to ensure a clean output transition from the adcmp572/ adcmp573 comparators unless hysteresis is programmed as discussed previously.
adcmp572/adcmp573 preliminary technical data rev. pra | page 12 of 16 typical application circuits q 3.3v 50 ? 50 ? adcmp572 q v in v p v tp v tn v n latch inputs 04409-0-029 v cci v cco figure 22. zero-crossing detector with 3.3 v cml outputs q 50 ? 50 ? q v p v n v p v tp v tn v n latch inputs 04409-0-030 v cci = 5.2v adcmp572 v cco figure 23. lvds to50 ? back-terminated (rs)pecl receiver 50 ? 50 ? + ? q q v in v th latch inputs gnd = ?1v 04409-0-031 v cci = 3.3v v cco = 2.5v/3.3v 2.5v/3.3v adcmp572 figure 24. comparator with 1 v input range and 2.5 v or 3.3 v cml outputs 50 ? 50 ? q q v in v th latch inputs 04409-0-032 v cci = 5.2v v cco = 3.3v/5.2v 3.3v/5.2v adcmp572 figure 25. comparator with 0 v to 3 v input range and 3.3 v or 5.2 v positive cml outputs latch inputs 04409-0-034 v cci v cco = 3.3v 5v 75 ? 50 ? 50 ? 100 ? 100 ? adcmp572 figure 26. interfacing 3.3 v cml to a 50 ? ground terminated instrument v cco v p v n v cco = 3.3v v cco 750 ? 04409-0-035 v cci adcmp572 50 ? 50 ? figure 27. disabling the latch feature rh v cco v cco 04409-0-036 v cci adcmp572 50 ? 50 ? 0 ? to 5k ? figure 28. adding hysteresis using the rh control pin
preliminary technical data adcmp572/adcmp573 rev. pra | page 13 of 16 timing information figure 29 illustrates the adcmp572/adcmp573 compare and latch timing relationships. table 4 provides a definition of the terms shown in the figure. 50% 50% v n v os 50% differential input voltage latch enable q output q output latch enable t h t pdl t pdh t ploh t plol t r t f v in v od t s t pl 04409-0-003 figure 29. system timing diagram table 4. timing descriptions symbol timing description t pdh input to output high delay propagation delay measured from the time th e input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. t pdl input to output low delay propagation delay measured from the time th e input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. t ploh latch enable to output high delay propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. t plol latch enable to output low delay propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. t h minimum hold time minimum time after the negative transition of th e latch enable signal that the input signal must remain unchanged to be acqu ired and held at the outputs. t pl minimum latch enable pulse width minimum ti me that the latch enable si gnal must be high to acquire an input signal change. t s minimum setup time minimum time before the negative transition of the latch enable signal that an input signal change must be present to be acquired and held at the outputs. t r output rise time amount of time required to transition from a low to a high output as measured at the 20% and 80% points. t f output fall time amount of time required to transition from a high to a low output as measured at the 20% and 80% points. v od voltage overdrive difference between the input voltages v a and v b .
adcmp572/adcmp573 preliminary technical data rev. pra | page 14 of 16 outline dimensions 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq 1.65 1.50 sq * 1.35 bottom view 16 5 13 8 9 12 4 * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension figure 30. 16-lead lead frame chip scale package [lfcsp] (cp-16) dimensions shown in millimeters ordering guide model temperature range package description package option adcmp572jcp 0c to 70c lfcsp-16 cp-16 ADCMP573JCP 0c to 70c lfcsp-16 cp-16
preliminary technical data adcmp572/adcmp573 rev. pra | page 15 of 16 notes
adcmp572/adcmp573 preliminary technical data rev. pra | page 16 of 16 notes ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr04409C0C2/04(pra)

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