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  www.irf.com 1 12/10/04 irfr220npbf irfu220npbf smps mosfet hexfet   power mosfet  high frequency dc-dc converters benefits applications  low gate to drain charge to reduce switching losses  fully characterized capacitance including effective c oss to simplify design, (see app. note an1001)  fully characterized avalanche voltage and current v dss r ds(on) max (m ?) i d 200v 600 5.0a typical smps topologies  telecom 48v input forward converters parameter max. units i d @ t c = 25c continuous drain current, v gs @ 10v 5.0 i d @ t c = 100c continuous drain current, v gs @ 10v 3.5 a i dm pulsed drain current  20 p d @t c = 25c power dissipation 43 w linear derating factor 0.71 w/c v gs gate-to-source voltage 20 v dv/dt peak diode recovery dv/dt  7.5 v/ns t j operating junction and -55 to + 175 t stg storage temperature range soldering temperature, for 10 seconds 300 (1.6mm from case ) c absolute maximum ratings 
notes   through  are on page 10 d-pak irfr22on i-pak irfu220n  lead-free

 2 www.irf.com parameter min. typ. max. units conditions g fs forward transconductance 2.6 ??? ??? s v ds = 50v, i d = 2.9a q g total gate charge ??? 15 23 i d = 2.9a q gs gate-to-source charge ??? 2.4 3.6 nc v ds = 160v q gd gate-to-drain ("miller") charge ??? 6.1 9.2 v gs = 10v, t d(on) turn-on delay time ??? 6.4 ??? v dd = 100v t r rise time ??? 11 ??? i d = 2.9a t d(off) turn-off delay time ??? 20 ??? r g = 24 ? t f fall time ??? 12 ??? v gs = 10v  c iss input capacitance ??? 300 ??? v gs = 0v c oss output capacitance ??? 53 ??? v ds = 25v c rss reverse transfer capacitance ??? 15 ??? pf ? = 1.0mhz c oss output capacitance ??? 300 ??? v gs = 0v, v ds = 1.0v, ? = 1.0mhz c oss output capacitance ??? 23 ??? v gs = 0v, v ds = 160v, ? = 1.0mhz c oss eff. effective output capacitance ??? 46 ??? v gs = 0v, v ds = 0v to 160v  dynamic @ t j = 25c (unless otherwise specified) ns parameter typ. max. units e as single pulse avalanche energy  ??? 46 mj i ar avalanche current  ??? 2.9 a e ar repetitive avalanche energy  ??? 4.3 mj avalanche characteristics s d g parameter min. typ. max. units conditions i s continuous source current mosfet symbol (body diode) ??? ??? showing the i sm pulsed source current integral reverse (body diode)  ??? ??? p-n junction diode. v sd diode forward voltage ??? ??? 1.3 v t j = 25c, i s = 2.9a, v gs = 0v  t rr reverse recovery time ??? 90 140 ns t j = 25c, i f = 2.9a q rr reverse recoverycharge ??? 320 480 nc di/dt = 100a/s   t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by l s +l d ) diode characteristics 5.0 20  static @ t j = 25c (unless otherwise specified) parameter min. typ. max. units conditions v (br)dss drain-to-source breakdown voltage 200 ??? ??? v v gs = 0v, i d = 250a ? v (br)dss / ? t j breakdown voltage temp. coefficient ??? 0.23 ??? v/c reference to 25c, i d = 1ma  r ds(on) static drain-to-source on-resistance ??? ??? 600 m ? v gs = 10v, i d = 2.9a  v gs(th) gate threshold voltage 2.0 ??? 4.0 v v ds = v gs , i d = 250a ??? ??? 25 a v ds = 200v, v gs = 0v ??? ??? 250 v ds = 160v, v gs = 0v, t j = 150c gate-to-source forward leakage ??? ??? 100 v gs = 20v gate-to-source reverse leakage ??? ??? -100 na v gs = -20v i gss i dss drain-to-source leakage current parameter typ. max. units r jc junction-to-case ??? 3.5 r ja junction-to-ambient (pcb mount)* ??? 50 c/w r ja junction-to-ambient ??? 110 thermal resistance

 www.irf.com 3 fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 0.01 0.1 1 10 100 0.1 1 10 100 20s pulse width t = 25 c j top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.5v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.5v 0.1 1 10 100 0.1 1 10 100 20s pulse width t = 175 c j top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.5v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.5v 0.1 1 10 100 4.0 5.0 6.0 7.0 8.0 9.0 10.0 v = 50v 20s pulse width ds v , gate-to-source voltage (v) i , drain-to-source current (a) gs d t = 25 c j t = 175 c j -60 -40 -20 0 20 40 60 80 100 120 140 160 180 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 t , junction temperature ( c) r , drain-to-source on resistance (normalized) j ds(on) v = i = gs d 10v 4.8a

 4 www.irf.com fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 0 5 10 15 20 25 0 4 8 12 16 20 q , total gate charge (nc) v , gate-to-source voltage (v) g gs for test circuit see figure i = d 13 2.9a v = 40v ds v = 100v ds v = 160v ds 0.1 1 10 100 0.4 0.6 0.8 1.0 1.2 v ,source-to-drain voltage (v) i , reverse drain current (a) sd sd v = 0 v gs t = 25 c j t = 175 c j 0.1 1 10 100 1 10 100 100 0 operation in this area limited by r ds(on) single pulse t t = 175 c = 25 c j c v , drain-to-source voltage (v) i , drain current (a) i , drain current (a) ds d 10us 100us 1ms 10ms 1 10 100 1000 v ds , drain-to-source voltage (v) 1 10 100 1000 10000 c , c a p a c i t a n c e ( p f ) coss crss ciss v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd

 www.irf.com 5 fig 10a. switching time test circuit v ds 9 0% 1 0% v gs t d(on) t r t d(off) t f fig 10b. switching time waveforms   
 1     0.1 %          + -   fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature 0.01 0.1 1 10 0.000001 0.00001 0.0001 0.001 0.01 0.1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response) 25 50 75 100 125 150 175 0.0 1.0 2.0 3.0 4.0 5.0 t , case temperature ( c) i , drain current (a) c d

 6 www.irf.com 25 50 75 100 125 150 175 0 20 40 60 80 starting t , junction temperature ( c) e , single pulse avalanche energy (mj) j as i d top bottom 1.2a 2.1a 2.9a q g q gs q gd v g charge d.u.t. v d s i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - fig 13b. gate charge test circuit fig 13a. basic gate charge waveform fig 12c. maximum avalanche energy vs. drain current fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v

 www.irf.com 7 p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop r e-applied v oltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - fig 14. for n-channel hexfet   power mosfets    
    
             ?     ?    ?      ! "" ? #   $   $    ?  %&    ? ' (  ?  %)  $   

 8 www.irf.com  

  

  
         12 in the assembly line "a" ass embled on ww 16, 1999 example: with assembly t his is an irfr120 lot code 1234 ye ar 9 = 199 9 dat e code we e k 16 part number logo int ernat ional rect ifier as s e mb l y lot code 916a irf u120 34 year 9 = 1999 dat e code or p = de s i gnat e s l e ad- f r e e product (opt ional) note: "p" in ass embly line position i ndicates "l ead-f r ee" 12 34 week 16 a = assembly site code part number irfu120 line a logo lot code assembly int ernational rect ifier

 www.irf.com 9  
   
          
  assembly example: wit h as s e mb l y this is an irfu120 year 9 = 199 9 dat e code line a week 19 in the as sembly line "a" as s emble d on ww 19, 1999 lot code 5678 part number 56 irf u120 international logo rectifier lot code 919a 78 note: "p" in as s embly line pos i ti on i ndi cates "l ead- f r ee"  56 78 as s e mb l y lot code rectifier logo international irf u120 part number we e k 19 dat e code year 9 = 1999 a = as s e mb l y s i t e code p = de s ignat es lead-f ree product (opt ional)

 10 www.irf.com   repetitive rating; pulse width limited by max. junction temperature.  i sd 2.9a, di/dt 320a/s, v dd v (br)dss , t j 175c 
  starting t j = 25c, l = 11mh r g = 25 ? , i as = 2.9a.  pulse width 400s; duty cycle 2%.  c oss eff. is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80% v dss * when mounted on 1" square pcb (fr-4 or g-10 material). for recommended footprint and soldering techniques refer to application note #an-994. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . data and specifications subject to change without notice. 12/04  

  
         tr 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) 12.1 ( .476 ) 11.9 ( .469 ) feed direction feed direction 16.3 ( .641 ) 15.7 ( .619 ) trr trl n otes : 1 . controlling dimension : millimeter. 2 . all dimensions are shown in millimeters ( inches ). 3 . outline conforms to eia-481 & eia-541. notes : 1. outline conforms to eia-481. 16 mm 13 inch
note: for the most current drawings please refer to the ir website at: http://www.irf.com/package/


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