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FDMS7602S dual n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation FDMS7602S rev.c1 www.fairchildsemi.com 1 august 2010 FDMS7602S dual n-channel powertrench ? mosfet q1: 30 v, 30 a, 7.5 m q2: 30 v, 30 a, 5.0 m features q1: n-channel ? max r ds(on) = 7.5 m at v gs = 10 v, i d = 12 a ? max r ds(on) = 12 m at v gs = 4.5 v, i d = 10 a q2: n-channel ? max r ds(on) = 5.0 m at v gs = 10 v, i d = 17 a ? max r ds(on) = 6.8 m at v gs = 4.5 v, i d = 14 a ? rohs compliant general description this device includes two specialized n-channel mosfets in a dual mlp package.the switch node has been internally connected to enable easy placement and routing of synchronous buck converters. the contro l mosfet (q1) and synchronous syncfet (q2) have been designed to provide optimal power efficiency. applications ? computing ? communications ? general purpose point of load ? notebook vcore mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter q1 q2 units v ds drain to source voltage 30 30 v v gs gate to source voltage (note 3) 20 20 v i d drain current -continuous (package limited) t c = 25 c 30 30 a -continuous (silicon limited) t c = 25 c 50 80 -continuous t a = 25 c 12 1a 17 1b -pulsed 40 60 p d power dissipation for single operation t a = 25 c 2.2 1a 2.5 1b w power dissipation for single operation t a = 25 c 1.0 1c 1.0 1d t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient 57 1a 50 1b c/w r ja thermal resistance, junction to ambient 125 1c 120 1d r jc thermal resistance, junction to case 3.5 2 device marking device package reel size tape width quantity FDMS7602S FDMS7602S power 56 13 ? 12 mm 3000 units 4 3 2 1 5 6 7 8 q 1 q 2 power 56 s2 s2 s2 g2 d1 d1 d1 g1 d1 s1/d2 s2 s2 s2 g2 d1 d1 d1 g1 top bottom
FDMS7602S dual n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation FDMS7602S rev.c1 www.fairchildsemi.com electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics symbol parameter test conditions type min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v i d = 1 ma, v gs = 0 v q1 q2 30 30 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c i d = 1 ma, referenced to 25 c q1 q2 15 15 mv/ c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v q1 q2 1 500 a a i gss gate to source leakage current v gs = 20 v, v ds = 0 v v gs = 20 v, v ds = 0 v q1 q2 100 100 na na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a v gs = v ds , i d = 1 ma q1 q2 1 1 1.8 1.8 3 3 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c i d = 1 ma, referenced to 25 c q1 q2 -6 -5 mv/ c r ds(on) drain to source on resistance v gs = 10 v, i d = 12 a v gs = 4.5 v, i d = 10 a v gs = 10 v, i d = 12 a , t j = 125 c q1 6.0 8.5 8.3 7.5 12 12 m v gs = 10 v, i d = 17 a v gs = 4.5 v, i d = 14 a v gs = 10 v, i d = 17 a , t j = 125 c q2 4.2 5.4 4.9 5.0 6.8 7.2 g fs forward transconductance v ds = 5 v, i d = 12 a v ds = 5 v, i d = 17 a q1 q2 63 87 s c iss input capacitance q1: v ds = 15 v, v gs = 0 v, f = 1 mhz q2: v ds = 15 v, v gs = 0 v, f = 1 mhz q1 q2 1315 2020 1750 2690 pf c oss output capacitance q1 q2 445 860 600 1145 pf c rss reverse transfer capacitance q1 q2 45 95 70 145 pf r g gate resistance q1 q2 0.9 0.7 t d(on) turn-on delay time q1: v dd = 15 v, i d = 12 a, r gen = 6 q2: v dd = 15 v, i d = 17 a, r gen = 6 q1 q2 8.6 11 18 20 ns t r rise time q1 q2 2.5 3.8 10 10 ns t d(off) turn-off delay time q1 q2 20 27 32 43 ns t f fall time q1 q2 2.3 3.2 10 10 ns q g total gate charge v gs = 0 v to 10 v q1 v dd = 15 v, i d = 12 a q2 v dd = 15 v, i d = 17 a q1 q2 20 33 28 46 nc q g total gate charge v gs = 0 v to 4.5 v q1 q2 9.3 16 13 22 nc q gs gate to source gate charge q1 q2 4.3 5.8 nc q gd gate to drain ?miller? charge q1 q2 2.2 4.6 nc
FDMS7602S dual n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation FDMS7602S rev.c1 www.fairchildsemi.com electrical characteristics t j = 25 c unless otherwise noted drain-source diod e characteristics symbol parameter test conditions type min typ max units v sd source to drain diode forward voltage v gs = 0 v, i s = 12 a (note 2) v gs = 0 v, i s = 17 a (note 2) q1 q2 0.8 0.8 1.2 1.2 v t rr reverse recovery time q1 i f = 12 a, di/dt = 100 a/ s q2 i f = 17 a, di/dt = 300 a/ s q1 q2 27 29 43 46 ns q rr reverse recovery charge q1 q2 10 31 18 50 nc notes: 1: r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2: pulse test: pulse width < 300 s, duty cycle < 2.0%. 3: as an n-ch device, the negative vgs rating is for low duty cycle pulse ocurrence only. no continuous rating is implied. a. 57 c/w when mounted on a 1 in 2 pad of 2 oz copper c. 125 c/w when mounted on a minimum pad of 2 oz copper b. 50 c/w when mounted on a 1 in 2 pad of 2 oz copper d. 120 c/w when mounted on a minimum pad of 2 oz copper
FDMS7602S dual n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation FDMS7602S rev.c1 www.fairchildsemi.com typical characteristics (q1 n-channel) t j = 25c unless otherwise noted figure 1. on region characteristics figure 2. n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e vs junction temperature figure 4. o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics figure 6. s o u r c e t o d r a i n d i o d e forward voltage vs source current 0.0 0.5 1.0 1.5 2.0 0 10 20 30 40 v gs = 4.5 v v gs = 3.5 v v gs = 6 v v gs = 4 v pulse duration = 80 s duty cycle = 0.5% max v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) 0 10203040 0 1 2 3 4 v gs = 4 v pulse duration = 80 s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4.5 v v gs = 6 v v gs = 3.5 v v gs = 10 v -75 -50 -25 0 25 50 75 100 125 150 0.8 1.0 1.2 1.4 1.6 i d = 12 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) 246810 0 10 20 30 40 t j = 125 o c i d = 12 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m ) pulse duration = 80 s duty cycle = 0.5% max 1.5 2.0 2.5 3.0 3.5 4.0 0 10 20 30 40 t j = 150 o c v ds = 5 v pulse duration = 80 s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 40 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v)
FDMS7602S dual n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation FDMS7602S rev.c1 www.fairchildsemi.com figure 7. gate charge characteristics figure 8. c a p a c i t a n c e v s d r a i n to source voltage figure 9. m a x i m u m c o n t i n u o u s d r a i n current vs case temperature figure 10. f o r w a r d b i a s s a f e o p e r a t i n g a r e a figure 11. single pulse maximum power dissipation typical characteristics (q1 n-channel) t j = 25c unless otherwise noted 0 5 10 15 20 0 2 4 6 8 10 i d = 12 a v dd = 20 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15 v 0.1 1 10 30 10 100 1000 2000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 25 50 75 100 125 150 0 20 40 60 limited by package v gs = 4.5 v r jc = 3.5 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) 0.01 0.1 1 10 100 0.01 0.1 1 10 100 dc 100 ms 10 ms 1 ms 1s i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds ( on ) single pulse t j = max rated r ja = 125 o c/w t a = 25 o c 10s 100us 200 10 -4 10 -3 10 -2 10 -1 110 100 1000 1 10 100 1000 p (pk) , peak transient power (w) single pulse r ja = 125 o c/w t a = 25 o c t, pulse width (s) 0.5
FDMS7602S dual n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation FDMS7602S rev.c1 www.fairchildsemi.com figure 12. junction-to-ambient transient thermal response curve typical characteristics (q1 n-channel) t j = 25c unless otherwise noted 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.001 0.01 0.1 1 single pulse r ja = 125 o c/w ( note 1c ) duty cycle-descending order normalized thermal impedance, z ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a
FDMS7602S dual n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation FDMS7602S rev.c1 www.fairchildsemi.com typical characteristics (q2 syncfet) figure 13. on-region characteristics figure 14. normalized on-resistance vs drain current and gate voltage figure 15. normalized on-resistance vs junction temperature figure 16. on-resistance vs gate to source voltage figure 17. transfer characteristics figure 18. source to drain diode forward voltage vs source current 0.0 0.5 1.0 1.5 2.0 0 20 40 60 v gs = 4.5 v v gs = 3 v v gs = 4 v v gs = 3.5 v pulse duration = 80 s duty cycle = 0.5% max v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) 0204060 0 1 2 3 4 5 v gs = 3.5 v pulse duration = 80 s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4.5 v v gs = 4 v v gs = 3 v v gs = 10 v -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 17 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) 246810 0 5 10 15 20 t j = 125 o c i d = 17 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m ) pulse duration = 80 s duty cycle = 0.5% max 1.5 2.0 2.5 3.0 3.5 0 20 40 60 t j = 125 o c v ds = 5 v pulse duration = 80 s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.01 0.1 1 10 60 t j = -55 o c t j = 25 o c t j = 125 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v)
FDMS7602S dual n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation FDMS7602S rev.c1 www.fairchildsemi.com typical characteristics (q2 syncfet) figure 19. gate charge characteristics figure 20. capacitance vs drain to source voltage f i g u r e 2 1 . m a x i m u m c o n t i n u o u s d r a i n current vs case temperature figure 22. forward bias safe operating area figure 23. single pulse maximum power dissipation 0 10203040 0 2 4 6 8 10 i d = 17 a v dd = 20 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15 v 0.1 1 10 30 60 100 1000 3000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 25 50 75 100 125 150 0 20 40 60 80 100 v gs = 4.5 v r jc = 2 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) limited by package 0.01 0.1 1 10 100 0.01 0.1 1 10 100 100 us dc 100 ms 10 ms 1 ms 1 s i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds ( on ) single pulse t j = max rated r ja = 120 o c/w t a = 25 o c 10 s 200 10 -4 10 -3 10 -2 10 -1 11010 2 10 3 1 10 100 1000 single pulse r ja = 120 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec)
FDMS7602S dual n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation FDMS7602S rev.c1 www.fairchildsemi.com typical characteristics (q2 syncfet) figure 24. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 11010 2 10 3 0.001 0.01 0.1 1 single pulse r ja = 120 o c/w ( note 1d ) duty cycle-descending order normalized thermal impedance, z ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a
FDMS7602S dual n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation FDMS7602S rev.c1 www.fairchildsemi.com syncfet schottky body diode characteristics fairchild?s syncfet process emb eds a schottky diode in parallel with powertrench mosfet. th is diode exhibits similar characteristics to a discrete exte rnal schottky diode in parallel with a mosfet. figure 25 shows the reverse recovery characteristic of the FDMS7602S. schottky barrier diodes exhibit significant leakage at high tem- perature and high reverse voltage. this will increase the power in the device. 0 50 100 150 200 -5 0 5 10 15 20 di/dt = 300 a/ s current (a) time (ns) figure 2 5 . FDMS7602S syncfet body diode reverse recovery characteristic 0 5 10 15 20 25 30 1 10 100 1000 10000 t j = 125 o c t j = 100 o c t j = 25 o c i dss , reverse leakage current (ua) v ds , reverse voltage (v) typical char acteristics (continued) figure 2 6 . syncfet body diode reverse leakage versus drain-source voltage
FDMS7602S dual n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation FDMS7602S rev.c1 www.fairchildsemi.com dimensional outline and pad layout
FDMS7602S dual n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation FDMS7602S rev.c1 www.fairchildsemi.com trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes wi thout further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights , nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support de vices or systems without the express written approval of fai rchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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