cystech electronics corp. spec. no. : c732l3 issued date : 2013.01.15 revised date : page no. : 1/8 MTBB0P10L3 cystek product specification p-channel logic level enha ncement mode power mosfet MTBB0P10L3 bv dss -100v i d -2.6a r dson @v gs =-10v, i d =-2a 171m (typ) 186 (typ) r dson @v gs =-4.5v, i d =-1a features ? low gate charge ? simple drive requirement ? pb-free lead plating & halogen-free package equivalent circuit outline absolute maximum ratings (t c =25 c, unless otherwise noted) MTBB0P10L3 sot-223 g d s d g gate d drain s source parameter symbol limits unit drain-source voltage v ds -100 v gs 20 v gate-source voltage i d -2.6 continuous drain current @ v gs =-10v, t a =25 c i d -2.1 continuous drain current @ v gs =-10v, t a =70 c pulsed drain current *1 i dm -10.4 i as -2 a avalanche current avalanche energy @ l=6mh, i d =-2a, r g =25 e as 12 repetitive avalanche energy @ l=0.05mh *2 e ar 0.5 mj total power dissipation @t a =25 2.5 pd w total power dissipation @t a =70 1.6 operating junction and storage te mperature range tj, tstg -55~+150 c note : *1 . pulse width limited by maximum junction temperature *2. duty cycle 1%
cystech electronics corp. spec. no. : c732l3 issued date : 2013.01.15 revised date : page no. : 2/8 MTBB0P10L3 cystek product specification thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 15 c/w thermal resistance, junction-to-ambient, max r th,j-a 50 (note) c/w note : surface mounted on a 1 in 2 pad of 2 oz. copper, t 10s; 120 c/w when mounted on minimum copper pad. characteristics (tc=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss -100 - - v v gs =0, i d =-250 a v gs(th) -1 -1.9 -3 v v ds =v gs , i d =-250 a i gss - - d 100 na v gs = d 20, v ds =0 - - -1 a v ds =-80v, v gs =0 i dss - - -25 a v ds =-70v, v gs =0, t j =125 c - 171 225 m v gs =-10v, i d =-2a r ds(on) *1 - 186 245 m v gs =-4.5v, i d =-1a g fs *1 - 6 - s v ds =-5v, i d =-2a dynamic qg *1, 2 - 20 - qgs *1, 2 - 4.6 - qgd *1, 2 - 4.3 - nc i d =-2.5a, v ds =-80v, v gs =-10v t d(on) *1, 2 - 14 - tr *1, 2 - 10 - t d(off) *1, 2 - 37 - t f *1, 2 - 10 - ns v ds =-50v, i d =-1a, v gs =-10v, r g =6 ciss - 1361 - coss - 46 - crss - 28 - pf v gs =0v, v ds =-25v, f=1mhz source-drain diode i s *1 - - -2.6 i sm *3 - - -10.4 a v sd *1 - -0.8 -1.3 v i s =-2a, v gs =0v trr - 40 - ns qrr - 220 - nc i f =-2a, di f /dt=100a/ s note : *1.pulse test : pulse width 300 s, duty cycle 2% *2.independent of operating temperature *3.pulse width limited by maximum junction temperature. ordering information device package shipping MTBB0P10L3-0-t3-g sot-223 (pb-free lead plating an d halogen-free package) 2500 pcs / tape & reel
cystech electronics corp. spec. no. : c732l3 issued date : 2013.01.15 revised date : page no. : 3/8 MTBB0P10L3 cystek product specification typical characteristics typical output characteristics 0 1 2 3 4 5 6 7 8 9 10 01234 5 brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -60 -20 20 60 100 140 180 tj, junction temperature(c) -bv dss , normalized drain-source breakdown voltage i d =-250 a, v gs =0v -v ds , drain-source voltage(v) -i d , drain current(a) 10v 8v 7v 6v 4.5v 4v -v gs =3.5v -v =3v gs static drain-source on-state resistance vs drain current 100 1000 0.001 0.01 0.1 1 10 100 -i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) vgs=-4.5v v gs =-10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 0 5 10 15 20 -i dr , reverse drain current(a) -v sd , source-drain voltage(v) tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 100 200 300 400 500 600 700 800 900 1000 024681 0 drain-source on-state resistance vs junction tempearture 0.4 0.8 1.2 1.6 2 2.4 -60 -20 20 60 100 140 180 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =-10v, i d =-2a r ds( on) @tj=25c : 171m -v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =-2a
cystech electronics corp. spec. no. : c732l3 issued date : 2013.01.15 revised date : page no. : 4/8 MTBB0P10L3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 10000 0.1 1 10 100 -v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -60 -20 20 60 100 140 180 tj, junction temperature(c) -v gs(th) , normalized threshold voltage i d =-250 a maximum safe operating area 0.01 0.1 1 10 100 0.1 1 10 100 1000 -v ds , drain-source voltage(v) -i d , drain current (a) r ds( on) limited dc 10ms 100ms 1ms 100 s 10 s t a =25c, tj=150c, v gs =10v, r ja =50c/w single pulse gate charge characteristics 0 2 4 6 8 10 048121620 qg, total gate charge(nc) -v gs , gate-source voltage(v) i d =-2.5a v ds =-20v v ds =-50v v ds =-80v maximum drain current vs junction temperature 0 0.5 1 1.5 2 2.5 3 25 50 75 100 125 150 175 tj, junctiontemperature(c) -i d , maximum drain current(a) t a =25c, v gs =10v, r ja =50c/w single pulse maximum power dissipation 0 10 20 30 40 50 0.0001 0.001 0.01 0.1 1 10 pulse width(s) peak transient power (w) t j(max) =150c t a =25c ja =50c/w
cystech electronics corp. spec. no. : c732l3 issued date : 2013.01.15 revised date : page no. : 5/8 MTBB0P10L3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 1 2 3 4 5 6 7 8 9 10 012345 -v gs , gate-source voltage(v) -i d , drain current(a) v ds =-5v forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 -i d , drain current(a) g fs , forward transfer admittance(s) pulsed ta=25c v ds =-5v v ds =-10v transient thermal response curves 0.01 0.1 1 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t1/t2 3.t jm -t a =p dm *r ja (t) 4.r ja =50c/w
cystech electronics corp. spec. no. : c732l3 issued date : 2013.01.15 revised date : page no. : 6/8 MTBB0P10L3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c732l3 issued date : 2013.01.15 revised date : page no. : 7/8 MTBB0P10L3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds ? time(ts min to ts max ) time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c732l3 issued date : 2013.01.15 revised date : page no. : 8/8 MTBB0P10L3 cystek product specification sot-223 dimension *: typical inches millimeters inches 321 f b a c d e g h a1 a2 i style: pin 1.gate 2.drain 3.source marking: 3-lead sot-223 plastic surface mounted package cystek package code: l3 device name date code bb0p10 millimeters dim min. max. min. max. dim min. max. min. max. a 0.1142 0.1220 2.90 3.10 g 0.0551 0.0709 1.40 1.80 b 0.2638 0.2874 6.70 7.30 h 0.0098 0.0138 0.25 0.35 c 0.1299 0.1457 3.30 3.70 i 0.0008 0.0039 0.02 0.10 d 0.0236 0.0315 0.60 0.80 a1 *13 o - *13 o - e *0.0906 - *2.30 - a2 0 o 10 o 0 o 10 o f 0.2480 0.2638 6.30 6.70 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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