1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi2gg46464v february 1999 rev. 2 eco# 10858 4x64kx64, 3.3v synchronous sram card edge dimm features n 4x64kx64 synchronous n access speed(s): t khqv = 9.5, 10, 11,12, 15ns n flow-through architecture n clock controlled registered bank enables (e 1 \,e 2 \, e 3 \, e 4 \) n clock controlled registered address n clock controlled registered global write (gw\) n aysnchronous output enable (g\) n internally self-timed write+ n gold lead finish n 3.3v 10%, -5% operation n common data i/o n high capacitance (30pf) drive, at rated access speed n single total array clock n multiple vcc and vss the edi2gg46464vxxd is a synchronous sram, 60 position dual key; card edge dimm (120 contacts) module, organized as 4x64kx64. the module contains eight (8) synchronous burst ram devices, packaged in the industry standard jedec 14mmx20mm tqfp placed on a multilayer fr4 substrate. the module architecture is defined as a synchronous only, flow-through, early write device. this module provides high performance, ultra fast access times at a cost per bit benefit over bicmos asynchronous devices. as well as improved cost per bit, the use of synchronous or synchronous burst devices or modules can ease the memory subsystem design by reducing or easing the memory controller requirement. synchronous operations are in relation to an externally supplied clock, registered address, registered global write, registered enables as well as an asynchronous output enable. all read and write operations are performed in quad words (64 bit operations). write cycles are internally self timed and are initiated by a rising clock edge. this feature relieves the designer the task of developing external pulse width circuitry.
2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi2gg46464v pin configuration vss vss a0 a1 a15 a2 a14 a3 a13 vcc vcc a4 a12 a5 a6 a7 vss a8 vss clk vss e4\ vcc e3\ g\ vss dq0 dq1 dq2 dq3 vcc dq8 dq9 dq10 dq16 dq17 dq18 dq19 vcc dq24 dq25 dq26 dq27 vss dq32 dq33 dq34 dq35 vcc dq40 dq41 dq42 dq43 vss dq48 dq49 dq50 dq51 vcc dq56 dq57 dq58 dq59 vss 11 13 15 17 19 vss dq11 a11 a10 a9 vss rfu vss nc 16 14 12 10 vss e2\ vcc e1\ gw\ vss dq7 dq6 dq5 dq4 vcc dq15 dq14 dq13 dq12 vss dq23 dq22 dq21 dq20 vcc dq31 dq30 dq29 dq28 vss dq39 dq38 dq37 dq36 vcc dq47 dq46 dq45 dq44 vss dq55 dq54 dq53 dq52 vcc dq63 dq62 dq61 dq60 vss nc 1 3 5 7 9 8 6 4 2 21 23 25 27 28 26 24 22 20 18 29 31 33 35 37 39 41 43 45 47 49 51 52 50 48 46 44 42 40 38 36 34 30 32 53 55 57 59 61 63 65 67 69 71 73 54 56 58 60 62 64 66 68 70 72 74 75 77 79 81 83 85 87 89 91 93 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 95 97 99 101 103 105 107 109 111 113 115 117 119 118 120
3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi2gg46464v g\ gw\ e1\ gw\ g\ e\ dq 64kx32 gw\ g\ e\ dq 64kx32 gw\ g\ e\ dq 64kx32 gw\ g\ e\ dq 64kx32 e3\ gw\ g\ e\ dq 64kx32 gw\ g\ e\ dq 64kx32 gw\ g\ e\ dq 64kx32 gw\ g\ e\ dq 64kx32 e2\ e4\ dq0-dq31 dq32-dq63 clk clk clk clk clk clk clk clk clk a0-a15 functional block diagram dq 0-63 input/output bus a 0-15 address bus e 1 \, e 2 \, synchronous bank e 3 \, e 4 \ enables clk array clock gw\ synchronous global write enable g\ asynchronous output enable vcc 3.3v power supply vss ground nc no connect pin names pin descriptions dimm pins symbol type description 3, 5, 7, 9, 13, 15, a0-15 input addresses: these inputs are registered and must meet the setup and hold times around the rising e dge of clk. 17, 19, 23, 20, 18, synchronous the burst counter generates internal addresses associated with a0 and a1, during burst and wait c ycle. 16, 14, 10, 8, 6 38 gw\ input global write: this active low input allows a full 72-bit write to occur independent of the bwe\ and bwx\ lines synchronous and must meet the setup and hold times around the rising edge of clk. 27 clk input clock: this signal registers the addresses, data, chip enables, write control and burst control inputs on its rising synchronous edge. all synchronous inputs must meet setup and hold times around the clock?s rising edge. 36, 32, e1\, e2\ input bank enables: these active low inputs are used to enable each individual bank and to gate adsp\. 35, 31 e3\, e4\ synchronous 37 g\ input output enable: this active low asynchronous input enables the data output drivers. various dq0-63 input/output data inputs/outputs: first byte is dq0-7, second byte is dq8-15, third byte is dq16-23, fourth byte is dq24-31, fifth byte is dq32-39, sixth byte is dq40-47, seventh byte is dq48-55 and the eight byte is dq56-64. various vcc supply core power supply: +3.3v -5%/+10% various vss ground ground
4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi2gg46464v parameter sym min typ max units supply voltage v cc 3.14 3.3 3.6 v supply voltage v ss 0.0 0.0 0.0 v input high v ih 2.2 3.0 v cc +0.3 v input low v il -0.3 0.0 0.8 v input leakage ili -2 1 2 ma output leakage ilo -2 1 2 ma output high v oh 2.4 - - v i oh = -4ma output low v ol - - 0.4 v i ol = 8ma recommended dc operating conditions synchronous only - truth table operation e1\ e2\ e3\ e4\ gw\ g\ clk dq synchronous write-bank 1 l h h h l h - high-z synchronous read-bank 1 l h h h h l - synchronous write-bank 2 h l h h l h - high-z synchronous read-bank 2 h l h h h l - synchronous write-bank 3 h h l h l h - high-z synchronous read-bank 3 h h l h h l - synchronous write-bank 4 h h h l l h - high-z synchronous read-bank 4 h h h l h l - snooze mode x x x xxxxhigh-z *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. absolute maximum ratings* voltage on vcc relative to vss -0.5v to +4.6v vin -0.5v to vcc +0.5v storage temperature -55 c to +125 c operating temperature (commercial) 0 c to +70 c operating temperature (industrial) -40 c to +85 c short circuit output current 20ma max description symbol typ 9.5 10 11 12 15 units power supply current icc1 1.8 * 1.2 1.1 1.0 0.9 a power supply current icc 0.8 * 0.9 0.8 0.8 0.7 a device selected,no operation snooze mode icczz 500 * 700 700 700 700 ma cmos standby icc3 270 * 350 350 350 350 ma clock running-deselect icck 900 * 1.1 1.0 1.0 1.0 a dc electrical characteristics - read cycle *tbd ac test circuit 50 w vt = 1.5v output z0 = 50 w z0 = 50 w ac test conditions parameter i/o unit input pulse levels vss to 3.0 v input and output timing ref. 1.25 v output test equivalencies see figure, at left ac output load equivalent
5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi2gg46464v 9.5ns 10ns 11ns 12ns 15ns description symbol min max min max min max min max min max units clock cycle time t khkh * * 12 12 15 20 ns clock high time t khkl **5556ns clock low time t klkh **5556ns address setup t avkh * * 2.5 2.5 2.5 2.5 ns address hold t khax * * 1.0 1.0 1.0 1.0 ns bank enable setup t evkh * * 2.5 2.5 2.5 2.5 ns bank enable hold t khex * * 1.0 1.0 1.0 1.0 ns global write enable setup t wvkh * * 2.5 2.5 2.5 2.5 ns global write enable hold t khwx * * 1.0 1.0 1.0 1.0 ns data setup t dvkh * * 2.5 2.5 2.5 2.5 ns data hold t khdx * * 1.0 1.0 1.0 1.0 ns write cycle timing parameters 9.5ns 10ns 11ns 12ns 15ns description symbol min max min max min max min max min max units clock cycle time t khkh * * 12 12 15 20 ns clock high time t khkl **5556ns clock low time t klkh **5556ns clock to output valid t khqv * * 10 11 12 15 ns clock to output invalid t khqx1 **3333ns clock to output low-z t khqx **2222ns output enable to output valid t glqv **5556ns output enable to output low-z t glqx **0000ns output enable to output high-z t ghqz **5556ns address setup t avkh * * 2.5 2.5 2.5 2.5 ns bank enable setup t evkh * * 2.5 2.5 2.5 2.5 ns address hold t khax * * 1.0 1.0 1.0 1.0 ns bank enable hold t khex * * 1.0 1.0 1.0 1.0 ns read cycle timing parameters *tbd *tbd
6 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi2gg46464v synchronous read cycle t khqx dq read cycle q(addr 1) q(addr 1) q(addr 2) t khqz gw\ oe\ addr ce\ clk t khqv addr 1 addr 2 addr 1 t khkh t klkh t khkl t glqx back to back read t khqx1 t glqv t khax t avkh ex\ g\
7 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi2gg46464v synchronous write cycle synchronous read/write cycle write cycle t dvkh back to back cycles g\ controlled d (addr 2) gw\ dq q (addr 1) read cycle t khqx t avkh g\ addr ce\ clk t khqv addr 1 addr 2 t khdx t khkh t klkh t khkl t khdx t ghkh t gwlkh t avkh t dvkh write cycle oe\ gw\ addr clk ce\ addr 1 addr 1 addr 2 t klkh t khkh t khkl back to back writes t khgh t khdx t khgwh t khax dq ex\ g\
8 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi2gg46464v package description ordering information part number organization voltage speed (ns) package edi2gg46464v95d* 4x64kx64 3.3 9.5 120 card edge dimm edi2gg46464v10d 4x64kx64 3.3 10 120 card edge dimm edi2gg46464v11d 4x64kx64 3.3 11 120 card edge dimm EDI2GG46464V12D 4x64kx64 3.3 12 120 card edge dimm edi2gg46464v15d 4x64kx64 3.3 15 120 card edge dimm *consult factory for availability all dimensions are in inches r1 r4 3.513 max. .041 .002 1.250 1.360 .003 1.760 .002 1.650 .050 typ. .150 .074 .003 1.125 max. r.031(2x) .210 max. .200 min. .200 typ. .195 r7 r8 rev.# 173 r2 r3 r5 r6 r9 r10 120 card edge dimm
|
