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july 2010 ? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels FXMA108 dual-supply, 8-bit signal translator with configurable voltage supplies and signals levels, 3-state outputs and auto direction sensing features ? bi-directional interface between two levels from 1.65v to 5.5v ? fully configurable: inputs and outputs track v cc ? non-preferential power-up; either v cc may be powered-up first ? outputs remain in 3-state until active v cc level is reached ? outputs switch to 3-state if either v cc is at gnd ? power-off protection ? bus hold on data inputs eliminates the need for pull-up resistors ? control input (/oe) is referenced to v cca voltage ? packaged in 20-terminal dqfn ? direction control not needed ? 80mbps throughput when translating between 2.5v and 5.0v ? esd protection exceeds: ? 8kv human body model (b port i/o to gnd) (jesd22-a114 & mil std 883e 3015.7) ? 5kv human body model (a port i/o to gnd) (jesd22-a114 & mil std 883e 3015.7) ? 2kv charged device model (esd stm 5.3) (jesd22-c101) description the FXMA108 is a configurable dual-voltage supply translator designed for both uni-directional and bi- directional voltage translation between two logic levels. the device allows translation between voltages as high as 5.5v to as low as 1.65v. the a port tracks the v cca level and the b port tracks the v ccb level. this allows for bi-directional voltage translation over a variety of voltage levels: 1.8v, 2.5v, 3.3v, and 5.0v. the device remains in 3-state until both v cc s reach active levels, allowing either v cc to be powered-up first. internal power-down control circuits place the device in 3-state if either v cc is removed. the /oe input, when high, disables both the a and b side by placing them in a 3-state condition. the /oe input is supplied by v cca . the FXMA108 supports bi-directional translation without the need for a direction control pin. the two sides of the device have auto-direction-sense capability. either port may sense an input signal and transfer it as an output signal to the other port. applications ? cell phones, pda, digital camera, portable gps, and storage ordering information part number operating temperature range package packing method FXMA108bqx -40 to 85c 20-lead, dqfn, jedec mo-241, 2.5x4.5mm 3000 units tape and reel
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 2 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels functional diagram figure 1. block diagram functional table control outputs /oe low logic level normal operation high logic level 3-state
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 3 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels pin configuration figure 2. pin configur ation (top through view) pin definitions pin # name description 1 v cca a-side power supply 2 a0 a-side inputs or 3-state outputs 3 a1 a-side inputs or 3-state outputs 4 a2 a-side inputs or 3-state outputs 5 a3 a-side inputs or 3-state outputs 6 a4 a-side inputs or 3-state outputs 7 a5 a-side inputs or 3-state outputs 8 a6 a-side inputs or 3-state outputs 9 a7 a-side inputs or 3-state outputs 10 gnd ground 11 /oe output enable input 12 b7 b-side inputs or 3-state outputs 13 b6 b-side inputs or 3-state outputs 14 b5 b-side inputs or 3-state outputs 15 b4 b-side inputs or 3-state outputs 16 b3 b-side inputs or 3-state outputs 17 b2 b-side inputs or 3-state outputs 18 b1 b-side inputs or 3-state outputs 19 b0 b-side inputs or 3-state outputs 20 v ccb b-side power supply dap nc no connect 2 a 0 a 1 3 a 2 4 a 3 5 a 4 a 5 6 7 10 19 18 17 16 15 14 /oe 11 1 20 gnd v cca v ccb b 0 b 1 b 2 b 3 b 4 b 5 a 6 8 a 7 9 13 b 6 12 b 7
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 4 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter conditions min. max. unit v cc supply voltage v cca -0.5 7.0 v v ccb -0.5 7.0 v in dc input voltage i/o side a and b -0.5 7.0 v control input (/oe) -0.5 7.0 v o output voltage output 3-state -0.5 7.0 v output active (a n ) (1) -0.5 v cca +0.5 output active (b n ) (1) -0.5 v ccb +0.5 i ik dc input diode current v in < 0v -50 ma i ok dc output diode current v o < 0v -50 ma v o > v cc +50 i oh /i ol dc output source/sin k current -50 +50 ma i cc dc v cc or ground current (per supply pin) 100 ma t stg storage temperature range -65 +150 c esd electrostatic discharge capability human body model, jesd22- a114, and mil std 883e 3015.7 b port i/o to gnd 8000 v human body model, jesd22- a114 and mil std 883e 3015.7 a port i/o to gnd 5000 charged device model, jesd22-c101 per esd stm 5.3 2000 note: 1. i o absolute maximum ratings must be observed. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions typ. max. unit v cc power supply operating v cca or v ccb 1.65 5.50 v v in input voltage side a and b 0 5.5 v control input (/oe) 0 v cca v t a operating temperature, free air -40 +85 c dt/dv input edge rate v cca/b =1.65 to 5.5v 10 ns/v note: 2. all unused inputs and input/outputs must be held at v cci or gnd. v cci is the v cc associated with the input side.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 5 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels power-up/power-down sequence fairchild translators offer an advantage in that either v cc may be powered up first. this benefit derives from the chip design. when either v cc is at 0v, outputs are in a high-impedance state. the control input (/oe) is designed to track the v cca supply. a pull-up resistor tying /oe to v cca should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up or power-down. the size of the pull-up resistor is based upon the current-sinking capability of the device driving the /oe pin. the recommended power-up sequence is: 1. apply power to the first v cc . 2. apply power to the second v cc . 3. drive the /oe input low to enable the device. the recommended power-down sequence is: 1. drive /oe input high to disable the device. 2. remove power from either v cc . 3. remove power from the other v cc. pull-up/pull-down resistors do not use pull-up or pull-down resistors. this device has bus-hold circuits: pull-up or pull-down resistors are not recommended because they interfere with the output state. the current through these resistors may exceed the hold drive, i i(hold) and/or i i(od) bus-hold currents. the bus-hold feature eliminates the need for extra resistors.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 6 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels dc electrical characteristics t a =-40 c to +85 c. symbol parameter conditions v cca (v) v ccb (v) min. max. units v iha high level input voltage data inputs an control pin /oe 1.65 - 5.50 1.65 - 5.50 0.65 x v cca v v ihb data inputs bn 1.65 - 5.50 1.65 - 5.50 0.65 x v ccb v ila low level input voltage data inputs an control pin /oe 1.65 - 5.50 1.65 - 5.50 0.35 x v cca v v ilb data inputs bn 1.65 - 5.50 1.65 - 5.50 0.35 x v ccb v oha high level output voltage (3) i oh =-20a 1.65 - 5.50 1.65 - 5.50 v cca - 0.4 v v ohb i oh =-20a 1.65 - 5.50 1.65 - 5.50 v ccb - 0.4 v ola low level output voltage (3) i ol =20a 1.65 - 5.50 1.65 - 5.50 0.4 v v olb i ol =20a 1.65 - 5.50 1.65 - 5.50 0.4 i i(hold) bushold input minimum drive current v in =1.60v 4.5 4.5 140 a v in =2.90v 4.5 4.5 -140 v in =1.05v 3.0 3.0 75 v in =1.95v 3.0 3.0 -75 v in =0.80v 2.3 2.3 45 v in =1.50v 2.3 2.3 -45 v in =0.57v 1.65 1.65 25 v in =1.07v 1.65 1.65 -25 i i(odh) bushold input overdrive high current (4) data inputs an, bn 5.5 5.5 750 a 3.6 3.6 450 2.7 2.7 300 1.95 1.95 200 i i(odl) bushold input overdrive low current (5) data inputs an, bn 5.5 5.5 -750 3.6 3.6 -450 2.7 2.7 -300 1.95 1.95 -200 continued on the following page?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 7 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels dc electrical characteristics (continued) t a =-40 c to +85 c. symbol parameter conditions v cca (v) v ccb (v) min. max. units i i input leakage current control inputs /oe v in =v cca or gnd 1.65 - 5.50 5.5 1 a i off power off leakage current an, v o =0v to 5.5v 0 5.5 2 a bn, v o =0v to 5.5v 5.5 0 2 i oz 3-state output leakage an, bn v o =0v or 5.5v, /oe v ih 5.5 5.5 5 a an, v o =0v or 5.5v, /oe=gnd 5.5 0 5 bn, v o =0v or 5.5v, /oe=gnd 0 5.5 5 i cca/b quiescent supply current ( 6,7) v in =v cci or gnd, i o =0 /oe=gnd 1.65 - 5.50 1.65 - 5.50 10 a i ccz v in =v cci or gnd, i o =0 /oe=v ih 1.65 - 5.50 1.65 - 5.50 10 a i cca quiescent supply current ( 6,7) v in =v ccb or gnd, i o =0 b-to-a direction /oe=gnd 0 1.65 - 5.50 -10 a v in =v cca or gnd, i o =0 a-to-b 1.65 - 5.50 0 10 i ccb quiescent supply current v in =v cca or gnd, i o =0 a-to-b direction /oe=gnd 1.65 - 5.50 0 -10 a v in =v ccb or gnd, i o =0 b-to-a 0 1.65 - 5.50 10 notes: 3. this is the output voltage for static conditions. 4. an external driver must source at least the specified current to switch low-to-high. 5. an external driver must source at least the specified current to switch high-to-low. 6. v cci is the v cc associated with the input side. 7. reflects current per supply, v cca or v ccb .
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 8 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels dynamic output electrical characteristics (8) a port (an) output load: c l =15pf, r l 1m ? . symbol parameter t a =-40 c to +85 c units v cca =4.5v to 5.5v v cca =3.0v to 3.6v v cca =2.3v to 2.7v v cca =1.65v to 1.95v max. max. max. max. t rise output rise time a side (9) 2.5 3.0 3.5 4.0 ns t fall output fall time a side (10) 2.5 3.0 3.5 4.0 ns b port (bn) output load: c l =15pf, r l 1m ? . symbol parameter t a =-40 c to +85 c units v ccb =4.5v to 5.5v v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v max. max. max. max. t rise output rise time b side 9) 3.5 3.5 3.5 4.0 ns t fall output fall time b side (10) 3.5 3.5 3.5 4.0 ns notes: 8. dynamic output characteristics are guaranteed, but not tested in production. 9. see figure 8. 10. see figure 9.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 9 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels ac characteristics v cca =4.5v to 5.5v, output load (see table 2) symbol parameter t a =-40 c to +85 c units v ccb =4.5v to 5.5v v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v min. max. min. max. min. max. min. max. t plh ,t phl a-to-b side 1.5 5.0 1.75 6.0 2.0 6.5 2.6 10.5 ns b-to-a side 1.5 5.0 1.75 6.0 2.0 6.5 2.6 10.5 t pzl , t pzh /oe-to-a, /oe-to-b 1.7 1.7 1.7 1.7 s t skew a port, b side (11) 0.5 0.5 0.5 0.5 ns note: 11. skew is the variation of propagation delay between output signals and applies only to output signals on the same side (an or bn) and switching with the same polarity (low-to-high or high-to-low). skew is guaranteed, but not tested in production (see figure 11 ). v cca =3.0v to 3.6v, output load (see table 2) symbol parameter t a =-40 c to +85 c units v ccb =4.5v to 5.5v v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v min. max. min. max. min. max. min. max. t plh , t phl a-to-b side 2.0 5.5 2.2 6.5 2.4 7.5 2.6 11.0 ns b-to-a side 2.0 5.5 2.2 6.5 2.4 7.5 2.6 11.0 t pzl , t pzh /oe-to-a, /oe-to-b 1.7 1.7 1.7 1.7 s t skew a side, b side (12) 0.7 0.7 0.7 0.7 ns note: 12. skew is the variation of propagation delay between output signals and applies only to output signals on the same side (an or bn) and switching with the same polarity (low-to-high or high-to-low). skew is guaranteed, but not tested in production (see figure 11).
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 10 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels ac characteristics (continued) v cca =2.3v to 2.7v, output load (see table 2) symbol parameter t a =-40 c to +85 c units v ccb =4.5v to 5.5v v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v min. max. min. max. min. max. min. max. t plh , t phl a-to-b side 2.0 6.5 2.2 7.7 2.4 8.5 2.6 11.0 ns b-to-a side 2.0 7.0 2.2 7.5 2.4 8.5 2.6 12.0 t pzl , t pzh /oe- to-a /oe-to-b 1.7 1.7 1.7 1.7 s t skew a side, b side (13) 0.7 0.7 0.7 0.7 ns note: 13. skew is the variation of propagation delay between output signals and applies only to output signals on the same side (an or bn) and switching with the same polarity (low-to-high or high-to-low). skew is guaranteed but not tested in production (see figure 11). v cca =1.65v to 1.95v, output load (see table 2) symbol parameter t a =-40 c to +85 c units v ccb =4.5v to 5.5v v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v min. max. min. max. min. max. min. max. t plh , t phl a-to-b side 2.0 10.0 2.2 11.0 2.4 12.0 2.6 14.0 ns b-to-a side 2.0 10.0 2.2 10.5 2.4 11.0 2.6 14.0 t pzl , t pzh /oe-to-a /oe to b 1.7 1.7 1.7 1.7 s t skew a side, b side (14) 1.2 1.2 1.2 1.2 ns note: 14. skew is the variation of propagation delay between output signals and applies only to output signals on the same side (an or bn) and switching with the same polarity (low-to-high or high-to-low). skew is guaranteed, but not tested in production (see figure 11).
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 11 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels maximum data rate (15, 16) for output load, see table 2. v cca direction t a =-40 c to +85 c units v ccb =4.5v to 5.5v v ccb =3.0v to 3.6v v ccb =2.3v to 2.7v v ccb =1.65v to 1.95v min. min. min. min. v cca =4.5v to 5.5v a-to-b 100 100 80 60 mbps b-to-a 100 100 80 80 v cca =3.0v to 3.6v a-to-b 100 100 80 60 b-to-a 100 100 80 80 v cca =2.3v to 2.7v a-to-b 80 80 60 40 b-to-a 80 80 60 60 v cca =1.65v to 1.95v a-to-b 80 80 60 40 b-to-a 60 60 40 40 notes: 15. maximum data rate is guaranteed, but not tested in production. 16. maximum data rate is specified in megabits per second with all outputs switching, (see figure 10). it is equivalent to two times the f-toggle frequency, specifi ed in megahertz. for example, 100mbps is equivalent to 50mhz. capacitance t a =+25 c. symbol parameter conditions typical unit c in input capacitance, control pin /(oe) v cca =v ccb =gnd 3 pf c i/o input / output capacitance an v cca =v ccb =5.0v, /oe=v cca 4 pf bn 5 c pd power dissipation capacitance v cca =v ccb =5.0v, v in =0v or v cc , f=10mhz 28 pf
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 12 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels i/o architecture benefit the FXMA108 i/o architecture benefits the end user, beyond level translation, in the following three ways: auto direction without an external direction pin. drive capacitive loads . automatically shifts to a higher current drive mode only during ?dynamic mode? or hl / lh transitions. lower power consumption . automatically shifts to low-power mode during ?stati c mode? (no transitions), lowering power consumption. the FXMA108 does not require a direction pin. instead, the i/o architecture detects input transitions on both side and automatically transfers the data to the corresponding output. for example, for a given channel, if both a and b side are at a static low, the direction has been established as a ? b, and a lh transition occurs on the b port; the FXMA108 internal i/o architecture automatically changes direction from a ? b to b ? a. during hl / lh transitions, or ?dynamic mode,? a strong (typically 30ma) output driv er drives the output channel in parallel with a weak (typically 100a) output driver. after a typical delay of approximately 10ns ? 50ns, the strong driver is turned off, leaving the weak driver enabled for holding the logic state of the channel. this weak driver is called the ?bus hold.? ?static mode? is when only the bus hold drives the channel. the bus hold can be over ridden (typically 500a) in the event of a direction change. the strong driver allows the FXMA108 to quickly charge and discharge capacitive transmission lines during dynamic mode. static mode conserves power, where i cc is typically < 5a. bus hold minimum drive current specifies the minimum amount of current the bus hold driver can source/sink. the bus hold minimum drive current (i hold ) is v cc dependent and guaranteed in the dc electrical tables. the intent is to maintain a valid output state in a static mode, but that can be overridden when an input data transition occurs. bus hold input overdrive drive current specifies the minimum amount of current required (by an external device) to overdrive the bus hold in the event of a direction change. the bus hold overdrive (i odh , i odl ) is v cc dependent and guaranteed in the dc electrical tables. dynamic output current the strength of the output driver during lh / hl transitions is captured in figure 3 (i olh , i ohd ). the plot depicts the FXMA108 typical dynamic output current with a lumped capacitance of 4pf. because the strong output driver is turned on only during lh / hl transitions, the actual drive current is difficult to measure directly. approximate the drive current with the following formula: rise cco o i out o i ohd t v c t v c i * 6 . 0 ) ( ) ( / / = (1) where c i/o = the typical lumped capacitance and v cco is the supply voltage of the output driver. figure 3. typical dynamic output current
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 13 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels ac tests and waveforms v cc dut c1 r1 test signal figure 4. ac test circuit table 1. test circuit parameters test input signal output enable control t plh , t phl data pulses 0v t pzl 0v high-to-low switch t pzh v cci high-to-low switch table 2. ac load table v cco c1 r1 1.8v 0.15v 15pf 1m 2.5v 0.2v 15pf 1m 3.3 0.3v 15pf 1m 5.0 0.5v 15pf 1m
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 14 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels ac tests and waveforms figure 5. waveform for inverting and non-inverting functions notes: 17. input t r = t f = 2.0ns, 10% to 90%. 18. input t r = t f = 2.5ns, 10% to 90%, at v in = 3.0v to 5.5v only. figure 6. 3-state output low enable time for low voltage logic notes: 19. input t r = t f = 2.0ns, 10% to 90%. 20. input t r = t f = 2.5ns, 10% to 90%, at v in = 3.0v to 5.5v only. figure 7. 3-state output high enable time for low voltage logic notes: 21. input t r = t f = 2.0ns, 10% to 90%. 22. input t r = t f = 2.5ns, 10% to 90%, at v in = 3.0v to 5.5v only.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 15 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels ac tests and waveforms (continued) symbol v cc v mi (23) v cci /2 v mo v cco /2 v x 0.9 x v cco v y 0.1 x v cco note: 23. v cci = v cca for control pin /oe or v mi = (v cca /2). figure 8. active output rise time figure 9. active output fall time figure 10. maximum data rate figure 11. output skew time
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 16 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels physical dimensions figure 12. 20-lead, dqfn, jedec mo-241, 2.5x4.5mm package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 17 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXMA108 ? rev. 1.0.1 18 FXMA108 ? dual-supply, 8-bit signal translator with configurable voltage s upplies and signal levels

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